target-arm/kvm32.c

   1 /*
   2  * ARM implementation of KVM hooks, 32 bit specific code.
   3  *
   4  * Copyright Christoffer Dall 2009-2010
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include <stdio.h>
  12 #include <sys/types.h>
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/timer.h"
  20 #include "sysemu/sysemu.h"
  21 #include "sysemu/kvm.h"
  22 #include "kvm_arm.h"
  23 #include "cpu.h"
  24 #include "internals.h"
  25 #include "hw/arm/arm.h"
  26
  27 static inline void set_feature(uint64_t *features, int feature)
  28 {
  29     *features |= 1ULL << feature;
  30 }
  31
  32 bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
  33 {
  34     /* Identify the feature bits corresponding to the host CPU, and
  35      * fill out the ARMHostCPUClass fields accordingly. To do this
  36      * we have to create a scratch VM, create a single CPU inside it,
  37      * and then query that CPU for the relevant ID registers.
  38      */
  39     int i, ret, fdarray[3];
  40     uint32_t midr, id_pfr0, id_isar0, mvfr1;
  41     uint64_t features = 0;
  42     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
  43      * we know these will only support creating one kind of guest CPU,
  44      * which is its preferred CPU type.
  45      */
  46     static const uint32_t cpus_to_try[] = {
  47         QEMU_KVM_ARM_TARGET_CORTEX_A15,
  48         QEMU_KVM_ARM_TARGET_NONE
  49     };
  50     struct kvm_vcpu_init init;
  51     struct kvm_one_reg idregs[] = {
  52         {
  53             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  54             | ENCODE_CP_REG(15, 0, 0, 0, 0, 0),
  55             .addr = (uintptr_t)&midr,
  56         },
  57         {
  58             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  59             | ENCODE_CP_REG(15, 0, 0, 1, 0, 0),
  60             .addr = (uintptr_t)&id_pfr0,
  61         },
  62         {
  63             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  64             | ENCODE_CP_REG(15, 0, 0, 2, 0, 0),
  65             .addr = (uintptr_t)&id_isar0,
  66         },
  67         {
  68             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  69             | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
  70             .addr = (uintptr_t)&mvfr1,
  71         },
  72     };
  73
  74     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
  75         return false;
  76     }
  77
  78     ahcc->target = init.target;
  79
  80     /* This is not strictly blessed by the device tree binding docs yet,
  81      * but in practice the kernel does not care about this string so
  82      * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
  83      */
  84     ahcc->dtb_compatible = "arm,arm-v7";
  85
  86     for (i = 0; i < ARRAY_SIZE(idregs); i++) {
  87         ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
  88         if (ret) {
  89             break;
  90         }
  91     }
  92
  93     kvm_arm_destroy_scratch_host_vcpu(fdarray);
  94
  95     if (ret) {
  96         return false;
  97     }
  98
  99     /* Now we've retrieved all the register information we can
 100      * set the feature bits based on the ID register fields.
 101      * We can assume any KVM supporting CPU is at least a v7
 102      * with VFPv3, LPAE and the generic timers; this in turn implies
 103      * most of the other feature bits, but a few must be tested.
 104      */
 105     set_feature(&features, ARM_FEATURE_V7);
 106     set_feature(&features, ARM_FEATURE_VFP3);
 107     set_feature(&features, ARM_FEATURE_LPAE);
 108     set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
 109
 110     switch (extract32(id_isar0, 24, 4)) {
 111     case 1:
 112         set_feature(&features, ARM_FEATURE_THUMB_DIV);
 113         break;
 114     case 2:
 115         set_feature(&features, ARM_FEATURE_ARM_DIV);
 116         set_feature(&features, ARM_FEATURE_THUMB_DIV);
 117         break;
 118     default:
 119         break;
 120     }
 121
 122     if (extract32(id_pfr0, 12, 4) == 1) {
 123         set_feature(&features, ARM_FEATURE_THUMB2EE);
 124     }
 125     if (extract32(mvfr1, 20, 4) == 1) {
 126         set_feature(&features, ARM_FEATURE_VFP_FP16);
 127     }
 128     if (extract32(mvfr1, 12, 4) == 1) {
 129         set_feature(&features, ARM_FEATURE_NEON);
 130     }
 131     if (extract32(mvfr1, 28, 4) == 1) {
 132         /* FMAC support implies VFPv4 */
 133         set_feature(&features, ARM_FEATURE_VFP4);
 134     }
 135
 136     ahcc->features = features;
 137
 138     return true;
 139 }
 140
 141 static bool reg_syncs_via_tuple_list(uint64_t regidx)
 142 {
 143     /* Return true if the regidx is a register we should synchronize
 144      * via the cpreg_tuples array (ie is not a core reg we sync by
 145      * hand in kvm_arch_get/put_registers())
 146      */
 147     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 148     case KVM_REG_ARM_CORE:
 149     case KVM_REG_ARM_VFP:
 150         return false;
 151     default:
 152         return true;
 153     }
 154 }
 155
 156 static int compare_u64(const void *a, const void *b)
 157 {
 158     if (*(uint64_t *)a > *(uint64_t *)b) {
 159         return 1;
 160     }
 161     if (*(uint64_t *)a < *(uint64_t *)b) {
 162         return -1;
 163     }
 164     return 0;
 165 }
 166
 167 int kvm_arch_init_vcpu(CPUState *cs)
 168 {
 169     struct kvm_vcpu_init init;
 170     int i, ret, arraylen;
 171     uint64_t v;
 172     struct kvm_one_reg r;
 173     struct kvm_reg_list rl;
 174     struct kvm_reg_list *rlp;
 175     ARMCPU *cpu = ARM_CPU(cs);
 176
 177     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
 178         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 179         return -EINVAL;
 180     }
 181
 182     init.target = cpu->kvm_target;
 183     memset(init.features, 0, sizeof(init.features));
 184     if (cpu->start_powered_off) {
 185         init.features[0] = 1 << KVM_ARM_VCPU_POWER_OFF;
 186     }
 187     ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
 188     if (ret) {
 189         return ret;
 190     }
 191     /* Query the kernel to make sure it supports 32 VFP
 192      * registers: QEMU's "cortex-a15" CPU is always a
 193      * VFP-D32 core. The simplest way to do this is just
 194      * to attempt to read register d31.
 195      */
 196     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
 197     r.addr = (uintptr_t)(&v);
 198     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 199     if (ret == -ENOENT) {
 200         return -EINVAL;
 201     }
 202
 203     /* Populate the cpreg list based on the kernel's idea
 204      * of what registers exist (and throw away the TCG-created list).
 205      */
 206     rl.n = 0;
 207     ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl);
 208     if (ret != -E2BIG) {
 209         return ret;
 210     }
 211     rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t));
 212     rlp->n = rl.n;
 213     ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp);
 214     if (ret) {
 215         goto out;
 216     }
 217     /* Sort the list we get back from the kernel, since cpreg_tuples
 218      * must be in strictly ascending order.
 219      */
 220     qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64);
 221
 222     for (i = 0, arraylen = 0; i < rlp->n; i++) {
 223         if (!reg_syncs_via_tuple_list(rlp->reg[i])) {
 224             continue;
 225         }
 226         switch (rlp->reg[i] & KVM_REG_SIZE_MASK) {
 227         case KVM_REG_SIZE_U32:
 228         case KVM_REG_SIZE_U64:
 229             break;
 230         default:
 231             fprintf(stderr, "Can't handle size of register in kernel list\n");
 232             ret = -EINVAL;
 233             goto out;
 234         }
 235
 236         arraylen++;
 237     }
 238
 239     cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
 240     cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
 241     cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
 242                                          arraylen);
 243     cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
 244                                         arraylen);
 245     cpu->cpreg_array_len = arraylen;
 246     cpu->cpreg_vmstate_array_len = arraylen;
 247
 248     for (i = 0, arraylen = 0; i < rlp->n; i++) {
 249         uint64_t regidx = rlp->reg[i];
 250         if (!reg_syncs_via_tuple_list(regidx)) {
 251             continue;
 252         }
 253         cpu->cpreg_indexes[arraylen] = regidx;
 254         arraylen++;
 255     }
 256     assert(cpu->cpreg_array_len == arraylen);
 257
 258     if (!write_kvmstate_to_list(cpu)) {
 259         /* Shouldn't happen unless kernel is inconsistent about
 260          * what registers exist.
 261          */
 262         fprintf(stderr, "Initial read of kernel register state failed\n");
 263         ret = -EINVAL;
 264         goto out;
 265     }
 266
 267     /* Save a copy of the initial register values so that we can
 268      * feed it back to the kernel on VCPU reset.
 269      */
 270     cpu->cpreg_reset_values = g_memdup(cpu->cpreg_values,
 271                                        cpu->cpreg_array_len *
 272                                        sizeof(cpu->cpreg_values[0]));
 273
 274 out:
 275     g_free(rlp);
 276     return ret;
 277 }
 278
 279 typedef struct Reg {
 280     uint64_t id;
 281     int offset;
 282 } Reg;
 283
 284 #define COREREG(KERNELNAME, QEMUFIELD)                       \
 285     {                                                        \
 286         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 287         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 288         offsetof(CPUARMState, QEMUFIELD)                     \
 289     }
 290
 291 #define VFPSYSREG(R)                                       \
 292     {                                                      \
 293         KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
 294         KVM_REG_ARM_VFP_##R,                               \
 295         offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R])      \
 296     }
 297
 298 /* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
 299 #define COREREG64(KERNELNAME, QEMUFIELD)                     \
 300     {                                                        \
 301         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 302         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 303         offsetoflow32(CPUARMState, QEMUFIELD)                \
 304     }
 305
 306 static const Reg regs[] = {
 307     /* R0_usr .. R14_usr */
 308     COREREG(usr_regs.uregs[0], regs[0]),
 309     COREREG(usr_regs.uregs[1], regs[1]),
 310     COREREG(usr_regs.uregs[2], regs[2]),
 311     COREREG(usr_regs.uregs[3], regs[3]),
 312     COREREG(usr_regs.uregs[4], regs[4]),
 313     COREREG(usr_regs.uregs[5], regs[5]),
 314     COREREG(usr_regs.uregs[6], regs[6]),
 315     COREREG(usr_regs.uregs[7], regs[7]),
 316     COREREG(usr_regs.uregs[8], usr_regs[0]),
 317     COREREG(usr_regs.uregs[9], usr_regs[1]),
 318     COREREG(usr_regs.uregs[10], usr_regs[2]),
 319     COREREG(usr_regs.uregs[11], usr_regs[3]),
 320     COREREG(usr_regs.uregs[12], usr_regs[4]),
 321     COREREG(usr_regs.uregs[13], banked_r13[0]),
 322     COREREG(usr_regs.uregs[14], banked_r14[0]),
 323     /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
 324     COREREG(svc_regs[0], banked_r13[1]),
 325     COREREG(svc_regs[1], banked_r14[1]),
 326     COREREG64(svc_regs[2], banked_spsr[1]),
 327     COREREG(abt_regs[0], banked_r13[2]),
 328     COREREG(abt_regs[1], banked_r14[2]),
 329     COREREG64(abt_regs[2], banked_spsr[2]),
 330     COREREG(und_regs[0], banked_r13[3]),
 331     COREREG(und_regs[1], banked_r14[3]),
 332     COREREG64(und_regs[2], banked_spsr[3]),
 333     COREREG(irq_regs[0], banked_r13[4]),
 334     COREREG(irq_regs[1], banked_r14[4]),
 335     COREREG64(irq_regs[2], banked_spsr[4]),
 336     /* R8_fiq .. R14_fiq and SPSR_fiq */
 337     COREREG(fiq_regs[0], fiq_regs[0]),
 338     COREREG(fiq_regs[1], fiq_regs[1]),
 339     COREREG(fiq_regs[2], fiq_regs[2]),
 340     COREREG(fiq_regs[3], fiq_regs[3]),
 341     COREREG(fiq_regs[4], fiq_regs[4]),
 342     COREREG(fiq_regs[5], banked_r13[5]),
 343     COREREG(fiq_regs[6], banked_r14[5]),
 344     COREREG64(fiq_regs[7], banked_spsr[5]),
 345     /* R15 */
 346     COREREG(usr_regs.uregs[15], regs[15]),
 347     /* VFP system registers */
 348     VFPSYSREG(FPSID),
 349     VFPSYSREG(MVFR1),
 350     VFPSYSREG(MVFR0),
 351     VFPSYSREG(FPEXC),
 352     VFPSYSREG(FPINST),
 353     VFPSYSREG(FPINST2),
 354 };
 355
 356 int kvm_arch_put_registers(CPUState *cs, int level)
 357 {
 358     ARMCPU *cpu = ARM_CPU(cs);
 359     CPUARMState *env = &cpu->env;
 360     struct kvm_one_reg r;
 361     int mode, bn;
 362     int ret, i;
 363     uint32_t cpsr, fpscr;
 364
 365     /* Make sure the banked regs are properly set */
 366     mode = env->uncached_cpsr & CPSR_M;
 367     bn = bank_number(mode);
 368     if (mode == ARM_CPU_MODE_FIQ) {
 369         memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
 370     } else {
 371         memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
 372     }
 373     env->banked_r13[bn] = env->regs[13];
 374     env->banked_r14[bn] = env->regs[14];
 375     env->banked_spsr[bn] = env->spsr;
 376
 377     /* Now we can safely copy stuff down to the kernel */
 378     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 379         r.id = regs[i].id;
 380         r.addr = (uintptr_t)(env) + regs[i].offset;
 381         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 382         if (ret) {
 383             return ret;
 384         }
 385     }
 386
 387     /* Special cases which aren't a single CPUARMState field */
 388     cpsr = cpsr_read(env);
 389     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 390         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 391     r.addr = (uintptr_t)(&cpsr);
 392     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 393     if (ret) {
 394         return ret;
 395     }
 396
 397     /* VFP registers */
 398     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 399     for (i = 0; i < 32; i++) {
 400         r.addr = (uintptr_t)(&env->vfp.regs[i]);
 401         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 402         if (ret) {
 403             return ret;
 404         }
 405         r.id++;
 406     }
 407
 408     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 409         KVM_REG_ARM_VFP_FPSCR;
 410     fpscr = vfp_get_fpscr(env);
 411     r.addr = (uintptr_t)&fpscr;
 412     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 413     if (ret) {
 414         return ret;
 415     }
 416
 417     /* Note that we do not call write_cpustate_to_list()
 418      * here, so we are only writing the tuple list back to
 419      * KVM. This is safe because nothing can change the
 420      * CPUARMState cp15 fields (in particular gdb accesses cannot)
 421      * and so there are no changes to sync. In fact syncing would
 422      * be wrong at this point: for a constant register where TCG and
 423      * KVM disagree about its value, the preceding write_list_to_cpustate()
 424      * would not have had any effect on the CPUARMState value (since the
 425      * register is read-only), and a write_cpustate_to_list() here would
 426      * then try to write the TCG value back into KVM -- this would either
 427      * fail or incorrectly change the value the guest sees.
 428      *
 429      * If we ever want to allow the user to modify cp15 registers via
 430      * the gdb stub, we would need to be more clever here (for instance
 431      * tracking the set of registers kvm_arch_get_registers() successfully
 432      * managed to update the CPUARMState with, and only allowing those
 433      * to be written back up into the kernel).
 434      */
 435     if (!write_list_to_kvmstate(cpu)) {
 436         return EINVAL;
 437     }
 438
 439     return ret;
 440 }
 441
 442 int kvm_arch_get_registers(CPUState *cs)
 443 {
 444     ARMCPU *cpu = ARM_CPU(cs);
 445     CPUARMState *env = &cpu->env;
 446     struct kvm_one_reg r;
 447     int mode, bn;
 448     int ret, i;
 449     uint32_t cpsr, fpscr;
 450
 451     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 452         r.id = regs[i].id;
 453         r.addr = (uintptr_t)(env) + regs[i].offset;
 454         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 455         if (ret) {
 456             return ret;
 457         }
 458     }
 459
 460     /* Special cases which aren't a single CPUARMState field */
 461     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 462         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 463     r.addr = (uintptr_t)(&cpsr);
 464     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 465     if (ret) {
 466         return ret;
 467     }
 468     cpsr_write(env, cpsr, 0xffffffff);
 469
 470     /* Make sure the current mode regs are properly set */
 471     mode = env->uncached_cpsr & CPSR_M;
 472     bn = bank_number(mode);
 473     if (mode == ARM_CPU_MODE_FIQ) {
 474         memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
 475     } else {
 476         memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
 477     }
 478     env->regs[13] = env->banked_r13[bn];
 479     env->regs[14] = env->banked_r14[bn];
 480     env->spsr = env->banked_spsr[bn];
 481
 482     /* VFP registers */
 483     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 484     for (i = 0; i < 32; i++) {
 485         r.addr = (uintptr_t)(&env->vfp.regs[i]);
 486         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 487         if (ret) {
 488             return ret;
 489         }
 490         r.id++;
 491     }
 492
 493     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 494         KVM_REG_ARM_VFP_FPSCR;
 495     r.addr = (uintptr_t)&fpscr;
 496     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 497     if (ret) {
 498         return ret;
 499     }
 500     vfp_set_fpscr(env, fpscr);
 501
 502     if (!write_kvmstate_to_list(cpu)) {
 503         return EINVAL;
 504     }
 505     /* Note that it's OK to have registers which aren't in CPUState,
 506      * so we can ignore a failure return here.
 507      */
 508     write_list_to_cpustate(cpu);
 509
 510     return 0;
 511 }
 512
 513 void kvm_arm_reset_vcpu(ARMCPU *cpu)
 514 {
 515     /* Feed the kernel back its initial register state */
 516     memmove(cpu->cpreg_values, cpu->cpreg_reset_values,
 517             cpu->cpreg_array_len * sizeof(cpu->cpreg_values[0]));
 518
 519     if (!write_list_to_kvmstate(cpu)) {
 520         abort();
 521     }
 522 }