2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "sysemu/sysemu.h"
29 #include "hw/fw-path-provider.h"
32 #include "sysemu/blockdev.h"
33 #include "sysemu/cpus.h"
34 #include "sysemu/kvm.h"
36 #include "mmu-hash64.h"
38 #include "hw/boards.h"
39 #include "hw/ppc/ppc.h"
40 #include "hw/loader.h"
42 #include "hw/ppc/spapr.h"
43 #include "hw/ppc/spapr_vio.h"
44 #include "hw/pci-host/spapr.h"
45 #include "hw/ppc/xics.h"
46 #include "hw/pci/msi.h"
48 #include "hw/pci/pci.h"
49 #include "hw/scsi/scsi.h"
50 #include "hw/virtio/virtio-scsi.h"
52 #include "exec/address-spaces.h"
54 #include "qemu/config-file.h"
55 #include "qemu/error-report.h"
59 /* SLOF memory layout:
61 * SLOF raw image loaded at 0, copies its romfs right below the flat
62 * device-tree, then position SLOF itself 31M below that
64 * So we set FW_OVERHEAD to 40MB which should account for all of that
67 * We load our kernel at 4M, leaving space for SLOF initial image
69 #define FDT_MAX_SIZE 0x40000
70 #define RTAS_MAX_SIZE 0x10000
71 #define FW_MAX_SIZE 0x400000
72 #define FW_FILE_NAME "slof.bin"
73 #define FW_OVERHEAD 0x2800000
74 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
76 #define MIN_RMA_SLOF 128UL
78 #define TIMEBASE_FREQ 512000000ULL
81 #define XICS_IRQS 1024
83 #define PHANDLE_XICP 0x00001111
85 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
87 #define TYPE_SPAPR_MACHINE "spapr-machine"
89 sPAPREnvironment
*spapr
;
91 int spapr_allocate_irq(int hint
, bool lsi
)
97 if (hint
>= spapr
->next_irq
) {
98 spapr
->next_irq
= hint
+ 1;
100 /* FIXME: we should probably check for collisions somehow */
102 irq
= spapr
->next_irq
++;
105 /* Configure irq type */
106 if (!xics_get_qirq(spapr
->icp
, irq
)) {
110 xics_set_irq_type(spapr
->icp
, irq
, lsi
);
116 * Allocate block of consequtive IRQs, returns a number of the first.
117 * If msi==true, aligns the first IRQ number to num.
119 int spapr_allocate_irq_block(int num
, bool lsi
, bool msi
)
125 * MSIMesage::data is used for storing VIRQ so
126 * it has to be aligned to num to support multiple
127 * MSI vectors. MSI-X is not affected by this.
128 * The hint is used for the first IRQ, the rest should
129 * be allocated continuously.
132 assert((num
== 1) || (num
== 2) || (num
== 4) ||
133 (num
== 8) || (num
== 16) || (num
== 32));
134 hint
= (spapr
->next_irq
+ num
- 1) & ~(num
- 1);
137 for (i
= 0; i
< num
; ++i
) {
140 irq
= spapr_allocate_irq(hint
, lsi
);
150 /* If the above doesn't create a consecutive block then that's
152 assert(irq
== (first
+ i
));
158 static XICSState
*try_create_xics(const char *type
, int nr_servers
,
163 dev
= qdev_create(NULL
, type
);
164 qdev_prop_set_uint32(dev
, "nr_servers", nr_servers
);
165 qdev_prop_set_uint32(dev
, "nr_irqs", nr_irqs
);
166 if (qdev_init(dev
) < 0) {
170 return XICS_COMMON(dev
);
173 static XICSState
*xics_system_init(int nr_servers
, int nr_irqs
)
175 XICSState
*icp
= NULL
;
178 QemuOpts
*machine_opts
= qemu_get_machine_opts();
179 bool irqchip_allowed
= qemu_opt_get_bool(machine_opts
,
180 "kernel_irqchip", true);
181 bool irqchip_required
= qemu_opt_get_bool(machine_opts
,
182 "kernel_irqchip", false);
183 if (irqchip_allowed
) {
184 icp
= try_create_xics(TYPE_KVM_XICS
, nr_servers
, nr_irqs
);
187 if (irqchip_required
&& !icp
) {
188 perror("Failed to create in-kernel XICS\n");
194 icp
= try_create_xics(TYPE_XICS
, nr_servers
, nr_irqs
);
198 perror("Failed to create XICS\n");
205 static int spapr_fixup_cpu_dt(void *fdt
, sPAPREnvironment
*spapr
)
210 int smt
= kvmppc_smt_threads();
211 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
214 DeviceClass
*dc
= DEVICE_GET_CLASS(cpu
);
215 int index
= ppc_get_vcpu_dt_id(POWERPC_CPU(cpu
));
216 uint32_t associativity
[] = {cpu_to_be32(0x5),
220 cpu_to_be32(cpu
->numa_node
),
223 if ((index
% smt
) != 0) {
227 snprintf(cpu_model
, 32, "/cpus/%s@%x", dc
->fw_name
,
230 offset
= fdt_path_offset(fdt
, cpu_model
);
235 if (nb_numa_nodes
> 1) {
236 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
237 sizeof(associativity
));
243 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
244 pft_size_prop
, sizeof(pft_size_prop
));
253 static size_t create_page_sizes_prop(CPUPPCState
*env
, uint32_t *prop
,
256 size_t maxcells
= maxsize
/ sizeof(uint32_t);
260 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
261 struct ppc_one_seg_page_size
*sps
= &env
->sps
.sps
[i
];
263 if (!sps
->page_shift
) {
266 for (count
= 0; count
< PPC_PAGE_SIZES_MAX_SZ
; count
++) {
267 if (sps
->enc
[count
].page_shift
== 0) {
271 if ((p
- prop
) >= (maxcells
- 3 - count
* 2)) {
274 *(p
++) = cpu_to_be32(sps
->page_shift
);
275 *(p
++) = cpu_to_be32(sps
->slb_enc
);
276 *(p
++) = cpu_to_be32(count
);
277 for (j
= 0; j
< count
; j
++) {
278 *(p
++) = cpu_to_be32(sps
->enc
[j
].page_shift
);
279 *(p
++) = cpu_to_be32(sps
->enc
[j
].pte_enc
);
283 return (p
- prop
) * sizeof(uint32_t);
290 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
291 #exp, fdt_strerror(ret)); \
297 static void *spapr_create_fdt_skel(hwaddr initrd_base
,
301 const char *boot_device
,
302 const char *kernel_cmdline
,
307 uint32_t start_prop
= cpu_to_be32(initrd_base
);
308 uint32_t end_prop
= cpu_to_be32(initrd_base
+ initrd_size
);
309 char hypertas_prop
[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
310 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk\0hcall-set-mode";
311 char qemu_hypertas_prop
[] = "hcall-memop1";
312 uint32_t refpoints
[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
313 uint32_t interrupt_server_ranges_prop
[] = {0, cpu_to_be32(smp_cpus
)};
314 int i
, smt
= kvmppc_smt_threads();
315 unsigned char vec5
[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
317 fdt
= g_malloc0(FDT_MAX_SIZE
);
318 _FDT((fdt_create(fdt
, FDT_MAX_SIZE
)));
321 _FDT((fdt_add_reservemap_entry(fdt
, KERNEL_LOAD_ADDR
, kernel_size
)));
324 _FDT((fdt_add_reservemap_entry(fdt
, initrd_base
, initrd_size
)));
326 _FDT((fdt_finish_reservemap(fdt
)));
329 _FDT((fdt_begin_node(fdt
, "")));
330 _FDT((fdt_property_string(fdt
, "device_type", "chrp")));
331 _FDT((fdt_property_string(fdt
, "model", "IBM pSeries (emulated by qemu)")));
332 _FDT((fdt_property_string(fdt
, "compatible", "qemu,pseries")));
334 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x2)));
335 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x2)));
338 _FDT((fdt_begin_node(fdt
, "chosen")));
340 /* Set Form1_affinity */
341 _FDT((fdt_property(fdt
, "ibm,architecture-vec-5", vec5
, sizeof(vec5
))));
343 _FDT((fdt_property_string(fdt
, "bootargs", kernel_cmdline
)));
344 _FDT((fdt_property(fdt
, "linux,initrd-start",
345 &start_prop
, sizeof(start_prop
))));
346 _FDT((fdt_property(fdt
, "linux,initrd-end",
347 &end_prop
, sizeof(end_prop
))));
349 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
350 cpu_to_be64(kernel_size
) };
352 _FDT((fdt_property(fdt
, "qemu,boot-kernel", &kprop
, sizeof(kprop
))));
354 _FDT((fdt_property(fdt
, "qemu,boot-kernel-le", NULL
, 0)));
358 _FDT((fdt_property_string(fdt
, "qemu,boot-device", boot_device
)));
360 _FDT((fdt_property_cell(fdt
, "qemu,graphic-width", graphic_width
)));
361 _FDT((fdt_property_cell(fdt
, "qemu,graphic-height", graphic_height
)));
362 _FDT((fdt_property_cell(fdt
, "qemu,graphic-depth", graphic_depth
)));
364 _FDT((fdt_end_node(fdt
)));
367 _FDT((fdt_begin_node(fdt
, "cpus")));
369 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
370 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
373 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
374 CPUPPCState
*env
= &cpu
->env
;
375 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
376 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
377 int index
= ppc_get_vcpu_dt_id(cpu
);
378 uint32_t servers_prop
[smp_threads
];
379 uint32_t gservers_prop
[smp_threads
* 2];
381 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
382 0xffffffff, 0xffffffff};
383 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ
;
384 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
385 uint32_t page_sizes_prop
[64];
386 size_t page_sizes_prop_size
;
388 if ((index
% smt
) != 0) {
392 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
394 _FDT((fdt_begin_node(fdt
, nodename
)));
398 _FDT((fdt_property_cell(fdt
, "reg", index
)));
399 _FDT((fdt_property_string(fdt
, "device_type", "cpu")));
401 _FDT((fdt_property_cell(fdt
, "cpu-version", env
->spr
[SPR_PVR
])));
402 _FDT((fdt_property_cell(fdt
, "d-cache-block-size",
403 env
->dcache_line_size
)));
404 _FDT((fdt_property_cell(fdt
, "d-cache-line-size",
405 env
->dcache_line_size
)));
406 _FDT((fdt_property_cell(fdt
, "i-cache-block-size",
407 env
->icache_line_size
)));
408 _FDT((fdt_property_cell(fdt
, "i-cache-line-size",
409 env
->icache_line_size
)));
411 if (pcc
->l1_dcache_size
) {
412 _FDT((fdt_property_cell(fdt
, "d-cache-size", pcc
->l1_dcache_size
)));
414 fprintf(stderr
, "Warning: Unknown L1 dcache size for cpu\n");
416 if (pcc
->l1_icache_size
) {
417 _FDT((fdt_property_cell(fdt
, "i-cache-size", pcc
->l1_icache_size
)));
419 fprintf(stderr
, "Warning: Unknown L1 icache size for cpu\n");
422 _FDT((fdt_property_cell(fdt
, "timebase-frequency", tbfreq
)));
423 _FDT((fdt_property_cell(fdt
, "clock-frequency", cpufreq
)));
424 _FDT((fdt_property_cell(fdt
, "ibm,slb-size", env
->slb_nr
)));
425 _FDT((fdt_property_string(fdt
, "status", "okay")));
426 _FDT((fdt_property(fdt
, "64-bit", NULL
, 0)));
428 /* Build interrupt servers and gservers properties */
429 for (i
= 0; i
< smp_threads
; i
++) {
430 servers_prop
[i
] = cpu_to_be32(index
+ i
);
431 /* Hack, direct the group queues back to cpu 0 */
432 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
433 gservers_prop
[i
*2 + 1] = 0;
435 _FDT((fdt_property(fdt
, "ibm,ppc-interrupt-server#s",
436 servers_prop
, sizeof(servers_prop
))));
437 _FDT((fdt_property(fdt
, "ibm,ppc-interrupt-gserver#s",
438 gservers_prop
, sizeof(gservers_prop
))));
440 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
441 _FDT((fdt_property(fdt
, "ibm,purr", NULL
, 0)));
444 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
445 _FDT((fdt_property(fdt
, "ibm,processor-segment-sizes",
446 segs
, sizeof(segs
))));
449 /* Advertise VMX/VSX (vector extensions) if available
450 * 0 / no property == no vector extensions
451 * 1 == VMX / Altivec available
452 * 2 == VSX available */
453 if (env
->insns_flags
& PPC_ALTIVEC
) {
454 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
456 _FDT((fdt_property_cell(fdt
, "ibm,vmx", vmx
)));
459 /* Advertise DFP (Decimal Floating Point) if available
460 * 0 / no property == no DFP
461 * 1 == DFP available */
462 if (env
->insns_flags2
& PPC2_DFP
) {
463 _FDT((fdt_property_cell(fdt
, "ibm,dfp", 1)));
466 page_sizes_prop_size
= create_page_sizes_prop(env
, page_sizes_prop
,
467 sizeof(page_sizes_prop
));
468 if (page_sizes_prop_size
) {
469 _FDT((fdt_property(fdt
, "ibm,segment-page-sizes",
470 page_sizes_prop
, page_sizes_prop_size
)));
473 _FDT((fdt_end_node(fdt
)));
476 _FDT((fdt_end_node(fdt
)));
479 _FDT((fdt_begin_node(fdt
, "rtas")));
481 _FDT((fdt_property(fdt
, "ibm,hypertas-functions", hypertas_prop
,
482 sizeof(hypertas_prop
))));
483 _FDT((fdt_property(fdt
, "qemu,hypertas-functions", qemu_hypertas_prop
,
484 sizeof(qemu_hypertas_prop
))));
486 _FDT((fdt_property(fdt
, "ibm,associativity-reference-points",
487 refpoints
, sizeof(refpoints
))));
489 _FDT((fdt_property_cell(fdt
, "rtas-error-log-max", RTAS_ERROR_LOG_MAX
)));
491 _FDT((fdt_end_node(fdt
)));
493 /* interrupt controller */
494 _FDT((fdt_begin_node(fdt
, "interrupt-controller")));
496 _FDT((fdt_property_string(fdt
, "device_type",
497 "PowerPC-External-Interrupt-Presentation")));
498 _FDT((fdt_property_string(fdt
, "compatible", "IBM,ppc-xicp")));
499 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
500 _FDT((fdt_property(fdt
, "ibm,interrupt-server-ranges",
501 interrupt_server_ranges_prop
,
502 sizeof(interrupt_server_ranges_prop
))));
503 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 2)));
504 _FDT((fdt_property_cell(fdt
, "linux,phandle", PHANDLE_XICP
)));
505 _FDT((fdt_property_cell(fdt
, "phandle", PHANDLE_XICP
)));
507 _FDT((fdt_end_node(fdt
)));
510 _FDT((fdt_begin_node(fdt
, "vdevice")));
512 _FDT((fdt_property_string(fdt
, "device_type", "vdevice")));
513 _FDT((fdt_property_string(fdt
, "compatible", "IBM,vdevice")));
514 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
515 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
516 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 0x2)));
517 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
519 _FDT((fdt_end_node(fdt
)));
522 spapr_events_fdt_skel(fdt
, epow_irq
);
524 _FDT((fdt_end_node(fdt
))); /* close root node */
525 _FDT((fdt_finish(fdt
)));
530 static int spapr_populate_memory(sPAPREnvironment
*spapr
, void *fdt
)
532 uint32_t associativity
[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
533 cpu_to_be32(0x0), cpu_to_be32(0x0),
536 hwaddr node0_size
, mem_start
, node_size
;
537 uint64_t mem_reg_property
[2];
541 if (nb_numa_nodes
> 1 && node_mem
[0] < ram_size
) {
542 node0_size
= node_mem
[0];
544 node0_size
= ram_size
;
548 mem_reg_property
[0] = 0;
549 mem_reg_property
[1] = cpu_to_be64(spapr
->rma_size
);
550 off
= fdt_add_subnode(fdt
, 0, "memory@0");
552 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
553 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
554 sizeof(mem_reg_property
))));
555 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
556 sizeof(associativity
))));
559 if (node0_size
> spapr
->rma_size
) {
560 mem_reg_property
[0] = cpu_to_be64(spapr
->rma_size
);
561 mem_reg_property
[1] = cpu_to_be64(node0_size
- spapr
->rma_size
);
563 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, spapr
->rma_size
);
564 off
= fdt_add_subnode(fdt
, 0, mem_name
);
566 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
567 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
568 sizeof(mem_reg_property
))));
569 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
570 sizeof(associativity
))));
573 /* RAM: Node 1 and beyond */
574 mem_start
= node0_size
;
575 for (i
= 1; i
< nb_numa_nodes
; i
++) {
576 mem_reg_property
[0] = cpu_to_be64(mem_start
);
577 if (mem_start
>= ram_size
) {
580 node_size
= node_mem
[i
];
581 if (node_size
> ram_size
- mem_start
) {
582 node_size
= ram_size
- mem_start
;
585 mem_reg_property
[1] = cpu_to_be64(node_size
);
586 associativity
[3] = associativity
[4] = cpu_to_be32(i
);
587 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, mem_start
);
588 off
= fdt_add_subnode(fdt
, 0, mem_name
);
590 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
591 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
592 sizeof(mem_reg_property
))));
593 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
594 sizeof(associativity
))));
595 mem_start
+= node_size
;
601 static void spapr_finalize_fdt(sPAPREnvironment
*spapr
,
612 fdt
= g_malloc(FDT_MAX_SIZE
);
614 /* open out the base tree into a temp buffer for the final tweaks */
615 _FDT((fdt_open_into(spapr
->fdt_skel
, fdt
, FDT_MAX_SIZE
)));
617 ret
= spapr_populate_memory(spapr
, fdt
);
619 fprintf(stderr
, "couldn't setup memory nodes in fdt\n");
623 ret
= spapr_populate_vdevice(spapr
->vio_bus
, fdt
);
625 fprintf(stderr
, "couldn't setup vio devices in fdt\n");
629 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
630 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
);
634 fprintf(stderr
, "couldn't setup PCI devices in fdt\n");
639 ret
= spapr_rtas_device_tree_setup(fdt
, rtas_addr
, rtas_size
);
641 fprintf(stderr
, "Couldn't set up RTAS device tree properties\n");
644 /* Advertise NUMA via ibm,associativity */
645 ret
= spapr_fixup_cpu_dt(fdt
, spapr
);
647 fprintf(stderr
, "Couldn't finalize CPU device tree properties\n");
650 bootlist
= get_boot_devices_list(&cb
, true);
651 if (cb
&& bootlist
) {
652 int offset
= fdt_path_offset(fdt
, "/chosen");
656 for (i
= 0; i
< cb
; i
++) {
657 if (bootlist
[i
] == '\n') {
662 ret
= fdt_setprop_string(fdt
, offset
, "qemu,boot-list", bootlist
);
665 if (!spapr
->has_graphics
) {
666 spapr_populate_chosen_stdout(fdt
, spapr
->vio_bus
);
669 _FDT((fdt_pack(fdt
)));
671 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
672 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
673 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
677 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
682 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
684 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
687 static void emulate_spapr_hypercall(PowerPCCPU
*cpu
)
689 CPUPPCState
*env
= &cpu
->env
;
692 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
693 env
->gpr
[3] = H_PRIVILEGE
;
695 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
699 static void spapr_reset_htab(sPAPREnvironment
*spapr
)
703 /* allocate hash page table. For now we always make this 16mb,
704 * later we should probably make it scale to the size of guest
707 shift
= kvmppc_reset_htab(spapr
->htab_shift
);
710 /* Kernel handles htab, we don't need to allocate one */
711 spapr
->htab_shift
= shift
;
712 kvmppc_kern_htab
= true;
715 /* Allocate an htab if we don't yet have one */
716 spapr
->htab
= qemu_memalign(HTAB_SIZE(spapr
), HTAB_SIZE(spapr
));
720 memset(spapr
->htab
, 0, HTAB_SIZE(spapr
));
723 /* Update the RMA size if necessary */
724 if (spapr
->vrma_adjust
) {
725 hwaddr node0_size
= (nb_numa_nodes
> 1) ? node_mem
[0] : ram_size
;
726 spapr
->rma_size
= kvmppc_rma_size(node0_size
, spapr
->htab_shift
);
730 static void ppc_spapr_reset(void)
732 PowerPCCPU
*first_ppc_cpu
;
734 /* Reset the hash table & recalc the RMA */
735 spapr_reset_htab(spapr
);
737 qemu_devices_reset();
740 spapr_finalize_fdt(spapr
, spapr
->fdt_addr
, spapr
->rtas_addr
,
743 /* Set up the entry state */
744 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
745 first_ppc_cpu
->env
.gpr
[3] = spapr
->fdt_addr
;
746 first_ppc_cpu
->env
.gpr
[5] = 0;
747 first_cpu
->halted
= 0;
748 first_ppc_cpu
->env
.nip
= spapr
->entry_point
;
752 static void spapr_cpu_reset(void *opaque
)
754 PowerPCCPU
*cpu
= opaque
;
755 CPUState
*cs
= CPU(cpu
);
756 CPUPPCState
*env
= &cpu
->env
;
760 /* All CPUs start halted. CPU0 is unhalted from the machine level
761 * reset code and the rest are explicitly started up by the guest
762 * using an RTAS call */
765 env
->spr
[SPR_HIOR
] = 0;
767 env
->external_htab
= (uint8_t *)spapr
->htab
;
768 if (kvm_enabled() && !env
->external_htab
) {
770 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
771 * functions do the right thing.
773 env
->external_htab
= (void *)1;
777 * htab_mask is the mask used to normalize hash value to PTEG index.
778 * htab_shift is log2 of hash table size.
779 * We have 8 hpte per group, and each hpte is 16 bytes.
780 * ie have 128 bytes per hpte entry.
782 env
->htab_mask
= (1ULL << ((spapr
)->htab_shift
- 7)) - 1;
783 env
->spr
[SPR_SDR1
] = (target_ulong
)(uintptr_t)spapr
->htab
|
784 (spapr
->htab_shift
- 18);
787 static void spapr_create_nvram(sPAPREnvironment
*spapr
)
789 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
790 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
793 qdev_prop_set_drive_nofail(dev
, "drive", dinfo
->bdrv
);
796 qdev_init_nofail(dev
);
798 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
801 /* Returns whether we want to use VGA or not */
802 static int spapr_vga_init(PCIBus
*pci_bus
)
804 switch (vga_interface_type
) {
810 return pci_vga_init(pci_bus
) != NULL
;
812 fprintf(stderr
, "This vga model is not supported,"
813 "currently it only supports -vga std\n");
818 static const VMStateDescription vmstate_spapr
= {
821 .minimum_version_id
= 1,
822 .minimum_version_id_old
= 1,
823 .fields
= (VMStateField
[]) {
824 VMSTATE_UINT32(next_irq
, sPAPREnvironment
),
827 VMSTATE_UINT64(rtc_offset
, sPAPREnvironment
),
829 VMSTATE_END_OF_LIST()
833 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
834 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
835 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
836 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
838 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
840 sPAPREnvironment
*spapr
= opaque
;
842 /* "Iteration" header */
843 qemu_put_be32(f
, spapr
->htab_shift
);
846 spapr
->htab_save_index
= 0;
847 spapr
->htab_first_pass
= true;
849 assert(kvm_enabled());
851 spapr
->htab_fd
= kvmppc_get_htab_fd(false);
852 if (spapr
->htab_fd
< 0) {
853 fprintf(stderr
, "Unable to open fd for reading hash table from KVM: %s\n",
863 static void htab_save_first_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
866 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
867 int index
= spapr
->htab_save_index
;
868 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
870 assert(spapr
->htab_first_pass
);
875 /* Consume invalid HPTEs */
876 while ((index
< htabslots
)
877 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
879 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
882 /* Consume valid HPTEs */
884 while ((index
< htabslots
)
885 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
887 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
890 if (index
> chunkstart
) {
891 int n_valid
= index
- chunkstart
;
893 qemu_put_be32(f
, chunkstart
);
894 qemu_put_be16(f
, n_valid
);
896 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
897 HASH_PTE_SIZE_64
* n_valid
);
899 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
903 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
905 if (index
>= htabslots
) {
906 assert(index
== htabslots
);
908 spapr
->htab_first_pass
= false;
910 spapr
->htab_save_index
= index
;
913 static int htab_save_later_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
916 bool final
= max_ns
< 0;
917 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
918 int examined
= 0, sent
= 0;
919 int index
= spapr
->htab_save_index
;
920 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
922 assert(!spapr
->htab_first_pass
);
925 int chunkstart
, invalidstart
;
927 /* Consume non-dirty HPTEs */
928 while ((index
< htabslots
)
929 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
935 /* Consume valid dirty HPTEs */
936 while ((index
< htabslots
)
937 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
938 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
939 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
944 invalidstart
= index
;
945 /* Consume invalid dirty HPTEs */
946 while ((index
< htabslots
)
947 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
948 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
949 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
954 if (index
> chunkstart
) {
955 int n_valid
= invalidstart
- chunkstart
;
956 int n_invalid
= index
- invalidstart
;
958 qemu_put_be32(f
, chunkstart
);
959 qemu_put_be16(f
, n_valid
);
960 qemu_put_be16(f
, n_invalid
);
961 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
962 HASH_PTE_SIZE_64
* n_valid
);
963 sent
+= index
- chunkstart
;
965 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
970 if (examined
>= htabslots
) {
974 if (index
>= htabslots
) {
975 assert(index
== htabslots
);
978 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
980 if (index
>= htabslots
) {
981 assert(index
== htabslots
);
985 spapr
->htab_save_index
= index
;
987 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
990 #define MAX_ITERATION_NS 5000000 /* 5 ms */
991 #define MAX_KVM_BUF_SIZE 2048
993 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
995 sPAPREnvironment
*spapr
= opaque
;
998 /* Iteration header */
1002 assert(kvm_enabled());
1004 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
,
1005 MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
1009 } else if (spapr
->htab_first_pass
) {
1010 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
1012 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
1016 qemu_put_be32(f
, 0);
1017 qemu_put_be16(f
, 0);
1018 qemu_put_be16(f
, 0);
1023 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
1025 sPAPREnvironment
*spapr
= opaque
;
1027 /* Iteration header */
1028 qemu_put_be32(f
, 0);
1033 assert(kvm_enabled());
1035 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
, MAX_KVM_BUF_SIZE
, -1);
1039 close(spapr
->htab_fd
);
1040 spapr
->htab_fd
= -1;
1042 htab_save_later_pass(f
, spapr
, -1);
1046 qemu_put_be32(f
, 0);
1047 qemu_put_be16(f
, 0);
1048 qemu_put_be16(f
, 0);
1053 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
1055 sPAPREnvironment
*spapr
= opaque
;
1056 uint32_t section_hdr
;
1059 if (version_id
< 1 || version_id
> 1) {
1060 fprintf(stderr
, "htab_load() bad version\n");
1064 section_hdr
= qemu_get_be32(f
);
1067 /* First section, just the hash shift */
1068 if (spapr
->htab_shift
!= section_hdr
) {
1075 assert(kvm_enabled());
1077 fd
= kvmppc_get_htab_fd(true);
1079 fprintf(stderr
, "Unable to open fd to restore KVM hash table: %s\n",
1086 uint16_t n_valid
, n_invalid
;
1088 index
= qemu_get_be32(f
);
1089 n_valid
= qemu_get_be16(f
);
1090 n_invalid
= qemu_get_be16(f
);
1092 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
1097 if ((index
+ n_valid
+ n_invalid
) >
1098 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
1099 /* Bad index in stream */
1100 fprintf(stderr
, "htab_load() bad index %d (%hd+%hd entries) "
1101 "in htab stream (htab_shift=%d)\n", index
, n_valid
, n_invalid
,
1108 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
1109 HASH_PTE_SIZE_64
* n_valid
);
1112 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
1113 HASH_PTE_SIZE_64
* n_invalid
);
1120 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
1135 static SaveVMHandlers savevm_htab_handlers
= {
1136 .save_live_setup
= htab_save_setup
,
1137 .save_live_iterate
= htab_save_iterate
,
1138 .save_live_complete
= htab_save_complete
,
1139 .load_state
= htab_load
,
1142 /* pSeries LPAR / sPAPR hardware init */
1143 static void ppc_spapr_init(QEMUMachineInitArgs
*args
)
1145 ram_addr_t ram_size
= args
->ram_size
;
1146 const char *cpu_model
= args
->cpu_model
;
1147 const char *kernel_filename
= args
->kernel_filename
;
1148 const char *kernel_cmdline
= args
->kernel_cmdline
;
1149 const char *initrd_filename
= args
->initrd_filename
;
1150 const char *boot_device
= args
->boot_order
;
1155 MemoryRegion
*sysmem
= get_system_memory();
1156 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1157 hwaddr rma_alloc_size
;
1158 hwaddr node0_size
= (nb_numa_nodes
> 1) ? node_mem
[0] : ram_size
;
1159 uint32_t initrd_base
= 0;
1160 long kernel_size
= 0, initrd_size
= 0;
1161 long load_limit
, rtas_limit
, fw_size
;
1162 bool kernel_le
= false;
1165 msi_supported
= true;
1167 spapr
= g_malloc0(sizeof(*spapr
));
1168 QLIST_INIT(&spapr
->phbs
);
1170 cpu_ppc_hypercall
= emulate_spapr_hypercall
;
1172 /* Allocate RMA if necessary */
1173 rma_alloc_size
= kvmppc_alloc_rma("ppc_spapr.rma", sysmem
);
1175 if (rma_alloc_size
== -1) {
1176 hw_error("qemu: Unable to create RMA\n");
1180 if (rma_alloc_size
&& (rma_alloc_size
< node0_size
)) {
1181 spapr
->rma_size
= rma_alloc_size
;
1183 spapr
->rma_size
= node0_size
;
1185 /* With KVM, we don't actually know whether KVM supports an
1186 * unbounded RMA (PR KVM) or is limited by the hash table size
1187 * (HV KVM using VRMA), so we always assume the latter
1189 * In that case, we also limit the initial allocations for RTAS
1190 * etc... to 256M since we have no way to know what the VRMA size
1191 * is going to be as it depends on the size of the hash table
1192 * isn't determined yet.
1194 if (kvm_enabled()) {
1195 spapr
->vrma_adjust
= 1;
1196 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
1200 if (spapr
->rma_size
> node0_size
) {
1201 fprintf(stderr
, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")\n",
1206 /* We place the device tree and RTAS just below either the top of the RMA,
1207 * or just below 2GB, whichever is lowere, so that it can be
1208 * processed with 32-bit real mode code if necessary */
1209 rtas_limit
= MIN(spapr
->rma_size
, 0x80000000);
1210 spapr
->rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1211 spapr
->fdt_addr
= spapr
->rtas_addr
- FDT_MAX_SIZE
;
1212 load_limit
= spapr
->fdt_addr
- FW_OVERHEAD
;
1214 /* We aim for a hash table of size 1/128 the size of RAM. The
1215 * normal rule of thumb is 1/64 the size of RAM, but that's much
1216 * more than needed for the Linux guests we support. */
1217 spapr
->htab_shift
= 18; /* Minimum architected size */
1218 while (spapr
->htab_shift
<= 46) {
1219 if ((1ULL << (spapr
->htab_shift
+ 7)) >= ram_size
) {
1222 spapr
->htab_shift
++;
1225 /* Set up Interrupt Controller before we create the VCPUs */
1226 spapr
->icp
= xics_system_init(smp_cpus
* kvmppc_smt_threads() / smp_threads
,
1228 spapr
->next_irq
= XICS_IRQ_BASE
;
1231 if (cpu_model
== NULL
) {
1232 cpu_model
= kvm_enabled() ? "host" : "POWER7";
1234 for (i
= 0; i
< smp_cpus
; i
++) {
1235 cpu
= cpu_ppc_init(cpu_model
);
1237 fprintf(stderr
, "Unable to find PowerPC CPU definition\n");
1242 /* Set time-base frequency to 512 MHz */
1243 cpu_ppc_tb_init(env
, TIMEBASE_FREQ
);
1245 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1246 * MSR[IP] should never be set.
1248 env
->msr_mask
&= ~(1 << 6);
1250 /* Tell KVM that we're in PAPR mode */
1251 if (kvm_enabled()) {
1252 kvmppc_set_papr(cpu
);
1255 xics_cpu_setup(spapr
->icp
, cpu
);
1257 qemu_register_reset(spapr_cpu_reset
, cpu
);
1261 spapr
->ram_limit
= ram_size
;
1262 if (spapr
->ram_limit
> rma_alloc_size
) {
1263 ram_addr_t nonrma_base
= rma_alloc_size
;
1264 ram_addr_t nonrma_size
= spapr
->ram_limit
- rma_alloc_size
;
1266 memory_region_init_ram(ram
, NULL
, "ppc_spapr.ram", nonrma_size
);
1267 vmstate_register_ram_global(ram
);
1268 memory_region_add_subregion(sysmem
, nonrma_base
, ram
);
1271 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
1272 spapr
->rtas_size
= load_image_targphys(filename
, spapr
->rtas_addr
,
1273 rtas_limit
- spapr
->rtas_addr
);
1274 if (spapr
->rtas_size
< 0) {
1275 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1278 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
1279 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
1280 spapr
->rtas_size
, RTAS_MAX_SIZE
);
1285 /* Set up EPOW events infrastructure */
1286 spapr_events_init(spapr
);
1288 /* Set up VIO bus */
1289 spapr
->vio_bus
= spapr_vio_bus_init();
1291 for (i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1292 if (serial_hds
[i
]) {
1293 spapr_vty_create(spapr
->vio_bus
, serial_hds
[i
]);
1297 /* We always have at least the nvram device on VIO */
1298 spapr_create_nvram(spapr
);
1301 spapr_pci_msi_init(spapr
, SPAPR_PCI_MSI_WINDOW
);
1302 spapr_pci_rtas_init();
1304 phb
= spapr_create_phb(spapr
, 0);
1306 for (i
= 0; i
< nb_nics
; i
++) {
1307 NICInfo
*nd
= &nd_table
[i
];
1310 nd
->model
= g_strdup("ibmveth");
1313 if (strcmp(nd
->model
, "ibmveth") == 0) {
1314 spapr_vlan_create(spapr
->vio_bus
, nd
);
1316 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
1320 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
1321 spapr_vscsi_create(spapr
->vio_bus
);
1325 if (spapr_vga_init(phb
->bus
)) {
1326 spapr
->has_graphics
= true;
1329 if (usb_enabled(spapr
->has_graphics
)) {
1330 pci_create_simple(phb
->bus
, -1, "pci-ohci");
1331 if (spapr
->has_graphics
) {
1332 usbdevice_create("keyboard");
1333 usbdevice_create("mouse");
1337 if (spapr
->rma_size
< (MIN_RMA_SLOF
<< 20)) {
1338 fprintf(stderr
, "qemu: pSeries SLOF firmware requires >= "
1339 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF
);
1343 if (kernel_filename
) {
1344 uint64_t lowaddr
= 0;
1346 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
1347 NULL
, &lowaddr
, NULL
, 1, ELF_MACHINE
, 0);
1348 if (kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
1349 kernel_size
= load_elf(kernel_filename
,
1350 translate_kernel_address
, NULL
,
1351 NULL
, &lowaddr
, NULL
, 0, ELF_MACHINE
, 0);
1352 kernel_le
= kernel_size
> 0;
1354 if (kernel_size
< 0) {
1355 fprintf(stderr
, "qemu: error loading %s: %s\n",
1356 kernel_filename
, load_elf_strerror(kernel_size
));
1361 if (initrd_filename
) {
1362 /* Try to locate the initrd in the gap between the kernel
1363 * and the firmware. Add a bit of space just in case
1365 initrd_base
= (KERNEL_LOAD_ADDR
+ kernel_size
+ 0x1ffff) & ~0xffff;
1366 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
1367 load_limit
- initrd_base
);
1368 if (initrd_size
< 0) {
1369 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
1379 if (bios_name
== NULL
) {
1380 bios_name
= FW_FILE_NAME
;
1382 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1383 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
1385 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1390 spapr
->entry_point
= 0x100;
1392 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
1393 register_savevm_live(NULL
, "spapr/htab", -1, 1,
1394 &savevm_htab_handlers
, spapr
);
1396 /* Prepare the device tree */
1397 spapr
->fdt_skel
= spapr_create_fdt_skel(initrd_base
, initrd_size
,
1398 kernel_size
, kernel_le
,
1399 boot_device
, kernel_cmdline
,
1401 assert(spapr
->fdt_skel
!= NULL
);
1404 static int spapr_kvm_type(const char *vm_type
)
1410 if (!strcmp(vm_type
, "HV")) {
1414 if (!strcmp(vm_type
, "PR")) {
1418 error_report("Unknown kvm-type specified '%s'", vm_type
);
1422 static QEMUMachine spapr_machine
= {
1424 .desc
= "pSeries Logical Partition (PAPR compliant)",
1426 .init
= ppc_spapr_init
,
1427 .reset
= ppc_spapr_reset
,
1428 .block_default_type
= IF_SCSI
,
1429 .max_cpus
= MAX_CPUS
,
1431 .default_boot_order
= NULL
,
1432 .kvm_type
= spapr_kvm_type
,
1436 * Implementation of an interface to adjust firmware patch
1437 * for the bootindex property handling.
1439 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
1442 #define CAST(type, obj, name) \
1443 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
1444 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
1445 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
1448 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
1449 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
1450 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
1454 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
1455 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
1456 * in the top 16 bits of the 64-bit LUN
1458 unsigned id
= 0x8000 | (d
->id
<< 8) | d
->lun
;
1459 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1460 (uint64_t)id
<< 48);
1461 } else if (virtio
) {
1463 * We use SRP luns of the form 01000000 | (target << 8) | lun
1464 * in the top 32 bits of the 64-bit LUN
1465 * Note: the quote above is from SLOF and it is wrong,
1466 * the actual binding is:
1467 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
1469 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
1470 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1471 (uint64_t)id
<< 32);
1474 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
1475 * in the top 32 bits of the 64-bit LUN
1477 unsigned usb_port
= atoi(usb
->port
->path
);
1478 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
1479 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1480 (uint64_t)id
<< 32);
1485 /* Replace "pci" with "pci@800000020000000" */
1486 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
1492 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
1494 MachineClass
*mc
= MACHINE_CLASS(oc
);
1495 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
1497 mc
->qemu_machine
= data
;
1498 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
1501 static const TypeInfo spapr_machine_info
= {
1502 .name
= TYPE_SPAPR_MACHINE
,
1503 .parent
= TYPE_MACHINE
,
1504 .class_init
= spapr_machine_class_init
,
1505 .class_data
= &spapr_machine
,
1506 .interfaces
= (InterfaceInfo
[]) {
1507 { TYPE_FW_PATH_PROVIDER
},
1512 static void spapr_machine_register_types(void)
1514 type_register_static(&spapr_machine_info
);
1517 type_init(spapr_machine_register_types
)