2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licensed under the GPL.
10 #include "hw/sysbus.h"
11 #include "hw/arm/pxa.h"
12 #include "sysemu/sysemu.h"
13 #include "hw/char/serial.h"
14 #include "hw/i2c/i2c.h"
16 #include "sysemu/char.h"
17 #include "sysemu/blockdev.h"
23 { 0x40100000, PXA2XX_PIC_FFUART
},
24 { 0x40200000, PXA2XX_PIC_BTUART
},
25 { 0x40700000, PXA2XX_PIC_STUART
},
26 { 0x41600000, PXA25X_PIC_HWUART
},
28 }, pxa270_serial
[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART
},
30 { 0x40200000, PXA2XX_PIC_BTUART
},
31 { 0x40700000, PXA2XX_PIC_STUART
},
35 typedef struct PXASSPDef
{
41 static PXASSPDef pxa250_ssp
[] = {
42 { 0x41000000, PXA2XX_PIC_SSP
},
47 static PXASSPDef pxa255_ssp
[] = {
48 { 0x41000000, PXA2XX_PIC_SSP
},
49 { 0x41400000, PXA25X_PIC_NSSP
},
54 static PXASSPDef pxa26x_ssp
[] = {
55 { 0x41000000, PXA2XX_PIC_SSP
},
56 { 0x41400000, PXA25X_PIC_NSSP
},
57 { 0x41500000, PXA26X_PIC_ASSP
},
62 static PXASSPDef pxa27x_ssp
[] = {
63 { 0x41000000, PXA2XX_PIC_SSP
},
64 { 0x41700000, PXA27X_PIC_SSP2
},
65 { 0x41900000, PXA2XX_PIC_SSP3
},
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
91 static uint64_t pxa2xx_pm_read(void *opaque
, hwaddr addr
,
94 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
101 return s
->pm_regs
[addr
>> 2];
104 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
110 static void pxa2xx_pm_write(void *opaque
, hwaddr addr
,
111 uint64_t value
, unsigned size
)
113 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
117 /* Clear the write-one-to-clear bits... */
118 s
->pm_regs
[addr
>> 2] &= ~(value
& 0x2a);
119 /* ...and set the plain r/w bits */
120 s
->pm_regs
[addr
>> 2] &= ~0x15;
121 s
->pm_regs
[addr
>> 2] |= value
& 0x15;
124 case PSSR
: /* Read-clean registers */
127 s
->pm_regs
[addr
>> 2] &= ~value
;
130 default: /* Read-write registers */
132 s
->pm_regs
[addr
>> 2] = value
;
136 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
141 static const MemoryRegionOps pxa2xx_pm_ops
= {
142 .read
= pxa2xx_pm_read
,
143 .write
= pxa2xx_pm_write
,
144 .endianness
= DEVICE_NATIVE_ENDIAN
,
147 static const VMStateDescription vmstate_pxa2xx_pm
= {
150 .minimum_version_id
= 0,
151 .minimum_version_id_old
= 0,
152 .fields
= (VMStateField
[]) {
153 VMSTATE_UINT32_ARRAY(pm_regs
, PXA2xxState
, 0x40),
154 VMSTATE_END_OF_LIST()
158 #define CCCR 0x00 /* Core Clock Configuration register */
159 #define CKEN 0x04 /* Clock Enable register */
160 #define OSCC 0x08 /* Oscillator Configuration register */
161 #define CCSR 0x0c /* Core Clock Status register */
163 static uint64_t pxa2xx_cm_read(void *opaque
, hwaddr addr
,
166 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
172 return s
->cm_regs
[addr
>> 2];
175 return s
->cm_regs
[CCCR
>> 2] | (3 << 28);
178 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
184 static void pxa2xx_cm_write(void *opaque
, hwaddr addr
,
185 uint64_t value
, unsigned size
)
187 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
192 s
->cm_regs
[addr
>> 2] = value
;
196 s
->cm_regs
[addr
>> 2] &= ~0x6c;
197 s
->cm_regs
[addr
>> 2] |= value
& 0x6e;
198 if ((value
>> 1) & 1) /* OON */
199 s
->cm_regs
[addr
>> 2] |= 1 << 0; /* Oscillator is now stable */
203 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
208 static const MemoryRegionOps pxa2xx_cm_ops
= {
209 .read
= pxa2xx_cm_read
,
210 .write
= pxa2xx_cm_write
,
211 .endianness
= DEVICE_NATIVE_ENDIAN
,
214 static const VMStateDescription vmstate_pxa2xx_cm
= {
217 .minimum_version_id
= 0,
218 .minimum_version_id_old
= 0,
219 .fields
= (VMStateField
[]) {
220 VMSTATE_UINT32_ARRAY(cm_regs
, PXA2xxState
, 4),
221 VMSTATE_UINT32(clkcfg
, PXA2xxState
),
222 VMSTATE_UINT32(pmnc
, PXA2xxState
),
223 VMSTATE_END_OF_LIST()
227 static uint64_t pxa2xx_clkcfg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
229 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
233 static void pxa2xx_clkcfg_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
236 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
237 s
->clkcfg
= value
& 0xf;
239 printf("%s: CPU frequency change attempt\n", __func__
);
243 static void pxa2xx_pwrmode_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
246 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
247 static const char *pwrmode
[8] = {
248 "Normal", "Idle", "Deep-idle", "Standby",
249 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
253 printf("%s: CPU voltage change attempt\n", __func__
);
262 if (!(s
->cm_regs
[CCCR
>> 2] & (1U << 31))) { /* CPDIS */
263 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HALT
);
270 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HALT
);
271 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
275 s
->cpu
->env
.uncached_cpsr
= ARM_CPU_MODE_SVC
;
276 s
->cpu
->env
.daif
= PSTATE_A
| PSTATE_F
| PSTATE_I
;
277 s
->cpu
->env
.cp15
.c1_sys
= 0;
278 s
->cpu
->env
.cp15
.c1_coproc
= 0;
279 s
->cpu
->env
.cp15
.ttbr0_el1
= 0;
280 s
->cpu
->env
.cp15
.c3
= 0;
281 s
->pm_regs
[PSSR
>> 2] |= 0x8; /* Set STS */
282 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
285 * The scratch-pad register is almost universally used
286 * for storing the return address on suspend. For the
287 * lack of a resuming bootloader, perform a jump
288 * directly to that address.
290 memset(s
->cpu
->env
.regs
, 0, 4 * 15);
291 s
->cpu
->env
.regs
[15] = s
->pm_regs
[PSPR
>> 2];
294 buffer
= 0xe59ff000; /* ldr pc, [pc, #0] */
295 cpu_physical_memory_write(0, &buffer
, 4);
296 buffer
= s
->pm_regs
[PSPR
>> 2];
297 cpu_physical_memory_write(8, &buffer
, 4);
301 cpu_interrupt(current_cpu
, CPU_INTERRUPT_HALT
);
307 printf("%s: machine entered %s mode\n", __func__
,
312 static uint64_t pxa2xx_cppmnc_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
314 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
318 static void pxa2xx_cppmnc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
321 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
325 static uint64_t pxa2xx_cpccnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
327 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
329 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
335 static const ARMCPRegInfo pxa_cp_reginfo
[] = {
336 /* cp14 crm==1: perf registers */
337 { .name
= "CPPMNC", .cp
= 14, .crn
= 0, .crm
= 1, .opc1
= 0, .opc2
= 0,
339 .readfn
= pxa2xx_cppmnc_read
, .writefn
= pxa2xx_cppmnc_write
},
340 { .name
= "CPCCNT", .cp
= 14, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
342 .readfn
= pxa2xx_cpccnt_read
, .writefn
= arm_cp_write_ignore
},
343 { .name
= "CPINTEN", .cp
= 14, .crn
= 4, .crm
= 1, .opc1
= 0, .opc2
= 0,
344 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
345 { .name
= "CPFLAG", .cp
= 14, .crn
= 5, .crm
= 1, .opc1
= 0, .opc2
= 0,
346 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
347 { .name
= "CPEVTSEL", .cp
= 14, .crn
= 8, .crm
= 1, .opc1
= 0, .opc2
= 0,
348 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
349 /* cp14 crm==2: performance count registers */
350 { .name
= "CPPMN0", .cp
= 14, .crn
= 0, .crm
= 2, .opc1
= 0, .opc2
= 0,
351 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
352 { .name
= "CPPMN1", .cp
= 14, .crn
= 1, .crm
= 2, .opc1
= 0, .opc2
= 0,
353 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
354 { .name
= "CPPMN2", .cp
= 14, .crn
= 2, .crm
= 2, .opc1
= 0, .opc2
= 0,
355 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
356 { .name
= "CPPMN3", .cp
= 14, .crn
= 2, .crm
= 3, .opc1
= 0, .opc2
= 0,
357 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
358 /* cp14 crn==6: CLKCFG */
359 { .name
= "CLKCFG", .cp
= 14, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
361 .readfn
= pxa2xx_clkcfg_read
, .writefn
= pxa2xx_clkcfg_write
},
362 /* cp14 crn==7: PWRMODE */
363 { .name
= "PWRMODE", .cp
= 14, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 0,
365 .readfn
= arm_cp_read_zero
, .writefn
= pxa2xx_pwrmode_write
},
369 static void pxa2xx_setup_cp14(PXA2xxState
*s
)
371 define_arm_cp_regs_with_opaque(s
->cpu
, pxa_cp_reginfo
, s
);
374 #define MDCNFG 0x00 /* SDRAM Configuration register */
375 #define MDREFR 0x04 /* SDRAM Refresh Control register */
376 #define MSC0 0x08 /* Static Memory Control register 0 */
377 #define MSC1 0x0c /* Static Memory Control register 1 */
378 #define MSC2 0x10 /* Static Memory Control register 2 */
379 #define MECR 0x14 /* Expansion Memory Bus Config register */
380 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
381 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
382 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
383 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
384 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
385 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
386 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
387 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
388 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
389 #define ARB_CNTL 0x48 /* Arbiter Control register */
390 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
391 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
392 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
393 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
394 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
395 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
396 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
398 static uint64_t pxa2xx_mm_read(void *opaque
, hwaddr addr
,
401 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
404 case MDCNFG
... SA1110
:
406 return s
->mm_regs
[addr
>> 2];
409 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
415 static void pxa2xx_mm_write(void *opaque
, hwaddr addr
,
416 uint64_t value
, unsigned size
)
418 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
421 case MDCNFG
... SA1110
:
422 if ((addr
& 3) == 0) {
423 s
->mm_regs
[addr
>> 2] = value
;
428 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
433 static const MemoryRegionOps pxa2xx_mm_ops
= {
434 .read
= pxa2xx_mm_read
,
435 .write
= pxa2xx_mm_write
,
436 .endianness
= DEVICE_NATIVE_ENDIAN
,
439 static const VMStateDescription vmstate_pxa2xx_mm
= {
442 .minimum_version_id
= 0,
443 .minimum_version_id_old
= 0,
444 .fields
= (VMStateField
[]) {
445 VMSTATE_UINT32_ARRAY(mm_regs
, PXA2xxState
, 0x1a),
446 VMSTATE_END_OF_LIST()
450 #define TYPE_PXA2XX_SSP "pxa2xx-ssp"
451 #define PXA2XX_SSP(obj) \
452 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
454 /* Synchronous Serial Ports */
457 SysBusDevice parent_obj
;
474 uint32_t rx_fifo
[16];
479 #define SSCR0 0x00 /* SSP Control register 0 */
480 #define SSCR1 0x04 /* SSP Control register 1 */
481 #define SSSR 0x08 /* SSP Status register */
482 #define SSITR 0x0c /* SSP Interrupt Test register */
483 #define SSDR 0x10 /* SSP Data register */
484 #define SSTO 0x28 /* SSP Time-Out register */
485 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
486 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
487 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
488 #define SSTSS 0x38 /* SSP Time Slot Status register */
489 #define SSACD 0x3c /* SSP Audio Clock Divider register */
491 /* Bitfields for above registers */
492 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
493 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
494 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
495 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
496 #define SSCR0_SSE (1 << 7)
497 #define SSCR0_RIM (1 << 22)
498 #define SSCR0_TIM (1 << 23)
499 #define SSCR0_MOD (1U << 31)
500 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
501 #define SSCR1_RIE (1 << 0)
502 #define SSCR1_TIE (1 << 1)
503 #define SSCR1_LBM (1 << 2)
504 #define SSCR1_MWDS (1 << 5)
505 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
506 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
507 #define SSCR1_EFWR (1 << 14)
508 #define SSCR1_PINTE (1 << 18)
509 #define SSCR1_TINTE (1 << 19)
510 #define SSCR1_RSRE (1 << 20)
511 #define SSCR1_TSRE (1 << 21)
512 #define SSCR1_EBCEI (1 << 29)
513 #define SSITR_INT (7 << 5)
514 #define SSSR_TNF (1 << 2)
515 #define SSSR_RNE (1 << 3)
516 #define SSSR_TFS (1 << 5)
517 #define SSSR_RFS (1 << 6)
518 #define SSSR_ROR (1 << 7)
519 #define SSSR_PINT (1 << 18)
520 #define SSSR_TINT (1 << 19)
521 #define SSSR_EOC (1 << 20)
522 #define SSSR_TUR (1 << 21)
523 #define SSSR_BCE (1 << 23)
524 #define SSSR_RW 0x00bc0080
526 static void pxa2xx_ssp_int_update(PXA2xxSSPState
*s
)
530 level
|= s
->ssitr
& SSITR_INT
;
531 level
|= (s
->sssr
& SSSR_BCE
) && (s
->sscr
[1] & SSCR1_EBCEI
);
532 level
|= (s
->sssr
& SSSR_TUR
) && !(s
->sscr
[0] & SSCR0_TIM
);
533 level
|= (s
->sssr
& SSSR_EOC
) && (s
->sssr
& (SSSR_TINT
| SSSR_PINT
));
534 level
|= (s
->sssr
& SSSR_TINT
) && (s
->sscr
[1] & SSCR1_TINTE
);
535 level
|= (s
->sssr
& SSSR_PINT
) && (s
->sscr
[1] & SSCR1_PINTE
);
536 level
|= (s
->sssr
& SSSR_ROR
) && !(s
->sscr
[0] & SSCR0_RIM
);
537 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
538 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
539 qemu_set_irq(s
->irq
, !!level
);
542 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState
*s
)
544 s
->sssr
&= ~(0xf << 12); /* Clear RFL */
545 s
->sssr
&= ~(0xf << 8); /* Clear TFL */
546 s
->sssr
&= ~SSSR_TFS
;
547 s
->sssr
&= ~SSSR_TNF
;
549 s
->sssr
|= ((s
->rx_level
- 1) & 0xf) << 12;
550 if (s
->rx_level
>= SSCR1_RFT(s
->sscr
[1]))
553 s
->sssr
&= ~SSSR_RFS
;
557 s
->sssr
&= ~SSSR_RNE
;
558 /* TX FIFO is never filled, so it is always in underrun
559 condition if SSP is enabled */
564 pxa2xx_ssp_int_update(s
);
567 static uint64_t pxa2xx_ssp_read(void *opaque
, hwaddr addr
,
570 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
585 return s
->sssr
| s
->ssitr
;
589 if (s
->rx_level
< 1) {
590 printf("%s: SSP Rx Underrun\n", __FUNCTION__
);
594 retval
= s
->rx_fifo
[s
->rx_start
++];
596 pxa2xx_ssp_fifo_update(s
);
607 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
613 static void pxa2xx_ssp_write(void *opaque
, hwaddr addr
,
614 uint64_t value64
, unsigned size
)
616 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
617 uint32_t value
= value64
;
621 s
->sscr
[0] = value
& 0xc7ffffff;
622 s
->enable
= value
& SSCR0_SSE
;
623 if (value
& SSCR0_MOD
)
624 printf("%s: Attempt to use network mode\n", __FUNCTION__
);
625 if (s
->enable
&& SSCR0_DSS(value
) < 4)
626 printf("%s: Wrong data size: %i bits\n", __FUNCTION__
,
628 if (!(value
& SSCR0_SSE
)) {
633 pxa2xx_ssp_fifo_update(s
);
638 if (value
& (SSCR1_LBM
| SSCR1_EFWR
))
639 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__
);
640 pxa2xx_ssp_fifo_update(s
);
652 s
->ssitr
= value
& SSITR_INT
;
653 pxa2xx_ssp_int_update(s
);
657 s
->sssr
&= ~(value
& SSSR_RW
);
658 pxa2xx_ssp_int_update(s
);
662 if (SSCR0_UWIRE(s
->sscr
[0])) {
663 if (s
->sscr
[1] & SSCR1_MWDS
)
668 /* Note how 32bits overflow does no harm here */
669 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
671 /* Data goes from here to the Tx FIFO and is shifted out from
672 * there directly to the slave, no need to buffer it.
676 readval
= ssi_transfer(s
->bus
, value
);
677 if (s
->rx_level
< 0x10) {
678 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] = readval
;
683 pxa2xx_ssp_fifo_update(s
);
699 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
704 static const MemoryRegionOps pxa2xx_ssp_ops
= {
705 .read
= pxa2xx_ssp_read
,
706 .write
= pxa2xx_ssp_write
,
707 .endianness
= DEVICE_NATIVE_ENDIAN
,
710 static void pxa2xx_ssp_save(QEMUFile
*f
, void *opaque
)
712 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
715 qemu_put_be32(f
, s
->enable
);
717 qemu_put_be32s(f
, &s
->sscr
[0]);
718 qemu_put_be32s(f
, &s
->sscr
[1]);
719 qemu_put_be32s(f
, &s
->sspsp
);
720 qemu_put_be32s(f
, &s
->ssto
);
721 qemu_put_be32s(f
, &s
->ssitr
);
722 qemu_put_be32s(f
, &s
->sssr
);
723 qemu_put_8s(f
, &s
->sstsa
);
724 qemu_put_8s(f
, &s
->ssrsa
);
725 qemu_put_8s(f
, &s
->ssacd
);
727 qemu_put_byte(f
, s
->rx_level
);
728 for (i
= 0; i
< s
->rx_level
; i
++)
729 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 0xf]);
732 static int pxa2xx_ssp_load(QEMUFile
*f
, void *opaque
, int version_id
)
734 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
737 s
->enable
= qemu_get_be32(f
);
739 qemu_get_be32s(f
, &s
->sscr
[0]);
740 qemu_get_be32s(f
, &s
->sscr
[1]);
741 qemu_get_be32s(f
, &s
->sspsp
);
742 qemu_get_be32s(f
, &s
->ssto
);
743 qemu_get_be32s(f
, &s
->ssitr
);
744 qemu_get_be32s(f
, &s
->sssr
);
745 qemu_get_8s(f
, &s
->sstsa
);
746 qemu_get_8s(f
, &s
->ssrsa
);
747 qemu_get_8s(f
, &s
->ssacd
);
749 s
->rx_level
= qemu_get_byte(f
);
751 for (i
= 0; i
< s
->rx_level
; i
++)
752 s
->rx_fifo
[i
] = qemu_get_byte(f
);
757 static int pxa2xx_ssp_init(SysBusDevice
*sbd
)
759 DeviceState
*dev
= DEVICE(sbd
);
760 PXA2xxSSPState
*s
= PXA2XX_SSP(dev
);
762 sysbus_init_irq(sbd
, &s
->irq
);
764 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pxa2xx_ssp_ops
, s
,
765 "pxa2xx-ssp", 0x1000);
766 sysbus_init_mmio(sbd
, &s
->iomem
);
767 register_savevm(dev
, "pxa2xx_ssp", -1, 0,
768 pxa2xx_ssp_save
, pxa2xx_ssp_load
, s
);
770 s
->bus
= ssi_create_bus(dev
, "ssi");
774 /* Real-Time Clock */
775 #define RCNR 0x00 /* RTC Counter register */
776 #define RTAR 0x04 /* RTC Alarm register */
777 #define RTSR 0x08 /* RTC Status register */
778 #define RTTR 0x0c /* RTC Timer Trim register */
779 #define RDCR 0x10 /* RTC Day Counter register */
780 #define RYCR 0x14 /* RTC Year Counter register */
781 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
782 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
783 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
784 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
785 #define SWCR 0x28 /* RTC Stopwatch Counter register */
786 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
787 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
788 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
789 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
791 #define TYPE_PXA2XX_RTC "pxa2xx_rtc"
792 #define PXA2XX_RTC(obj) \
793 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
797 SysBusDevice parent_obj
;
815 uint32_t last_rtcpicr
;
820 QEMUTimer
*rtc_rdal1
;
821 QEMUTimer
*rtc_rdal2
;
822 QEMUTimer
*rtc_swal1
;
823 QEMUTimer
*rtc_swal2
;
828 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState
*s
)
830 qemu_set_irq(s
->rtc_irq
, !!(s
->rtsr
& 0x2553));
833 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState
*s
)
835 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
836 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
837 (1000 * ((s
->rttr
& 0xffff) + 1));
838 s
->last_rdcr
+= ((rt
- s
->last_hz
) << 15) /
839 (1000 * ((s
->rttr
& 0xffff) + 1));
843 static void pxa2xx_rtc_swupdate(PXA2xxRTCState
*s
)
845 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
846 if (s
->rtsr
& (1 << 12))
847 s
->last_swcr
+= (rt
- s
->last_sw
) / 10;
851 static void pxa2xx_rtc_piupdate(PXA2xxRTCState
*s
)
853 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
854 if (s
->rtsr
& (1 << 15))
855 s
->last_swcr
+= rt
- s
->last_pi
;
859 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState
*s
,
862 if ((rtsr
& (1 << 2)) && !(rtsr
& (1 << 0)))
863 timer_mod(s
->rtc_hz
, s
->last_hz
+
864 (((s
->rtar
- s
->last_rcnr
) * 1000 *
865 ((s
->rttr
& 0xffff) + 1)) >> 15));
867 timer_del(s
->rtc_hz
);
869 if ((rtsr
& (1 << 5)) && !(rtsr
& (1 << 4)))
870 timer_mod(s
->rtc_rdal1
, s
->last_hz
+
871 (((s
->rdar1
- s
->last_rdcr
) * 1000 *
872 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
874 timer_del(s
->rtc_rdal1
);
876 if ((rtsr
& (1 << 7)) && !(rtsr
& (1 << 6)))
877 timer_mod(s
->rtc_rdal2
, s
->last_hz
+
878 (((s
->rdar2
- s
->last_rdcr
) * 1000 *
879 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
881 timer_del(s
->rtc_rdal2
);
883 if ((rtsr
& 0x1200) == 0x1200 && !(rtsr
& (1 << 8)))
884 timer_mod(s
->rtc_swal1
, s
->last_sw
+
885 (s
->swar1
- s
->last_swcr
) * 10); /* TODO: fixup */
887 timer_del(s
->rtc_swal1
);
889 if ((rtsr
& 0x1800) == 0x1800 && !(rtsr
& (1 << 10)))
890 timer_mod(s
->rtc_swal2
, s
->last_sw
+
891 (s
->swar2
- s
->last_swcr
) * 10); /* TODO: fixup */
893 timer_del(s
->rtc_swal2
);
895 if ((rtsr
& 0xc000) == 0xc000 && !(rtsr
& (1 << 13)))
896 timer_mod(s
->rtc_pi
, s
->last_pi
+
897 (s
->piar
& 0xffff) - s
->last_rtcpicr
);
899 timer_del(s
->rtc_pi
);
902 static inline void pxa2xx_rtc_hz_tick(void *opaque
)
904 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
906 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
907 pxa2xx_rtc_int_update(s
);
910 static inline void pxa2xx_rtc_rdal1_tick(void *opaque
)
912 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
914 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
915 pxa2xx_rtc_int_update(s
);
918 static inline void pxa2xx_rtc_rdal2_tick(void *opaque
)
920 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
922 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
923 pxa2xx_rtc_int_update(s
);
926 static inline void pxa2xx_rtc_swal1_tick(void *opaque
)
928 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
930 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
931 pxa2xx_rtc_int_update(s
);
934 static inline void pxa2xx_rtc_swal2_tick(void *opaque
)
936 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
937 s
->rtsr
|= (1 << 10);
938 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
939 pxa2xx_rtc_int_update(s
);
942 static inline void pxa2xx_rtc_pi_tick(void *opaque
)
944 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
945 s
->rtsr
|= (1 << 13);
946 pxa2xx_rtc_piupdate(s
);
948 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
949 pxa2xx_rtc_int_update(s
);
952 static uint64_t pxa2xx_rtc_read(void *opaque
, hwaddr addr
,
955 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
979 return s
->last_rcnr
+
980 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
981 (1000 * ((s
->rttr
& 0xffff) + 1));
983 return s
->last_rdcr
+
984 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
985 (1000 * ((s
->rttr
& 0xffff) + 1));
989 if (s
->rtsr
& (1 << 12))
990 return s
->last_swcr
+
991 (qemu_clock_get_ms(rtc_clock
) - s
->last_sw
) / 10;
995 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1001 static void pxa2xx_rtc_write(void *opaque
, hwaddr addr
,
1002 uint64_t value64
, unsigned size
)
1004 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1005 uint32_t value
= value64
;
1009 if (!(s
->rttr
& (1U << 31))) {
1010 pxa2xx_rtc_hzupdate(s
);
1012 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1017 if ((s
->rtsr
^ value
) & (1 << 15))
1018 pxa2xx_rtc_piupdate(s
);
1020 if ((s
->rtsr
^ value
) & (1 << 12))
1021 pxa2xx_rtc_swupdate(s
);
1023 if (((s
->rtsr
^ value
) & 0x4aac) | (value
& ~0xdaac))
1024 pxa2xx_rtc_alarm_update(s
, value
);
1026 s
->rtsr
= (value
& 0xdaac) | (s
->rtsr
& ~(value
& ~0xdaac));
1027 pxa2xx_rtc_int_update(s
);
1032 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1037 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1042 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1047 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1052 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1056 pxa2xx_rtc_swupdate(s
);
1059 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1064 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1069 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1073 pxa2xx_rtc_hzupdate(s
);
1074 s
->last_rcnr
= value
;
1075 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1079 pxa2xx_rtc_hzupdate(s
);
1080 s
->last_rdcr
= value
;
1081 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1085 s
->last_rycr
= value
;
1089 pxa2xx_rtc_swupdate(s
);
1090 s
->last_swcr
= value
;
1091 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1095 pxa2xx_rtc_piupdate(s
);
1096 s
->last_rtcpicr
= value
& 0xffff;
1097 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1101 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1105 static const MemoryRegionOps pxa2xx_rtc_ops
= {
1106 .read
= pxa2xx_rtc_read
,
1107 .write
= pxa2xx_rtc_write
,
1108 .endianness
= DEVICE_NATIVE_ENDIAN
,
1111 static int pxa2xx_rtc_init(SysBusDevice
*dev
)
1113 PXA2xxRTCState
*s
= PXA2XX_RTC(dev
);
1120 qemu_get_timedate(&tm
, 0);
1121 wom
= ((tm
.tm_mday
- 1) / 7) + 1;
1123 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
1124 s
->last_rdcr
= (wom
<< 20) | ((tm
.tm_wday
+ 1) << 17) |
1125 (tm
.tm_hour
<< 12) | (tm
.tm_min
<< 6) | tm
.tm_sec
;
1126 s
->last_rycr
= ((tm
.tm_year
+ 1900) << 9) |
1127 ((tm
.tm_mon
+ 1) << 5) | tm
.tm_mday
;
1128 s
->last_swcr
= (tm
.tm_hour
<< 19) |
1129 (tm
.tm_min
<< 13) | (tm
.tm_sec
<< 7);
1130 s
->last_rtcpicr
= 0;
1131 s
->last_hz
= s
->last_sw
= s
->last_pi
= qemu_clock_get_ms(rtc_clock
);
1133 s
->rtc_hz
= timer_new_ms(rtc_clock
, pxa2xx_rtc_hz_tick
, s
);
1134 s
->rtc_rdal1
= timer_new_ms(rtc_clock
, pxa2xx_rtc_rdal1_tick
, s
);
1135 s
->rtc_rdal2
= timer_new_ms(rtc_clock
, pxa2xx_rtc_rdal2_tick
, s
);
1136 s
->rtc_swal1
= timer_new_ms(rtc_clock
, pxa2xx_rtc_swal1_tick
, s
);
1137 s
->rtc_swal2
= timer_new_ms(rtc_clock
, pxa2xx_rtc_swal2_tick
, s
);
1138 s
->rtc_pi
= timer_new_ms(rtc_clock
, pxa2xx_rtc_pi_tick
, s
);
1140 sysbus_init_irq(dev
, &s
->rtc_irq
);
1142 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pxa2xx_rtc_ops
, s
,
1143 "pxa2xx-rtc", 0x10000);
1144 sysbus_init_mmio(dev
, &s
->iomem
);
1149 static void pxa2xx_rtc_pre_save(void *opaque
)
1151 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1153 pxa2xx_rtc_hzupdate(s
);
1154 pxa2xx_rtc_piupdate(s
);
1155 pxa2xx_rtc_swupdate(s
);
1158 static int pxa2xx_rtc_post_load(void *opaque
, int version_id
)
1160 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1162 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1167 static const VMStateDescription vmstate_pxa2xx_rtc_regs
= {
1168 .name
= "pxa2xx_rtc",
1170 .minimum_version_id
= 0,
1171 .minimum_version_id_old
= 0,
1172 .pre_save
= pxa2xx_rtc_pre_save
,
1173 .post_load
= pxa2xx_rtc_post_load
,
1174 .fields
= (VMStateField
[]) {
1175 VMSTATE_UINT32(rttr
, PXA2xxRTCState
),
1176 VMSTATE_UINT32(rtsr
, PXA2xxRTCState
),
1177 VMSTATE_UINT32(rtar
, PXA2xxRTCState
),
1178 VMSTATE_UINT32(rdar1
, PXA2xxRTCState
),
1179 VMSTATE_UINT32(rdar2
, PXA2xxRTCState
),
1180 VMSTATE_UINT32(ryar1
, PXA2xxRTCState
),
1181 VMSTATE_UINT32(ryar2
, PXA2xxRTCState
),
1182 VMSTATE_UINT32(swar1
, PXA2xxRTCState
),
1183 VMSTATE_UINT32(swar2
, PXA2xxRTCState
),
1184 VMSTATE_UINT32(piar
, PXA2xxRTCState
),
1185 VMSTATE_UINT32(last_rcnr
, PXA2xxRTCState
),
1186 VMSTATE_UINT32(last_rdcr
, PXA2xxRTCState
),
1187 VMSTATE_UINT32(last_rycr
, PXA2xxRTCState
),
1188 VMSTATE_UINT32(last_swcr
, PXA2xxRTCState
),
1189 VMSTATE_UINT32(last_rtcpicr
, PXA2xxRTCState
),
1190 VMSTATE_INT64(last_hz
, PXA2xxRTCState
),
1191 VMSTATE_INT64(last_sw
, PXA2xxRTCState
),
1192 VMSTATE_INT64(last_pi
, PXA2xxRTCState
),
1193 VMSTATE_END_OF_LIST(),
1197 static void pxa2xx_rtc_sysbus_class_init(ObjectClass
*klass
, void *data
)
1199 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1200 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1202 k
->init
= pxa2xx_rtc_init
;
1203 dc
->desc
= "PXA2xx RTC Controller";
1204 dc
->vmsd
= &vmstate_pxa2xx_rtc_regs
;
1207 static const TypeInfo pxa2xx_rtc_sysbus_info
= {
1208 .name
= TYPE_PXA2XX_RTC
,
1209 .parent
= TYPE_SYS_BUS_DEVICE
,
1210 .instance_size
= sizeof(PXA2xxRTCState
),
1211 .class_init
= pxa2xx_rtc_sysbus_class_init
,
1216 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
1217 #define PXA2XX_I2C_SLAVE(obj) \
1218 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE)
1220 typedef struct PXA2xxI2CSlaveState
{
1221 I2CSlave parent_obj
;
1223 PXA2xxI2CState
*host
;
1224 } PXA2xxI2CSlaveState
;
1226 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
1227 #define PXA2XX_I2C(obj) \
1228 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
1230 struct PXA2xxI2CState
{
1232 SysBusDevice parent_obj
;
1236 PXA2xxI2CSlaveState
*slave
;
1240 uint32_t region_size
;
1248 #define IBMR 0x80 /* I2C Bus Monitor register */
1249 #define IDBR 0x88 /* I2C Data Buffer register */
1250 #define ICR 0x90 /* I2C Control register */
1251 #define ISR 0x98 /* I2C Status register */
1252 #define ISAR 0xa0 /* I2C Slave Address register */
1254 static void pxa2xx_i2c_update(PXA2xxI2CState
*s
)
1257 level
|= s
->status
& s
->control
& (1 << 10); /* BED */
1258 level
|= (s
->status
& (1 << 7)) && (s
->control
& (1 << 9)); /* IRF */
1259 level
|= (s
->status
& (1 << 6)) && (s
->control
& (1 << 8)); /* ITE */
1260 level
|= s
->status
& (1 << 9); /* SAD */
1261 qemu_set_irq(s
->irq
, !!level
);
1264 /* These are only stubs now. */
1265 static void pxa2xx_i2c_event(I2CSlave
*i2c
, enum i2c_event event
)
1267 PXA2xxI2CSlaveState
*slave
= PXA2XX_I2C_SLAVE(i2c
);
1268 PXA2xxI2CState
*s
= slave
->host
;
1271 case I2C_START_SEND
:
1272 s
->status
|= (1 << 9); /* set SAD */
1273 s
->status
&= ~(1 << 0); /* clear RWM */
1275 case I2C_START_RECV
:
1276 s
->status
|= (1 << 9); /* set SAD */
1277 s
->status
|= 1 << 0; /* set RWM */
1280 s
->status
|= (1 << 4); /* set SSD */
1283 s
->status
|= 1 << 1; /* set ACKNAK */
1286 pxa2xx_i2c_update(s
);
1289 static int pxa2xx_i2c_rx(I2CSlave
*i2c
)
1291 PXA2xxI2CSlaveState
*slave
= PXA2XX_I2C_SLAVE(i2c
);
1292 PXA2xxI2CState
*s
= slave
->host
;
1294 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6))) {
1298 if (s
->status
& (1 << 0)) { /* RWM */
1299 s
->status
|= 1 << 6; /* set ITE */
1301 pxa2xx_i2c_update(s
);
1306 static int pxa2xx_i2c_tx(I2CSlave
*i2c
, uint8_t data
)
1308 PXA2xxI2CSlaveState
*slave
= PXA2XX_I2C_SLAVE(i2c
);
1309 PXA2xxI2CState
*s
= slave
->host
;
1311 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6))) {
1315 if (!(s
->status
& (1 << 0))) { /* RWM */
1316 s
->status
|= 1 << 7; /* set IRF */
1319 pxa2xx_i2c_update(s
);
1324 static uint64_t pxa2xx_i2c_read(void *opaque
, hwaddr addr
,
1327 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1335 return s
->status
| (i2c_bus_busy(s
->bus
) << 2);
1337 slave
= I2C_SLAVE(s
->slave
);
1338 return slave
->address
;
1342 if (s
->status
& (1 << 2))
1343 s
->ibmr
^= 3; /* Fake SCL and SDA pin changes */
1348 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1354 static void pxa2xx_i2c_write(void *opaque
, hwaddr addr
,
1355 uint64_t value64
, unsigned size
)
1357 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1358 uint32_t value
= value64
;
1364 s
->control
= value
& 0xfff7;
1365 if ((value
& (1 << 3)) && (value
& (1 << 6))) { /* TB and IUE */
1366 /* TODO: slave mode */
1367 if (value
& (1 << 0)) { /* START condition */
1369 s
->status
|= 1 << 0; /* set RWM */
1371 s
->status
&= ~(1 << 0); /* clear RWM */
1372 ack
= !i2c_start_transfer(s
->bus
, s
->data
>> 1, s
->data
& 1);
1374 if (s
->status
& (1 << 0)) { /* RWM */
1375 s
->data
= i2c_recv(s
->bus
);
1376 if (value
& (1 << 2)) /* ACKNAK */
1380 ack
= !i2c_send(s
->bus
, s
->data
);
1383 if (value
& (1 << 1)) /* STOP condition */
1384 i2c_end_transfer(s
->bus
);
1387 if (value
& (1 << 0)) /* START condition */
1388 s
->status
|= 1 << 6; /* set ITE */
1390 if (s
->status
& (1 << 0)) /* RWM */
1391 s
->status
|= 1 << 7; /* set IRF */
1393 s
->status
|= 1 << 6; /* set ITE */
1394 s
->status
&= ~(1 << 1); /* clear ACKNAK */
1396 s
->status
|= 1 << 6; /* set ITE */
1397 s
->status
|= 1 << 10; /* set BED */
1398 s
->status
|= 1 << 1; /* set ACKNAK */
1401 if (!(value
& (1 << 3)) && (value
& (1 << 6))) /* !TB and IUE */
1402 if (value
& (1 << 4)) /* MA */
1403 i2c_end_transfer(s
->bus
);
1404 pxa2xx_i2c_update(s
);
1408 s
->status
&= ~(value
& 0x07f0);
1409 pxa2xx_i2c_update(s
);
1413 i2c_set_slave_address(I2C_SLAVE(s
->slave
), value
& 0x7f);
1417 s
->data
= value
& 0xff;
1421 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1425 static const MemoryRegionOps pxa2xx_i2c_ops
= {
1426 .read
= pxa2xx_i2c_read
,
1427 .write
= pxa2xx_i2c_write
,
1428 .endianness
= DEVICE_NATIVE_ENDIAN
,
1431 static const VMStateDescription vmstate_pxa2xx_i2c_slave
= {
1432 .name
= "pxa2xx_i2c_slave",
1434 .minimum_version_id
= 1,
1435 .minimum_version_id_old
= 1,
1436 .fields
= (VMStateField
[]) {
1437 VMSTATE_I2C_SLAVE(parent_obj
, PXA2xxI2CSlaveState
),
1438 VMSTATE_END_OF_LIST()
1442 static const VMStateDescription vmstate_pxa2xx_i2c
= {
1443 .name
= "pxa2xx_i2c",
1445 .minimum_version_id
= 1,
1446 .minimum_version_id_old
= 1,
1447 .fields
= (VMStateField
[]) {
1448 VMSTATE_UINT16(control
, PXA2xxI2CState
),
1449 VMSTATE_UINT16(status
, PXA2xxI2CState
),
1450 VMSTATE_UINT8(ibmr
, PXA2xxI2CState
),
1451 VMSTATE_UINT8(data
, PXA2xxI2CState
),
1452 VMSTATE_STRUCT_POINTER(slave
, PXA2xxI2CState
,
1453 vmstate_pxa2xx_i2c_slave
, PXA2xxI2CSlaveState
),
1454 VMSTATE_END_OF_LIST()
1458 static int pxa2xx_i2c_slave_init(I2CSlave
*i2c
)
1460 /* Nothing to do. */
1464 static void pxa2xx_i2c_slave_class_init(ObjectClass
*klass
, void *data
)
1466 I2CSlaveClass
*k
= I2C_SLAVE_CLASS(klass
);
1468 k
->init
= pxa2xx_i2c_slave_init
;
1469 k
->event
= pxa2xx_i2c_event
;
1470 k
->recv
= pxa2xx_i2c_rx
;
1471 k
->send
= pxa2xx_i2c_tx
;
1474 static const TypeInfo pxa2xx_i2c_slave_info
= {
1475 .name
= TYPE_PXA2XX_I2C_SLAVE
,
1476 .parent
= TYPE_I2C_SLAVE
,
1477 .instance_size
= sizeof(PXA2xxI2CSlaveState
),
1478 .class_init
= pxa2xx_i2c_slave_class_init
,
1481 PXA2xxI2CState
*pxa2xx_i2c_init(hwaddr base
,
1482 qemu_irq irq
, uint32_t region_size
)
1485 SysBusDevice
*i2c_dev
;
1489 dev
= qdev_create(NULL
, TYPE_PXA2XX_I2C
);
1490 qdev_prop_set_uint32(dev
, "size", region_size
+ 1);
1491 qdev_prop_set_uint32(dev
, "offset", base
& region_size
);
1492 qdev_init_nofail(dev
);
1494 i2c_dev
= SYS_BUS_DEVICE(dev
);
1495 sysbus_mmio_map(i2c_dev
, 0, base
& ~region_size
);
1496 sysbus_connect_irq(i2c_dev
, 0, irq
);
1498 s
= PXA2XX_I2C(i2c_dev
);
1499 /* FIXME: Should the slave device really be on a separate bus? */
1500 i2cbus
= i2c_init_bus(dev
, "dummy");
1501 dev
= i2c_create_slave(i2cbus
, TYPE_PXA2XX_I2C_SLAVE
, 0);
1502 s
->slave
= PXA2XX_I2C_SLAVE(dev
);
1508 static int pxa2xx_i2c_initfn(SysBusDevice
*sbd
)
1510 DeviceState
*dev
= DEVICE(sbd
);
1511 PXA2xxI2CState
*s
= PXA2XX_I2C(dev
);
1513 s
->bus
= i2c_init_bus(dev
, "i2c");
1515 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pxa2xx_i2c_ops
, s
,
1516 "pxa2xx-i2c", s
->region_size
);
1517 sysbus_init_mmio(sbd
, &s
->iomem
);
1518 sysbus_init_irq(sbd
, &s
->irq
);
1523 I2CBus
*pxa2xx_i2c_bus(PXA2xxI2CState
*s
)
1528 static Property pxa2xx_i2c_properties
[] = {
1529 DEFINE_PROP_UINT32("size", PXA2xxI2CState
, region_size
, 0x10000),
1530 DEFINE_PROP_UINT32("offset", PXA2xxI2CState
, offset
, 0),
1531 DEFINE_PROP_END_OF_LIST(),
1534 static void pxa2xx_i2c_class_init(ObjectClass
*klass
, void *data
)
1536 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1537 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1539 k
->init
= pxa2xx_i2c_initfn
;
1540 dc
->desc
= "PXA2xx I2C Bus Controller";
1541 dc
->vmsd
= &vmstate_pxa2xx_i2c
;
1542 dc
->props
= pxa2xx_i2c_properties
;
1545 static const TypeInfo pxa2xx_i2c_info
= {
1546 .name
= TYPE_PXA2XX_I2C
,
1547 .parent
= TYPE_SYS_BUS_DEVICE
,
1548 .instance_size
= sizeof(PXA2xxI2CState
),
1549 .class_init
= pxa2xx_i2c_class_init
,
1552 /* PXA Inter-IC Sound Controller */
1553 static void pxa2xx_i2s_reset(PXA2xxI2SState
*i2s
)
1559 i2s
->control
[0] = 0x00;
1560 i2s
->control
[1] = 0x00;
1565 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1566 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1567 #define SACR_DREC(val) (val & (1 << 3))
1568 #define SACR_DPRL(val) (val & (1 << 4))
1570 static inline void pxa2xx_i2s_update(PXA2xxI2SState
*i2s
)
1573 rfs
= SACR_RFTH(i2s
->control
[0]) < i2s
->rx_len
&&
1574 !SACR_DREC(i2s
->control
[1]);
1575 tfs
= (i2s
->tx_len
|| i2s
->fifo_len
< SACR_TFTH(i2s
->control
[0])) &&
1576 i2s
->enable
&& !SACR_DPRL(i2s
->control
[1]);
1578 qemu_set_irq(i2s
->rx_dma
, rfs
);
1579 qemu_set_irq(i2s
->tx_dma
, tfs
);
1581 i2s
->status
&= 0xe0;
1582 if (i2s
->fifo_len
< 16 || !i2s
->enable
)
1583 i2s
->status
|= 1 << 0; /* TNF */
1585 i2s
->status
|= 1 << 1; /* RNE */
1587 i2s
->status
|= 1 << 2; /* BSY */
1589 i2s
->status
|= 1 << 3; /* TFS */
1591 i2s
->status
|= 1 << 4; /* RFS */
1592 if (!(i2s
->tx_len
&& i2s
->enable
))
1593 i2s
->status
|= i2s
->fifo_len
<< 8; /* TFL */
1594 i2s
->status
|= MAX(i2s
->rx_len
, 0xf) << 12; /* RFL */
1596 qemu_set_irq(i2s
->irq
, i2s
->status
& i2s
->mask
);
1599 #define SACR0 0x00 /* Serial Audio Global Control register */
1600 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1601 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1602 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1603 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1604 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1605 #define SADR 0x80 /* Serial Audio Data register */
1607 static uint64_t pxa2xx_i2s_read(void *opaque
, hwaddr addr
,
1610 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1614 return s
->control
[0];
1616 return s
->control
[1];
1626 if (s
->rx_len
> 0) {
1628 pxa2xx_i2s_update(s
);
1629 return s
->codec_in(s
->opaque
);
1633 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1639 static void pxa2xx_i2s_write(void *opaque
, hwaddr addr
,
1640 uint64_t value
, unsigned size
)
1642 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1647 if (value
& (1 << 3)) /* RST */
1648 pxa2xx_i2s_reset(s
);
1649 s
->control
[0] = value
& 0xff3d;
1650 if (!s
->enable
&& (value
& 1) && s
->tx_len
) { /* ENB */
1651 for (sample
= s
->fifo
; s
->fifo_len
> 0; s
->fifo_len
--, sample
++)
1652 s
->codec_out(s
->opaque
, *sample
);
1653 s
->status
&= ~(1 << 7); /* I2SOFF */
1655 if (value
& (1 << 4)) /* EFWR */
1656 printf("%s: Attempt to use special function\n", __FUNCTION__
);
1657 s
->enable
= (value
& 9) == 1; /* ENB && !RST*/
1658 pxa2xx_i2s_update(s
);
1661 s
->control
[1] = value
& 0x0039;
1662 if (value
& (1 << 5)) /* ENLBF */
1663 printf("%s: Attempt to use loopback function\n", __FUNCTION__
);
1664 if (value
& (1 << 4)) /* DPRL */
1666 pxa2xx_i2s_update(s
);
1669 s
->mask
= value
& 0x0078;
1670 pxa2xx_i2s_update(s
);
1673 s
->status
&= ~(value
& (3 << 5));
1674 pxa2xx_i2s_update(s
);
1677 s
->clk
= value
& 0x007f;
1680 if (s
->tx_len
&& s
->enable
) {
1682 pxa2xx_i2s_update(s
);
1683 s
->codec_out(s
->opaque
, value
);
1684 } else if (s
->fifo_len
< 16) {
1685 s
->fifo
[s
->fifo_len
++] = value
;
1686 pxa2xx_i2s_update(s
);
1690 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1694 static const MemoryRegionOps pxa2xx_i2s_ops
= {
1695 .read
= pxa2xx_i2s_read
,
1696 .write
= pxa2xx_i2s_write
,
1697 .endianness
= DEVICE_NATIVE_ENDIAN
,
1700 static const VMStateDescription vmstate_pxa2xx_i2s
= {
1701 .name
= "pxa2xx_i2s",
1703 .minimum_version_id
= 0,
1704 .minimum_version_id_old
= 0,
1705 .fields
= (VMStateField
[]) {
1706 VMSTATE_UINT32_ARRAY(control
, PXA2xxI2SState
, 2),
1707 VMSTATE_UINT32(status
, PXA2xxI2SState
),
1708 VMSTATE_UINT32(mask
, PXA2xxI2SState
),
1709 VMSTATE_UINT32(clk
, PXA2xxI2SState
),
1710 VMSTATE_INT32(enable
, PXA2xxI2SState
),
1711 VMSTATE_INT32(rx_len
, PXA2xxI2SState
),
1712 VMSTATE_INT32(tx_len
, PXA2xxI2SState
),
1713 VMSTATE_INT32(fifo_len
, PXA2xxI2SState
),
1714 VMSTATE_END_OF_LIST()
1718 static void pxa2xx_i2s_data_req(void *opaque
, int tx
, int rx
)
1720 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1723 /* Signal FIFO errors */
1724 if (s
->enable
&& s
->tx_len
)
1725 s
->status
|= 1 << 5; /* TUR */
1726 if (s
->enable
&& s
->rx_len
)
1727 s
->status
|= 1 << 6; /* ROR */
1729 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1730 * handle the cases where it makes a difference. */
1731 s
->tx_len
= tx
- s
->fifo_len
;
1733 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1735 for (sample
= s
->fifo
; s
->fifo_len
; s
->fifo_len
--, sample
++)
1736 s
->codec_out(s
->opaque
, *sample
);
1737 pxa2xx_i2s_update(s
);
1740 static PXA2xxI2SState
*pxa2xx_i2s_init(MemoryRegion
*sysmem
,
1742 qemu_irq irq
, qemu_irq rx_dma
, qemu_irq tx_dma
)
1744 PXA2xxI2SState
*s
= (PXA2xxI2SState
*)
1745 g_malloc0(sizeof(PXA2xxI2SState
));
1750 s
->data_req
= pxa2xx_i2s_data_req
;
1752 pxa2xx_i2s_reset(s
);
1754 memory_region_init_io(&s
->iomem
, NULL
, &pxa2xx_i2s_ops
, s
,
1755 "pxa2xx-i2s", 0x100000);
1756 memory_region_add_subregion(sysmem
, base
, &s
->iomem
);
1758 vmstate_register(NULL
, base
, &vmstate_pxa2xx_i2s
, s
);
1763 /* PXA Fast Infra-red Communications Port */
1764 struct PXA2xxFIrState
{
1770 CharDriverState
*chr
;
1777 uint8_t rx_fifo
[64];
1780 static void pxa2xx_fir_reset(PXA2xxFIrState
*s
)
1782 s
->control
[0] = 0x00;
1783 s
->control
[1] = 0x00;
1784 s
->control
[2] = 0x00;
1785 s
->status
[0] = 0x00;
1786 s
->status
[1] = 0x00;
1790 static inline void pxa2xx_fir_update(PXA2xxFIrState
*s
)
1792 static const int tresh
[4] = { 8, 16, 32, 0 };
1794 if ((s
->control
[0] & (1 << 4)) && /* RXE */
1795 s
->rx_len
>= tresh
[s
->control
[2] & 3]) /* TRIG */
1796 s
->status
[0] |= 1 << 4; /* RFS */
1798 s
->status
[0] &= ~(1 << 4); /* RFS */
1799 if (s
->control
[0] & (1 << 3)) /* TXE */
1800 s
->status
[0] |= 1 << 3; /* TFS */
1802 s
->status
[0] &= ~(1 << 3); /* TFS */
1804 s
->status
[1] |= 1 << 2; /* RNE */
1806 s
->status
[1] &= ~(1 << 2); /* RNE */
1807 if (s
->control
[0] & (1 << 4)) /* RXE */
1808 s
->status
[1] |= 1 << 0; /* RSY */
1810 s
->status
[1] &= ~(1 << 0); /* RSY */
1812 intr
|= (s
->control
[0] & (1 << 5)) && /* RIE */
1813 (s
->status
[0] & (1 << 4)); /* RFS */
1814 intr
|= (s
->control
[0] & (1 << 6)) && /* TIE */
1815 (s
->status
[0] & (1 << 3)); /* TFS */
1816 intr
|= (s
->control
[2] & (1 << 4)) && /* TRAIL */
1817 (s
->status
[0] & (1 << 6)); /* EOC */
1818 intr
|= (s
->control
[0] & (1 << 2)) && /* TUS */
1819 (s
->status
[0] & (1 << 1)); /* TUR */
1820 intr
|= s
->status
[0] & 0x25; /* FRE, RAB, EIF */
1822 qemu_set_irq(s
->rx_dma
, (s
->status
[0] >> 4) & 1);
1823 qemu_set_irq(s
->tx_dma
, (s
->status
[0] >> 3) & 1);
1825 qemu_set_irq(s
->irq
, intr
&& s
->enable
);
1828 #define ICCR0 0x00 /* FICP Control register 0 */
1829 #define ICCR1 0x04 /* FICP Control register 1 */
1830 #define ICCR2 0x08 /* FICP Control register 2 */
1831 #define ICDR 0x0c /* FICP Data register */
1832 #define ICSR0 0x14 /* FICP Status register 0 */
1833 #define ICSR1 0x18 /* FICP Status register 1 */
1834 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1836 static uint64_t pxa2xx_fir_read(void *opaque
, hwaddr addr
,
1839 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1844 return s
->control
[0];
1846 return s
->control
[1];
1848 return s
->control
[2];
1850 s
->status
[0] &= ~0x01;
1851 s
->status
[1] &= ~0x72;
1854 ret
= s
->rx_fifo
[s
->rx_start
++];
1856 pxa2xx_fir_update(s
);
1859 printf("%s: Rx FIFO underrun.\n", __FUNCTION__
);
1862 return s
->status
[0];
1864 return s
->status
[1] | (1 << 3); /* TNF */
1868 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1874 static void pxa2xx_fir_write(void *opaque
, hwaddr addr
,
1875 uint64_t value64
, unsigned size
)
1877 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1878 uint32_t value
= value64
;
1883 s
->control
[0] = value
;
1884 if (!(value
& (1 << 4))) /* RXE */
1885 s
->rx_len
= s
->rx_start
= 0;
1886 if (!(value
& (1 << 3))) { /* TXE */
1889 s
->enable
= value
& 1; /* ITR */
1892 pxa2xx_fir_update(s
);
1895 s
->control
[1] = value
;
1898 s
->control
[2] = value
& 0x3f;
1899 pxa2xx_fir_update(s
);
1902 if (s
->control
[2] & (1 << 2)) /* TXP */
1906 if (s
->chr
&& s
->enable
&& (s
->control
[0] & (1 << 3))) /* TXE */
1907 qemu_chr_fe_write(s
->chr
, &ch
, 1);
1910 s
->status
[0] &= ~(value
& 0x66);
1911 pxa2xx_fir_update(s
);
1916 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1920 static const MemoryRegionOps pxa2xx_fir_ops
= {
1921 .read
= pxa2xx_fir_read
,
1922 .write
= pxa2xx_fir_write
,
1923 .endianness
= DEVICE_NATIVE_ENDIAN
,
1926 static int pxa2xx_fir_is_empty(void *opaque
)
1928 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1929 return (s
->rx_len
< 64);
1932 static void pxa2xx_fir_rx(void *opaque
, const uint8_t *buf
, int size
)
1934 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1935 if (!(s
->control
[0] & (1 << 4))) /* RXE */
1939 s
->status
[1] |= 1 << 4; /* EOF */
1940 if (s
->rx_len
>= 64) {
1941 s
->status
[1] |= 1 << 6; /* ROR */
1945 if (s
->control
[2] & (1 << 3)) /* RXP */
1946 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = *(buf
++);
1948 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = ~*(buf
++);
1951 pxa2xx_fir_update(s
);
1954 static void pxa2xx_fir_event(void *opaque
, int event
)
1958 static void pxa2xx_fir_save(QEMUFile
*f
, void *opaque
)
1960 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1963 qemu_put_be32(f
, s
->enable
);
1965 qemu_put_8s(f
, &s
->control
[0]);
1966 qemu_put_8s(f
, &s
->control
[1]);
1967 qemu_put_8s(f
, &s
->control
[2]);
1968 qemu_put_8s(f
, &s
->status
[0]);
1969 qemu_put_8s(f
, &s
->status
[1]);
1971 qemu_put_byte(f
, s
->rx_len
);
1972 for (i
= 0; i
< s
->rx_len
; i
++)
1973 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 63]);
1976 static int pxa2xx_fir_load(QEMUFile
*f
, void *opaque
, int version_id
)
1978 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1981 s
->enable
= qemu_get_be32(f
);
1983 qemu_get_8s(f
, &s
->control
[0]);
1984 qemu_get_8s(f
, &s
->control
[1]);
1985 qemu_get_8s(f
, &s
->control
[2]);
1986 qemu_get_8s(f
, &s
->status
[0]);
1987 qemu_get_8s(f
, &s
->status
[1]);
1989 s
->rx_len
= qemu_get_byte(f
);
1991 for (i
= 0; i
< s
->rx_len
; i
++)
1992 s
->rx_fifo
[i
] = qemu_get_byte(f
);
1997 static PXA2xxFIrState
*pxa2xx_fir_init(MemoryRegion
*sysmem
,
1999 qemu_irq irq
, qemu_irq rx_dma
, qemu_irq tx_dma
,
2000 CharDriverState
*chr
)
2002 PXA2xxFIrState
*s
= (PXA2xxFIrState
*)
2003 g_malloc0(sizeof(PXA2xxFIrState
));
2010 pxa2xx_fir_reset(s
);
2012 memory_region_init_io(&s
->iomem
, NULL
, &pxa2xx_fir_ops
, s
, "pxa2xx-fir", 0x1000);
2013 memory_region_add_subregion(sysmem
, base
, &s
->iomem
);
2016 qemu_chr_fe_claim_no_fail(chr
);
2017 qemu_chr_add_handlers(chr
, pxa2xx_fir_is_empty
,
2018 pxa2xx_fir_rx
, pxa2xx_fir_event
, s
);
2021 register_savevm(NULL
, "pxa2xx_fir", 0, 0, pxa2xx_fir_save
,
2022 pxa2xx_fir_load
, s
);
2027 static void pxa2xx_reset(void *opaque
, int line
, int level
)
2029 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
2031 if (level
&& (s
->pm_regs
[PCFR
>> 2] & 0x10)) { /* GPR_EN */
2032 cpu_reset(CPU(s
->cpu
));
2033 /* TODO: reset peripherals */
2037 /* Initialise a PXA270 integrated chip (ARM based core). */
2038 PXA2xxState
*pxa270_init(MemoryRegion
*address_space
,
2039 unsigned int sdram_size
, const char *revision
)
2044 s
= (PXA2xxState
*) g_malloc0(sizeof(PXA2xxState
));
2046 if (revision
&& strncmp(revision
, "pxa27", 5)) {
2047 fprintf(stderr
, "Machine requires a PXA27x processor.\n");
2051 revision
= "pxa270";
2053 s
->cpu
= cpu_arm_init(revision
);
2054 if (s
->cpu
== NULL
) {
2055 fprintf(stderr
, "Unable to find CPU definition\n");
2058 s
->reset
= qemu_allocate_irqs(pxa2xx_reset
, s
, 1)[0];
2060 /* SDRAM & Internal Memory Storage */
2061 memory_region_init_ram(&s
->sdram
, NULL
, "pxa270.sdram", sdram_size
);
2062 vmstate_register_ram_global(&s
->sdram
);
2063 memory_region_add_subregion(address_space
, PXA2XX_SDRAM_BASE
, &s
->sdram
);
2064 memory_region_init_ram(&s
->internal
, NULL
, "pxa270.internal", 0x40000);
2065 vmstate_register_ram_global(&s
->internal
);
2066 memory_region_add_subregion(address_space
, PXA2XX_INTERNAL_BASE
,
2069 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->cpu
);
2071 s
->dma
= pxa27x_dma_init(0x40000000,
2072 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_DMA
));
2074 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2075 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 0),
2076 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 1),
2077 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 2),
2078 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 3),
2079 qdev_get_gpio_in(s
->pic
, PXA27X_PIC_OST_4_11
),
2082 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->cpu
, s
->pic
, 121);
2084 dinfo
= drive_get(IF_SD
, 0, 0);
2086 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2089 s
->mmc
= pxa2xx_mmci_init(address_space
, 0x41100000, dinfo
->bdrv
,
2090 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_MMC
),
2091 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_MMCI
),
2092 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_MMCI
));
2094 for (i
= 0; pxa270_serial
[i
].io_base
; i
++) {
2095 if (serial_hds
[i
]) {
2096 serial_mm_init(address_space
, pxa270_serial
[i
].io_base
, 2,
2097 qdev_get_gpio_in(s
->pic
, pxa270_serial
[i
].irqn
),
2098 14857000 / 16, serial_hds
[i
],
2099 DEVICE_NATIVE_ENDIAN
);
2105 s
->fir
= pxa2xx_fir_init(address_space
, 0x40800000,
2106 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_ICP
),
2107 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_ICP
),
2108 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_ICP
),
2111 s
->lcd
= pxa2xx_lcdc_init(address_space
, 0x44000000,
2112 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_LCD
));
2114 s
->cm_base
= 0x41300000;
2115 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2116 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2117 memory_region_init_io(&s
->cm_iomem
, NULL
, &pxa2xx_cm_ops
, s
, "pxa2xx-cm", 0x1000);
2118 memory_region_add_subregion(address_space
, s
->cm_base
, &s
->cm_iomem
);
2119 vmstate_register(NULL
, 0, &vmstate_pxa2xx_cm
, s
);
2121 pxa2xx_setup_cp14(s
);
2123 s
->mm_base
= 0x48000000;
2124 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2125 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2126 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2127 memory_region_init_io(&s
->mm_iomem
, NULL
, &pxa2xx_mm_ops
, s
, "pxa2xx-mm", 0x1000);
2128 memory_region_add_subregion(address_space
, s
->mm_base
, &s
->mm_iomem
);
2129 vmstate_register(NULL
, 0, &vmstate_pxa2xx_mm
, s
);
2131 s
->pm_base
= 0x40f00000;
2132 memory_region_init_io(&s
->pm_iomem
, NULL
, &pxa2xx_pm_ops
, s
, "pxa2xx-pm", 0x100);
2133 memory_region_add_subregion(address_space
, s
->pm_base
, &s
->pm_iomem
);
2134 vmstate_register(NULL
, 0, &vmstate_pxa2xx_pm
, s
);
2136 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++);
2137 s
->ssp
= (SSIBus
**)g_malloc0(sizeof(SSIBus
*) * i
);
2138 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++) {
2140 dev
= sysbus_create_simple(TYPE_PXA2XX_SSP
, pxa27x_ssp
[i
].io_base
,
2141 qdev_get_gpio_in(s
->pic
, pxa27x_ssp
[i
].irqn
));
2142 s
->ssp
[i
] = (SSIBus
*)qdev_get_child_bus(dev
, "ssi");
2145 if (usb_enabled(false)) {
2146 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2147 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_USBH1
));
2150 s
->pcmcia
[0] = pxa2xx_pcmcia_init(address_space
, 0x20000000);
2151 s
->pcmcia
[1] = pxa2xx_pcmcia_init(address_space
, 0x30000000);
2153 sysbus_create_simple(TYPE_PXA2XX_RTC
, 0x40900000,
2154 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_RTCALARM
));
2156 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600,
2157 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2C
), 0xffff);
2158 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100,
2159 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_PWRI2C
), 0xff);
2161 s
->i2s
= pxa2xx_i2s_init(address_space
, 0x40400000,
2162 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2S
),
2163 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_I2S
),
2164 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_I2S
));
2166 s
->kp
= pxa27x_keypad_init(address_space
, 0x41500000,
2167 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_KEYPAD
));
2169 /* GPIO1 resets the processor */
2170 /* The handler can be overridden by board-specific code */
2171 qdev_connect_gpio_out(s
->gpio
, 1, s
->reset
);
2175 /* Initialise a PXA255 integrated chip (ARM based core). */
2176 PXA2xxState
*pxa255_init(MemoryRegion
*address_space
, unsigned int sdram_size
)
2182 s
= (PXA2xxState
*) g_malloc0(sizeof(PXA2xxState
));
2184 s
->cpu
= cpu_arm_init("pxa255");
2185 if (s
->cpu
== NULL
) {
2186 fprintf(stderr
, "Unable to find CPU definition\n");
2189 s
->reset
= qemu_allocate_irqs(pxa2xx_reset
, s
, 1)[0];
2191 /* SDRAM & Internal Memory Storage */
2192 memory_region_init_ram(&s
->sdram
, NULL
, "pxa255.sdram", sdram_size
);
2193 vmstate_register_ram_global(&s
->sdram
);
2194 memory_region_add_subregion(address_space
, PXA2XX_SDRAM_BASE
, &s
->sdram
);
2195 memory_region_init_ram(&s
->internal
, NULL
, "pxa255.internal",
2196 PXA2XX_INTERNAL_SIZE
);
2197 vmstate_register_ram_global(&s
->internal
);
2198 memory_region_add_subregion(address_space
, PXA2XX_INTERNAL_BASE
,
2201 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->cpu
);
2203 s
->dma
= pxa255_dma_init(0x40000000,
2204 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_DMA
));
2206 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2207 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 0),
2208 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 1),
2209 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 2),
2210 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 3),
2213 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->cpu
, s
->pic
, 85);
2215 dinfo
= drive_get(IF_SD
, 0, 0);
2217 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2220 s
->mmc
= pxa2xx_mmci_init(address_space
, 0x41100000, dinfo
->bdrv
,
2221 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_MMC
),
2222 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_MMCI
),
2223 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_MMCI
));
2225 for (i
= 0; pxa255_serial
[i
].io_base
; i
++) {
2226 if (serial_hds
[i
]) {
2227 serial_mm_init(address_space
, pxa255_serial
[i
].io_base
, 2,
2228 qdev_get_gpio_in(s
->pic
, pxa255_serial
[i
].irqn
),
2229 14745600 / 16, serial_hds
[i
],
2230 DEVICE_NATIVE_ENDIAN
);
2236 s
->fir
= pxa2xx_fir_init(address_space
, 0x40800000,
2237 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_ICP
),
2238 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_ICP
),
2239 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_ICP
),
2242 s
->lcd
= pxa2xx_lcdc_init(address_space
, 0x44000000,
2243 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_LCD
));
2245 s
->cm_base
= 0x41300000;
2246 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2247 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2248 memory_region_init_io(&s
->cm_iomem
, NULL
, &pxa2xx_cm_ops
, s
, "pxa2xx-cm", 0x1000);
2249 memory_region_add_subregion(address_space
, s
->cm_base
, &s
->cm_iomem
);
2250 vmstate_register(NULL
, 0, &vmstate_pxa2xx_cm
, s
);
2252 pxa2xx_setup_cp14(s
);
2254 s
->mm_base
= 0x48000000;
2255 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2256 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2257 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2258 memory_region_init_io(&s
->mm_iomem
, NULL
, &pxa2xx_mm_ops
, s
, "pxa2xx-mm", 0x1000);
2259 memory_region_add_subregion(address_space
, s
->mm_base
, &s
->mm_iomem
);
2260 vmstate_register(NULL
, 0, &vmstate_pxa2xx_mm
, s
);
2262 s
->pm_base
= 0x40f00000;
2263 memory_region_init_io(&s
->pm_iomem
, NULL
, &pxa2xx_pm_ops
, s
, "pxa2xx-pm", 0x100);
2264 memory_region_add_subregion(address_space
, s
->pm_base
, &s
->pm_iomem
);
2265 vmstate_register(NULL
, 0, &vmstate_pxa2xx_pm
, s
);
2267 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++);
2268 s
->ssp
= (SSIBus
**)g_malloc0(sizeof(SSIBus
*) * i
);
2269 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++) {
2271 dev
= sysbus_create_simple(TYPE_PXA2XX_SSP
, pxa255_ssp
[i
].io_base
,
2272 qdev_get_gpio_in(s
->pic
, pxa255_ssp
[i
].irqn
));
2273 s
->ssp
[i
] = (SSIBus
*)qdev_get_child_bus(dev
, "ssi");
2276 if (usb_enabled(false)) {
2277 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2278 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_USBH1
));
2281 s
->pcmcia
[0] = pxa2xx_pcmcia_init(address_space
, 0x20000000);
2282 s
->pcmcia
[1] = pxa2xx_pcmcia_init(address_space
, 0x30000000);
2284 sysbus_create_simple(TYPE_PXA2XX_RTC
, 0x40900000,
2285 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_RTCALARM
));
2287 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600,
2288 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2C
), 0xffff);
2289 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100,
2290 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_PWRI2C
), 0xff);
2292 s
->i2s
= pxa2xx_i2s_init(address_space
, 0x40400000,
2293 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2S
),
2294 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_I2S
),
2295 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_I2S
));
2297 /* GPIO1 resets the processor */
2298 /* The handler can be overridden by board-specific code */
2299 qdev_connect_gpio_out(s
->gpio
, 1, s
->reset
);
2303 static void pxa2xx_ssp_class_init(ObjectClass
*klass
, void *data
)
2305 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
2307 sdc
->init
= pxa2xx_ssp_init
;
2310 static const TypeInfo pxa2xx_ssp_info
= {
2311 .name
= TYPE_PXA2XX_SSP
,
2312 .parent
= TYPE_SYS_BUS_DEVICE
,
2313 .instance_size
= sizeof(PXA2xxSSPState
),
2314 .class_init
= pxa2xx_ssp_class_init
,
2317 static void pxa2xx_register_types(void)
2319 type_register_static(&pxa2xx_i2c_slave_info
);
2320 type_register_static(&pxa2xx_ssp_info
);
2321 type_register_static(&pxa2xx_i2c_info
);
2322 type_register_static(&pxa2xx_rtc_sysbus_info
);
2325 type_init(pxa2xx_register_types
)