hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "acpi.h"
  24 #include "sysemu.h"
  25
  26 //#define DEBUG
  27
  28 #ifdef DEBUG
  29 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  30 #else
  31 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  32 #endif
  33
  34 #define ACPI_DBG_IO_ADDR  0xb044
  35
  36 #define GPE_BASE 0xafe0
  37 #define PCI_BASE 0xae00
  38 #define PCI_EJ_BASE 0xae08
  39
  40 struct gpe_regs {
  41     uint16_t sts; /* status */
  42     uint16_t en;  /* enabled */
  43 };
  44
  45 struct pci_status {
  46     uint32_t up;
  47     uint32_t down;
  48 };
  49
  50 typedef struct PIIX4PMState {
  51     PCIDevice dev;
  52     uint16_t pmsts;
  53     uint16_t pmen;
  54     uint16_t pmcntrl;
  55
  56     APMState apm;
  57
  58     QEMUTimer *tmr_timer;
  59     int64_t tmr_overflow_time;
  60
  61     PMSMBus smb;
  62     uint32_t smb_io_base;
  63
  64     qemu_irq irq;
  65     qemu_irq cmos_s3;
  66     qemu_irq smi_irq;
  67     int kvm_enabled;
  68
  69     /* for pci hotplug */
  70     struct gpe_regs gpe;
  71     struct pci_status pci0_status;
  72 } PIIX4PMState;
  73
  74 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  75
  76 #define ACPI_ENABLE 0xf1
  77 #define ACPI_DISABLE 0xf0
  78
  79 static uint32_t get_pmtmr(PIIX4PMState *s)
  80 {
  81     uint32_t d;
  82     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
  83     return d & 0xffffff;
  84 }
  85
  86 static int get_pmsts(PIIX4PMState *s)
  87 {
  88     int64_t d;
  89
  90     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
  91                  get_ticks_per_sec());
  92     if (d >= s->tmr_overflow_time)
  93         s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
  94     return s->pmsts;
  95 }
  96
  97 static void pm_update_sci(PIIX4PMState *s)
  98 {
  99     int sci_level, pmsts;
 100     int64_t expire_time;
 101
 102     pmsts = get_pmsts(s);
 103     sci_level = (((pmsts & s->pmen) &
 104                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 105                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 106                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 107                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
 108     qemu_set_irq(s->irq, sci_level);
 109     /* schedule a timer interruption if needed */
 110     if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
 111         !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
 112         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
 113                                PM_TIMER_FREQUENCY);
 114         qemu_mod_timer(s->tmr_timer, expire_time);
 115     } else {
 116         qemu_del_timer(s->tmr_timer);
 117     }
 118 }
 119
 120 static void pm_tmr_timer(void *opaque)
 121 {
 122     PIIX4PMState *s = opaque;
 123     pm_update_sci(s);
 124 }
 125
 126 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 127 {
 128     PIIX4PMState *s = opaque;
 129     addr &= 0x3f;
 130     switch(addr) {
 131     case 0x00:
 132         {
 133             int64_t d;
 134             int pmsts;
 135             pmsts = get_pmsts(s);
 136             if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
 137                 /* if TMRSTS is reset, then compute the new overflow time */
 138                 d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
 139                              get_ticks_per_sec());
 140                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 141             }
 142             s->pmsts &= ~val;
 143             pm_update_sci(s);
 144         }
 145         break;
 146     case 0x02:
 147         s->pmen = val;
 148         pm_update_sci(s);
 149         break;
 150     case 0x04:
 151         {
 152             int sus_typ;
 153             s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
 154             if (val & ACPI_BITMASK_SLEEP_ENABLE) {
 155                 /* change suspend type */
 156                 sus_typ = (val >> 10) & 7;
 157                 switch(sus_typ) {
 158                 case 0: /* soft power off */
 159                     qemu_system_shutdown_request();
 160                     break;
 161                 case 1:
 162                     /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
 163                        Pretend that resume was caused by power button */
 164                     s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
 165                                  ACPI_BITMASK_POWER_BUTTON_STATUS);
 166                     qemu_system_reset_request();
 167                     if (s->cmos_s3) {
 168                         qemu_irq_raise(s->cmos_s3);
 169                     }
 170                 default:
 171                     break;
 172                 }
 173             }
 174         }
 175         break;
 176     default:
 177         break;
 178     }
 179     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
 180 }
 181
 182 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 183 {
 184     PIIX4PMState *s = opaque;
 185     uint32_t val;
 186
 187     addr &= 0x3f;
 188     switch(addr) {
 189     case 0x00:
 190         val = get_pmsts(s);
 191         break;
 192     case 0x02:
 193         val = s->pmen;
 194         break;
 195     case 0x04:
 196         val = s->pmcntrl;
 197         break;
 198     default:
 199         val = 0;
 200         break;
 201     }
 202     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
 203     return val;
 204 }
 205
 206 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 207 {
 208     //    PIIX4PMState *s = opaque;
 209     PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val);
 210 }
 211
 212 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 213 {
 214     PIIX4PMState *s = opaque;
 215     uint32_t val;
 216
 217     addr &= 0x3f;
 218     switch(addr) {
 219     case 0x08:
 220         val = get_pmtmr(s);
 221         break;
 222     default:
 223         val = 0;
 224         break;
 225     }
 226     PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
 227     return val;
 228 }
 229
 230 static void apm_ctrl_changed(uint32_t val, void *arg)
 231 {
 232     PIIX4PMState *s = arg;
 233
 234     /* ACPI specs 3.0, 4.7.2.5 */
 235     if (val == ACPI_ENABLE) {
 236         s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
 237     } else if (val == ACPI_DISABLE) {
 238         s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
 239     }
 240
 241     if (s->dev.config[0x5b] & (1 << 1)) {
 242         if (s->smi_irq) {
 243             qemu_irq_raise(s->smi_irq);
 244         }
 245     }
 246 }
 247
 248 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 249 {
 250     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 251 }
 252
 253 static void pm_io_space_update(PIIX4PMState *s)
 254 {
 255     uint32_t pm_io_base;
 256
 257     if (s->dev.config[0x80] & 1) {
 258         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 259         pm_io_base &= 0xffc0;
 260
 261         /* XXX: need to improve memory and ioport allocation */
 262         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 263         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 264         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 265         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 266         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 267     }
 268 }
 269
 270 static void pm_write_config(PCIDevice *d,
 271                             uint32_t address, uint32_t val, int len)
 272 {
 273     pci_default_write_config(d, address, val, len);
 274     if (range_covers_byte(address, len, 0x80))
 275         pm_io_space_update((PIIX4PMState *)d);
 276 }
 277
 278 static int vmstate_acpi_post_load(void *opaque, int version_id)
 279 {
 280     PIIX4PMState *s = opaque;
 281
 282     pm_io_space_update(s);
 283     return 0;
 284 }
 285
 286 static const VMStateDescription vmstate_acpi = {
 287     .name = "piix4_pm",
 288     .version_id = 1,
 289     .minimum_version_id = 1,
 290     .minimum_version_id_old = 1,
 291     .post_load = vmstate_acpi_post_load,
 292     .fields      = (VMStateField []) {
 293         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 294         VMSTATE_UINT16(pmsts, PIIX4PMState),
 295         VMSTATE_UINT16(pmen, PIIX4PMState),
 296         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 297         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 298         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 299         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 300         VMSTATE_END_OF_LIST()
 301     }
 302 };
 303
 304 static void piix4_reset(void *opaque)
 305 {
 306     PIIX4PMState *s = opaque;
 307     uint8_t *pci_conf = s->dev.config;
 308
 309     pci_conf[0x58] = 0;
 310     pci_conf[0x59] = 0;
 311     pci_conf[0x5a] = 0;
 312     pci_conf[0x5b] = 0;
 313
 314     if (s->kvm_enabled) {
 315         /* Mark SMM as already inited (until KVM supports SMM). */
 316         pci_conf[0x5B] = 0x02;
 317     }
 318 }
 319
 320 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 321 {
 322     PIIX4PMState *s = opaque;
 323
 324     if (!s) {
 325         qemu_system_shutdown_request();
 326     } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
 327         s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
 328         pm_update_sci(s);
 329     }
 330 }
 331
 332 static int piix4_pm_initfn(PCIDevice *dev)
 333 {
 334     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 335     uint8_t *pci_conf;
 336
 337     pci_conf = s->dev.config;
 338     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 339     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 340     pci_conf[0x06] = 0x80;
 341     pci_conf[0x07] = 0x02;
 342     pci_conf[0x08] = 0x03; // revision number
 343     pci_conf[0x09] = 0x00;
 344     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 345     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 346     pci_conf[0x3d] = 0x01; // interrupt pin 1
 347
 348     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 349
 350     /* APM */
 351     apm_init(&s->apm, apm_ctrl_changed, s);
 352
 353     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 354
 355     if (s->kvm_enabled) {
 356         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 357          * support SMM mode. */
 358         pci_conf[0x5B] = 0x02;
 359     }
 360
 361     /* XXX: which specification is used ? The i82731AB has different
 362        mappings */
 363     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 364     pci_conf[0x63] = 0x60;
 365     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 366         (serial_hds[1] != NULL ? 0x90 : 0);
 367
 368     pci_conf[0x90] = s->smb_io_base | 1;
 369     pci_conf[0x91] = s->smb_io_base >> 8;
 370     pci_conf[0xd2] = 0x09;
 371     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 372     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 373
 374     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 375
 376     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 377
 378     pm_smbus_init(&s->dev.qdev, &s->smb);
 379     qemu_register_reset(piix4_reset, s);
 380     piix4_acpi_system_hot_add_init(dev->bus, s);
 381
 382     return 0;
 383 }
 384
 385 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 386                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 387                        int kvm_enabled)
 388 {
 389     PCIDevice *dev;
 390     PIIX4PMState *s;
 391
 392     dev = pci_create(bus, devfn, "PIIX4_PM");
 393     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 394
 395     s = DO_UPCAST(PIIX4PMState, dev, dev);
 396     s->irq = sci_irq;
 397     s->cmos_s3 = cmos_s3;
 398     s->smi_irq = smi_irq;
 399     s->kvm_enabled = kvm_enabled;
 400
 401     qdev_init_nofail(&dev->qdev);
 402
 403     return s->smb.smbus;
 404 }
 405
 406 static PCIDeviceInfo piix4_pm_info = {
 407     .qdev.name          = "PIIX4_PM",
 408     .qdev.desc          = "PM",
 409     .qdev.size          = sizeof(PIIX4PMState),
 410     .qdev.vmsd          = &vmstate_acpi,
 411     .init               = piix4_pm_initfn,
 412     .config_write       = pm_write_config,
 413     .qdev.props         = (Property[]) {
 414         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 415         DEFINE_PROP_END_OF_LIST(),
 416     }
 417 };
 418
 419 static void piix4_pm_register(void)
 420 {
 421     pci_qdev_register(&piix4_pm_info);
 422 }
 423
 424 device_init(piix4_pm_register);
 425
 426 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 427 {
 428     if (addr & 1)
 429         return (val >> 8) & 0xff;
 430     return val & 0xff;
 431 }
 432
 433 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 434 {
 435     uint32_t val = 0;
 436     struct gpe_regs *g = opaque;
 437     switch (addr) {
 438         case GPE_BASE:
 439         case GPE_BASE + 1:
 440             val = gpe_read_val(g->sts, addr);
 441             break;
 442         case GPE_BASE + 2:
 443         case GPE_BASE + 3:
 444             val = gpe_read_val(g->en, addr);
 445             break;
 446         default:
 447             break;
 448     }
 449
 450     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 451     return val;
 452 }
 453
 454 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 455 {
 456     if (addr & 1)
 457         *cur = (*cur & 0xff) | (val << 8);
 458     else
 459         *cur = (*cur & 0xff00) | (val & 0xff);
 460 }
 461
 462 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 463 {
 464     uint16_t x1, x0 = val & 0xff;
 465     int shift = (addr & 1) ? 8 : 0;
 466
 467     x1 = (*cur >> shift) & 0xff;
 468
 469     x1 = x1 & ~x0;
 470
 471     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 472 }
 473
 474 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 475 {
 476     struct gpe_regs *g = opaque;
 477     switch (addr) {
 478         case GPE_BASE:
 479         case GPE_BASE + 1:
 480             gpe_reset_val(&g->sts, addr, val);
 481             break;
 482         case GPE_BASE + 2:
 483         case GPE_BASE + 3:
 484             gpe_write_val(&g->en, addr, val);
 485             break;
 486         default:
 487             break;
 488    }
 489
 490     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 491 }
 492
 493 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 494 {
 495     uint32_t val = 0;
 496     struct pci_status *g = opaque;
 497     switch (addr) {
 498         case PCI_BASE:
 499             val = g->up;
 500             break;
 501         case PCI_BASE + 4:
 502             val = g->down;
 503             break;
 504         default:
 505             break;
 506     }
 507
 508     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
 509     return val;
 510 }
 511
 512 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 513 {
 514     struct pci_status *g = opaque;
 515     switch (addr) {
 516         case PCI_BASE:
 517             g->up = val;
 518             break;
 519         case PCI_BASE + 4:
 520             g->down = val;
 521             break;
 522    }
 523
 524     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 525 }
 526
 527 static uint32_t pciej_read(void *opaque, uint32_t addr)
 528 {
 529     PIIX4_DPRINTF("pciej read %x\n", addr);
 530     return 0;
 531 }
 532
 533 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 534 {
 535     BusState *bus = opaque;
 536     DeviceState *qdev, *next;
 537     PCIDevice *dev;
 538     int slot = ffs(val) - 1;
 539
 540     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 541         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 542         if (PCI_SLOT(dev->devfn) == slot) {
 543             qdev_free(qdev);
 544         }
 545     }
 546
 547
 548     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 549 }
 550
 551 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state);
 552
 553 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 554 {
 555     struct gpe_regs *gpe = &s->gpe;
 556     struct pci_status *pci0_status = &s->pci0_status;
 557
 558     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, gpe);
 559     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, gpe);
 560
 561     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
 562     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 563
 564     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 565     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 566
 567     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 568 }
 569
 570 static void enable_device(PIIX4PMState *s, int slot)
 571 {
 572     s->gpe.sts |= 2;
 573     s->pci0_status.up |= (1 << slot);
 574 }
 575
 576 static void disable_device(PIIX4PMState *s, int slot)
 577 {
 578     s->gpe.sts |= 2;
 579     s->pci0_status.down |= (1 << slot);
 580 }
 581
 582 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state)
 583 {
 584     int slot = PCI_SLOT(dev->devfn);
 585     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 586                                 DO_UPCAST(PCIDevice, qdev, qdev));
 587
 588     s->pci0_status.up = 0;
 589     s->pci0_status.down = 0;
 590     if (state) {
 591         enable_device(s, slot);
 592     } else {
 593         disable_device(s, slot);
 594     }
 595     if (s->gpe.en & 2) {
 596         qemu_set_irq(s->irq, 1);
 597         qemu_set_irq(s->irq, 0);
 598     }
 599     return 0;
 600 }