hw/sh_pci.c

   1 /*
   2  * SuperH on-chip PCIC emulation.
   3  *
   4  * Copyright (c) 2008 Takashi YOSHII
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sh.h"
  26 #include "pci.h"
  27 #include "bswap.h"
  28
  29 typedef struct {
  30     PCIBus *bus;
  31     PCIDevice *dev;
  32     uint32_t par;
  33     uint32_t mbr;
  34     uint32_t iobr;
  35 } SHPCIC;
  36
  37 static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
  38 {
  39     SHPCIC *pcic = p;
  40     switch(addr) {
  41     case 0 ... 0xfc:
  42         cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
  43         break;
  44     case 0x1c0:
  45         pcic->par = val;
  46         break;
  47     case 0x1c4:
  48         pcic->mbr = val;
  49         break;
  50     case 0x1c8:
  51         pcic->iobr = val;
  52         break;
  53     case 0x220:
  54         pci_data_write(pcic->bus, pcic->par, val, 4);
  55         break;
  56     }
  57 }
  58
  59 static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
  60 {
  61     SHPCIC *pcic = p;
  62     switch(addr) {
  63     case 0 ... 0xfc:
  64         return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
  65     case 0x1c0:
  66         return pcic->par;
  67     case 0x220:
  68         return pci_data_read(pcic->bus, pcic->par, 4);
  69     }
  70     return 0;
  71 }
  72
  73 static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr,
  74                                uint32_t val, int size)
  75 {
  76     pci_data_write(pcic->bus, addr + pcic->mbr, val, size);
  77 }
  78
  79 static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr,
  80                                  int size)
  81 {
  82     return pci_data_read(pcic->bus, addr + pcic->mbr, size);
  83 }
  84
  85 static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val)
  86 {
  87     sh_pci_data_write(p, addr, val, 1);
  88 }
  89
  90 static void sh_pci_writew (void *p, target_phys_addr_t addr, uint32_t val)
  91 {
  92     sh_pci_data_write(p, addr, val, 2);
  93 }
  94
  95 static void sh_pci_writel (void *p, target_phys_addr_t addr, uint32_t val)
  96 {
  97     sh_pci_data_write(p, addr, val, 4);
  98 }
  99
 100 static uint32_t sh_pci_readb (void *p, target_phys_addr_t addr)
 101 {
 102     return sh_pci_mem_read(p, addr, 1);
 103 }
 104
 105 static uint32_t sh_pci_readw (void *p, target_phys_addr_t addr)
 106 {
 107     return sh_pci_mem_read(p, addr, 2);
 108 }
 109
 110 static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr)
 111 {
 112     return sh_pci_mem_read(p, addr, 4);
 113 }
 114
 115 static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr)
 116 {
 117     return addr + pcic->iobr;
 118 }
 119
 120 static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val)
 121 {
 122     cpu_outb(NULL, sh_pci_addr2port(p, addr), val);
 123 }
 124
 125 static void sh_pci_outw (void *p, target_phys_addr_t addr, uint32_t val)
 126 {
 127     cpu_outw(NULL, sh_pci_addr2port(p, addr), val);
 128 }
 129
 130 static void sh_pci_outl (void *p, target_phys_addr_t addr, uint32_t val)
 131 {
 132     cpu_outl(NULL, sh_pci_addr2port(p, addr), val);
 133 }
 134
 135 static uint32_t sh_pci_inb (void *p, target_phys_addr_t addr)
 136 {
 137     return cpu_inb(NULL, sh_pci_addr2port(p, addr));
 138 }
 139
 140 static uint32_t sh_pci_inw (void *p, target_phys_addr_t addr)
 141 {
 142     return cpu_inw(NULL, sh_pci_addr2port(p, addr));
 143 }
 144
 145 static uint32_t sh_pci_inl (void *p, target_phys_addr_t addr)
 146 {
 147     return cpu_inl(NULL, sh_pci_addr2port(p, addr));
 148 }
 149
 150 typedef struct {
 151     CPUReadMemoryFunc * const r[3];
 152     CPUWriteMemoryFunc * const w[3];
 153 } MemOp;
 154
 155 static MemOp sh_pci_reg = {
 156     { NULL, NULL, sh_pci_reg_read },
 157     { NULL, NULL, sh_pci_reg_write },
 158 };
 159
 160 static MemOp sh_pci_mem = {
 161     { sh_pci_readb, sh_pci_readw, sh_pci_readl },
 162     { sh_pci_writeb, sh_pci_writew, sh_pci_writel },
 163 };
 164
 165 static MemOp sh_pci_iop = {
 166     { sh_pci_inb, sh_pci_inw, sh_pci_inl },
 167     { sh_pci_outb, sh_pci_outw, sh_pci_outl },
 168 };
 169
 170 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 171                             void *opaque, int devfn_min, int nirq)
 172 {
 173     SHPCIC *p;
 174     int mem, reg, iop;
 175
 176     p = qemu_mallocz(sizeof(SHPCIC));
 177     p->bus = pci_register_bus(NULL, "pci",
 178                               set_irq, map_irq, opaque, devfn_min, nirq);
 179
 180     p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
 181                                  -1, NULL, NULL);
 182     reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p);
 183     iop = cpu_register_io_memory(sh_pci_iop.r, sh_pci_iop.w, p);
 184     mem = cpu_register_io_memory(sh_pci_mem.r, sh_pci_mem.w, p);
 185     cpu_register_physical_memory(0x1e200000, 0x224, reg);
 186     cpu_register_physical_memory(0x1e240000, 0x40000, iop);
 187     cpu_register_physical_memory(0x1d000000, 0x1000000, mem);
 188     cpu_register_physical_memory(0xfe200000, 0x224, reg);
 189     cpu_register_physical_memory(0xfe240000, 0x40000, iop);
 190     cpu_register_physical_memory(0xfd000000, 0x1000000, mem);
 191
 192     pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI);
 193     pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R);
 194     p->dev->config[0x04] = 0x80;
 195     p->dev->config[0x05] = 0x00;
 196     p->dev->config[0x06] = 0x90;
 197     p->dev->config[0x07] = 0x02;
 198
 199     return p->bus;
 200 }