hw/timer/tusb6010.c

   1 /*
   2  * Texas Instruments TUSB6010 emulation.
   3  * Based on reverse-engineering of a linux driver.
   4  *
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Written by Andrzej Zaborowski <andrew@openedhand.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 or
  11  * (at your option) version 3 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21 #include "qemu-common.h"
  22 #include "qemu/timer.h"
  23 #include "hw/usb.h"
  24 #include "hw/arm/omap.h"
  25 #include "hw/irq.h"
  26 #include "hw/devices.h"
  27 #include "hw/sysbus.h"
  28
  29 #define TYPE_TUSB6010 "tusb6010"
  30 #define TUSB(obj) OBJECT_CHECK(TUSBState, (obj), TYPE_TUSB6010)
  31
  32 typedef struct TUSBState {
  33     SysBusDevice parent_obj;
  34
  35     MemoryRegion iomem[2];
  36     qemu_irq irq;
  37     MUSBState *musb;
  38     QEMUTimer *otg_timer;
  39     QEMUTimer *pwr_timer;
  40
  41     int power;
  42     uint32_t scratch;
  43     uint16_t test_reset;
  44     uint32_t prcm_config;
  45     uint32_t prcm_mngmt;
  46     uint16_t otg_status;
  47     uint32_t dev_config;
  48     int host_mode;
  49     uint32_t intr;
  50     uint32_t intr_ok;
  51     uint32_t mask;
  52     uint32_t usbip_intr;
  53     uint32_t usbip_mask;
  54     uint32_t gpio_intr;
  55     uint32_t gpio_mask;
  56     uint32_t gpio_config;
  57     uint32_t dma_intr;
  58     uint32_t dma_mask;
  59     uint32_t dma_map;
  60     uint32_t dma_config;
  61     uint32_t ep0_config;
  62     uint32_t rx_config[15];
  63     uint32_t tx_config[15];
  64     uint32_t wkup_mask;
  65     uint32_t pullup[2];
  66     uint32_t control_config;
  67     uint32_t otg_timer_val;
  68 } TUSBState;
  69
  70 #define TUSB_DEVCLOCK                   60000000        /* 60 MHz */
  71
  72 #define TUSB_VLYNQ_CTRL                 0x004
  73
  74 /* Mentor Graphics OTG core registers.  */
  75 #define TUSB_BASE_OFFSET                0x400
  76
  77 /* FIFO registers, 32-bit.  */
  78 #define TUSB_FIFO_BASE                  0x600
  79
  80 /* Device System & Control registers, 32-bit.  */
  81 #define TUSB_SYS_REG_BASE               0x800
  82
  83 #define TUSB_DEV_CONF                   (TUSB_SYS_REG_BASE + 0x000)
  84 #define TUSB_DEV_CONF_USB_HOST_MODE     (1 << 16)
  85 #define TUSB_DEV_CONF_PROD_TEST_MODE    (1 << 15)
  86 #define TUSB_DEV_CONF_SOFT_ID           (1 << 1)
  87 #define TUSB_DEV_CONF_ID_SEL            (1 << 0)
  88
  89 #define TUSB_PHY_OTG_CTRL_ENABLE        (TUSB_SYS_REG_BASE + 0x004)
  90 #define TUSB_PHY_OTG_CTRL               (TUSB_SYS_REG_BASE + 0x008)
  91 #define TUSB_PHY_OTG_CTRL_WRPROTECT     (0xa5 << 24)
  92 #define TUSB_PHY_OTG_CTRL_O_ID_PULLUP   (1 << 23)
  93 #define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19)
  94 #define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18)
  95 #define TUSB_PHY_OTG_CTRL_TESTM2        (1 << 17)
  96 #define TUSB_PHY_OTG_CTRL_TESTM1        (1 << 16)
  97 #define TUSB_PHY_OTG_CTRL_TESTM0        (1 << 15)
  98 #define TUSB_PHY_OTG_CTRL_TX_DATA2      (1 << 14)
  99 #define TUSB_PHY_OTG_CTRL_TX_GZ2        (1 << 13)
 100 #define TUSB_PHY_OTG_CTRL_TX_ENABLE2    (1 << 12)
 101 #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN   (1 << 11)
 102 #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN   (1 << 10)
 103 #define TUSB_PHY_OTG_CTRL_OSC_EN        (1 << 9)
 104 #define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7)
 105 #define TUSB_PHY_OTG_CTRL_PD            (1 << 6)
 106 #define TUSB_PHY_OTG_CTRL_PLL_ON        (1 << 5)
 107 #define TUSB_PHY_OTG_CTRL_EXT_RPU       (1 << 4)
 108 #define TUSB_PHY_OTG_CTRL_PWR_GOOD      (1 << 3)
 109 #define TUSB_PHY_OTG_CTRL_RESET         (1 << 2)
 110 #define TUSB_PHY_OTG_CTRL_SUSPENDM      (1 << 1)
 111 #define TUSB_PHY_OTG_CTRL_CLK_MODE      (1 << 0)
 112
 113 /* OTG status register */
 114 #define TUSB_DEV_OTG_STAT               (TUSB_SYS_REG_BASE + 0x00c)
 115 #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD  (1 << 8)
 116 #define TUSB_DEV_OTG_STAT_SESS_END      (1 << 7)
 117 #define TUSB_DEV_OTG_STAT_SESS_VALID    (1 << 6)
 118 #define TUSB_DEV_OTG_STAT_VBUS_VALID    (1 << 5)
 119 #define TUSB_DEV_OTG_STAT_VBUS_SENSE    (1 << 4)
 120 #define TUSB_DEV_OTG_STAT_ID_STATUS     (1 << 3)
 121 #define TUSB_DEV_OTG_STAT_HOST_DISCON   (1 << 2)
 122 #define TUSB_DEV_OTG_STAT_LINE_STATE    (3 << 0)
 123 #define TUSB_DEV_OTG_STAT_DP_ENABLE     (1 << 1)
 124 #define TUSB_DEV_OTG_STAT_DM_ENABLE     (1 << 0)
 125
 126 #define TUSB_DEV_OTG_TIMER              (TUSB_SYS_REG_BASE + 0x010)
 127 #define TUSB_DEV_OTG_TIMER_ENABLE       (1 << 31)
 128 #define TUSB_DEV_OTG_TIMER_VAL(v)       ((v) & 0x07ffffff)
 129 #define TUSB_PRCM_REV                   (TUSB_SYS_REG_BASE + 0x014)
 130
 131 /* PRCM configuration register */
 132 #define TUSB_PRCM_CONF                  (TUSB_SYS_REG_BASE + 0x018)
 133 #define TUSB_PRCM_CONF_SFW_CPEN         (1 << 24)
 134 #define TUSB_PRCM_CONF_SYS_CLKSEL(v)    (((v) & 3) << 16)
 135
 136 /* PRCM management register */
 137 #define TUSB_PRCM_MNGMT                 (TUSB_SYS_REG_BASE + 0x01c)
 138 #define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v)  (((v) & 0xf) << 25)
 139 #define TUSB_PRCM_MNGMT_SRP_FIX_EN      (1 << 24)
 140 #define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20)
 141 #define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19)
 142 #define TUSB_PRCM_MNGMT_DFT_CLK_DIS     (1 << 18)
 143 #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS   (1 << 17)
 144 #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10)
 145 #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9)
 146 #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP   (1 << 8)
 147 #define TUSB_PRCM_MNGMT_15_SW_EN        (1 << 4)
 148 #define TUSB_PRCM_MNGMT_33_SW_EN        (1 << 3)
 149 #define TUSB_PRCM_MNGMT_5V_CPEN         (1 << 2)
 150 #define TUSB_PRCM_MNGMT_PM_IDLE         (1 << 1)
 151 #define TUSB_PRCM_MNGMT_DEV_IDLE        (1 << 0)
 152
 153 /* Wake-up source clear and mask registers */
 154 #define TUSB_PRCM_WAKEUP_SOURCE         (TUSB_SYS_REG_BASE + 0x020)
 155 #define TUSB_PRCM_WAKEUP_CLEAR          (TUSB_SYS_REG_BASE + 0x028)
 156 #define TUSB_PRCM_WAKEUP_MASK           (TUSB_SYS_REG_BASE + 0x02c)
 157 #define TUSB_PRCM_WAKEUP_RESERVED_BITS  (0xffffe << 13)
 158 #define TUSB_PRCM_WGPIO_7               (1 << 12)
 159 #define TUSB_PRCM_WGPIO_6               (1 << 11)
 160 #define TUSB_PRCM_WGPIO_5               (1 << 10)
 161 #define TUSB_PRCM_WGPIO_4               (1 << 9)
 162 #define TUSB_PRCM_WGPIO_3               (1 << 8)
 163 #define TUSB_PRCM_WGPIO_2               (1 << 7)
 164 #define TUSB_PRCM_WGPIO_1               (1 << 6)
 165 #define TUSB_PRCM_WGPIO_0               (1 << 5)
 166 #define TUSB_PRCM_WHOSTDISCON           (1 << 4)        /* Host disconnect */
 167 #define TUSB_PRCM_WBUS                  (1 << 3)        /* USB bus resume */
 168 #define TUSB_PRCM_WNORCS                (1 << 2)        /* NOR chip select */
 169 #define TUSB_PRCM_WVBUS                 (1 << 1)        /* OTG PHY VBUS */
 170 #define TUSB_PRCM_WID                   (1 << 0)        /* OTG PHY ID detect */
 171
 172 #define TUSB_PULLUP_1_CTRL              (TUSB_SYS_REG_BASE + 0x030)
 173 #define TUSB_PULLUP_2_CTRL              (TUSB_SYS_REG_BASE + 0x034)
 174 #define TUSB_INT_CTRL_REV               (TUSB_SYS_REG_BASE + 0x038)
 175 #define TUSB_INT_CTRL_CONF              (TUSB_SYS_REG_BASE + 0x03c)
 176 #define TUSB_USBIP_INT_SRC              (TUSB_SYS_REG_BASE + 0x040)
 177 #define TUSB_USBIP_INT_SET              (TUSB_SYS_REG_BASE + 0x044)
 178 #define TUSB_USBIP_INT_CLEAR            (TUSB_SYS_REG_BASE + 0x048)
 179 #define TUSB_USBIP_INT_MASK             (TUSB_SYS_REG_BASE + 0x04c)
 180 #define TUSB_DMA_INT_SRC                (TUSB_SYS_REG_BASE + 0x050)
 181 #define TUSB_DMA_INT_SET                (TUSB_SYS_REG_BASE + 0x054)
 182 #define TUSB_DMA_INT_CLEAR              (TUSB_SYS_REG_BASE + 0x058)
 183 #define TUSB_DMA_INT_MASK               (TUSB_SYS_REG_BASE + 0x05c)
 184 #define TUSB_GPIO_INT_SRC               (TUSB_SYS_REG_BASE + 0x060)
 185 #define TUSB_GPIO_INT_SET               (TUSB_SYS_REG_BASE + 0x064)
 186 #define TUSB_GPIO_INT_CLEAR             (TUSB_SYS_REG_BASE + 0x068)
 187 #define TUSB_GPIO_INT_MASK              (TUSB_SYS_REG_BASE + 0x06c)
 188
 189 /* NOR flash interrupt source registers */
 190 #define TUSB_INT_SRC                    (TUSB_SYS_REG_BASE + 0x070)
 191 #define TUSB_INT_SRC_SET                (TUSB_SYS_REG_BASE + 0x074)
 192 #define TUSB_INT_SRC_CLEAR              (TUSB_SYS_REG_BASE + 0x078)
 193 #define TUSB_INT_MASK                   (TUSB_SYS_REG_BASE + 0x07c)
 194 #define TUSB_INT_SRC_TXRX_DMA_DONE      (1 << 24)
 195 #define TUSB_INT_SRC_USB_IP_CORE        (1 << 17)
 196 #define TUSB_INT_SRC_OTG_TIMEOUT        (1 << 16)
 197 #define TUSB_INT_SRC_VBUS_SENSE_CHNG    (1 << 15)
 198 #define TUSB_INT_SRC_ID_STATUS_CHNG     (1 << 14)
 199 #define TUSB_INT_SRC_DEV_WAKEUP         (1 << 13)
 200 #define TUSB_INT_SRC_DEV_READY          (1 << 12)
 201 #define TUSB_INT_SRC_USB_IP_TX          (1 << 9)
 202 #define TUSB_INT_SRC_USB_IP_RX          (1 << 8)
 203 #define TUSB_INT_SRC_USB_IP_VBUS_ERR    (1 << 7)
 204 #define TUSB_INT_SRC_USB_IP_VBUS_REQ    (1 << 6)
 205 #define TUSB_INT_SRC_USB_IP_DISCON      (1 << 5)
 206 #define TUSB_INT_SRC_USB_IP_CONN        (1 << 4)
 207 #define TUSB_INT_SRC_USB_IP_SOF         (1 << 3)
 208 #define TUSB_INT_SRC_USB_IP_RST_BABBLE  (1 << 2)
 209 #define TUSB_INT_SRC_USB_IP_RESUME      (1 << 1)
 210 #define TUSB_INT_SRC_USB_IP_SUSPEND     (1 << 0)
 211
 212 #define TUSB_GPIO_REV                   (TUSB_SYS_REG_BASE + 0x080)
 213 #define TUSB_GPIO_CONF                  (TUSB_SYS_REG_BASE + 0x084)
 214 #define TUSB_DMA_CTRL_REV               (TUSB_SYS_REG_BASE + 0x100)
 215 #define TUSB_DMA_REQ_CONF               (TUSB_SYS_REG_BASE + 0x104)
 216 #define TUSB_EP0_CONF                   (TUSB_SYS_REG_BASE + 0x108)
 217 #define TUSB_EP_IN_SIZE                 (TUSB_SYS_REG_BASE + 0x10c)
 218 #define TUSB_DMA_EP_MAP                 (TUSB_SYS_REG_BASE + 0x148)
 219 #define TUSB_EP_OUT_SIZE                (TUSB_SYS_REG_BASE + 0x14c)
 220 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET  (TUSB_SYS_REG_BASE + 0x188)
 221 #define TUSB_SCRATCH_PAD                (TUSB_SYS_REG_BASE + 0x1c4)
 222 #define TUSB_WAIT_COUNT                 (TUSB_SYS_REG_BASE + 0x1c8)
 223 #define TUSB_PROD_TEST_RESET            (TUSB_SYS_REG_BASE + 0x1d8)
 224
 225 #define TUSB_DIDR1_LO                   (TUSB_SYS_REG_BASE + 0x1f8)
 226 #define TUSB_DIDR1_HI                   (TUSB_SYS_REG_BASE + 0x1fc)
 227
 228 /* Device System & Control register bitfields */
 229 #define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18)
 230 #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17)
 231 #define TUSB_INT_CTRL_CONF_INT_MODE     (1 << 16)
 232 #define TUSB_GPIO_CONF_DMAREQ(v)        (((v) & 0x3f) << 24)
 233 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
 234 #define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v)  (((v) & 0x3f) << 20)
 235 #define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16)
 236 #define TUSB_EP0_CONFIG_SW_EN           (1 << 8)
 237 #define TUSB_EP0_CONFIG_DIR_TX          (1 << 7)
 238 #define TUSB_EP0_CONFIG_XFR_SIZE(v)     ((v) & 0x7f)
 239 #define TUSB_EP_CONFIG_SW_EN            (1 << 31)
 240 #define TUSB_EP_CONFIG_XFR_SIZE(v)      ((v) & 0x7fffffff)
 241 #define TUSB_PROD_TEST_RESET_VAL        0xa596
 242
 243 static void tusb_intr_update(TUSBState *s)
 244 {
 245     if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
 246         qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok);
 247     else
 248         qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok);
 249 }
 250
 251 static void tusb_usbip_intr_update(TUSBState *s)
 252 {
 253     /* TX interrupt in the MUSB */
 254     if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask)
 255         s->intr |= TUSB_INT_SRC_USB_IP_TX;
 256     else
 257         s->intr &= ~TUSB_INT_SRC_USB_IP_TX;
 258
 259     /* RX interrupt in the MUSB */
 260     if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask)
 261         s->intr |= TUSB_INT_SRC_USB_IP_RX;
 262     else
 263         s->intr &= ~TUSB_INT_SRC_USB_IP_RX;
 264
 265     /* XXX: What about TUSB_INT_SRC_USB_IP_CORE?  */
 266
 267     tusb_intr_update(s);
 268 }
 269
 270 static void tusb_dma_intr_update(TUSBState *s)
 271 {
 272     if (s->dma_intr & ~s->dma_mask)
 273         s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE;
 274     else
 275         s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE;
 276
 277     tusb_intr_update(s);
 278 }
 279
 280 static void tusb_gpio_intr_update(TUSBState *s)
 281 {
 282     /* TODO: How is this signalled?  */
 283 }
 284
 285 static uint32_t tusb_async_readb(void *opaque, hwaddr addr)
 286 {
 287     TUSBState *s = (TUSBState *) opaque;
 288
 289     switch (addr & 0xfff) {
 290     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 291         return musb_read[0](s->musb, addr & 0x1ff);
 292
 293     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 294         return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c));
 295     }
 296
 297     printf("%s: unknown register at %03x\n",
 298                     __FUNCTION__, (int) (addr & 0xfff));
 299     return 0;
 300 }
 301
 302 static uint32_t tusb_async_readh(void *opaque, hwaddr addr)
 303 {
 304     TUSBState *s = (TUSBState *) opaque;
 305
 306     switch (addr & 0xfff) {
 307     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 308         return musb_read[1](s->musb, addr & 0x1ff);
 309
 310     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 311         return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c));
 312     }
 313
 314     printf("%s: unknown register at %03x\n",
 315                     __FUNCTION__, (int) (addr & 0xfff));
 316     return 0;
 317 }
 318
 319 static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
 320 {
 321     TUSBState *s = (TUSBState *) opaque;
 322     int offset = addr & 0xfff;
 323     int epnum;
 324     uint32_t ret;
 325
 326     switch (offset) {
 327     case TUSB_DEV_CONF:
 328         return s->dev_config;
 329
 330     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 331         return musb_read[2](s->musb, offset & 0x1ff);
 332
 333     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 334         return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c));
 335
 336     case TUSB_PHY_OTG_CTRL_ENABLE:
 337     case TUSB_PHY_OTG_CTRL:
 338         return 0x00;    /* TODO */
 339
 340     case TUSB_DEV_OTG_STAT:
 341         ret = s->otg_status;
 342 #if 0
 343         if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN))
 344             ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
 345 #endif
 346         return ret;
 347     case TUSB_DEV_OTG_TIMER:
 348         return s->otg_timer_val;
 349
 350     case TUSB_PRCM_REV:
 351         return 0x20;
 352     case TUSB_PRCM_CONF:
 353         return s->prcm_config;
 354     case TUSB_PRCM_MNGMT:
 355         return s->prcm_mngmt;
 356     case TUSB_PRCM_WAKEUP_SOURCE:
 357     case TUSB_PRCM_WAKEUP_CLEAR:        /* TODO: What does this one return?  */
 358         return 0x00000000;
 359     case TUSB_PRCM_WAKEUP_MASK:
 360         return s->wkup_mask;
 361
 362     case TUSB_PULLUP_1_CTRL:
 363         return s->pullup[0];
 364     case TUSB_PULLUP_2_CTRL:
 365         return s->pullup[1];
 366
 367     case TUSB_INT_CTRL_REV:
 368         return 0x20;
 369     case TUSB_INT_CTRL_CONF:
 370         return s->control_config;
 371
 372     case TUSB_USBIP_INT_SRC:
 373     case TUSB_USBIP_INT_SET:    /* TODO: What do these two return?  */
 374     case TUSB_USBIP_INT_CLEAR:
 375         return s->usbip_intr;
 376     case TUSB_USBIP_INT_MASK:
 377         return s->usbip_mask;
 378
 379     case TUSB_DMA_INT_SRC:
 380     case TUSB_DMA_INT_SET:      /* TODO: What do these two return?  */
 381     case TUSB_DMA_INT_CLEAR:
 382         return s->dma_intr;
 383     case TUSB_DMA_INT_MASK:
 384         return s->dma_mask;
 385
 386     case TUSB_GPIO_INT_SRC:     /* TODO: What do these two return?  */
 387     case TUSB_GPIO_INT_SET:
 388     case TUSB_GPIO_INT_CLEAR:
 389         return s->gpio_intr;
 390     case TUSB_GPIO_INT_MASK:
 391         return s->gpio_mask;
 392
 393     case TUSB_INT_SRC:
 394     case TUSB_INT_SRC_SET:      /* TODO: What do these two return?  */
 395     case TUSB_INT_SRC_CLEAR:
 396         return s->intr;
 397     case TUSB_INT_MASK:
 398         return s->mask;
 399
 400     case TUSB_GPIO_REV:
 401         return 0x30;
 402     case TUSB_GPIO_CONF:
 403         return s->gpio_config;
 404
 405     case TUSB_DMA_CTRL_REV:
 406         return 0x30;
 407     case TUSB_DMA_REQ_CONF:
 408         return s->dma_config;
 409     case TUSB_EP0_CONF:
 410         return s->ep0_config;
 411     case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
 412         epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
 413         return s->tx_config[epnum];
 414     case TUSB_DMA_EP_MAP:
 415         return s->dma_map;
 416     case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
 417         epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
 418         return s->rx_config[epnum];
 419     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
 420             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
 421         return 0x00000000;      /* TODO */
 422     case TUSB_WAIT_COUNT:
 423         return 0x00;            /* TODO */
 424
 425     case TUSB_SCRATCH_PAD:
 426         return s->scratch;
 427
 428     case TUSB_PROD_TEST_RESET:
 429         return s->test_reset;
 430
 431     /* DIE IDs */
 432     case TUSB_DIDR1_LO:
 433         return 0xa9453c59;
 434     case TUSB_DIDR1_HI:
 435         return 0x54059adf;
 436     }
 437
 438     printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
 439     return 0;
 440 }
 441
 442 static void tusb_async_writeb(void *opaque, hwaddr addr,
 443                 uint32_t value)
 444 {
 445     TUSBState *s = (TUSBState *) opaque;
 446
 447     switch (addr & 0xfff) {
 448     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 449         musb_write[0](s->musb, addr & 0x1ff, value);
 450         break;
 451
 452     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 453         musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 454         break;
 455
 456     default:
 457         printf("%s: unknown register at %03x\n",
 458                         __FUNCTION__, (int) (addr & 0xfff));
 459         return;
 460     }
 461 }
 462
 463 static void tusb_async_writeh(void *opaque, hwaddr addr,
 464                 uint32_t value)
 465 {
 466     TUSBState *s = (TUSBState *) opaque;
 467
 468     switch (addr & 0xfff) {
 469     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 470         musb_write[1](s->musb, addr & 0x1ff, value);
 471         break;
 472
 473     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 474         musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 475         break;
 476
 477     default:
 478         printf("%s: unknown register at %03x\n",
 479                         __FUNCTION__, (int) (addr & 0xfff));
 480         return;
 481     }
 482 }
 483
 484 static void tusb_async_writew(void *opaque, hwaddr addr,
 485                 uint32_t value)
 486 {
 487     TUSBState *s = (TUSBState *) opaque;
 488     int offset = addr & 0xfff;
 489     int epnum;
 490
 491     switch (offset) {
 492     case TUSB_VLYNQ_CTRL:
 493         break;
 494
 495     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 496         musb_write[2](s->musb, offset & 0x1ff, value);
 497         break;
 498
 499     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 500         musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 501         break;
 502
 503     case TUSB_DEV_CONF:
 504         s->dev_config = value;
 505         s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE);
 506         if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
 507             hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
 508         break;
 509
 510     case TUSB_PHY_OTG_CTRL_ENABLE:
 511     case TUSB_PHY_OTG_CTRL:
 512         return;         /* TODO */
 513     case TUSB_DEV_OTG_TIMER:
 514         s->otg_timer_val = value;
 515         if (value & TUSB_DEV_OTG_TIMER_ENABLE)
 516             timer_mod(s->otg_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 517                             muldiv64(TUSB_DEV_OTG_TIMER_VAL(value),
 518                                      get_ticks_per_sec(), TUSB_DEVCLOCK));
 519         else
 520             timer_del(s->otg_timer);
 521         break;
 522
 523     case TUSB_PRCM_CONF:
 524         s->prcm_config = value;
 525         break;
 526     case TUSB_PRCM_MNGMT:
 527         s->prcm_mngmt = value;
 528         break;
 529     case TUSB_PRCM_WAKEUP_CLEAR:
 530         break;
 531     case TUSB_PRCM_WAKEUP_MASK:
 532         s->wkup_mask = value;
 533         break;
 534
 535     case TUSB_PULLUP_1_CTRL:
 536         s->pullup[0] = value;
 537         break;
 538     case TUSB_PULLUP_2_CTRL:
 539         s->pullup[1] = value;
 540         break;
 541     case TUSB_INT_CTRL_CONF:
 542         s->control_config = value;
 543         tusb_intr_update(s);
 544         break;
 545
 546     case TUSB_USBIP_INT_SET:
 547         s->usbip_intr |= value;
 548         tusb_usbip_intr_update(s);
 549         break;
 550     case TUSB_USBIP_INT_CLEAR:
 551         s->usbip_intr &= ~value;
 552         tusb_usbip_intr_update(s);
 553         musb_core_intr_clear(s->musb, ~value);
 554         break;
 555     case TUSB_USBIP_INT_MASK:
 556         s->usbip_mask = value;
 557         tusb_usbip_intr_update(s);
 558         break;
 559
 560     case TUSB_DMA_INT_SET:
 561         s->dma_intr |= value;
 562         tusb_dma_intr_update(s);
 563         break;
 564     case TUSB_DMA_INT_CLEAR:
 565         s->dma_intr &= ~value;
 566         tusb_dma_intr_update(s);
 567         break;
 568     case TUSB_DMA_INT_MASK:
 569         s->dma_mask = value;
 570         tusb_dma_intr_update(s);
 571         break;
 572
 573     case TUSB_GPIO_INT_SET:
 574         s->gpio_intr |= value;
 575         tusb_gpio_intr_update(s);
 576         break;
 577     case TUSB_GPIO_INT_CLEAR:
 578         s->gpio_intr &= ~value;
 579         tusb_gpio_intr_update(s);
 580         break;
 581     case TUSB_GPIO_INT_MASK:
 582         s->gpio_mask = value;
 583         tusb_gpio_intr_update(s);
 584         break;
 585
 586     case TUSB_INT_SRC_SET:
 587         s->intr |= value;
 588         tusb_intr_update(s);
 589         break;
 590     case TUSB_INT_SRC_CLEAR:
 591         s->intr &= ~value;
 592         tusb_intr_update(s);
 593         break;
 594     case TUSB_INT_MASK:
 595         s->mask = value;
 596         tusb_intr_update(s);
 597         break;
 598
 599     case TUSB_GPIO_CONF:
 600         s->gpio_config = value;
 601         break;
 602     case TUSB_DMA_REQ_CONF:
 603         s->dma_config = value;
 604         break;
 605     case TUSB_EP0_CONF:
 606         s->ep0_config = value & 0x1ff;
 607         musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value),
 608                         value & TUSB_EP0_CONFIG_DIR_TX);
 609         break;
 610     case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
 611         epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
 612         s->tx_config[epnum] = value;
 613         musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1);
 614         break;
 615     case TUSB_DMA_EP_MAP:
 616         s->dma_map = value;
 617         break;
 618     case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
 619         epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
 620         s->rx_config[epnum] = value;
 621         musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0);
 622         break;
 623     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
 624             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
 625         return;         /* TODO */
 626     case TUSB_WAIT_COUNT:
 627         return;         /* TODO */
 628
 629     case TUSB_SCRATCH_PAD:
 630         s->scratch = value;
 631         break;
 632
 633     case TUSB_PROD_TEST_RESET:
 634         s->test_reset = value;
 635         break;
 636
 637     default:
 638         printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
 639         return;
 640     }
 641 }
 642
 643 static const MemoryRegionOps tusb_async_ops = {
 644     .old_mmio = {
 645         .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
 646         .write =  { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
 647     },
 648     .endianness = DEVICE_NATIVE_ENDIAN,
 649 };
 650
 651 static void tusb_otg_tick(void *opaque)
 652 {
 653     TUSBState *s = (TUSBState *) opaque;
 654
 655     s->otg_timer_val = 0;
 656     s->intr |= TUSB_INT_SRC_OTG_TIMEOUT;
 657     tusb_intr_update(s);
 658 }
 659
 660 static void tusb_power_tick(void *opaque)
 661 {
 662     TUSBState *s = (TUSBState *) opaque;
 663
 664     if (s->power) {
 665         s->intr_ok = ~0;
 666         tusb_intr_update(s);
 667     }
 668 }
 669
 670 static void tusb_musb_core_intr(void *opaque, int source, int level)
 671 {
 672     TUSBState *s = (TUSBState *) opaque;
 673     uint16_t otg_status = s->otg_status;
 674
 675     switch (source) {
 676     case musb_set_vbus:
 677         if (level)
 678             otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID;
 679         else
 680             otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
 681
 682         /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set?  */
 683         /* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set?  */
 684         if (s->otg_status != otg_status) {
 685             s->otg_status = otg_status;
 686             s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG;
 687             tusb_intr_update(s);
 688         }
 689         break;
 690
 691     case musb_set_session:
 692         /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set?  */
 693         /* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set?  */
 694         if (level) {
 695             s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID;
 696             s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END;
 697         } else {
 698             s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID;
 699             s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END;
 700         }
 701
 702         /* XXX: some IRQ or anything?  */
 703         break;
 704
 705     case musb_irq_tx:
 706     case musb_irq_rx:
 707         s->usbip_intr = musb_core_intr_get(s->musb);
 708         /* Fall through.  */
 709     default:
 710         if (level)
 711             s->intr |= 1 << source;
 712         else
 713             s->intr &= ~(1 << source);
 714         tusb_intr_update(s);
 715         break;
 716     }
 717 }
 718
 719 static void tusb6010_power(TUSBState *s, int on)
 720 {
 721     if (!on) {
 722         s->power = 0;
 723     } else if (!s->power && on) {
 724         s->power = 1;
 725         /* Pull the interrupt down after TUSB6010 comes up.  */
 726         s->intr_ok = 0;
 727         tusb_intr_update(s);
 728         timer_mod(s->pwr_timer,
 729                        qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + get_ticks_per_sec() / 2);
 730     }
 731 }
 732
 733 static void tusb6010_irq(void *opaque, int source, int level)
 734 {
 735     if (source) {
 736         tusb_musb_core_intr(opaque, source - 1, level);
 737     } else {
 738         tusb6010_power(opaque, level);
 739     }
 740 }
 741
 742 static void tusb6010_reset(DeviceState *dev)
 743 {
 744     TUSBState *s = TUSB(dev);
 745     int i;
 746
 747     s->test_reset = TUSB_PROD_TEST_RESET_VAL;
 748     s->host_mode = 0;
 749     s->dev_config = 0;
 750     s->otg_status = 0;  /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */
 751     s->power = 0;
 752     s->mask = 0xffffffff;
 753     s->intr = 0x00000000;
 754     s->otg_timer_val = 0;
 755     s->scratch = 0;
 756     s->prcm_config = 0;
 757     s->prcm_mngmt = 0;
 758     s->intr_ok = 0;
 759     s->usbip_intr = 0;
 760     s->usbip_mask = 0;
 761     s->gpio_intr = 0;
 762     s->gpio_mask = 0;
 763     s->gpio_config = 0;
 764     s->dma_intr = 0;
 765     s->dma_mask = 0;
 766     s->dma_map = 0;
 767     s->dma_config = 0;
 768     s->ep0_config = 0;
 769     s->wkup_mask = 0;
 770     s->pullup[0] = s->pullup[1] = 0;
 771     s->control_config = 0;
 772     for (i = 0; i < 15; i++) {
 773         s->rx_config[i] = s->tx_config[i] = 0;
 774     }
 775     musb_reset(s->musb);
 776 }
 777
 778 static int tusb6010_init(SysBusDevice *sbd)
 779 {
 780     DeviceState *dev = DEVICE(sbd);
 781     TUSBState *s = TUSB(dev);
 782
 783     s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s);
 784     s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s);
 785     memory_region_init_io(&s->iomem[1], OBJECT(s), &tusb_async_ops, s,
 786                           "tusb-async", UINT32_MAX);
 787     sysbus_init_mmio(sbd, &s->iomem[0]);
 788     sysbus_init_mmio(sbd, &s->iomem[1]);
 789     sysbus_init_irq(sbd, &s->irq);
 790     qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1);
 791     s->musb = musb_init(dev, 1);
 792     return 0;
 793 }
 794
 795 static void tusb6010_class_init(ObjectClass *klass, void *data)
 796 {
 797     DeviceClass *dc = DEVICE_CLASS(klass);
 798     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 799
 800     k->init = tusb6010_init;
 801     dc->reset = tusb6010_reset;
 802 }
 803
 804 static const TypeInfo tusb6010_info = {
 805     .name          = TYPE_TUSB6010,
 806     .parent        = TYPE_SYS_BUS_DEVICE,
 807     .instance_size = sizeof(TUSBState),
 808     .class_init    = tusb6010_class_init,
 809 };
 810
 811 static void tusb6010_register_types(void)
 812 {
 813     type_register_static(&tusb6010_info);
 814 }
 815
 816 type_init(tusb6010_register_types)