hw/intc/arm_gicv3_its_common.c

   1 /*
   2  * ITS base class for a GICv3-based system
   3  *
   4  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   5  * Written by Pavel Fedin
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/pci/msi.h"
  23 #include "hw/intc/arm_gicv3_its_common.h"
  24 #include "qemu/log.h"
  25
  26 static void gicv3_its_pre_save(void *opaque)
  27 {
  28     GICv3ITSState *s = (GICv3ITSState *)opaque;
  29     GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
  30
  31     if (c->pre_save) {
  32         c->pre_save(s);
  33     }
  34 }
  35
  36 static int gicv3_its_post_load(void *opaque, int version_id)
  37 {
  38     GICv3ITSState *s = (GICv3ITSState *)opaque;
  39     GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
  40
  41     if (c->post_load) {
  42         c->post_load(s);
  43     }
  44     return 0;
  45 }
  46
  47 static const VMStateDescription vmstate_its = {
  48     .name = "arm_gicv3_its",
  49     .pre_save = gicv3_its_pre_save,
  50     .post_load = gicv3_its_post_load,
  51     .unmigratable = true,
  52 };
  53
  54 static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
  55                                         uint64_t *data, unsigned size,
  56                                         MemTxAttrs attrs)
  57 {
  58     qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
  59     return MEMTX_ERROR;
  60 }
  61
  62 static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
  63                                          uint64_t value, unsigned size,
  64                                          MemTxAttrs attrs)
  65 {
  66     if (offset == 0x0040 && ((size == 2) || (size == 4))) {
  67         GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque);
  68         GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
  69         int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id);
  70
  71         if (ret <= 0) {
  72             qemu_log_mask(LOG_GUEST_ERROR,
  73                           "ITS: Error sending MSI: %s\n", strerror(-ret));
  74             return MEMTX_DECODE_ERROR;
  75         }
  76
  77         return MEMTX_OK;
  78     } else {
  79         qemu_log_mask(LOG_GUEST_ERROR,
  80                       "ITS write at bad offset 0x%"PRIx64"\n", offset);
  81         return MEMTX_DECODE_ERROR;
  82     }
  83 }
  84
  85 static const MemoryRegionOps gicv3_its_trans_ops = {
  86     .read_with_attrs = gicv3_its_trans_read,
  87     .write_with_attrs = gicv3_its_trans_write,
  88     .endianness = DEVICE_NATIVE_ENDIAN,
  89 };
  90
  91 void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
  92 {
  93     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
  94
  95     memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
  96                           "control", ITS_CONTROL_SIZE);
  97     memory_region_init_io(&s->iomem_its_translation, OBJECT(s),
  98                           &gicv3_its_trans_ops, s,
  99                           "translation", ITS_TRANS_SIZE);
 100
 101     /* Our two regions are always adjacent, therefore we now combine them
 102      * into a single one in order to make our users' life easier.
 103      */
 104     memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE);
 105     memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl);
 106     memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE,
 107                                 &s->iomem_its_translation);
 108     sysbus_init_mmio(sbd, &s->iomem_main);
 109
 110     msi_nonbroken = true;
 111 }
 112
 113 static void gicv3_its_common_reset(DeviceState *dev)
 114 {
 115     GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
 116
 117     s->ctlr = 0;
 118     s->cbaser = 0;
 119     s->cwriter = 0;
 120     s->creadr = 0;
 121     memset(&s->baser, 0, sizeof(s->baser));
 122
 123     gicv3_its_post_load(s, 0);
 124 }
 125
 126 static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
 127 {
 128     DeviceClass *dc = DEVICE_CLASS(klass);
 129
 130     dc->reset = gicv3_its_common_reset;
 131     dc->vmsd = &vmstate_its;
 132 }
 133
 134 static const TypeInfo gicv3_its_common_info = {
 135     .name = TYPE_ARM_GICV3_ITS_COMMON,
 136     .parent = TYPE_SYS_BUS_DEVICE,
 137     .instance_size = sizeof(GICv3ITSState),
 138     .class_size = sizeof(GICv3ITSCommonClass),
 139     .class_init = gicv3_its_common_class_init,
 140     .abstract = true,
 141 };
 142
 143 static void gicv3_its_common_register_types(void)
 144 {
 145     type_register_static(&gicv3_its_common_info);
 146 }
 147
 148 type_init(gicv3_its_common_register_types)