Update version for v2.3.0-rc4 release
[qemu.git] / hw / net / vmxnet3.c
blobdfb328debdfec7e9f9be450d43dd367792f4bb4b
1 /*
2 * QEMU VMWARE VMXNET3 paravirtual NIC
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
18 #include "hw/hw.h"
19 #include "hw/pci/pci.h"
20 #include "net/net.h"
21 #include "net/tap.h"
22 #include "net/checksum.h"
23 #include "sysemu/sysemu.h"
24 #include "qemu-common.h"
25 #include "qemu/bswap.h"
26 #include "hw/pci/msix.h"
27 #include "hw/pci/msi.h"
29 #include "vmxnet3.h"
30 #include "vmxnet_debug.h"
31 #include "vmware_utils.h"
32 #include "vmxnet_tx_pkt.h"
33 #include "vmxnet_rx_pkt.h"
35 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
36 #define VMXNET3_MSIX_BAR_SIZE 0x2000
37 #define MIN_BUF_SIZE 60
39 #define VMXNET3_BAR0_IDX (0)
40 #define VMXNET3_BAR1_IDX (1)
41 #define VMXNET3_MSIX_BAR_IDX (2)
43 #define VMXNET3_OFF_MSIX_TABLE (0x000)
44 #define VMXNET3_OFF_MSIX_PBA (0x800)
46 /* Link speed in Mbps should be shifted by 16 */
47 #define VMXNET3_LINK_SPEED (1000 << 16)
49 /* Link status: 1 - up, 0 - down. */
50 #define VMXNET3_LINK_STATUS_UP 0x1
52 /* Least significant bit should be set for revision and version */
53 #define VMXNET3_DEVICE_VERSION 0x1
54 #define VMXNET3_DEVICE_REVISION 0x1
56 /* Number of interrupt vectors for non-MSIx modes */
57 #define VMXNET3_MAX_NMSIX_INTRS (1)
59 /* Macros for rings descriptors access */
60 #define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \
61 (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
63 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \
64 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
66 #define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \
67 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
69 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \
70 (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
72 #define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \
73 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
75 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \
76 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
78 #define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \
79 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
81 #define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \
82 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
84 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \
85 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
87 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \
88 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
90 /* Macros for guest driver shared area access */
91 #define VMXNET3_READ_DRV_SHARED64(shpa, field) \
92 (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
94 #define VMXNET3_READ_DRV_SHARED32(shpa, field) \
95 (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
97 #define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \
98 (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
100 #define VMXNET3_READ_DRV_SHARED16(shpa, field) \
101 (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
103 #define VMXNET3_READ_DRV_SHARED8(shpa, field) \
104 (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
106 #define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \
107 (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
109 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
111 #define TYPE_VMXNET3 "vmxnet3"
112 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
114 /* Cyclic ring abstraction */
115 typedef struct {
116 hwaddr pa;
117 size_t size;
118 size_t cell_size;
119 size_t next;
120 uint8_t gen;
121 } Vmxnet3Ring;
123 static inline void vmxnet3_ring_init(Vmxnet3Ring *ring,
124 hwaddr pa,
125 size_t size,
126 size_t cell_size,
127 bool zero_region)
129 ring->pa = pa;
130 ring->size = size;
131 ring->cell_size = cell_size;
132 ring->gen = VMXNET3_INIT_GEN;
133 ring->next = 0;
135 if (zero_region) {
136 vmw_shmem_set(pa, 0, size * cell_size);
140 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
141 macro("%s#%d: base %" PRIx64 " size %lu cell_size %lu gen %d next %lu", \
142 (ring_name), (ridx), \
143 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
145 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)
147 if (++ring->next >= ring->size) {
148 ring->next = 0;
149 ring->gen ^= 1;
153 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)
155 if (ring->next-- == 0) {
156 ring->next = ring->size - 1;
157 ring->gen ^= 1;
161 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
163 return ring->pa + ring->next * ring->cell_size;
166 static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring *ring, void *buff)
168 vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
171 static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring *ring, void *buff)
173 vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
176 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)
178 return ring->next;
181 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)
183 return ring->gen;
186 /* Debug trace-related functions */
187 static inline void
188 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)
190 VMW_PKPRN("TX DESCR: "
191 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
192 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
193 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
194 le64_to_cpu(descr->addr), descr->len, descr->gen, descr->rsvd,
195 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,
196 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);
199 static inline void
200 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)
202 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
203 "csum_start: %d, csum_offset: %d",
204 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,
205 vhdr->csum_start, vhdr->csum_offset);
208 static inline void
209 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)
211 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
212 "dtype: %d, ext1: %d, btype: %d",
213 le64_to_cpu(descr->addr), descr->len, descr->gen,
214 descr->rsvd, descr->dtype, descr->ext1, descr->btype);
217 /* Device state and helper functions */
218 #define VMXNET3_RX_RINGS_PER_QUEUE (2)
220 typedef struct {
221 Vmxnet3Ring tx_ring;
222 Vmxnet3Ring comp_ring;
224 uint8_t intr_idx;
225 hwaddr tx_stats_pa;
226 struct UPT1_TxStats txq_stats;
227 } Vmxnet3TxqDescr;
229 typedef struct {
230 Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE];
231 Vmxnet3Ring comp_ring;
232 uint8_t intr_idx;
233 hwaddr rx_stats_pa;
234 struct UPT1_RxStats rxq_stats;
235 } Vmxnet3RxqDescr;
237 typedef struct {
238 bool is_masked;
239 bool is_pending;
240 bool is_asserted;
241 } Vmxnet3IntState;
243 typedef struct {
244 PCIDevice parent_obj;
245 NICState *nic;
246 NICConf conf;
247 MemoryRegion bar0;
248 MemoryRegion bar1;
249 MemoryRegion msix_bar;
251 Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES];
252 Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES];
254 /* Whether MSI-X support was installed successfully */
255 bool msix_used;
256 /* Whether MSI support was installed successfully */
257 bool msi_used;
258 hwaddr drv_shmem;
259 hwaddr temp_shared_guest_driver_memory;
261 uint8_t txq_num;
263 /* This boolean tells whether RX packet being indicated has to */
264 /* be split into head and body chunks from different RX rings */
265 bool rx_packets_compound;
267 bool rx_vlan_stripping;
268 bool lro_supported;
270 uint8_t rxq_num;
272 /* Network MTU */
273 uint32_t mtu;
275 /* Maximum number of fragments for indicated TX packets */
276 uint32_t max_tx_frags;
278 /* Maximum number of fragments for indicated RX packets */
279 uint16_t max_rx_frags;
281 /* Index for events interrupt */
282 uint8_t event_int_idx;
284 /* Whether automatic interrupts masking enabled */
285 bool auto_int_masking;
287 bool peer_has_vhdr;
289 /* TX packets to QEMU interface */
290 struct VmxnetTxPkt *tx_pkt;
291 uint32_t offload_mode;
292 uint32_t cso_or_gso_size;
293 uint16_t tci;
294 bool needs_vlan;
296 struct VmxnetRxPkt *rx_pkt;
298 bool tx_sop;
299 bool skip_current_tx_pkt;
301 uint32_t device_active;
302 uint32_t last_command;
304 uint32_t link_status_and_speed;
306 Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS];
308 uint32_t temp_mac; /* To store the low part first */
310 MACAddr perm_mac;
311 uint32_t vlan_table[VMXNET3_VFT_SIZE];
312 uint32_t rx_mode;
313 MACAddr *mcast_list;
314 uint32_t mcast_list_len;
315 uint32_t mcast_list_buff_size; /* needed for live migration. */
316 } VMXNET3State;
318 /* Interrupt management */
321 *This function returns sign whether interrupt line is in asserted state
322 * This depends on the type of interrupt used. For INTX interrupt line will
323 * be asserted until explicit deassertion, for MSI(X) interrupt line will
324 * be deasserted automatically due to notification semantics of the MSI(X)
325 * interrupts
327 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
329 PCIDevice *d = PCI_DEVICE(s);
331 if (s->msix_used && msix_enabled(d)) {
332 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);
333 msix_notify(d, int_idx);
334 return false;
336 if (s->msi_used && msi_enabled(d)) {
337 VMW_IRPRN("Sending MSI notification for vector %u", int_idx);
338 msi_notify(d, int_idx);
339 return false;
342 VMW_IRPRN("Asserting line for interrupt %u", int_idx);
343 pci_irq_assert(d);
344 return true;
347 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
349 PCIDevice *d = PCI_DEVICE(s);
352 * This function should never be called for MSI(X) interrupts
353 * because deassertion never required for message interrupts
355 assert(!s->msix_used || !msix_enabled(d));
357 * This function should never be called for MSI(X) interrupts
358 * because deassertion never required for message interrupts
360 assert(!s->msi_used || !msi_enabled(d));
362 VMW_IRPRN("Deasserting line for interrupt %u", lidx);
363 pci_irq_deassert(d);
366 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
368 if (!s->interrupt_states[lidx].is_pending &&
369 s->interrupt_states[lidx].is_asserted) {
370 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);
371 _vmxnet3_deassert_interrupt_line(s, lidx);
372 s->interrupt_states[lidx].is_asserted = false;
373 return;
376 if (s->interrupt_states[lidx].is_pending &&
377 !s->interrupt_states[lidx].is_masked &&
378 !s->interrupt_states[lidx].is_asserted) {
379 VMW_IRPRN("New interrupt line state for index %d is UP", lidx);
380 s->interrupt_states[lidx].is_asserted =
381 _vmxnet3_assert_interrupt_line(s, lidx);
382 s->interrupt_states[lidx].is_pending = false;
383 return;
387 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)
389 PCIDevice *d = PCI_DEVICE(s);
390 s->interrupt_states[lidx].is_pending = true;
391 vmxnet3_update_interrupt_line_state(s, lidx);
393 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {
394 goto do_automask;
397 if (s->msi_used && msi_enabled(d) && s->auto_int_masking) {
398 goto do_automask;
401 return;
403 do_automask:
404 s->interrupt_states[lidx].is_masked = true;
405 vmxnet3_update_interrupt_line_state(s, lidx);
408 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)
410 return s->interrupt_states[lidx].is_asserted;
413 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)
415 s->interrupt_states[int_idx].is_pending = false;
416 if (s->auto_int_masking) {
417 s->interrupt_states[int_idx].is_masked = true;
419 vmxnet3_update_interrupt_line_state(s, int_idx);
422 static void
423 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)
425 s->interrupt_states[lidx].is_masked = is_masked;
426 vmxnet3_update_interrupt_line_state(s, lidx);
429 static bool vmxnet3_verify_driver_magic(hwaddr dshmem)
431 return (VMXNET3_READ_DRV_SHARED32(dshmem, magic) == VMXNET3_REV1_MAGIC);
434 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
435 #define VMXNET3_MAKE_BYTE(byte_num, val) \
436 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
438 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)
440 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0);
441 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1);
442 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2);
443 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3);
444 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);
445 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);
447 VMW_CFPRN("Variable MAC: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
449 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
452 static uint64_t vmxnet3_get_mac_low(MACAddr *addr)
454 return VMXNET3_MAKE_BYTE(0, addr->a[0]) |
455 VMXNET3_MAKE_BYTE(1, addr->a[1]) |
456 VMXNET3_MAKE_BYTE(2, addr->a[2]) |
457 VMXNET3_MAKE_BYTE(3, addr->a[3]);
460 static uint64_t vmxnet3_get_mac_high(MACAddr *addr)
462 return VMXNET3_MAKE_BYTE(0, addr->a[4]) |
463 VMXNET3_MAKE_BYTE(1, addr->a[5]);
466 static void
467 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)
469 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);
472 static inline void
473 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)
475 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);
478 static inline void
479 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)
481 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);
484 static void
485 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)
487 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);
490 static void
491 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)
493 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);
496 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32 tx_ridx)
498 struct Vmxnet3_TxCompDesc txcq_descr;
500 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);
502 txcq_descr.txdIdx = tx_ridx;
503 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);
505 vmxnet3_ring_write_curr_cell(&s->txq_descr[qidx].comp_ring, &txcq_descr);
507 /* Flush changes in TX descriptor before changing the counter value */
508 smp_wmb();
510 vmxnet3_inc_tx_completion_counter(s, qidx);
511 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);
514 static bool
515 vmxnet3_setup_tx_offloads(VMXNET3State *s)
517 switch (s->offload_mode) {
518 case VMXNET3_OM_NONE:
519 vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);
520 break;
522 case VMXNET3_OM_CSUM:
523 vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);
524 VMW_PKPRN("L4 CSO requested\n");
525 break;
527 case VMXNET3_OM_TSO:
528 vmxnet_tx_pkt_build_vheader(s->tx_pkt, true, true,
529 s->cso_or_gso_size);
530 vmxnet_tx_pkt_update_ip_checksums(s->tx_pkt);
531 VMW_PKPRN("GSO offload requested.");
532 break;
534 default:
535 g_assert_not_reached();
536 return false;
539 return true;
542 static void
543 vmxnet3_tx_retrieve_metadata(VMXNET3State *s,
544 const struct Vmxnet3_TxDesc *txd)
546 s->offload_mode = txd->om;
547 s->cso_or_gso_size = txd->msscof;
548 s->tci = txd->tci;
549 s->needs_vlan = txd->ti;
552 typedef enum {
553 VMXNET3_PKT_STATUS_OK,
554 VMXNET3_PKT_STATUS_ERROR,
555 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */
556 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */
557 } Vmxnet3PktStatus;
559 static void
560 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
561 Vmxnet3PktStatus status)
563 size_t tot_len = vmxnet_tx_pkt_get_total_len(s->tx_pkt);
564 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;
566 switch (status) {
567 case VMXNET3_PKT_STATUS_OK:
568 switch (vmxnet_tx_pkt_get_packet_type(s->tx_pkt)) {
569 case ETH_PKT_BCAST:
570 stats->bcastPktsTxOK++;
571 stats->bcastBytesTxOK += tot_len;
572 break;
573 case ETH_PKT_MCAST:
574 stats->mcastPktsTxOK++;
575 stats->mcastBytesTxOK += tot_len;
576 break;
577 case ETH_PKT_UCAST:
578 stats->ucastPktsTxOK++;
579 stats->ucastBytesTxOK += tot_len;
580 break;
581 default:
582 g_assert_not_reached();
585 if (s->offload_mode == VMXNET3_OM_TSO) {
587 * According to VMWARE headers this statistic is a number
588 * of packets after segmentation but since we don't have
589 * this information in QEMU model, the best we can do is to
590 * provide number of non-segmented packets
592 stats->TSOPktsTxOK++;
593 stats->TSOBytesTxOK += tot_len;
595 break;
597 case VMXNET3_PKT_STATUS_DISCARD:
598 stats->pktsTxDiscard++;
599 break;
601 case VMXNET3_PKT_STATUS_ERROR:
602 stats->pktsTxError++;
603 break;
605 default:
606 g_assert_not_reached();
610 static void
611 vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
612 int qidx,
613 Vmxnet3PktStatus status)
615 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;
616 size_t tot_len = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
618 switch (status) {
619 case VMXNET3_PKT_STATUS_OUT_OF_BUF:
620 stats->pktsRxOutOfBuf++;
621 break;
623 case VMXNET3_PKT_STATUS_ERROR:
624 stats->pktsRxError++;
625 break;
626 case VMXNET3_PKT_STATUS_OK:
627 switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
628 case ETH_PKT_BCAST:
629 stats->bcastPktsRxOK++;
630 stats->bcastBytesRxOK += tot_len;
631 break;
632 case ETH_PKT_MCAST:
633 stats->mcastPktsRxOK++;
634 stats->mcastBytesRxOK += tot_len;
635 break;
636 case ETH_PKT_UCAST:
637 stats->ucastPktsRxOK++;
638 stats->ucastBytesRxOK += tot_len;
639 break;
640 default:
641 g_assert_not_reached();
644 if (tot_len > s->mtu) {
645 stats->LROPktsRxOK++;
646 stats->LROBytesRxOK += tot_len;
648 break;
649 default:
650 g_assert_not_reached();
654 static inline bool
655 vmxnet3_pop_next_tx_descr(VMXNET3State *s,
656 int qidx,
657 struct Vmxnet3_TxDesc *txd,
658 uint32_t *descr_idx)
660 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;
662 vmxnet3_ring_read_curr_cell(ring, txd);
663 if (txd->gen == vmxnet3_ring_curr_gen(ring)) {
664 /* Only read after generation field verification */
665 smp_rmb();
666 /* Re-read to be sure we got the latest version */
667 vmxnet3_ring_read_curr_cell(ring, txd);
668 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);
669 *descr_idx = vmxnet3_ring_curr_cell_idx(ring);
670 vmxnet3_inc_tx_consumption_counter(s, qidx);
671 return true;
674 return false;
677 static bool
678 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)
680 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;
682 if (!vmxnet3_setup_tx_offloads(s)) {
683 status = VMXNET3_PKT_STATUS_ERROR;
684 goto func_exit;
687 /* debug prints */
688 vmxnet3_dump_virt_hdr(vmxnet_tx_pkt_get_vhdr(s->tx_pkt));
689 vmxnet_tx_pkt_dump(s->tx_pkt);
691 if (!vmxnet_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {
692 status = VMXNET3_PKT_STATUS_DISCARD;
693 goto func_exit;
696 func_exit:
697 vmxnet3_on_tx_done_update_stats(s, qidx, status);
698 return (status == VMXNET3_PKT_STATUS_OK);
701 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
703 struct Vmxnet3_TxDesc txd;
704 uint32_t txd_idx;
705 uint32_t data_len;
706 hwaddr data_pa;
708 for (;;) {
709 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
710 break;
713 vmxnet3_dump_tx_descr(&txd);
715 if (!s->skip_current_tx_pkt) {
716 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
717 data_pa = le64_to_cpu(txd.addr);
719 if (!vmxnet_tx_pkt_add_raw_fragment(s->tx_pkt,
720 data_pa,
721 data_len)) {
722 s->skip_current_tx_pkt = true;
726 if (s->tx_sop) {
727 vmxnet3_tx_retrieve_metadata(s, &txd);
728 s->tx_sop = false;
731 if (txd.eop) {
732 if (!s->skip_current_tx_pkt) {
733 vmxnet_tx_pkt_parse(s->tx_pkt);
735 if (s->needs_vlan) {
736 vmxnet_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
739 vmxnet3_send_packet(s, qidx);
740 } else {
741 vmxnet3_on_tx_done_update_stats(s, qidx,
742 VMXNET3_PKT_STATUS_ERROR);
745 vmxnet3_complete_packet(s, qidx, txd_idx);
746 s->tx_sop = true;
747 s->skip_current_tx_pkt = false;
748 vmxnet_tx_pkt_reset(s->tx_pkt);
753 static inline void
754 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
755 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
757 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
758 *didx = vmxnet3_ring_curr_cell_idx(ring);
759 vmxnet3_ring_read_curr_cell(ring, dbuf);
762 static inline uint8_t
763 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)
765 return s->rxq_descr[qidx].rx_ring[ridx].gen;
768 static inline hwaddr
769 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
771 uint8_t ring_gen;
772 struct Vmxnet3_RxCompDesc rxcd;
774 hwaddr daddr =
775 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
777 cpu_physical_memory_read(daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
778 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
780 if (rxcd.gen != ring_gen) {
781 *descr_gen = ring_gen;
782 vmxnet3_inc_rx_completion_counter(s, qidx);
783 return daddr;
786 return 0;
789 static inline void
790 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)
792 vmxnet3_dec_rx_completion_counter(s, qidx);
795 #define RXQ_IDX (0)
796 #define RX_HEAD_BODY_RING (0)
797 #define RX_BODY_ONLY_RING (1)
799 static bool
800 vmxnet3_get_next_head_rx_descr(VMXNET3State *s,
801 struct Vmxnet3_RxDesc *descr_buf,
802 uint32_t *descr_idx,
803 uint32_t *ridx)
805 for (;;) {
806 uint32_t ring_gen;
807 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
808 descr_buf, descr_idx);
810 /* If no more free descriptors - return */
811 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);
812 if (descr_buf->gen != ring_gen) {
813 return false;
816 /* Only read after generation field verification */
817 smp_rmb();
818 /* Re-read to be sure we got the latest version */
819 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
820 descr_buf, descr_idx);
822 /* Mark current descriptor as used/skipped */
823 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
825 /* If this is what we are looking for - return */
826 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {
827 *ridx = RX_HEAD_BODY_RING;
828 return true;
833 static bool
834 vmxnet3_get_next_body_rx_descr(VMXNET3State *s,
835 struct Vmxnet3_RxDesc *d,
836 uint32_t *didx,
837 uint32_t *ridx)
839 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
841 /* Try to find corresponding descriptor in head/body ring */
842 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {
843 /* Only read after generation field verification */
844 smp_rmb();
845 /* Re-read to be sure we got the latest version */
846 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
847 if (d->btype == VMXNET3_RXD_BTYPE_BODY) {
848 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
849 *ridx = RX_HEAD_BODY_RING;
850 return true;
855 * If there is no free descriptors on head/body ring or next free
856 * descriptor is a head descriptor switch to body only ring
858 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
860 /* If no more free descriptors - return */
861 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {
862 /* Only read after generation field verification */
863 smp_rmb();
864 /* Re-read to be sure we got the latest version */
865 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
866 assert(d->btype == VMXNET3_RXD_BTYPE_BODY);
867 *ridx = RX_BODY_ONLY_RING;
868 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);
869 return true;
872 return false;
875 static inline bool
876 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,
877 struct Vmxnet3_RxDesc *descr_buf,
878 uint32_t *descr_idx,
879 uint32_t *ridx)
881 if (is_head || !s->rx_packets_compound) {
882 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);
883 } else {
884 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);
888 static void vmxnet3_rx_update_descr(struct VmxnetRxPkt *pkt,
889 struct Vmxnet3_RxCompDesc *rxcd)
891 int csum_ok, is_gso;
892 bool isip4, isip6, istcp, isudp;
893 struct virtio_net_hdr *vhdr;
894 uint8_t offload_type;
896 if (vmxnet_rx_pkt_is_vlan_stripped(pkt)) {
897 rxcd->ts = 1;
898 rxcd->tci = vmxnet_rx_pkt_get_vlan_tag(pkt);
901 if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {
902 goto nocsum;
905 vhdr = vmxnet_rx_pkt_get_vhdr(pkt);
907 * Checksum is valid when lower level tell so or when lower level
908 * requires checksum offload telling that packet produced/bridged
909 * locally and did travel over network after last checksum calculation
910 * or production
912 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
913 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
915 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
916 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
918 if (!csum_ok && !is_gso) {
919 goto nocsum;
922 vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
923 if ((!istcp && !isudp) || (!isip4 && !isip6)) {
924 goto nocsum;
927 rxcd->cnc = 0;
928 rxcd->v4 = isip4 ? 1 : 0;
929 rxcd->v6 = isip6 ? 1 : 0;
930 rxcd->tcp = istcp ? 1 : 0;
931 rxcd->udp = isudp ? 1 : 0;
932 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
933 return;
935 nocsum:
936 rxcd->cnc = 1;
937 return;
940 static void
941 vmxnet3_physical_memory_writev(const struct iovec *iov,
942 size_t start_iov_off,
943 hwaddr target_addr,
944 size_t bytes_to_copy)
946 size_t curr_off = 0;
947 size_t copied = 0;
949 while (bytes_to_copy) {
950 if (start_iov_off < (curr_off + iov->iov_len)) {
951 size_t chunk_len =
952 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
954 cpu_physical_memory_write(target_addr + copied,
955 iov->iov_base + start_iov_off - curr_off,
956 chunk_len);
958 copied += chunk_len;
959 start_iov_off += chunk_len;
960 curr_off = start_iov_off;
961 bytes_to_copy -= chunk_len;
962 } else {
963 curr_off += iov->iov_len;
965 iov++;
969 static bool
970 vmxnet3_indicate_packet(VMXNET3State *s)
972 struct Vmxnet3_RxDesc rxd;
973 bool is_head = true;
974 uint32_t rxd_idx;
975 uint32_t rx_ridx = 0;
977 struct Vmxnet3_RxCompDesc rxcd;
978 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;
979 hwaddr new_rxcd_pa = 0;
980 hwaddr ready_rxcd_pa = 0;
981 struct iovec *data = vmxnet_rx_pkt_get_iovec(s->rx_pkt);
982 size_t bytes_copied = 0;
983 size_t bytes_left = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
984 uint16_t num_frags = 0;
985 size_t chunk_size;
987 vmxnet_rx_pkt_dump(s->rx_pkt);
989 while (bytes_left > 0) {
991 /* cannot add more frags to packet */
992 if (num_frags == s->max_rx_frags) {
993 break;
996 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);
997 if (!new_rxcd_pa) {
998 break;
1001 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {
1002 break;
1005 chunk_size = MIN(bytes_left, rxd.len);
1006 vmxnet3_physical_memory_writev(data, bytes_copied,
1007 le64_to_cpu(rxd.addr), chunk_size);
1008 bytes_copied += chunk_size;
1009 bytes_left -= chunk_size;
1011 vmxnet3_dump_rx_descr(&rxd);
1013 if (ready_rxcd_pa != 0) {
1014 cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
1017 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));
1018 rxcd.rxdIdx = rxd_idx;
1019 rxcd.len = chunk_size;
1020 rxcd.sop = is_head;
1021 rxcd.gen = new_rxcd_gen;
1022 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;
1024 if (bytes_left == 0) {
1025 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);
1028 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1029 "sop %d csum_correct %lu",
1030 (unsigned long) rx_ridx,
1031 (unsigned long) rxcd.rxdIdx,
1032 (unsigned long) rxcd.len,
1033 (int) rxcd.sop,
1034 (unsigned long) rxcd.tuc);
1036 is_head = false;
1037 ready_rxcd_pa = new_rxcd_pa;
1038 new_rxcd_pa = 0;
1039 num_frags++;
1042 if (ready_rxcd_pa != 0) {
1043 rxcd.eop = 1;
1044 rxcd.err = (bytes_left != 0);
1045 cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
1047 /* Flush RX descriptor changes */
1048 smp_wmb();
1051 if (new_rxcd_pa != 0) {
1052 vmxnet3_revert_rxc_descr(s, RXQ_IDX);
1055 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);
1057 if (bytes_left == 0) {
1058 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);
1059 return true;
1060 } else if (num_frags == s->max_rx_frags) {
1061 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);
1062 return false;
1063 } else {
1064 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,
1065 VMXNET3_PKT_STATUS_OUT_OF_BUF);
1066 return false;
1070 static void
1071 vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
1072 uint64_t val, unsigned size)
1074 VMXNET3State *s = opaque;
1076 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
1077 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
1078 int tx_queue_idx =
1079 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
1080 VMXNET3_REG_ALIGN);
1081 assert(tx_queue_idx <= s->txq_num);
1082 vmxnet3_process_tx_queue(s, tx_queue_idx);
1083 return;
1086 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1087 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1088 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1089 VMXNET3_REG_ALIGN);
1091 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);
1093 vmxnet3_on_interrupt_mask_changed(s, l, val);
1094 return;
1097 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
1098 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
1099 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
1100 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
1101 return;
1104 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",
1105 (uint64_t) addr, val, size);
1108 static uint64_t
1109 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
1111 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1112 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1113 g_assert_not_reached();
1116 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
1117 return 0;
1120 static void vmxnet3_reset_interrupt_states(VMXNET3State *s)
1122 int i;
1123 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {
1124 s->interrupt_states[i].is_asserted = false;
1125 s->interrupt_states[i].is_pending = false;
1126 s->interrupt_states[i].is_masked = true;
1130 static void vmxnet3_reset_mac(VMXNET3State *s)
1132 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
1133 VMW_CFPRN("MAC address set to: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
1136 static void vmxnet3_deactivate_device(VMXNET3State *s)
1138 VMW_CBPRN("Deactivating vmxnet3...");
1139 s->device_active = false;
1142 static void vmxnet3_reset(VMXNET3State *s)
1144 VMW_CBPRN("Resetting vmxnet3...");
1146 vmxnet3_deactivate_device(s);
1147 vmxnet3_reset_interrupt_states(s);
1148 vmxnet_tx_pkt_reset(s->tx_pkt);
1149 s->drv_shmem = 0;
1150 s->tx_sop = true;
1151 s->skip_current_tx_pkt = false;
1154 static void vmxnet3_update_rx_mode(VMXNET3State *s)
1156 s->rx_mode = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
1157 devRead.rxFilterConf.rxMode);
1158 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
1161 static void vmxnet3_update_vlan_filters(VMXNET3State *s)
1163 int i;
1165 /* Copy configuration from shared memory */
1166 VMXNET3_READ_DRV_SHARED(s->drv_shmem,
1167 devRead.rxFilterConf.vfTable,
1168 s->vlan_table,
1169 sizeof(s->vlan_table));
1171 /* Invert byte order when needed */
1172 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {
1173 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);
1176 /* Dump configuration for debugging purposes */
1177 VMW_CFPRN("Configured VLANs:");
1178 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {
1179 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {
1180 VMW_CFPRN("\tVLAN %d is present", i);
1185 static void vmxnet3_update_mcast_filters(VMXNET3State *s)
1187 uint16_t list_bytes =
1188 VMXNET3_READ_DRV_SHARED16(s->drv_shmem,
1189 devRead.rxFilterConf.mfTableLen);
1191 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
1193 s->mcast_list = g_realloc(s->mcast_list, list_bytes);
1194 if (!s->mcast_list) {
1195 if (s->mcast_list_len == 0) {
1196 VMW_CFPRN("Current multicast list is empty");
1197 } else {
1198 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1199 s->mcast_list_len);
1201 s->mcast_list_len = 0;
1202 } else {
1203 int i;
1204 hwaddr mcast_list_pa =
1205 VMXNET3_READ_DRV_SHARED64(s->drv_shmem,
1206 devRead.rxFilterConf.mfTablePA);
1208 cpu_physical_memory_read(mcast_list_pa, s->mcast_list, list_bytes);
1209 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
1210 for (i = 0; i < s->mcast_list_len; i++) {
1211 VMW_CFPRN("\t" VMXNET_MF, VMXNET_MA(s->mcast_list[i].a));
1216 static void vmxnet3_setup_rx_filtering(VMXNET3State *s)
1218 vmxnet3_update_rx_mode(s);
1219 vmxnet3_update_vlan_filters(s);
1220 vmxnet3_update_mcast_filters(s);
1223 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)
1225 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);
1226 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);
1227 return interrupt_mode;
1230 static void vmxnet3_fill_stats(VMXNET3State *s)
1232 int i;
1233 for (i = 0; i < s->txq_num; i++) {
1234 cpu_physical_memory_write(s->txq_descr[i].tx_stats_pa,
1235 &s->txq_descr[i].txq_stats,
1236 sizeof(s->txq_descr[i].txq_stats));
1239 for (i = 0; i < s->rxq_num; i++) {
1240 cpu_physical_memory_write(s->rxq_descr[i].rx_stats_pa,
1241 &s->rxq_descr[i].rxq_stats,
1242 sizeof(s->rxq_descr[i].rxq_stats));
1246 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
1248 struct Vmxnet3_GOSInfo gos;
1250 VMXNET3_READ_DRV_SHARED(s->drv_shmem, devRead.misc.driverInfo.gos,
1251 &gos, sizeof(gos));
1252 s->rx_packets_compound =
1253 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
1255 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
1258 static void
1259 vmxnet3_dump_conf_descr(const char *name,
1260 struct Vmxnet3_VariableLenConfDesc *pm_descr)
1262 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1263 name, pm_descr->confVer, pm_descr->confLen);
1267 static void vmxnet3_update_pm_state(VMXNET3State *s)
1269 struct Vmxnet3_VariableLenConfDesc pm_descr;
1271 pm_descr.confLen =
1272 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confLen);
1273 pm_descr.confVer =
1274 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confVer);
1275 pm_descr.confPA =
1276 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.pmConfDesc.confPA);
1278 vmxnet3_dump_conf_descr("PM State", &pm_descr);
1281 static void vmxnet3_update_features(VMXNET3State *s)
1283 uint32_t guest_features;
1284 int rxcso_supported;
1286 guest_features = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
1287 devRead.misc.uptFeatures);
1289 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
1290 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
1291 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
1293 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1294 s->lro_supported, rxcso_supported,
1295 s->rx_vlan_stripping);
1296 if (s->peer_has_vhdr) {
1297 qemu_set_offload(qemu_get_queue(s->nic)->peer,
1298 rxcso_supported,
1299 s->lro_supported,
1300 s->lro_supported,
1306 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx)
1308 return s->msix_used || s->msi_used || (intx ==
1309 (pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1));
1312 static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx)
1314 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS;
1315 if (idx >= max_ints) {
1316 hw_error("Bad interrupt index: %d\n", idx);
1320 static void vmxnet3_validate_interrupts(VMXNET3State *s)
1322 int i;
1324 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx);
1325 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx);
1327 for (i = 0; i < s->txq_num; i++) {
1328 int idx = s->txq_descr[i].intr_idx;
1329 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx);
1330 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1333 for (i = 0; i < s->rxq_num; i++) {
1334 int idx = s->rxq_descr[i].intr_idx;
1335 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx);
1336 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1340 static void vmxnet3_validate_queues(VMXNET3State *s)
1343 * txq_num and rxq_num are total number of queues
1344 * configured by guest. These numbers must not
1345 * exceed corresponding maximal values.
1348 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) {
1349 hw_error("Bad TX queues number: %d\n", s->txq_num);
1352 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) {
1353 hw_error("Bad RX queues number: %d\n", s->rxq_num);
1357 static void vmxnet3_activate_device(VMXNET3State *s)
1359 int i;
1360 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;
1361 hwaddr qdescr_table_pa;
1362 uint64_t pa;
1363 uint32_t size;
1365 /* Verify configuration consistency */
1366 if (!vmxnet3_verify_driver_magic(s->drv_shmem)) {
1367 VMW_ERPRN("Device configuration received from driver is invalid");
1368 return;
1371 vmxnet3_adjust_by_guest_type(s);
1372 vmxnet3_update_features(s);
1373 vmxnet3_update_pm_state(s);
1374 vmxnet3_setup_rx_filtering(s);
1375 /* Cache fields from shared memory */
1376 s->mtu = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.misc.mtu);
1377 VMW_CFPRN("MTU is %u", s->mtu);
1379 s->max_rx_frags =
1380 VMXNET3_READ_DRV_SHARED16(s->drv_shmem, devRead.misc.maxNumRxSG);
1382 if (s->max_rx_frags == 0) {
1383 s->max_rx_frags = 1;
1386 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);
1388 s->event_int_idx =
1389 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.eventIntrIdx);
1390 assert(vmxnet3_verify_intx(s, s->event_int_idx));
1391 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
1393 s->auto_int_masking =
1394 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.autoMask);
1395 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);
1397 s->txq_num =
1398 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numTxQueues);
1399 s->rxq_num =
1400 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numRxQueues);
1402 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
1403 vmxnet3_validate_queues(s);
1405 qdescr_table_pa =
1406 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.misc.queueDescPA);
1407 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);
1410 * Worst-case scenario is a packet that holds all TX rings space so
1411 * we calculate total size of all TX rings for max TX fragments number
1413 s->max_tx_frags = 0;
1415 /* TX queues */
1416 for (i = 0; i < s->txq_num; i++) {
1417 hwaddr qdescr_pa =
1418 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);
1420 /* Read interrupt number for this TX queue */
1421 s->txq_descr[i].intr_idx =
1422 VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa, conf.intrIdx);
1423 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx));
1425 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
1427 /* Read rings memory locations for TX queues */
1428 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.txRingBasePA);
1429 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.txRingSize);
1431 vmxnet3_ring_init(&s->txq_descr[i].tx_ring, pa, size,
1432 sizeof(struct Vmxnet3_TxDesc), false);
1433 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);
1435 s->max_tx_frags += size;
1437 /* TXC ring */
1438 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.compRingBasePA);
1439 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.compRingSize);
1440 vmxnet3_ring_init(&s->txq_descr[i].comp_ring, pa, size,
1441 sizeof(struct Vmxnet3_TxCompDesc), true);
1442 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);
1444 s->txq_descr[i].tx_stats_pa =
1445 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats);
1447 memset(&s->txq_descr[i].txq_stats, 0,
1448 sizeof(s->txq_descr[i].txq_stats));
1450 /* Fill device-managed parameters for queues */
1451 VMXNET3_WRITE_TX_QUEUE_DESCR32(qdescr_pa,
1452 ctrl.txThreshold,
1453 VMXNET3_DEF_TX_THRESHOLD);
1456 /* Preallocate TX packet wrapper */
1457 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
1458 vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
1459 vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
1461 /* Read rings memory locations for RX queues */
1462 for (i = 0; i < s->rxq_num; i++) {
1463 int j;
1464 hwaddr qd_pa =
1465 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1466 i * sizeof(struct Vmxnet3_RxQueueDesc);
1468 /* Read interrupt number for this RX queue */
1469 s->rxq_descr[i].intr_idx =
1470 VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa, conf.intrIdx);
1471 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx));
1473 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
1475 /* Read rings memory locations */
1476 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) {
1477 /* RX rings */
1478 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.rxRingBasePA[j]);
1479 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.rxRingSize[j]);
1480 vmxnet3_ring_init(&s->rxq_descr[i].rx_ring[j], pa, size,
1481 sizeof(struct Vmxnet3_RxDesc), false);
1482 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d",
1483 i, j, pa, size);
1486 /* RXC ring */
1487 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.compRingBasePA);
1488 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.compRingSize);
1489 vmxnet3_ring_init(&s->rxq_descr[i].comp_ring, pa, size,
1490 sizeof(struct Vmxnet3_RxCompDesc), true);
1491 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);
1493 s->rxq_descr[i].rx_stats_pa =
1494 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats);
1495 memset(&s->rxq_descr[i].rxq_stats, 0,
1496 sizeof(s->rxq_descr[i].rxq_stats));
1499 vmxnet3_validate_interrupts(s);
1501 /* Make sure everything is in place before device activation */
1502 smp_wmb();
1504 vmxnet3_reset_mac(s);
1506 s->device_active = true;
1509 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
1511 s->last_command = cmd;
1513 switch (cmd) {
1514 case VMXNET3_CMD_GET_PERM_MAC_HI:
1515 VMW_CBPRN("Set: Get upper part of permanent MAC");
1516 break;
1518 case VMXNET3_CMD_GET_PERM_MAC_LO:
1519 VMW_CBPRN("Set: Get lower part of permanent MAC");
1520 break;
1522 case VMXNET3_CMD_GET_STATS:
1523 VMW_CBPRN("Set: Get device statistics");
1524 vmxnet3_fill_stats(s);
1525 break;
1527 case VMXNET3_CMD_ACTIVATE_DEV:
1528 VMW_CBPRN("Set: Activating vmxnet3 device");
1529 vmxnet3_activate_device(s);
1530 break;
1532 case VMXNET3_CMD_UPDATE_RX_MODE:
1533 VMW_CBPRN("Set: Update rx mode");
1534 vmxnet3_update_rx_mode(s);
1535 break;
1537 case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
1538 VMW_CBPRN("Set: Update VLAN filters");
1539 vmxnet3_update_vlan_filters(s);
1540 break;
1542 case VMXNET3_CMD_UPDATE_MAC_FILTERS:
1543 VMW_CBPRN("Set: Update MAC filters");
1544 vmxnet3_update_mcast_filters(s);
1545 break;
1547 case VMXNET3_CMD_UPDATE_FEATURE:
1548 VMW_CBPRN("Set: Update features");
1549 vmxnet3_update_features(s);
1550 break;
1552 case VMXNET3_CMD_UPDATE_PMCFG:
1553 VMW_CBPRN("Set: Update power management config");
1554 vmxnet3_update_pm_state(s);
1555 break;
1557 case VMXNET3_CMD_GET_LINK:
1558 VMW_CBPRN("Set: Get link");
1559 break;
1561 case VMXNET3_CMD_RESET_DEV:
1562 VMW_CBPRN("Set: Reset device");
1563 vmxnet3_reset(s);
1564 break;
1566 case VMXNET3_CMD_QUIESCE_DEV:
1567 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - pause the device");
1568 vmxnet3_deactivate_device(s);
1569 break;
1571 case VMXNET3_CMD_GET_CONF_INTR:
1572 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1573 break;
1575 default:
1576 VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
1577 break;
1581 static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
1583 uint64_t ret;
1585 switch (s->last_command) {
1586 case VMXNET3_CMD_ACTIVATE_DEV:
1587 ret = (s->device_active) ? 0 : -1;
1588 VMW_CFPRN("Device active: %" PRIx64, ret);
1589 break;
1591 case VMXNET3_CMD_RESET_DEV:
1592 case VMXNET3_CMD_QUIESCE_DEV:
1593 case VMXNET3_CMD_GET_QUEUE_STATUS:
1594 ret = 0;
1595 break;
1597 case VMXNET3_CMD_GET_LINK:
1598 ret = s->link_status_and_speed;
1599 VMW_CFPRN("Link and speed: %" PRIx64, ret);
1600 break;
1602 case VMXNET3_CMD_GET_PERM_MAC_LO:
1603 ret = vmxnet3_get_mac_low(&s->perm_mac);
1604 break;
1606 case VMXNET3_CMD_GET_PERM_MAC_HI:
1607 ret = vmxnet3_get_mac_high(&s->perm_mac);
1608 break;
1610 case VMXNET3_CMD_GET_CONF_INTR:
1611 ret = vmxnet3_get_interrupt_config(s);
1612 break;
1614 default:
1615 VMW_WRPRN("Received request for unknown command: %x", s->last_command);
1616 ret = -1;
1617 break;
1620 return ret;
1623 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
1625 uint32_t events;
1627 VMW_CBPRN("Setting events: 0x%x", val);
1628 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) | val;
1629 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
1632 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
1634 uint32_t events;
1636 VMW_CBPRN("Clearing events: 0x%x", val);
1637 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) & ~val;
1638 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
1641 static void
1642 vmxnet3_io_bar1_write(void *opaque,
1643 hwaddr addr,
1644 uint64_t val,
1645 unsigned size)
1647 VMXNET3State *s = opaque;
1649 switch (addr) {
1650 /* Vmxnet3 Revision Report Selection */
1651 case VMXNET3_REG_VRRS:
1652 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
1653 val, size);
1654 break;
1656 /* UPT Version Report Selection */
1657 case VMXNET3_REG_UVRS:
1658 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
1659 val, size);
1660 break;
1662 /* Driver Shared Address Low */
1663 case VMXNET3_REG_DSAL:
1664 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
1665 val, size);
1667 * Guest driver will first write the low part of the shared
1668 * memory address. We save it to temp variable and set the
1669 * shared address only after we get the high part
1671 if (val == 0) {
1672 s->device_active = false;
1674 s->temp_shared_guest_driver_memory = val;
1675 s->drv_shmem = 0;
1676 break;
1678 /* Driver Shared Address High */
1679 case VMXNET3_REG_DSAH:
1680 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
1681 val, size);
1683 * Set the shared memory between guest driver and device.
1684 * We already should have low address part.
1686 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
1687 break;
1689 /* Command */
1690 case VMXNET3_REG_CMD:
1691 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
1692 val, size);
1693 vmxnet3_handle_command(s, val);
1694 break;
1696 /* MAC Address Low */
1697 case VMXNET3_REG_MACL:
1698 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
1699 val, size);
1700 s->temp_mac = val;
1701 break;
1703 /* MAC Address High */
1704 case VMXNET3_REG_MACH:
1705 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
1706 val, size);
1707 vmxnet3_set_variable_mac(s, val, s->temp_mac);
1708 break;
1710 /* Interrupt Cause Register */
1711 case VMXNET3_REG_ICR:
1712 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
1713 val, size);
1714 g_assert_not_reached();
1715 break;
1717 /* Event Cause Register */
1718 case VMXNET3_REG_ECR:
1719 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
1720 val, size);
1721 vmxnet3_ack_events(s, val);
1722 break;
1724 default:
1725 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
1726 addr, val, size);
1727 break;
1731 static uint64_t
1732 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
1734 VMXNET3State *s = opaque;
1735 uint64_t ret = 0;
1737 switch (addr) {
1738 /* Vmxnet3 Revision Report Selection */
1739 case VMXNET3_REG_VRRS:
1740 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
1741 ret = VMXNET3_DEVICE_REVISION;
1742 break;
1744 /* UPT Version Report Selection */
1745 case VMXNET3_REG_UVRS:
1746 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
1747 ret = VMXNET3_DEVICE_VERSION;
1748 break;
1750 /* Command */
1751 case VMXNET3_REG_CMD:
1752 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
1753 ret = vmxnet3_get_command_status(s);
1754 break;
1756 /* MAC Address Low */
1757 case VMXNET3_REG_MACL:
1758 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
1759 ret = vmxnet3_get_mac_low(&s->conf.macaddr);
1760 break;
1762 /* MAC Address High */
1763 case VMXNET3_REG_MACH:
1764 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
1765 ret = vmxnet3_get_mac_high(&s->conf.macaddr);
1766 break;
1769 * Interrupt Cause Register
1770 * Used for legacy interrupts only so interrupt index always 0
1772 case VMXNET3_REG_ICR:
1773 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
1774 if (vmxnet3_interrupt_asserted(s, 0)) {
1775 vmxnet3_clear_interrupt(s, 0);
1776 ret = true;
1777 } else {
1778 ret = false;
1780 break;
1782 default:
1783 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size);
1784 break;
1787 return ret;
1790 static int
1791 vmxnet3_can_receive(NetClientState *nc)
1793 VMXNET3State *s = qemu_get_nic_opaque(nc);
1794 return s->device_active &&
1795 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP);
1798 static inline bool
1799 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data)
1801 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK;
1802 if (IS_SPECIAL_VLAN_ID(vlan_tag)) {
1803 return true;
1806 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag);
1809 static bool
1810 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac)
1812 int i;
1813 for (i = 0; i < s->mcast_list_len; i++) {
1814 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) {
1815 return true;
1818 return false;
1821 static bool
1822 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
1823 size_t size)
1825 struct eth_header *ehdr = PKT_GET_ETH_HDR(data);
1827 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) {
1828 return true;
1831 if (!vmxnet3_is_registered_vlan(s, data)) {
1832 return false;
1835 switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
1836 case ETH_PKT_UCAST:
1837 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) {
1838 return false;
1840 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) {
1841 return false;
1843 break;
1845 case ETH_PKT_BCAST:
1846 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) {
1847 return false;
1849 break;
1851 case ETH_PKT_MCAST:
1852 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) {
1853 return true;
1855 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) {
1856 return false;
1858 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) {
1859 return false;
1861 break;
1863 default:
1864 g_assert_not_reached();
1867 return true;
1870 static ssize_t
1871 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1873 VMXNET3State *s = qemu_get_nic_opaque(nc);
1874 size_t bytes_indicated;
1875 uint8_t min_buf[MIN_BUF_SIZE];
1877 if (!vmxnet3_can_receive(nc)) {
1878 VMW_PKPRN("Cannot receive now");
1879 return -1;
1882 /* Pad to minimum Ethernet frame length */
1883 if (size < sizeof(min_buf)) {
1884 memcpy(min_buf, buf, size);
1885 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1886 buf = min_buf;
1887 size = sizeof(min_buf);
1890 if (s->peer_has_vhdr) {
1891 vmxnet_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
1892 buf += sizeof(struct virtio_net_hdr);
1893 size -= sizeof(struct virtio_net_hdr);
1896 vmxnet_rx_pkt_set_packet_type(s->rx_pkt,
1897 get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
1899 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
1900 vmxnet_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
1901 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
1902 if (bytes_indicated < size) {
1903 VMW_PKPRN("RX: %lu of %lu bytes indicated", bytes_indicated, size);
1905 } else {
1906 VMW_PKPRN("Packet dropped by RX filter");
1907 bytes_indicated = size;
1910 assert(size > 0);
1911 assert(bytes_indicated != 0);
1912 return bytes_indicated;
1915 static void vmxnet3_set_link_status(NetClientState *nc)
1917 VMXNET3State *s = qemu_get_nic_opaque(nc);
1919 if (nc->link_down) {
1920 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP;
1921 } else {
1922 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP;
1925 vmxnet3_set_events(s, VMXNET3_ECR_LINK);
1926 vmxnet3_trigger_interrupt(s, s->event_int_idx);
1929 static NetClientInfo net_vmxnet3_info = {
1930 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1931 .size = sizeof(NICState),
1932 .can_receive = vmxnet3_can_receive,
1933 .receive = vmxnet3_receive,
1934 .link_status_changed = vmxnet3_set_link_status,
1937 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
1939 NetClientState *nc = qemu_get_queue(s->nic);
1941 if (qemu_has_vnet_hdr(nc->peer)) {
1942 return true;
1945 VMW_WRPRN("Peer has no virtio extension. Task offloads will be emulated.");
1946 return false;
1949 static void vmxnet3_net_uninit(VMXNET3State *s)
1951 g_free(s->mcast_list);
1952 vmxnet_tx_pkt_reset(s->tx_pkt);
1953 vmxnet_tx_pkt_uninit(s->tx_pkt);
1954 vmxnet_rx_pkt_uninit(s->rx_pkt);
1955 qemu_del_nic(s->nic);
1958 static void vmxnet3_net_init(VMXNET3State *s)
1960 DeviceState *d = DEVICE(s);
1962 VMW_CBPRN("vmxnet3_net_init called...");
1964 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1966 /* Windows guest will query the address that was set on init */
1967 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a));
1969 s->mcast_list = NULL;
1970 s->mcast_list_len = 0;
1972 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP;
1974 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a));
1976 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf,
1977 object_get_typename(OBJECT(s)),
1978 d->id, s);
1980 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s);
1981 s->tx_sop = true;
1982 s->skip_current_tx_pkt = false;
1983 s->tx_pkt = NULL;
1984 s->rx_pkt = NULL;
1985 s->rx_vlan_stripping = false;
1986 s->lro_supported = false;
1988 if (s->peer_has_vhdr) {
1989 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
1990 sizeof(struct virtio_net_hdr));
1992 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1);
1995 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1998 static void
1999 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors)
2001 PCIDevice *d = PCI_DEVICE(s);
2002 int i;
2003 for (i = 0; i < num_vectors; i++) {
2004 msix_vector_unuse(d, i);
2008 static bool
2009 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors)
2011 PCIDevice *d = PCI_DEVICE(s);
2012 int i;
2013 for (i = 0; i < num_vectors; i++) {
2014 int res = msix_vector_use(d, i);
2015 if (0 > res) {
2016 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res);
2017 vmxnet3_unuse_msix_vectors(s, i);
2018 return false;
2021 return true;
2024 static bool
2025 vmxnet3_init_msix(VMXNET3State *s)
2027 PCIDevice *d = PCI_DEVICE(s);
2028 int res = msix_init(d, VMXNET3_MAX_INTRS,
2029 &s->msix_bar,
2030 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
2031 &s->msix_bar,
2032 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA,
2035 if (0 > res) {
2036 VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
2037 s->msix_used = false;
2038 } else {
2039 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2040 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res);
2041 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2042 s->msix_used = false;
2043 } else {
2044 s->msix_used = true;
2047 return s->msix_used;
2050 static void
2051 vmxnet3_cleanup_msix(VMXNET3State *s)
2053 PCIDevice *d = PCI_DEVICE(s);
2055 if (s->msix_used) {
2056 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS);
2057 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2061 #define VMXNET3_MSI_OFFSET (0x50)
2062 #define VMXNET3_USE_64BIT (true)
2063 #define VMXNET3_PER_VECTOR_MASK (false)
2065 static bool
2066 vmxnet3_init_msi(VMXNET3State *s)
2068 PCIDevice *d = PCI_DEVICE(s);
2069 int res;
2071 res = msi_init(d, VMXNET3_MSI_OFFSET, VMXNET3_MAX_NMSIX_INTRS,
2072 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK);
2073 if (0 > res) {
2074 VMW_WRPRN("Failed to initialize MSI, error %d", res);
2075 s->msi_used = false;
2076 } else {
2077 s->msi_used = true;
2080 return s->msi_used;
2083 static void
2084 vmxnet3_cleanup_msi(VMXNET3State *s)
2086 PCIDevice *d = PCI_DEVICE(s);
2088 if (s->msi_used) {
2089 msi_uninit(d);
2093 static void
2094 vmxnet3_msix_save(QEMUFile *f, void *opaque)
2096 PCIDevice *d = PCI_DEVICE(opaque);
2097 msix_save(d, f);
2100 static int
2101 vmxnet3_msix_load(QEMUFile *f, void *opaque, int version_id)
2103 PCIDevice *d = PCI_DEVICE(opaque);
2104 msix_load(d, f);
2105 return 0;
2108 static const MemoryRegionOps b0_ops = {
2109 .read = vmxnet3_io_bar0_read,
2110 .write = vmxnet3_io_bar0_write,
2111 .endianness = DEVICE_LITTLE_ENDIAN,
2112 .impl = {
2113 .min_access_size = 4,
2114 .max_access_size = 4,
2118 static const MemoryRegionOps b1_ops = {
2119 .read = vmxnet3_io_bar1_read,
2120 .write = vmxnet3_io_bar1_write,
2121 .endianness = DEVICE_LITTLE_ENDIAN,
2122 .impl = {
2123 .min_access_size = 4,
2124 .max_access_size = 4,
2128 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
2130 DeviceState *dev = DEVICE(pci_dev);
2131 VMXNET3State *s = VMXNET3(pci_dev);
2133 VMW_CBPRN("Starting init...");
2135 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
2136 "vmxnet3-b0", VMXNET3_PT_REG_SIZE);
2137 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
2138 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
2140 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
2141 "vmxnet3-b1", VMXNET3_VD_REG_SIZE);
2142 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
2143 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
2145 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
2146 VMXNET3_MSIX_BAR_SIZE);
2147 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
2148 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
2150 vmxnet3_reset_interrupt_states(s);
2152 /* Interrupt pin A */
2153 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
2155 if (!vmxnet3_init_msix(s)) {
2156 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2159 if (!vmxnet3_init_msi(s)) {
2160 VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
2163 vmxnet3_net_init(s);
2165 register_savevm(dev, "vmxnet3-msix", -1, 1,
2166 vmxnet3_msix_save, vmxnet3_msix_load, s);
2169 static void vmxnet3_instance_init(Object *obj)
2171 VMXNET3State *s = VMXNET3(obj);
2172 device_add_bootindex_property(obj, &s->conf.bootindex,
2173 "bootindex", "/ethernet-phy@0",
2174 DEVICE(obj), NULL);
2177 static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
2179 DeviceState *dev = DEVICE(pci_dev);
2180 VMXNET3State *s = VMXNET3(pci_dev);
2182 VMW_CBPRN("Starting uninit...");
2184 unregister_savevm(dev, "vmxnet3-msix", s);
2186 vmxnet3_net_uninit(s);
2188 vmxnet3_cleanup_msix(s);
2190 vmxnet3_cleanup_msi(s);
2193 static void vmxnet3_qdev_reset(DeviceState *dev)
2195 PCIDevice *d = PCI_DEVICE(dev);
2196 VMXNET3State *s = VMXNET3(d);
2198 VMW_CBPRN("Starting QDEV reset...");
2199 vmxnet3_reset(s);
2202 static bool vmxnet3_mc_list_needed(void *opaque)
2204 return true;
2207 static int vmxnet3_mcast_list_pre_load(void *opaque)
2209 VMXNET3State *s = opaque;
2211 s->mcast_list = g_malloc(s->mcast_list_buff_size);
2213 return 0;
2217 static void vmxnet3_pre_save(void *opaque)
2219 VMXNET3State *s = opaque;
2221 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr);
2224 static const VMStateDescription vmxstate_vmxnet3_mcast_list = {
2225 .name = "vmxnet3/mcast_list",
2226 .version_id = 1,
2227 .minimum_version_id = 1,
2228 .pre_load = vmxnet3_mcast_list_pre_load,
2229 .fields = (VMStateField[]) {
2230 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 0,
2231 mcast_list_buff_size),
2232 VMSTATE_END_OF_LIST()
2236 static void vmxnet3_get_ring_from_file(QEMUFile *f, Vmxnet3Ring *r)
2238 r->pa = qemu_get_be64(f);
2239 r->size = qemu_get_be32(f);
2240 r->cell_size = qemu_get_be32(f);
2241 r->next = qemu_get_be32(f);
2242 r->gen = qemu_get_byte(f);
2245 static void vmxnet3_put_ring_to_file(QEMUFile *f, Vmxnet3Ring *r)
2247 qemu_put_be64(f, r->pa);
2248 qemu_put_be32(f, r->size);
2249 qemu_put_be32(f, r->cell_size);
2250 qemu_put_be32(f, r->next);
2251 qemu_put_byte(f, r->gen);
2254 static void vmxnet3_get_tx_stats_from_file(QEMUFile *f,
2255 struct UPT1_TxStats *tx_stat)
2257 tx_stat->TSOPktsTxOK = qemu_get_be64(f);
2258 tx_stat->TSOBytesTxOK = qemu_get_be64(f);
2259 tx_stat->ucastPktsTxOK = qemu_get_be64(f);
2260 tx_stat->ucastBytesTxOK = qemu_get_be64(f);
2261 tx_stat->mcastPktsTxOK = qemu_get_be64(f);
2262 tx_stat->mcastBytesTxOK = qemu_get_be64(f);
2263 tx_stat->bcastPktsTxOK = qemu_get_be64(f);
2264 tx_stat->bcastBytesTxOK = qemu_get_be64(f);
2265 tx_stat->pktsTxError = qemu_get_be64(f);
2266 tx_stat->pktsTxDiscard = qemu_get_be64(f);
2269 static void vmxnet3_put_tx_stats_to_file(QEMUFile *f,
2270 struct UPT1_TxStats *tx_stat)
2272 qemu_put_be64(f, tx_stat->TSOPktsTxOK);
2273 qemu_put_be64(f, tx_stat->TSOBytesTxOK);
2274 qemu_put_be64(f, tx_stat->ucastPktsTxOK);
2275 qemu_put_be64(f, tx_stat->ucastBytesTxOK);
2276 qemu_put_be64(f, tx_stat->mcastPktsTxOK);
2277 qemu_put_be64(f, tx_stat->mcastBytesTxOK);
2278 qemu_put_be64(f, tx_stat->bcastPktsTxOK);
2279 qemu_put_be64(f, tx_stat->bcastBytesTxOK);
2280 qemu_put_be64(f, tx_stat->pktsTxError);
2281 qemu_put_be64(f, tx_stat->pktsTxDiscard);
2284 static int vmxnet3_get_txq_descr(QEMUFile *f, void *pv, size_t size)
2286 Vmxnet3TxqDescr *r = pv;
2288 vmxnet3_get_ring_from_file(f, &r->tx_ring);
2289 vmxnet3_get_ring_from_file(f, &r->comp_ring);
2290 r->intr_idx = qemu_get_byte(f);
2291 r->tx_stats_pa = qemu_get_be64(f);
2293 vmxnet3_get_tx_stats_from_file(f, &r->txq_stats);
2295 return 0;
2298 static void vmxnet3_put_txq_descr(QEMUFile *f, void *pv, size_t size)
2300 Vmxnet3TxqDescr *r = pv;
2302 vmxnet3_put_ring_to_file(f, &r->tx_ring);
2303 vmxnet3_put_ring_to_file(f, &r->comp_ring);
2304 qemu_put_byte(f, r->intr_idx);
2305 qemu_put_be64(f, r->tx_stats_pa);
2306 vmxnet3_put_tx_stats_to_file(f, &r->txq_stats);
2309 static const VMStateInfo txq_descr_info = {
2310 .name = "txq_descr",
2311 .get = vmxnet3_get_txq_descr,
2312 .put = vmxnet3_put_txq_descr
2315 static void vmxnet3_get_rx_stats_from_file(QEMUFile *f,
2316 struct UPT1_RxStats *rx_stat)
2318 rx_stat->LROPktsRxOK = qemu_get_be64(f);
2319 rx_stat->LROBytesRxOK = qemu_get_be64(f);
2320 rx_stat->ucastPktsRxOK = qemu_get_be64(f);
2321 rx_stat->ucastBytesRxOK = qemu_get_be64(f);
2322 rx_stat->mcastPktsRxOK = qemu_get_be64(f);
2323 rx_stat->mcastBytesRxOK = qemu_get_be64(f);
2324 rx_stat->bcastPktsRxOK = qemu_get_be64(f);
2325 rx_stat->bcastBytesRxOK = qemu_get_be64(f);
2326 rx_stat->pktsRxOutOfBuf = qemu_get_be64(f);
2327 rx_stat->pktsRxError = qemu_get_be64(f);
2330 static void vmxnet3_put_rx_stats_to_file(QEMUFile *f,
2331 struct UPT1_RxStats *rx_stat)
2333 qemu_put_be64(f, rx_stat->LROPktsRxOK);
2334 qemu_put_be64(f, rx_stat->LROBytesRxOK);
2335 qemu_put_be64(f, rx_stat->ucastPktsRxOK);
2336 qemu_put_be64(f, rx_stat->ucastBytesRxOK);
2337 qemu_put_be64(f, rx_stat->mcastPktsRxOK);
2338 qemu_put_be64(f, rx_stat->mcastBytesRxOK);
2339 qemu_put_be64(f, rx_stat->bcastPktsRxOK);
2340 qemu_put_be64(f, rx_stat->bcastBytesRxOK);
2341 qemu_put_be64(f, rx_stat->pktsRxOutOfBuf);
2342 qemu_put_be64(f, rx_stat->pktsRxError);
2345 static int vmxnet3_get_rxq_descr(QEMUFile *f, void *pv, size_t size)
2347 Vmxnet3RxqDescr *r = pv;
2348 int i;
2350 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
2351 vmxnet3_get_ring_from_file(f, &r->rx_ring[i]);
2354 vmxnet3_get_ring_from_file(f, &r->comp_ring);
2355 r->intr_idx = qemu_get_byte(f);
2356 r->rx_stats_pa = qemu_get_be64(f);
2358 vmxnet3_get_rx_stats_from_file(f, &r->rxq_stats);
2360 return 0;
2363 static void vmxnet3_put_rxq_descr(QEMUFile *f, void *pv, size_t size)
2365 Vmxnet3RxqDescr *r = pv;
2366 int i;
2368 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
2369 vmxnet3_put_ring_to_file(f, &r->rx_ring[i]);
2372 vmxnet3_put_ring_to_file(f, &r->comp_ring);
2373 qemu_put_byte(f, r->intr_idx);
2374 qemu_put_be64(f, r->rx_stats_pa);
2375 vmxnet3_put_rx_stats_to_file(f, &r->rxq_stats);
2378 static int vmxnet3_post_load(void *opaque, int version_id)
2380 VMXNET3State *s = opaque;
2381 PCIDevice *d = PCI_DEVICE(s);
2383 vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
2384 vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
2386 if (s->msix_used) {
2387 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2388 VMW_WRPRN("Failed to re-use MSI-X vectors");
2389 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2390 s->msix_used = false;
2391 return -1;
2395 vmxnet3_validate_queues(s);
2396 vmxnet3_validate_interrupts(s);
2398 return 0;
2401 static const VMStateInfo rxq_descr_info = {
2402 .name = "rxq_descr",
2403 .get = vmxnet3_get_rxq_descr,
2404 .put = vmxnet3_put_rxq_descr
2407 static int vmxnet3_get_int_state(QEMUFile *f, void *pv, size_t size)
2409 Vmxnet3IntState *r = pv;
2411 r->is_masked = qemu_get_byte(f);
2412 r->is_pending = qemu_get_byte(f);
2413 r->is_asserted = qemu_get_byte(f);
2415 return 0;
2418 static void vmxnet3_put_int_state(QEMUFile *f, void *pv, size_t size)
2420 Vmxnet3IntState *r = pv;
2422 qemu_put_byte(f, r->is_masked);
2423 qemu_put_byte(f, r->is_pending);
2424 qemu_put_byte(f, r->is_asserted);
2427 static const VMStateInfo int_state_info = {
2428 .name = "int_state",
2429 .get = vmxnet3_get_int_state,
2430 .put = vmxnet3_put_int_state
2433 static const VMStateDescription vmstate_vmxnet3 = {
2434 .name = "vmxnet3",
2435 .version_id = 1,
2436 .minimum_version_id = 1,
2437 .pre_save = vmxnet3_pre_save,
2438 .post_load = vmxnet3_post_load,
2439 .fields = (VMStateField[]) {
2440 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State),
2441 VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
2442 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
2443 VMSTATE_BOOL(lro_supported, VMXNET3State),
2444 VMSTATE_UINT32(rx_mode, VMXNET3State),
2445 VMSTATE_UINT32(mcast_list_len, VMXNET3State),
2446 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State),
2447 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE),
2448 VMSTATE_UINT32(mtu, VMXNET3State),
2449 VMSTATE_UINT16(max_rx_frags, VMXNET3State),
2450 VMSTATE_UINT32(max_tx_frags, VMXNET3State),
2451 VMSTATE_UINT8(event_int_idx, VMXNET3State),
2452 VMSTATE_BOOL(auto_int_masking, VMXNET3State),
2453 VMSTATE_UINT8(txq_num, VMXNET3State),
2454 VMSTATE_UINT8(rxq_num, VMXNET3State),
2455 VMSTATE_UINT32(device_active, VMXNET3State),
2456 VMSTATE_UINT32(last_command, VMXNET3State),
2457 VMSTATE_UINT32(link_status_and_speed, VMXNET3State),
2458 VMSTATE_UINT32(temp_mac, VMXNET3State),
2459 VMSTATE_UINT64(drv_shmem, VMXNET3State),
2460 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State),
2462 VMSTATE_ARRAY(txq_descr, VMXNET3State,
2463 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, txq_descr_info,
2464 Vmxnet3TxqDescr),
2465 VMSTATE_ARRAY(rxq_descr, VMXNET3State,
2466 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, rxq_descr_info,
2467 Vmxnet3RxqDescr),
2468 VMSTATE_ARRAY(interrupt_states, VMXNET3State, VMXNET3_MAX_INTRS,
2469 0, int_state_info, Vmxnet3IntState),
2471 VMSTATE_END_OF_LIST()
2473 .subsections = (VMStateSubsection[]) {
2475 .vmsd = &vmxstate_vmxnet3_mcast_list,
2476 .needed = vmxnet3_mc_list_needed
2479 /* empty element. */
2484 static void
2485 vmxnet3_write_config(PCIDevice *pci_dev, uint32_t addr, uint32_t val, int len)
2487 pci_default_write_config(pci_dev, addr, val, len);
2488 msix_write_config(pci_dev, addr, val, len);
2489 msi_write_config(pci_dev, addr, val, len);
2492 static Property vmxnet3_properties[] = {
2493 DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
2494 DEFINE_PROP_END_OF_LIST(),
2497 static void vmxnet3_class_init(ObjectClass *class, void *data)
2499 DeviceClass *dc = DEVICE_CLASS(class);
2500 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
2502 c->realize = vmxnet3_pci_realize;
2503 c->exit = vmxnet3_pci_uninit;
2504 c->vendor_id = PCI_VENDOR_ID_VMWARE;
2505 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2506 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
2507 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
2508 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
2509 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2510 c->config_write = vmxnet3_write_config,
2511 dc->desc = "VMWare Paravirtualized Ethernet v3";
2512 dc->reset = vmxnet3_qdev_reset;
2513 dc->vmsd = &vmstate_vmxnet3;
2514 dc->props = vmxnet3_properties;
2515 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
2518 static const TypeInfo vmxnet3_info = {
2519 .name = TYPE_VMXNET3,
2520 .parent = TYPE_PCI_DEVICE,
2521 .instance_size = sizeof(VMXNET3State),
2522 .class_init = vmxnet3_class_init,
2523 .instance_init = vmxnet3_instance_init,
2526 static void vmxnet3_register_types(void)
2528 VMW_CBPRN("vmxnet3_register_types called...");
2529 type_register_static(&vmxnet3_info);
2532 type_init(vmxnet3_register_types)