2 * QEMU NE2000 emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/pci/pci.h"
28 #include "hw/loader.h"
29 #include "sysemu/sysemu.h"
31 /* debug NE2000 card */
32 //#define DEBUG_NE2000
34 #define MAX_ETH_FRAME_SIZE 1514
36 #define E8390_CMD 0x00 /* The command register (for all pages) */
37 /* Page 0 register offsets. */
38 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
39 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
40 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
41 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
42 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
43 #define EN0_TSR 0x04 /* Transmit status reg RD */
44 #define EN0_TPSR 0x04 /* Transmit starting page WR */
45 #define EN0_NCR 0x05 /* Number of collision reg RD */
46 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
47 #define EN0_FIFO 0x06 /* FIFO RD */
48 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
49 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
50 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
51 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
52 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
53 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
54 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
55 #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
56 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
57 #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
58 #define EN0_RSR 0x0c /* rx status reg RD */
59 #define EN0_RXCR 0x0c /* RX configuration reg WR */
60 #define EN0_TXCR 0x0d /* TX configuration reg WR */
61 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
62 #define EN0_DCFG 0x0e /* Data configuration reg WR */
63 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
64 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
65 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
68 #define EN1_CURPAG 0x17
71 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
72 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
74 #define EN3_CONFIG0 0x33
75 #define EN3_CONFIG1 0x34
76 #define EN3_CONFIG2 0x35
77 #define EN3_CONFIG3 0x36
79 /* Register accessed at EN_CMD, the 8390 base addr. */
80 #define E8390_STOP 0x01 /* Stop and reset the chip */
81 #define E8390_START 0x02 /* Start the chip, clear reset */
82 #define E8390_TRANS 0x04 /* Transmit a frame */
83 #define E8390_RREAD 0x08 /* Remote read */
84 #define E8390_RWRITE 0x10 /* Remote write */
85 #define E8390_NODMA 0x20 /* Remote DMA */
86 #define E8390_PAGE0 0x00 /* Select page chip registers */
87 #define E8390_PAGE1 0x40 /* using the two high-order bits */
88 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
90 /* Bits in EN0_ISR - Interrupt status register */
91 #define ENISR_RX 0x01 /* Receiver, no error */
92 #define ENISR_TX 0x02 /* Transmitter, no error */
93 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
94 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
95 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
96 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
97 #define ENISR_RDC 0x40 /* remote dma complete */
98 #define ENISR_RESET 0x80 /* Reset completed */
99 #define ENISR_ALL 0x3f /* Interrupts we will enable */
101 /* Bits in received packet status byte and EN0_RSR*/
102 #define ENRSR_RXOK 0x01 /* Received a good packet */
103 #define ENRSR_CRC 0x02 /* CRC error */
104 #define ENRSR_FAE 0x04 /* frame alignment error */
105 #define ENRSR_FO 0x08 /* FIFO overrun */
106 #define ENRSR_MPA 0x10 /* missed pkt */
107 #define ENRSR_PHY 0x20 /* physical/multicast address */
108 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
109 #define ENRSR_DEF 0x80 /* deferring */
111 /* Transmitted packet status, EN0_TSR. */
112 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
113 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
114 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
115 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
116 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
117 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
118 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
119 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
121 typedef struct PCINE2000State
{
126 void ne2000_reset(NE2000State
*s
)
130 s
->isr
= ENISR_RESET
;
131 memcpy(s
->mem
, &s
->c
.macaddr
, 6);
135 /* duplicate prom data */
136 for(i
= 15;i
>= 0; i
--) {
137 s
->mem
[2 * i
] = s
->mem
[i
];
138 s
->mem
[2 * i
+ 1] = s
->mem
[i
];
142 static void ne2000_update_irq(NE2000State
*s
)
145 isr
= (s
->isr
& s
->imr
) & 0x7f;
146 #if defined(DEBUG_NE2000)
147 printf("NE2000: Set IRQ to %d (%02x %02x)\n",
148 isr
? 1 : 0, s
->isr
, s
->imr
);
150 qemu_set_irq(s
->irq
, (isr
!= 0));
153 static int ne2000_buffer_full(NE2000State
*s
)
155 int avail
, index
, boundary
;
157 index
= s
->curpag
<< 8;
158 boundary
= s
->boundary
<< 8;
159 if (index
< boundary
)
160 avail
= boundary
- index
;
162 avail
= (s
->stop
- s
->start
) - (index
- boundary
);
163 if (avail
< (MAX_ETH_FRAME_SIZE
+ 4))
168 int ne2000_can_receive(NetClientState
*nc
)
170 NE2000State
*s
= qemu_get_nic_opaque(nc
);
172 if (s
->cmd
& E8390_STOP
)
174 return !ne2000_buffer_full(s
);
177 #define MIN_BUF_SIZE 60
179 ssize_t
ne2000_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size_
)
181 NE2000State
*s
= qemu_get_nic_opaque(nc
);
184 unsigned int total_len
, next
, avail
, len
, index
, mcast_idx
;
186 static const uint8_t broadcast_macaddr
[6] =
187 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
189 #if defined(DEBUG_NE2000)
190 printf("NE2000: received len=%d\n", size
);
193 if (s
->cmd
& E8390_STOP
|| ne2000_buffer_full(s
))
196 /* XXX: check this */
197 if (s
->rxcr
& 0x10) {
198 /* promiscuous: receive all */
200 if (!memcmp(buf
, broadcast_macaddr
, 6)) {
201 /* broadcast address */
202 if (!(s
->rxcr
& 0x04))
204 } else if (buf
[0] & 0x01) {
206 if (!(s
->rxcr
& 0x08))
208 mcast_idx
= compute_mcast_idx(buf
);
209 if (!(s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7))))
211 } else if (s
->mem
[0] == buf
[0] &&
212 s
->mem
[2] == buf
[1] &&
213 s
->mem
[4] == buf
[2] &&
214 s
->mem
[6] == buf
[3] &&
215 s
->mem
[8] == buf
[4] &&
216 s
->mem
[10] == buf
[5]) {
224 /* if too small buffer, then expand it */
225 if (size
< MIN_BUF_SIZE
) {
226 memcpy(buf1
, buf
, size
);
227 memset(buf1
+ size
, 0, MIN_BUF_SIZE
- size
);
232 index
= s
->curpag
<< 8;
233 /* 4 bytes for header */
234 total_len
= size
+ 4;
235 /* address for next packet (4 bytes for CRC) */
236 next
= index
+ ((total_len
+ 4 + 255) & ~0xff);
238 next
-= (s
->stop
- s
->start
);
239 /* prepare packet header */
241 s
->rsr
= ENRSR_RXOK
; /* receive status */
242 /* XXX: check this */
248 p
[3] = total_len
>> 8;
251 /* write packet data */
253 if (index
<= s
->stop
)
254 avail
= s
->stop
- index
;
260 memcpy(s
->mem
+ index
, buf
, len
);
263 if (index
== s
->stop
)
267 s
->curpag
= next
>> 8;
269 /* now we can signal we have received something */
271 ne2000_update_irq(s
);
276 static void ne2000_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
278 NE2000State
*s
= opaque
;
279 int offset
, page
, index
;
283 printf("NE2000: write addr=0x%x val=0x%02x\n", addr
, val
);
285 if (addr
== E8390_CMD
) {
286 /* control register */
288 if (!(val
& E8390_STOP
)) { /* START bit makes no sense on RTL8029... */
289 s
->isr
&= ~ENISR_RESET
;
290 /* test specific case: zero length transfer */
291 if ((val
& (E8390_RREAD
| E8390_RWRITE
)) &&
294 ne2000_update_irq(s
);
296 if (val
& E8390_TRANS
) {
297 index
= (s
->tpsr
<< 8);
298 /* XXX: next 2 lines are a hack to make netware 3.11 work */
299 if (index
>= NE2000_PMEM_END
)
300 index
-= NE2000_PMEM_SIZE
;
301 /* fail safe: check range on the transmitted length */
302 if (index
+ s
->tcnt
<= NE2000_PMEM_END
) {
303 qemu_send_packet(qemu_get_queue(s
->nic
), s
->mem
+ index
,
306 /* signal end of transfer */
309 s
->cmd
&= ~E8390_TRANS
;
310 ne2000_update_irq(s
);
315 offset
= addr
| (page
<< 4);
328 ne2000_update_irq(s
);
334 s
->tcnt
= (s
->tcnt
& 0xff00) | val
;
337 s
->tcnt
= (s
->tcnt
& 0x00ff) | (val
<< 8);
340 s
->rsar
= (s
->rsar
& 0xff00) | val
;
343 s
->rsar
= (s
->rsar
& 0x00ff) | (val
<< 8);
346 s
->rcnt
= (s
->rcnt
& 0xff00) | val
;
349 s
->rcnt
= (s
->rcnt
& 0x00ff) | (val
<< 8);
358 s
->isr
&= ~(val
& 0x7f);
359 ne2000_update_irq(s
);
361 case EN1_PHYS
... EN1_PHYS
+ 5:
362 s
->phys
[offset
- EN1_PHYS
] = val
;
367 case EN1_MULT
... EN1_MULT
+ 7:
368 s
->mult
[offset
- EN1_MULT
] = val
;
374 static uint32_t ne2000_ioport_read(void *opaque
, uint32_t addr
)
376 NE2000State
*s
= opaque
;
377 int offset
, page
, ret
;
380 if (addr
== E8390_CMD
) {
384 offset
= addr
| (page
<< 4);
396 ret
= s
->rsar
& 0x00ff;
401 case EN1_PHYS
... EN1_PHYS
+ 5:
402 ret
= s
->phys
[offset
- EN1_PHYS
];
407 case EN1_MULT
... EN1_MULT
+ 7:
408 ret
= s
->mult
[offset
- EN1_MULT
];
426 ret
= 0; /* 10baseT media */
429 ret
= 0x40; /* 10baseT active */
432 ret
= 0x40; /* Full duplex */
440 printf("NE2000: read addr=0x%x val=%02x\n", addr
, ret
);
445 static inline void ne2000_mem_writeb(NE2000State
*s
, uint32_t addr
,
449 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
454 static inline void ne2000_mem_writew(NE2000State
*s
, uint32_t addr
,
457 addr
&= ~1; /* XXX: check exact behaviour if not even */
459 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
460 *(uint16_t *)(s
->mem
+ addr
) = cpu_to_le16(val
);
464 static inline void ne2000_mem_writel(NE2000State
*s
, uint32_t addr
,
467 addr
&= ~1; /* XXX: check exact behaviour if not even */
469 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
470 stl_le_p(s
->mem
+ addr
, val
);
474 static inline uint32_t ne2000_mem_readb(NE2000State
*s
, uint32_t addr
)
477 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
484 static inline uint32_t ne2000_mem_readw(NE2000State
*s
, uint32_t addr
)
486 addr
&= ~1; /* XXX: check exact behaviour if not even */
488 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
489 return le16_to_cpu(*(uint16_t *)(s
->mem
+ addr
));
495 static inline uint32_t ne2000_mem_readl(NE2000State
*s
, uint32_t addr
)
497 addr
&= ~1; /* XXX: check exact behaviour if not even */
499 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
500 return ldl_le_p(s
->mem
+ addr
);
506 static inline void ne2000_dma_update(NE2000State
*s
, int len
)
510 /* XXX: check what to do if rsar > stop */
511 if (s
->rsar
== s
->stop
)
514 if (s
->rcnt
<= len
) {
516 /* signal end of transfer */
518 ne2000_update_irq(s
);
524 static void ne2000_asic_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
526 NE2000State
*s
= opaque
;
529 printf("NE2000: asic write val=0x%04x\n", val
);
533 if (s
->dcfg
& 0x01) {
535 ne2000_mem_writew(s
, s
->rsar
, val
);
536 ne2000_dma_update(s
, 2);
539 ne2000_mem_writeb(s
, s
->rsar
, val
);
540 ne2000_dma_update(s
, 1);
544 static uint32_t ne2000_asic_ioport_read(void *opaque
, uint32_t addr
)
546 NE2000State
*s
= opaque
;
549 if (s
->dcfg
& 0x01) {
551 ret
= ne2000_mem_readw(s
, s
->rsar
);
552 ne2000_dma_update(s
, 2);
555 ret
= ne2000_mem_readb(s
, s
->rsar
);
556 ne2000_dma_update(s
, 1);
559 printf("NE2000: asic read val=0x%04x\n", ret
);
564 static void ne2000_asic_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
566 NE2000State
*s
= opaque
;
569 printf("NE2000: asic writel val=0x%04x\n", val
);
574 ne2000_mem_writel(s
, s
->rsar
, val
);
575 ne2000_dma_update(s
, 4);
578 static uint32_t ne2000_asic_ioport_readl(void *opaque
, uint32_t addr
)
580 NE2000State
*s
= opaque
;
584 ret
= ne2000_mem_readl(s
, s
->rsar
);
585 ne2000_dma_update(s
, 4);
587 printf("NE2000: asic readl val=0x%04x\n", ret
);
592 static void ne2000_reset_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
594 /* nothing to do (end of reset pulse) */
597 static uint32_t ne2000_reset_ioport_read(void *opaque
, uint32_t addr
)
599 NE2000State
*s
= opaque
;
604 static int ne2000_post_load(void* opaque
, int version_id
)
606 NE2000State
* s
= opaque
;
608 if (version_id
< 2) {
614 const VMStateDescription vmstate_ne2000
= {
617 .minimum_version_id
= 0,
618 .post_load
= ne2000_post_load
,
619 .fields
= (VMStateField
[]) {
620 VMSTATE_UINT8_V(rxcr
, NE2000State
, 2),
621 VMSTATE_UINT8(cmd
, NE2000State
),
622 VMSTATE_UINT32(start
, NE2000State
),
623 VMSTATE_UINT32(stop
, NE2000State
),
624 VMSTATE_UINT8(boundary
, NE2000State
),
625 VMSTATE_UINT8(tsr
, NE2000State
),
626 VMSTATE_UINT8(tpsr
, NE2000State
),
627 VMSTATE_UINT16(tcnt
, NE2000State
),
628 VMSTATE_UINT16(rcnt
, NE2000State
),
629 VMSTATE_UINT32(rsar
, NE2000State
),
630 VMSTATE_UINT8(rsr
, NE2000State
),
631 VMSTATE_UINT8(isr
, NE2000State
),
632 VMSTATE_UINT8(dcfg
, NE2000State
),
633 VMSTATE_UINT8(imr
, NE2000State
),
634 VMSTATE_BUFFER(phys
, NE2000State
),
635 VMSTATE_UINT8(curpag
, NE2000State
),
636 VMSTATE_BUFFER(mult
, NE2000State
),
637 VMSTATE_UNUSED(4), /* was irq */
638 VMSTATE_BUFFER(mem
, NE2000State
),
639 VMSTATE_END_OF_LIST()
643 static const VMStateDescription vmstate_pci_ne2000
= {
646 .minimum_version_id
= 3,
647 .fields
= (VMStateField
[]) {
648 VMSTATE_PCI_DEVICE(dev
, PCINE2000State
),
649 VMSTATE_STRUCT(ne2000
, PCINE2000State
, 0, vmstate_ne2000
, NE2000State
),
650 VMSTATE_END_OF_LIST()
654 static uint64_t ne2000_read(void *opaque
, hwaddr addr
,
657 NE2000State
*s
= opaque
;
659 if (addr
< 0x10 && size
== 1) {
660 return ne2000_ioport_read(s
, addr
);
661 } else if (addr
== 0x10) {
663 return ne2000_asic_ioport_read(s
, addr
);
665 return ne2000_asic_ioport_readl(s
, addr
);
667 } else if (addr
== 0x1f && size
== 1) {
668 return ne2000_reset_ioport_read(s
, addr
);
670 return ((uint64_t)1 << (size
* 8)) - 1;
673 static void ne2000_write(void *opaque
, hwaddr addr
,
674 uint64_t data
, unsigned size
)
676 NE2000State
*s
= opaque
;
678 if (addr
< 0x10 && size
== 1) {
679 ne2000_ioport_write(s
, addr
, data
);
680 } else if (addr
== 0x10) {
682 ne2000_asic_ioport_write(s
, addr
, data
);
684 ne2000_asic_ioport_writel(s
, addr
, data
);
686 } else if (addr
== 0x1f && size
== 1) {
687 ne2000_reset_ioport_write(s
, addr
, data
);
691 static const MemoryRegionOps ne2000_ops
= {
693 .write
= ne2000_write
,
694 .endianness
= DEVICE_LITTLE_ENDIAN
,
697 /***********************************************************/
698 /* PCI NE2000 definitions */
700 void ne2000_setup_io(NE2000State
*s
, DeviceState
*dev
, unsigned size
)
702 memory_region_init_io(&s
->io
, OBJECT(dev
), &ne2000_ops
, s
, "ne2000", size
);
705 static NetClientInfo net_ne2000_info
= {
706 .type
= NET_CLIENT_OPTIONS_KIND_NIC
,
707 .size
= sizeof(NICState
),
708 .can_receive
= ne2000_can_receive
,
709 .receive
= ne2000_receive
,
712 static void pci_ne2000_realize(PCIDevice
*pci_dev
, Error
**errp
)
714 PCINE2000State
*d
= DO_UPCAST(PCINE2000State
, dev
, pci_dev
);
718 pci_conf
= d
->dev
.config
;
719 pci_conf
[PCI_INTERRUPT_PIN
] = 1; /* interrupt pin A */
722 ne2000_setup_io(s
, DEVICE(pci_dev
), 0x100);
723 pci_register_bar(&d
->dev
, 0, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io
);
724 s
->irq
= pci_allocate_irq(&d
->dev
);
726 qemu_macaddr_default_if_unset(&s
->c
.macaddr
);
729 s
->nic
= qemu_new_nic(&net_ne2000_info
, &s
->c
,
730 object_get_typename(OBJECT(pci_dev
)), pci_dev
->qdev
.id
, s
);
731 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->c
.macaddr
.a
);
734 static void pci_ne2000_exit(PCIDevice
*pci_dev
)
736 PCINE2000State
*d
= DO_UPCAST(PCINE2000State
, dev
, pci_dev
);
737 NE2000State
*s
= &d
->ne2000
;
739 qemu_del_nic(s
->nic
);
740 qemu_free_irq(s
->irq
);
743 static void ne2000_instance_init(Object
*obj
)
745 PCIDevice
*pci_dev
= PCI_DEVICE(obj
);
746 PCINE2000State
*d
= DO_UPCAST(PCINE2000State
, dev
, pci_dev
);
747 NE2000State
*s
= &d
->ne2000
;
749 device_add_bootindex_property(obj
, &s
->c
.bootindex
,
750 "bootindex", "/ethernet-phy@0",
751 &pci_dev
->qdev
, NULL
);
754 static Property ne2000_properties
[] = {
755 DEFINE_NIC_PROPERTIES(PCINE2000State
, ne2000
.c
),
756 DEFINE_PROP_END_OF_LIST(),
759 static void ne2000_class_init(ObjectClass
*klass
, void *data
)
761 DeviceClass
*dc
= DEVICE_CLASS(klass
);
762 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
764 k
->realize
= pci_ne2000_realize
;
765 k
->exit
= pci_ne2000_exit
;
766 k
->romfile
= "efi-ne2k_pci.rom",
767 k
->vendor_id
= PCI_VENDOR_ID_REALTEK
;
768 k
->device_id
= PCI_DEVICE_ID_REALTEK_8029
;
769 k
->class_id
= PCI_CLASS_NETWORK_ETHERNET
;
770 dc
->vmsd
= &vmstate_pci_ne2000
;
771 dc
->props
= ne2000_properties
;
772 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
775 static const TypeInfo ne2000_info
= {
777 .parent
= TYPE_PCI_DEVICE
,
778 .instance_size
= sizeof(PCINE2000State
),
779 .class_init
= ne2000_class_init
,
780 .instance_init
= ne2000_instance_init
,
783 static void ne2000_register_types(void)
785 type_register_static(&ne2000_info
);
788 type_init(ne2000_register_types
)