hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7 #include "memory.h"
   8 #include "dma.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "isa.h"
  12
  13 #include "pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  79
  80 #define FMT_PCIBUS                      PRIx64
  81
  82 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  83                                 uint32_t address, uint32_t data, int len);
  84 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  85                                    uint32_t address, int len);
  86 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  87                                 pcibus_t addr, pcibus_t size, int type);
  88 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  89
  90 typedef struct PCIIORegion {
  91     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  92 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  93     pcibus_t size;
  94     uint8_t type;
  95     MemoryRegion *memory;
  96     MemoryRegion *address_space;
  97 } PCIIORegion;
  98
  99 #define PCI_ROM_SLOT 6
 100 #define PCI_NUM_REGIONS 7
 101
 102 #include "pci_regs.h"
 103
 104 /* PCI HEADER_TYPE */
 105 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 106
 107 /* Size of the standard PCI config header */
 108 #define PCI_CONFIG_HEADER_SIZE 0x40
 109 /* Size of the standard PCI config space */
 110 #define PCI_CONFIG_SPACE_SIZE 0x100
 111 /* Size of the standart PCIe config space: 4KB */
 112 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 113
 114 #define PCI_NUM_PINS 4 /* A-D */
 115
 116 /* Bits in cap_present field. */
 117 enum {
 118     QEMU_PCI_CAP_MSI = 0x1,
 119     QEMU_PCI_CAP_MSIX = 0x2,
 120     QEMU_PCI_CAP_EXPRESS = 0x4,
 121
 122     /* multifunction capable device */
 123 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 124     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 125
 126     /* command register SERR bit enabled */
 127 #define QEMU_PCI_CAP_SERR_BITNR 4
 128     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 129     /* Standard hot plug controller. */
 130 #define QEMU_PCI_SHPC_BITNR 5
 131     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 132 #define QEMU_PCI_SLOTID_BITNR 6
 133     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 134 };
 135
 136 #define TYPE_PCI_DEVICE "pci-device"
 137 #define PCI_DEVICE(obj) \
 138      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 139 #define PCI_DEVICE_CLASS(klass) \
 140      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 141 #define PCI_DEVICE_GET_CLASS(obj) \
 142      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 143
 144 typedef struct PCIDeviceClass {
 145     DeviceClass parent_class;
 146
 147     int (*init)(PCIDevice *dev);
 148     PCIUnregisterFunc *exit;
 149     PCIConfigReadFunc *config_read;
 150     PCIConfigWriteFunc *config_write;
 151
 152     uint16_t vendor_id;
 153     uint16_t device_id;
 154     uint8_t revision;
 155     uint16_t class_id;
 156     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 157     uint16_t subsystem_id;              /* only for header type = 0 */
 158
 159     /*
 160      * pci-to-pci bridge or normal device.
 161      * This doesn't mean pci host switch.
 162      * When card bus bridge is supported, this would be enhanced.
 163      */
 164     int is_bridge;
 165
 166     /* pcie stuff */
 167     int is_express;   /* is this device pci express? */
 168
 169     /* device isn't hot-pluggable */
 170     int no_hotplug;
 171
 172     /* rom bar */
 173     const char *romfile;
 174 } PCIDeviceClass;
 175
 176 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 177                                       MSIMessage msg);
 178 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 179
 180 struct PCIDevice {
 181     DeviceState qdev;
 182
 183     /* PCI config space */
 184     uint8_t *config;
 185
 186     /* Used to enable config checks on load. Note that writable bits are
 187      * never checked even if set in cmask. */
 188     uint8_t *cmask;
 189
 190     /* Used to implement R/W bytes */
 191     uint8_t *wmask;
 192
 193     /* Used to implement RW1C(Write 1 to Clear) bytes */
 194     uint8_t *w1cmask;
 195
 196     /* Used to allocate config space for capabilities. */
 197     uint8_t *used;
 198
 199     /* the following fields are read only */
 200     PCIBus *bus;
 201     int32_t devfn;
 202     char name[64];
 203     PCIIORegion io_regions[PCI_NUM_REGIONS];
 204     DMAContext *dma;
 205
 206     /* do not access the following fields */
 207     PCIConfigReadFunc *config_read;
 208     PCIConfigWriteFunc *config_write;
 209
 210     /* IRQ objects for the INTA-INTD pins.  */
 211     qemu_irq *irq;
 212
 213     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 214     uint8_t irq_state;
 215
 216     /* Capability bits */
 217     uint32_t cap_present;
 218
 219     /* Offset of MSI-X capability in config space */
 220     uint8_t msix_cap;
 221
 222     /* MSI-X entries */
 223     int msix_entries_nr;
 224
 225     /* Space to store MSIX table */
 226     uint8_t *msix_table_page;
 227     /* MMIO index used to map MSIX table and pending bit entries. */
 228     MemoryRegion msix_mmio;
 229     /* Reference-count for entries actually in use by driver. */
 230     unsigned *msix_entry_used;
 231     /* Region including the MSI-X table */
 232     uint32_t msix_bar_size;
 233     /* MSIX function mask set or MSIX disabled */
 234     bool msix_function_masked;
 235     /* Version id needed for VMState */
 236     int32_t version_id;
 237
 238     /* Offset of MSI capability in config space */
 239     uint8_t msi_cap;
 240
 241     /* PCI Express */
 242     PCIExpressDevice exp;
 243
 244     /* SHPC */
 245     SHPCDevice *shpc;
 246
 247     /* Location of option rom */
 248     char *romfile;
 249     bool has_rom;
 250     MemoryRegion rom;
 251     uint32_t rom_bar;
 252
 253     /* MSI-X notifiers */
 254     MSIVectorUseNotifier msix_vector_use_notifier;
 255     MSIVectorReleaseNotifier msix_vector_release_notifier;
 256 };
 257
 258 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 259                       uint8_t attr, MemoryRegion *memory);
 260 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 261
 262 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 263                        uint8_t offset, uint8_t size);
 264
 265 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 266
 267 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 268
 269
 270 uint32_t pci_default_read_config(PCIDevice *d,
 271                                  uint32_t address, int len);
 272 void pci_default_write_config(PCIDevice *d,
 273                               uint32_t address, uint32_t val, int len);
 274 void pci_device_save(PCIDevice *s, QEMUFile *f);
 275 int pci_device_load(PCIDevice *s, QEMUFile *f);
 276 MemoryRegion *pci_address_space(PCIDevice *dev);
 277 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 278
 279 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 280 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 281
 282 typedef enum {
 283     PCI_HOTPLUG_DISABLED,
 284     PCI_HOTPLUG_ENABLED,
 285     PCI_COLDPLUG_ENABLED,
 286 } PCIHotplugState;
 287
 288 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 289                               PCIHotplugState state);
 290 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 291                          const char *name,
 292                          MemoryRegion *address_space_mem,
 293                          MemoryRegion *address_space_io,
 294                          uint8_t devfn_min);
 295 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 296                     MemoryRegion *address_space_mem,
 297                     MemoryRegion *address_space_io,
 298                     uint8_t devfn_min);
 299 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 300                   void *irq_opaque, int nirq);
 301 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 302 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 303 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 304                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 305                          void *irq_opaque,
 306                          MemoryRegion *address_space_mem,
 307                          MemoryRegion *address_space_io,
 308                          uint8_t devfn_min, int nirq);
 309 void pci_device_reset(PCIDevice *dev);
 310 void pci_bus_reset(PCIBus *bus);
 311
 312 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 313                         const char *default_devaddr);
 314 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 315                                const char *default_devaddr);
 316 int pci_bus_num(PCIBus *s);
 317 void pci_for_each_device(PCIBus *bus, int bus_num,
 318                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 319                          void *opaque);
 320 PCIBus *pci_find_root_bus(int domain);
 321 int pci_find_domain(const PCIBus *bus);
 322 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 323 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 324 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 325
 326 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 327                      unsigned *slotp);
 328
 329 void pci_device_deassert_intx(PCIDevice *dev);
 330
 331 typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int);
 332
 333 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque);
 334
 335 static inline void
 336 pci_set_byte(uint8_t *config, uint8_t val)
 337 {
 338     *config = val;
 339 }
 340
 341 static inline uint8_t
 342 pci_get_byte(const uint8_t *config)
 343 {
 344     return *config;
 345 }
 346
 347 static inline void
 348 pci_set_word(uint8_t *config, uint16_t val)
 349 {
 350     cpu_to_le16wu((uint16_t *)config, val);
 351 }
 352
 353 static inline uint16_t
 354 pci_get_word(const uint8_t *config)
 355 {
 356     return le16_to_cpupu((const uint16_t *)config);
 357 }
 358
 359 static inline void
 360 pci_set_long(uint8_t *config, uint32_t val)
 361 {
 362     cpu_to_le32wu((uint32_t *)config, val);
 363 }
 364
 365 static inline uint32_t
 366 pci_get_long(const uint8_t *config)
 367 {
 368     return le32_to_cpupu((const uint32_t *)config);
 369 }
 370
 371 static inline void
 372 pci_set_quad(uint8_t *config, uint64_t val)
 373 {
 374     cpu_to_le64w((uint64_t *)config, val);
 375 }
 376
 377 static inline uint64_t
 378 pci_get_quad(const uint8_t *config)
 379 {
 380     return le64_to_cpup((const uint64_t *)config);
 381 }
 382
 383 static inline void
 384 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 385 {
 386     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 387 }
 388
 389 static inline void
 390 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 391 {
 392     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 393 }
 394
 395 static inline void
 396 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 397 {
 398     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 399 }
 400
 401 static inline void
 402 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 403 {
 404     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 405 }
 406
 407 static inline void
 408 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 409 {
 410     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 411 }
 412
 413 static inline void
 414 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 415 {
 416     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 417 }
 418
 419 /*
 420  * helper functions to do bit mask operation on configuration space.
 421  * Just to set bit, use test-and-set and discard returned value.
 422  * Just to clear bit, use test-and-clear and discard returned value.
 423  * NOTE: They aren't atomic.
 424  */
 425 static inline uint8_t
 426 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 427 {
 428     uint8_t val = pci_get_byte(config);
 429     pci_set_byte(config, val & ~mask);
 430     return val & mask;
 431 }
 432
 433 static inline uint8_t
 434 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 435 {
 436     uint8_t val = pci_get_byte(config);
 437     pci_set_byte(config, val | mask);
 438     return val & mask;
 439 }
 440
 441 static inline uint16_t
 442 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 443 {
 444     uint16_t val = pci_get_word(config);
 445     pci_set_word(config, val & ~mask);
 446     return val & mask;
 447 }
 448
 449 static inline uint16_t
 450 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 451 {
 452     uint16_t val = pci_get_word(config);
 453     pci_set_word(config, val | mask);
 454     return val & mask;
 455 }
 456
 457 static inline uint32_t
 458 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 459 {
 460     uint32_t val = pci_get_long(config);
 461     pci_set_long(config, val & ~mask);
 462     return val & mask;
 463 }
 464
 465 static inline uint32_t
 466 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 467 {
 468     uint32_t val = pci_get_long(config);
 469     pci_set_long(config, val | mask);
 470     return val & mask;
 471 }
 472
 473 static inline uint64_t
 474 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 475 {
 476     uint64_t val = pci_get_quad(config);
 477     pci_set_quad(config, val & ~mask);
 478     return val & mask;
 479 }
 480
 481 static inline uint64_t
 482 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 483 {
 484     uint64_t val = pci_get_quad(config);
 485     pci_set_quad(config, val | mask);
 486     return val & mask;
 487 }
 488
 489 /* Access a register specified by a mask */
 490 static inline void
 491 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 492 {
 493     uint8_t val = pci_get_byte(config);
 494     uint8_t rval = reg << (ffs(mask) - 1);
 495     pci_set_byte(config, (~mask & val) | (mask & rval));
 496 }
 497
 498 static inline uint8_t
 499 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 500 {
 501     uint8_t val = pci_get_byte(config);
 502     return (val & mask) >> (ffs(mask) - 1);
 503 }
 504
 505 static inline void
 506 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 507 {
 508     uint16_t val = pci_get_word(config);
 509     uint16_t rval = reg << (ffs(mask) - 1);
 510     pci_set_word(config, (~mask & val) | (mask & rval));
 511 }
 512
 513 static inline uint16_t
 514 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 515 {
 516     uint16_t val = pci_get_word(config);
 517     return (val & mask) >> (ffs(mask) - 1);
 518 }
 519
 520 static inline void
 521 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 522 {
 523     uint32_t val = pci_get_long(config);
 524     uint32_t rval = reg << (ffs(mask) - 1);
 525     pci_set_long(config, (~mask & val) | (mask & rval));
 526 }
 527
 528 static inline uint32_t
 529 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 530 {
 531     uint32_t val = pci_get_long(config);
 532     return (val & mask) >> (ffs(mask) - 1);
 533 }
 534
 535 static inline void
 536 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 537 {
 538     uint64_t val = pci_get_quad(config);
 539     uint64_t rval = reg << (ffs(mask) - 1);
 540     pci_set_quad(config, (~mask & val) | (mask & rval));
 541 }
 542
 543 static inline uint64_t
 544 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 545 {
 546     uint64_t val = pci_get_quad(config);
 547     return (val & mask) >> (ffs(mask) - 1);
 548 }
 549
 550 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 551                                     const char *name);
 552 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 553                                            bool multifunction,
 554                                            const char *name);
 555 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 556 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 557
 558 static inline int pci_is_express(const PCIDevice *d)
 559 {
 560     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 561 }
 562
 563 static inline uint32_t pci_config_size(const PCIDevice *d)
 564 {
 565     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 566 }
 567
 568 /* DMA access functions */
 569 static inline DMAContext *pci_dma_context(PCIDevice *dev)
 570 {
 571     return dev->dma;
 572 }
 573
 574 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 575                              void *buf, dma_addr_t len, DMADirection dir)
 576 {
 577     dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir);
 578     return 0;
 579 }
 580
 581 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 582                                void *buf, dma_addr_t len)
 583 {
 584     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 585 }
 586
 587 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 588                                 const void *buf, dma_addr_t len)
 589 {
 590     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 591 }
 592
 593 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 594     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 595                                                    dma_addr_t addr)     \
 596     {                                                                   \
 597         return ld##_l##_dma(pci_dma_context(dev), addr);                \
 598     }                                                                   \
 599     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 600                                         dma_addr_t addr, uint##_bits##_t val) \
 601     {                                                                   \
 602         st##_s##_dma(pci_dma_context(dev), addr, val);                  \
 603     }
 604
 605 PCI_DMA_DEFINE_LDST(ub, b, 8);
 606 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 607 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 608 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 609 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 610 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 611 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 612
 613 #undef PCI_DMA_DEFINE_LDST
 614
 615 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 616                                 dma_addr_t *plen, DMADirection dir)
 617 {
 618     void *buf;
 619
 620     buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir);
 621     return buf;
 622 }
 623
 624 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 625                                  DMADirection dir, dma_addr_t access_len)
 626 {
 627     dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len);
 628 }
 629
 630 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 631                                        int alloc_hint)
 632 {
 633     qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev));
 634 }
 635
 636 extern const VMStateDescription vmstate_pci_device;
 637
 638 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 639     .name       = (stringify(_field)),                               \
 640     .size       = sizeof(PCIDevice),                                 \
 641     .vmsd       = &vmstate_pci_device,                               \
 642     .flags      = VMS_STRUCT,                                        \
 643     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 644 }
 645
 646 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 647     .name       = (stringify(_field)),                               \
 648     .size       = sizeof(PCIDevice),                                 \
 649     .vmsd       = &vmstate_pci_device,                               \
 650     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 651     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 652 }
 653
 654 #endif