target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #include "config.h"
  23
  24 #include "kvm-consts.h"
  25
  26 #if defined(TARGET_AARCH64)
  27   /* AArch64 definitions */
  28 #  define TARGET_LONG_BITS 64
  29 #  define ELF_MACHINE EM_AARCH64
  30 #else
  31 #  define TARGET_LONG_BITS 32
  32 #  define ELF_MACHINE EM_ARM
  33 #endif
  34
  35 #define CPUArchState struct CPUARMState
  36
  37 #include "qemu-common.h"
  38 #include "exec/cpu-defs.h"
  39
  40 #include "fpu/softfloat.h"
  41
  42 #define TARGET_HAS_ICE 1
  43
  44 #define EXCP_UDEF            1   /* undefined instruction */
  45 #define EXCP_SWI             2   /* software interrupt */
  46 #define EXCP_PREFETCH_ABORT  3
  47 #define EXCP_DATA_ABORT      4
  48 #define EXCP_IRQ             5
  49 #define EXCP_FIQ             6
  50 #define EXCP_BKPT            7
  51 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  52 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  53 #define EXCP_STREX          10
  54
  55 #define ARMV7M_EXCP_RESET   1
  56 #define ARMV7M_EXCP_NMI     2
  57 #define ARMV7M_EXCP_HARD    3
  58 #define ARMV7M_EXCP_MEM     4
  59 #define ARMV7M_EXCP_BUS     5
  60 #define ARMV7M_EXCP_USAGE   6
  61 #define ARMV7M_EXCP_SVC     11
  62 #define ARMV7M_EXCP_DEBUG   12
  63 #define ARMV7M_EXCP_PENDSV  14
  64 #define ARMV7M_EXCP_SYSTICK 15
  65
  66 /* ARM-specific interrupt pending bits.  */
  67 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  68
  69 /* Meanings of the ARMCPU object's two inbound GPIO lines */
  70 #define ARM_CPU_IRQ 0
  71 #define ARM_CPU_FIQ 1
  72
  73 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  74                             int srcreg, int operand, uint32_t value);
  75 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  76                                int dstreg, int operand);
  77
  78 struct arm_boot_info;
  79
  80 #define NB_MMU_MODES 2
  81
  82 /* We currently assume float and double are IEEE single and double
  83    precision respectively.
  84    Doing runtime conversions is tricky because VFP registers may contain
  85    integer values (eg. as the result of a FTOSI instruction).
  86    s<2n> maps to the least significant half of d<n>
  87    s<2n+1> maps to the most significant half of d<n>
  88  */
  89
  90 /* CPU state for each instance of a generic timer (in cp15 c14) */
  91 typedef struct ARMGenericTimer {
  92     uint64_t cval; /* Timer CompareValue register */
  93     uint32_t ctl; /* Timer Control register */
  94 } ARMGenericTimer;
  95
  96 #define GTIMER_PHYS 0
  97 #define GTIMER_VIRT 1
  98 #define NUM_GTIMERS 2
  99
 100 /* Scale factor for generic timers, ie number of ns per tick.
 101  * This gives a 62.5MHz timer.
 102  */
 103 #define GTIMER_SCALE 16
 104
 105 typedef struct CPUARMState {
 106     /* Regs for current mode.  */
 107     uint32_t regs[16];
 108
 109     /* 32/64 switch only happens when taking and returning from
 110      * exceptions so the overlap semantics are taken care of then
 111      * instead of having a complicated union.
 112      */
 113     /* Regs for A64 mode.  */
 114     uint64_t xregs[32];
 115     uint64_t pc;
 116     /* TODO: pstate doesn't correspond to an architectural register;
 117      * it would be better modelled as the underlying fields.
 118      */
 119     uint32_t pstate;
 120     uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
 121
 122     /* Frequently accessed CPSR bits are stored separately for efficiency.
 123        This contains all the other bits.  Use cpsr_{read,write} to access
 124        the whole CPSR.  */
 125     uint32_t uncached_cpsr;
 126     uint32_t spsr;
 127
 128     /* Banked registers.  */
 129     uint32_t banked_spsr[6];
 130     uint32_t banked_r13[6];
 131     uint32_t banked_r14[6];
 132
 133     /* These hold r8-r12.  */
 134     uint32_t usr_regs[5];
 135     uint32_t fiq_regs[5];
 136
 137     /* cpsr flag cache for faster execution */
 138     uint32_t CF; /* 0 or 1 */
 139     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 140     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 141     uint32_t ZF; /* Z set if zero.  */
 142     uint32_t QF; /* 0 or 1 */
 143     uint32_t GE; /* cpsr[19:16] */
 144     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 145     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 146
 147     /* System control coprocessor (cp15) */
 148     struct {
 149         uint32_t c0_cpuid;
 150         uint32_t c0_cssel; /* Cache size selection.  */
 151         uint32_t c1_sys; /* System control register.  */
 152         uint32_t c1_coproc; /* Coprocessor access register.  */
 153         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 154         uint32_t c1_scr; /* secure config register.  */
 155         uint32_t c2_base0; /* MMU translation table base 0.  */
 156         uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
 157         uint32_t c2_base1; /* MMU translation table base 0.  */
 158         uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */
 159         uint32_t c2_control; /* MMU translation table base control.  */
 160         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 161         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 162         uint32_t c2_data; /* MPU data cachable bits.  */
 163         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 164         uint32_t c3; /* MMU domain access control register
 165                         MPU write buffer control.  */
 166         uint32_t c5_insn; /* Fault status registers.  */
 167         uint32_t c5_data;
 168         uint32_t c6_region[8]; /* MPU base/size registers.  */
 169         uint32_t c6_insn; /* Fault address registers.  */
 170         uint32_t c6_data;
 171         uint32_t c7_par;  /* Translation result. */
 172         uint32_t c7_par_hi;  /* Translation result, high 32 bits */
 173         uint32_t c9_insn; /* Cache lockdown registers.  */
 174         uint32_t c9_data;
 175         uint32_t c9_pmcr; /* performance monitor control register */
 176         uint32_t c9_pmcnten; /* perf monitor counter enables */
 177         uint32_t c9_pmovsr; /* perf monitor overflow status */
 178         uint32_t c9_pmxevtyper; /* perf monitor event type */
 179         uint32_t c9_pmuserenr; /* perf monitor user enable */
 180         uint32_t c9_pminten; /* perf monitor interrupt enables */
 181         uint32_t c12_vbar; /* vector base address register */
 182         uint32_t c13_fcse; /* FCSE PID.  */
 183         uint32_t c13_context; /* Context ID.  */
 184         uint32_t c13_tls1; /* User RW Thread register.  */
 185         uint32_t c13_tls2; /* User RO Thread register.  */
 186         uint32_t c13_tls3; /* Privileged Thread register.  */
 187         uint32_t c14_cntfrq; /* Counter Frequency register */
 188         uint32_t c14_cntkctl; /* Timer Control register */
 189         ARMGenericTimer c14_timer[NUM_GTIMERS];
 190         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 191         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 192         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 193         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 194         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 195         uint32_t c15_config_base_address; /* SCU base address.  */
 196         uint32_t c15_diagnostic; /* diagnostic register */
 197         uint32_t c15_power_diagnostic;
 198         uint32_t c15_power_control; /* power control */
 199     } cp15;
 200
 201     /* System registers (AArch64) */
 202     struct {
 203         uint64_t tpidr_el0;
 204     } sr;
 205
 206     struct {
 207         uint32_t other_sp;
 208         uint32_t vecbase;
 209         uint32_t basepri;
 210         uint32_t control;
 211         int current_sp;
 212         int exception;
 213         int pending_exception;
 214     } v7m;
 215
 216     /* Thumb-2 EE state.  */
 217     uint32_t teecr;
 218     uint32_t teehbr;
 219
 220     /* VFP coprocessor state.  */
 221     struct {
 222         /* VFP/Neon register state. Note that the mapping between S, D and Q
 223          * views of the register bank differs between AArch64 and AArch32:
 224          * In AArch32:
 225          *  Qn = regs[2n+1]:regs[2n]
 226          *  Dn = regs[n]
 227          *  Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
 228          * (and regs[32] to regs[63] are inaccessible)
 229          * In AArch64:
 230          *  Qn = regs[2n+1]:regs[2n]
 231          *  Dn = regs[2n]
 232          *  Sn = regs[2n] bits 31..0
 233          * This corresponds to the architecturally defined mapping between
 234          * the two execution states, and means we do not need to explicitly
 235          * map these registers when changing states.
 236          */
 237         float64 regs[64];
 238
 239         uint32_t xregs[16];
 240         /* We store these fpcsr fields separately for convenience.  */
 241         int vec_len;
 242         int vec_stride;
 243
 244         /* scratch space when Tn are not sufficient.  */
 245         uint32_t scratch[8];
 246
 247         /* fp_status is the "normal" fp status. standard_fp_status retains
 248          * values corresponding to the ARM "Standard FPSCR Value", ie
 249          * default-NaN, flush-to-zero, round-to-nearest and is used by
 250          * any operations (generally Neon) which the architecture defines
 251          * as controlled by the standard FPSCR value rather than the FPSCR.
 252          *
 253          * To avoid having to transfer exception bits around, we simply
 254          * say that the FPSCR cumulative exception flags are the logical
 255          * OR of the flags in the two fp statuses. This relies on the
 256          * only thing which needs to read the exception flags being
 257          * an explicit FPSCR read.
 258          */
 259         float_status fp_status;
 260         float_status standard_fp_status;
 261     } vfp;
 262     uint32_t exclusive_addr;
 263     uint32_t exclusive_val;
 264     uint32_t exclusive_high;
 265 #if defined(CONFIG_USER_ONLY)
 266     uint32_t exclusive_test;
 267     uint32_t exclusive_info;
 268 #endif
 269
 270     /* iwMMXt coprocessor state.  */
 271     struct {
 272         uint64_t regs[16];
 273         uint64_t val;
 274
 275         uint32_t cregs[16];
 276     } iwmmxt;
 277
 278     /* For mixed endian mode.  */
 279     bool bswap_code;
 280
 281 #if defined(CONFIG_USER_ONLY)
 282     /* For usermode syscall translation.  */
 283     int eabi;
 284 #endif
 285
 286     CPU_COMMON
 287
 288     /* These fields after the common ones so they are preserved on reset.  */
 289
 290     /* Internal CPU feature flags.  */
 291     uint64_t features;
 292
 293     void *nvic;
 294     const struct arm_boot_info *boot_info;
 295 } CPUARMState;
 296
 297 #include "cpu-qom.h"
 298
 299 ARMCPU *cpu_arm_init(const char *cpu_model);
 300 void arm_translate_init(void);
 301 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 302 int cpu_arm_exec(CPUARMState *s);
 303 int bank_number(int mode);
 304 void switch_mode(CPUARMState *, int);
 305 uint32_t do_arm_semihosting(CPUARMState *env);
 306
 307 static inline bool is_a64(CPUARMState *env)
 308 {
 309     return env->aarch64;
 310 }
 311
 312 #define PSTATE_N_SHIFT 3
 313 #define PSTATE_N  (1 << PSTATE_N_SHIFT)
 314 #define PSTATE_Z_SHIFT 2
 315 #define PSTATE_Z  (1 << PSTATE_Z_SHIFT)
 316 #define PSTATE_C_SHIFT 1
 317 #define PSTATE_C  (1 << PSTATE_C_SHIFT)
 318 #define PSTATE_V_SHIFT 0
 319 #define PSTATE_V  (1 << PSTATE_V_SHIFT)
 320
 321 /* you can call this signal handler from your SIGBUS and SIGSEGV
 322    signal handlers to inform the virtual CPU of exceptions. non zero
 323    is returned if the signal was handled by the virtual CPU.  */
 324 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 325                            void *puc);
 326 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 327                               int mmu_idx);
 328 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 329
 330 #define CPSR_M (0x1fU)
 331 #define CPSR_T (1U << 5)
 332 #define CPSR_F (1U << 6)
 333 #define CPSR_I (1U << 7)
 334 #define CPSR_A (1U << 8)
 335 #define CPSR_E (1U << 9)
 336 #define CPSR_IT_2_7 (0xfc00U)
 337 #define CPSR_GE (0xfU << 16)
 338 #define CPSR_RESERVED (0xfU << 20)
 339 #define CPSR_J (1U << 24)
 340 #define CPSR_IT_0_1 (3U << 25)
 341 #define CPSR_Q (1U << 27)
 342 #define CPSR_V (1U << 28)
 343 #define CPSR_C (1U << 29)
 344 #define CPSR_Z (1U << 30)
 345 #define CPSR_N (1U << 31)
 346 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 347
 348 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 349 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 350 /* Bits writable in user mode.  */
 351 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 352 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 353 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 354
 355 /* Return the current CPSR value.  */
 356 uint32_t cpsr_read(CPUARMState *env);
 357 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 358 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 359
 360 /* Return the current xPSR value.  */
 361 static inline uint32_t xpsr_read(CPUARMState *env)
 362 {
 363     int ZF;
 364     ZF = (env->ZF == 0);
 365     return (env->NF & 0x80000000) | (ZF << 30)
 366         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 367         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 368         | ((env->condexec_bits & 0xfc) << 8)
 369         | env->v7m.exception;
 370 }
 371
 372 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 373 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 374 {
 375     if (mask & CPSR_NZCV) {
 376         env->ZF = (~val) & CPSR_Z;
 377         env->NF = val;
 378         env->CF = (val >> 29) & 1;
 379         env->VF = (val << 3) & 0x80000000;
 380     }
 381     if (mask & CPSR_Q)
 382         env->QF = ((val & CPSR_Q) != 0);
 383     if (mask & (1 << 24))
 384         env->thumb = ((val & (1 << 24)) != 0);
 385     if (mask & CPSR_IT_0_1) {
 386         env->condexec_bits &= ~3;
 387         env->condexec_bits |= (val >> 25) & 3;
 388     }
 389     if (mask & CPSR_IT_2_7) {
 390         env->condexec_bits &= 3;
 391         env->condexec_bits |= (val >> 8) & 0xfc;
 392     }
 393     if (mask & 0x1ff) {
 394         env->v7m.exception = val & 0x1ff;
 395     }
 396 }
 397
 398 /* Return the current FPSCR value.  */
 399 uint32_t vfp_get_fpscr(CPUARMState *env);
 400 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 401
 402 enum arm_cpu_mode {
 403   ARM_CPU_MODE_USR = 0x10,
 404   ARM_CPU_MODE_FIQ = 0x11,
 405   ARM_CPU_MODE_IRQ = 0x12,
 406   ARM_CPU_MODE_SVC = 0x13,
 407   ARM_CPU_MODE_ABT = 0x17,
 408   ARM_CPU_MODE_UND = 0x1b,
 409   ARM_CPU_MODE_SYS = 0x1f
 410 };
 411
 412 /* VFP system registers.  */
 413 #define ARM_VFP_FPSID   0
 414 #define ARM_VFP_FPSCR   1
 415 #define ARM_VFP_MVFR1   6
 416 #define ARM_VFP_MVFR0   7
 417 #define ARM_VFP_FPEXC   8
 418 #define ARM_VFP_FPINST  9
 419 #define ARM_VFP_FPINST2 10
 420
 421 /* iwMMXt coprocessor control registers.  */
 422 #define ARM_IWMMXT_wCID         0
 423 #define ARM_IWMMXT_wCon         1
 424 #define ARM_IWMMXT_wCSSF        2
 425 #define ARM_IWMMXT_wCASF        3
 426 #define ARM_IWMMXT_wCGR0        8
 427 #define ARM_IWMMXT_wCGR1        9
 428 #define ARM_IWMMXT_wCGR2        10
 429 #define ARM_IWMMXT_wCGR3        11
 430
 431 /* If adding a feature bit which corresponds to a Linux ELF
 432  * HWCAP bit, remember to update the feature-bit-to-hwcap
 433  * mapping in linux-user/elfload.c:get_elf_hwcap().
 434  */
 435 enum arm_features {
 436     ARM_FEATURE_VFP,
 437     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 438     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 439     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 440     ARM_FEATURE_V6,
 441     ARM_FEATURE_V6K,
 442     ARM_FEATURE_V7,
 443     ARM_FEATURE_THUMB2,
 444     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 445     ARM_FEATURE_VFP3,
 446     ARM_FEATURE_VFP_FP16,
 447     ARM_FEATURE_NEON,
 448     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 449     ARM_FEATURE_M, /* Microcontroller profile.  */
 450     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 451     ARM_FEATURE_THUMB2EE,
 452     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 453     ARM_FEATURE_V4T,
 454     ARM_FEATURE_V5,
 455     ARM_FEATURE_STRONGARM,
 456     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 457     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 458     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 459     ARM_FEATURE_GENERIC_TIMER,
 460     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 461     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
 462     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
 463     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
 464     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
 465     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
 466     ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
 467     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
 468     ARM_FEATURE_V8,
 469     ARM_FEATURE_AARCH64, /* supports 64 bit mode */
 470     ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
 471     ARM_FEATURE_CBAR, /* has cp15 CBAR */
 472 };
 473
 474 static inline int arm_feature(CPUARMState *env, int feature)
 475 {
 476     return (env->features & (1ULL << feature)) != 0;
 477 }
 478
 479 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 480
 481 /* Interface between CPU and Interrupt controller.  */
 482 void armv7m_nvic_set_pending(void *opaque, int irq);
 483 int armv7m_nvic_acknowledge_irq(void *opaque);
 484 void armv7m_nvic_complete_irq(void *opaque, int irq);
 485
 486 /* Interface for defining coprocessor registers.
 487  * Registers are defined in tables of arm_cp_reginfo structs
 488  * which are passed to define_arm_cp_regs().
 489  */
 490
 491 /* When looking up a coprocessor register we look for it
 492  * via an integer which encodes all of:
 493  *  coprocessor number
 494  *  Crn, Crm, opc1, opc2 fields
 495  *  32 or 64 bit register (ie is it accessed via MRC/MCR
 496  *    or via MRRC/MCRR?)
 497  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 498  * (In this case crn and opc2 should be zero.)
 499  */
 500 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2)   \
 501     (((cp) << 16) | ((is64) << 15) | ((crn) << 11) |    \
 502      ((crm) << 7) | ((opc1) << 3) | (opc2))
 503
 504 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
 505  * version used as a key for the coprocessor register hashtable
 506  */
 507 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 508 {
 509     uint32_t cpregid = kvmid;
 510     if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 511         cpregid |= (1 << 15);
 512     }
 513     return cpregid;
 514 }
 515
 516 /* Convert a truncated 32 bit hashtable key into the full
 517  * 64 bit KVM register ID.
 518  */
 519 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 520 {
 521     uint64_t kvmid = cpregid & ~(1 << 15);
 522     if (cpregid & (1 << 15)) {
 523         kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 524     } else {
 525         kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 526     }
 527     return kvmid;
 528 }
 529
 530 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
 531  * special-behaviour cp reg and bits [15..8] indicate what behaviour
 532  * it has. Otherwise it is a simple cp reg, where CONST indicates that
 533  * TCG can assume the value to be constant (ie load at translate time)
 534  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 535  * indicates that the TB should not be ended after a write to this register
 536  * (the default is that the TB ends after cp writes). OVERRIDE permits
 537  * a register definition to override a previous definition for the
 538  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 539  * old must have the OVERRIDE bit set.
 540  * NO_MIGRATE indicates that this register should be ignored for migration;
 541  * (eg because any state is accessed via some other coprocessor register).
 542  * IO indicates that this register does I/O and therefore its accesses
 543  * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
 544  * registers which implement clocks or timers require this.
 545  */
 546 #define ARM_CP_SPECIAL 1
 547 #define ARM_CP_CONST 2
 548 #define ARM_CP_64BIT 4
 549 #define ARM_CP_SUPPRESS_TB_END 8
 550 #define ARM_CP_OVERRIDE 16
 551 #define ARM_CP_NO_MIGRATE 32
 552 #define ARM_CP_IO 64
 553 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
 554 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
 555 #define ARM_LAST_SPECIAL ARM_CP_WFI
 556 /* Used only as a terminator for ARMCPRegInfo lists */
 557 #define ARM_CP_SENTINEL 0xffff
 558 /* Mask of only the flag bits in a type field */
 559 #define ARM_CP_FLAG_MASK 0x7f
 560
 561 /* Return true if cptype is a valid type field. This is used to try to
 562  * catch errors where the sentinel has been accidentally left off the end
 563  * of a list of registers.
 564  */
 565 static inline bool cptype_valid(int cptype)
 566 {
 567     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 568         || ((cptype & ARM_CP_SPECIAL) &&
 569             ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
 570 }
 571
 572 /* Access rights:
 573  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 574  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 575  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 576  * (ie any of the privileged modes in Secure state, or Monitor mode).
 577  * If a register is accessible in one privilege level it's always accessible
 578  * in higher privilege levels too. Since "Secure PL1" also follows this rule
 579  * (ie anything visible in PL2 is visible in S-PL1, some things are only
 580  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 581  * terminology a little and call this PL3.
 582  *
 583  * If access permissions for a register are more complex than can be
 584  * described with these bits, then use a laxer set of restrictions, and
 585  * do the more restrictive/complex check inside a helper function.
 586  */
 587 #define PL3_R 0x80
 588 #define PL3_W 0x40
 589 #define PL2_R (0x20 | PL3_R)
 590 #define PL2_W (0x10 | PL3_W)
 591 #define PL1_R (0x08 | PL2_R)
 592 #define PL1_W (0x04 | PL2_W)
 593 #define PL0_R (0x02 | PL1_R)
 594 #define PL0_W (0x01 | PL1_W)
 595
 596 #define PL3_RW (PL3_R | PL3_W)
 597 #define PL2_RW (PL2_R | PL2_W)
 598 #define PL1_RW (PL1_R | PL1_W)
 599 #define PL0_RW (PL0_R | PL0_W)
 600
 601 static inline int arm_current_pl(CPUARMState *env)
 602 {
 603     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
 604         return 0;
 605     }
 606     /* We don't currently implement the Virtualization or TrustZone
 607      * extensions, so PL2 and PL3 don't exist for us.
 608      */
 609     return 1;
 610 }
 611
 612 typedef struct ARMCPRegInfo ARMCPRegInfo;
 613
 614 /* Access functions for coprocessor registers. These should return
 615  * 0 on success, or one of the EXCP_* constants if access should cause
 616  * an exception (in which case *value is not written).
 617  */
 618 typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 619                      uint64_t *value);
 620 typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 621                       uint64_t value);
 622 /* Hook function for register reset */
 623 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 624
 625 #define CP_ANY 0xff
 626
 627 /* Definition of an ARM coprocessor register */
 628 struct ARMCPRegInfo {
 629     /* Name of register (useful mainly for debugging, need not be unique) */
 630     const char *name;
 631     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 632      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 633      * 'wildcard' field -- any value of that field in the MRC/MCR insn
 634      * will be decoded to this register. The register read and write
 635      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 636      * used by the program, so it is possible to register a wildcard and
 637      * then behave differently on read/write if necessary.
 638      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 639      * must both be zero.
 640      */
 641     uint8_t cp;
 642     uint8_t crn;
 643     uint8_t crm;
 644     uint8_t opc1;
 645     uint8_t opc2;
 646     /* Register type: ARM_CP_* bits/values */
 647     int type;
 648     /* Access rights: PL*_[RW] */
 649     int access;
 650     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 651      * this register was defined: can be used to hand data through to the
 652      * register read/write functions, since they are passed the ARMCPRegInfo*.
 653      */
 654     void *opaque;
 655     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 656      * fieldoffset is non-zero, the reset value of the register.
 657      */
 658     uint64_t resetvalue;
 659     /* Offset of the field in CPUARMState for this register. This is not
 660      * needed if either:
 661      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 662      *  2. both readfn and writefn are specified
 663      */
 664     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 665     /* Function for handling reads of this register. If NULL, then reads
 666      * will be done by loading from the offset into CPUARMState specified
 667      * by fieldoffset.
 668      */
 669     CPReadFn *readfn;
 670     /* Function for handling writes of this register. If NULL, then writes
 671      * will be done by writing to the offset into CPUARMState specified
 672      * by fieldoffset.
 673      */
 674     CPWriteFn *writefn;
 675     /* Function for doing a "raw" read; used when we need to copy
 676      * coprocessor state to the kernel for KVM or out for
 677      * migration. This only needs to be provided if there is also a
 678      * readfn and it makes an access permission check.
 679      */
 680     CPReadFn *raw_readfn;
 681     /* Function for doing a "raw" write; used when we need to copy KVM
 682      * kernel coprocessor state into userspace, or for inbound
 683      * migration. This only needs to be provided if there is also a
 684      * writefn and it makes an access permission check or masks out
 685      * "unwritable" bits or has write-one-to-clear or similar behaviour.
 686      */
 687     CPWriteFn *raw_writefn;
 688     /* Function for resetting the register. If NULL, then reset will be done
 689      * by writing resetvalue to the field specified in fieldoffset. If
 690      * fieldoffset is 0 then no reset will be done.
 691      */
 692     CPResetFn *resetfn;
 693 };
 694
 695 /* Macros which are lvalues for the field in CPUARMState for the
 696  * ARMCPRegInfo *ri.
 697  */
 698 #define CPREG_FIELD32(env, ri) \
 699     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 700 #define CPREG_FIELD64(env, ri) \
 701     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 702
 703 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 704
 705 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 706                                     const ARMCPRegInfo *regs, void *opaque);
 707 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 708                                        const ARMCPRegInfo *regs, void *opaque);
 709 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 710 {
 711     define_arm_cp_regs_with_opaque(cpu, regs, 0);
 712 }
 713 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 714 {
 715     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 716 }
 717 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
 718
 719 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 720 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 721                         uint64_t value);
 722 /* CPReadFn that can be used for read-as-zero behaviour */
 723 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
 724
 725 static inline bool cp_access_ok(CPUARMState *env,
 726                                 const ARMCPRegInfo *ri, int isread)
 727 {
 728     return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
 729 }
 730
 731 /**
 732  * write_list_to_cpustate
 733  * @cpu: ARMCPU
 734  *
 735  * For each register listed in the ARMCPU cpreg_indexes list, write
 736  * its value from the cpreg_values list into the ARMCPUState structure.
 737  * This updates TCG's working data structures from KVM data or
 738  * from incoming migration state.
 739  *
 740  * Returns: true if all register values were updated correctly,
 741  * false if some register was unknown or could not be written.
 742  * Note that we do not stop early on failure -- we will attempt
 743  * writing all registers in the list.
 744  */
 745 bool write_list_to_cpustate(ARMCPU *cpu);
 746
 747 /**
 748  * write_cpustate_to_list:
 749  * @cpu: ARMCPU
 750  *
 751  * For each register listed in the ARMCPU cpreg_indexes list, write
 752  * its value from the ARMCPUState structure into the cpreg_values list.
 753  * This is used to copy info from TCG's working data structures into
 754  * KVM or for outbound migration.
 755  *
 756  * Returns: true if all register values were read correctly,
 757  * false if some register was unknown or could not be read.
 758  * Note that we do not stop early on failure -- we will attempt
 759  * reading all registers in the list.
 760  */
 761 bool write_cpustate_to_list(ARMCPU *cpu);
 762
 763 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 764    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 765    conventional cores (ie. Application or Realtime profile).  */
 766
 767 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 768
 769 #define ARM_CPUID_TI915T      0x54029152
 770 #define ARM_CPUID_TI925T      0x54029252
 771
 772 #if defined(CONFIG_USER_ONLY)
 773 #define TARGET_PAGE_BITS 12
 774 #else
 775 /* The ARM MMU allows 1k pages.  */
 776 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 777    architecture revisions.  Maybe a configure option to disable them.  */
 778 #define TARGET_PAGE_BITS 10
 779 #endif
 780
 781 #if defined(TARGET_AARCH64)
 782 #  define TARGET_PHYS_ADDR_SPACE_BITS 48
 783 #  define TARGET_VIRT_ADDR_SPACE_BITS 64
 784 #else
 785 #  define TARGET_PHYS_ADDR_SPACE_BITS 40
 786 #  define TARGET_VIRT_ADDR_SPACE_BITS 32
 787 #endif
 788
 789 static inline CPUARMState *cpu_init(const char *cpu_model)
 790 {
 791     ARMCPU *cpu = cpu_arm_init(cpu_model);
 792     if (cpu) {
 793         return &cpu->env;
 794     }
 795     return NULL;
 796 }
 797
 798 #define cpu_exec cpu_arm_exec
 799 #define cpu_gen_code cpu_arm_gen_code
 800 #define cpu_signal_handler cpu_arm_signal_handler
 801 #define cpu_list arm_cpu_list
 802
 803 /* MMU modes definitions */
 804 #define MMU_MODE0_SUFFIX _kernel
 805 #define MMU_MODE1_SUFFIX _user
 806 #define MMU_USER_IDX 1
 807 static inline int cpu_mmu_index (CPUARMState *env)
 808 {
 809     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 810 }
 811
 812 #include "exec/cpu-all.h"
 813
 814 /* Bit usage in the TB flags field: bit 31 indicates whether we are
 815  * in 32 or 64 bit mode. The meaning of the other bits depends on that.
 816  */
 817 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
 818 #define ARM_TBFLAG_AARCH64_STATE_MASK  (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
 819
 820 /* Bit usage when in AArch32 state: */
 821 #define ARM_TBFLAG_THUMB_SHIFT      0
 822 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 823 #define ARM_TBFLAG_VECLEN_SHIFT     1
 824 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 825 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 826 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 827 #define ARM_TBFLAG_PRIV_SHIFT       6
 828 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 829 #define ARM_TBFLAG_VFPEN_SHIFT      7
 830 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 831 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 832 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 833 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 834 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 835
 836 /* Bit usage when in AArch64 state: currently no bits defined */
 837
 838 /* some convenience accessor macros */
 839 #define ARM_TBFLAG_AARCH64_STATE(F) \
 840     (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
 841 #define ARM_TBFLAG_THUMB(F) \
 842     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 843 #define ARM_TBFLAG_VECLEN(F) \
 844     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 845 #define ARM_TBFLAG_VECSTRIDE(F) \
 846     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 847 #define ARM_TBFLAG_PRIV(F) \
 848     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 849 #define ARM_TBFLAG_VFPEN(F) \
 850     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 851 #define ARM_TBFLAG_CONDEXEC(F) \
 852     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 853 #define ARM_TBFLAG_BSWAP_CODE(F) \
 854     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 855
 856 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 857                                         target_ulong *cs_base, int *flags)
 858 {
 859     if (is_a64(env)) {
 860         *pc = env->pc;
 861         *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
 862     } else {
 863         int privmode;
 864         *pc = env->regs[15];
 865         *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 866             | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 867             | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 868             | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 869             | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 870         if (arm_feature(env, ARM_FEATURE_M)) {
 871             privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 872         } else {
 873             privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 874         }
 875         if (privmode) {
 876             *flags |= ARM_TBFLAG_PRIV_MASK;
 877         }
 878         if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 879             *flags |= ARM_TBFLAG_VFPEN_MASK;
 880         }
 881     }
 882
 883     *cs_base = 0;
 884 }
 885
 886 static inline bool cpu_has_work(CPUState *cpu)
 887 {
 888     return cpu->interrupt_request &
 889         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 890 }
 891
 892 #include "exec/exec-all.h"
 893
 894 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
 895 {
 896     if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
 897         env->pc = tb->pc;
 898     } else {
 899         env->regs[15] = tb->pc;
 900     }
 901 }
 902
 903 /* Load an instruction and return it in the standard little-endian order */
 904 static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
 905                                     bool do_swap)
 906 {
 907     uint32_t insn = cpu_ldl_code(env, addr);
 908     if (do_swap) {
 909         return bswap32(insn);
 910     }
 911     return insn;
 912 }
 913
 914 /* Ditto, for a halfword (Thumb) instruction */
 915 static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
 916                                      bool do_swap)
 917 {
 918     uint16_t insn = cpu_lduw_code(env, addr);
 919     if (do_swap) {
 920         return bswap16(insn);
 921     }
 922     return insn;
 923 }
 924
 925 #endif