target/s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef S390X_CPU_H
  24 #define S390X_CPU_H
  25
  26 #include "qemu-common.h"
  27 #include "cpu-qom.h"
  28 #include "cpu_models.h"
  29
  30 #define TARGET_LONG_BITS 64
  31
  32 #define ELF_MACHINE_UNAME "S390X"
  33
  34 #define CPUArchState struct CPUS390XState
  35
  36 #include "exec/cpu-defs.h"
  37 #define TARGET_PAGE_BITS 12
  38
  39 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  40 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  41
  42 #include "exec/cpu-all.h"
  43
  44 #define NB_MMU_MODES 4
  45 #define TARGET_INSN_START_EXTRA_WORDS 1
  46
  47 #define MMU_MODE0_SUFFIX _primary
  48 #define MMU_MODE1_SUFFIX _secondary
  49 #define MMU_MODE2_SUFFIX _home
  50 #define MMU_MODE3_SUFFIX _real
  51
  52 #define MMU_USER_IDX 0
  53
  54 #define S390_MAX_CPUS 248
  55
  56 typedef struct PSW {
  57     uint64_t mask;
  58     uint64_t addr;
  59 } PSW;
  60
  61 struct CPUS390XState {
  62     uint64_t regs[16];     /* GP registers */
  63     /*
  64      * The floating point registers are part of the vector registers.
  65      * vregs[0][0] -> vregs[15][0] are 16 floating point registers
  66      */
  67     CPU_DoubleU vregs[32][2];  /* vector registers */
  68     uint32_t aregs[16];    /* access registers */
  69     uint8_t riccb[64];     /* runtime instrumentation control */
  70     uint64_t gscb[4];      /* guarded storage control */
  71
  72     /* Fields up to this point are not cleared by initial CPU reset */
  73     struct {} start_initial_reset_fields;
  74
  75     uint32_t fpc;          /* floating-point control register */
  76     uint32_t cc_op;
  77     bool bpbc;             /* branch prediction blocking */
  78
  79     float_status fpu_status; /* passed to softfloat lib */
  80
  81     /* The low part of a 128-bit return, or remainder of a divide.  */
  82     uint64_t retxl;
  83
  84     PSW psw;
  85
  86     S390CrashReason crash_reason;
  87
  88     uint64_t cc_src;
  89     uint64_t cc_dst;
  90     uint64_t cc_vr;
  91
  92     uint64_t ex_value;
  93
  94     uint64_t __excp_addr;
  95     uint64_t psa;
  96
  97     uint32_t int_pgm_code;
  98     uint32_t int_pgm_ilen;
  99
 100     uint32_t int_svc_code;
 101     uint32_t int_svc_ilen;
 102
 103     uint64_t per_address;
 104     uint16_t per_perc_atmid;
 105
 106     uint64_t cregs[16]; /* control registers */
 107
 108     int pending_int;
 109     uint16_t external_call_addr;
 110     DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
 111
 112     uint64_t ckc;
 113     uint64_t cputm;
 114     uint32_t todpr;
 115
 116     uint64_t pfault_token;
 117     uint64_t pfault_compare;
 118     uint64_t pfault_select;
 119
 120     uint64_t gbea;
 121     uint64_t pp;
 122
 123     /* Fields up to this point are cleared by a CPU reset */
 124     struct {} end_reset_fields;
 125
 126     CPU_COMMON
 127
 128 #if !defined(CONFIG_USER_ONLY)
 129     uint32_t core_id; /* PoP "CPU address", same as cpu_index */
 130     uint64_t cpuid;
 131 #endif
 132
 133     uint64_t tod_offset;
 134     uint64_t tod_basetime;
 135     QEMUTimer *tod_timer;
 136
 137     QEMUTimer *cpu_timer;
 138
 139     /*
 140      * The cpu state represents the logical state of a cpu. In contrast to other
 141      * architectures, there is a difference between a halt and a stop on s390.
 142      * If all cpus are either stopped (including check stop) or in the disabled
 143      * wait state, the vm can be shut down.
 144      */
 145 #define CPU_STATE_UNINITIALIZED        0x00
 146 #define CPU_STATE_STOPPED              0x01
 147 #define CPU_STATE_CHECK_STOP           0x02
 148 #define CPU_STATE_OPERATING            0x03
 149 #define CPU_STATE_LOAD                 0x04
 150     uint8_t cpu_state;
 151
 152     /* currently processed sigp order */
 153     uint8_t sigp_order;
 154
 155 };
 156
 157 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
 158 {
 159     return &cs->vregs[nr][0];
 160 }
 161
 162 /**
 163  * S390CPU:
 164  * @env: #CPUS390XState.
 165  *
 166  * An S/390 CPU.
 167  */
 168 struct S390CPU {
 169     /*< private >*/
 170     CPUState parent_obj;
 171     /*< public >*/
 172
 173     CPUS390XState env;
 174     S390CPUModel *model;
 175     /* needed for live migration */
 176     void *irqstate;
 177     uint32_t irqstate_saved_size;
 178 };
 179
 180 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
 181 {
 182     return container_of(env, S390CPU, env);
 183 }
 184
 185 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
 186
 187 #define ENV_OFFSET offsetof(S390CPU, env)
 188
 189 #ifndef CONFIG_USER_ONLY
 190 extern const struct VMStateDescription vmstate_s390_cpu;
 191 #endif
 192
 193 /* distinguish between 24 bit and 31 bit addressing */
 194 #define HIGH_ORDER_BIT 0x80000000
 195
 196 /* Interrupt Codes */
 197 /* Program Interrupts */
 198 #define PGM_OPERATION                   0x0001
 199 #define PGM_PRIVILEGED                  0x0002
 200 #define PGM_EXECUTE                     0x0003
 201 #define PGM_PROTECTION                  0x0004
 202 #define PGM_ADDRESSING                  0x0005
 203 #define PGM_SPECIFICATION               0x0006
 204 #define PGM_DATA                        0x0007
 205 #define PGM_FIXPT_OVERFLOW              0x0008
 206 #define PGM_FIXPT_DIVIDE                0x0009
 207 #define PGM_DEC_OVERFLOW                0x000a
 208 #define PGM_DEC_DIVIDE                  0x000b
 209 #define PGM_HFP_EXP_OVERFLOW            0x000c
 210 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 211 #define PGM_HFP_SIGNIFICANCE            0x000e
 212 #define PGM_HFP_DIVIDE                  0x000f
 213 #define PGM_SEGMENT_TRANS               0x0010
 214 #define PGM_PAGE_TRANS                  0x0011
 215 #define PGM_TRANS_SPEC                  0x0012
 216 #define PGM_SPECIAL_OP                  0x0013
 217 #define PGM_OPERAND                     0x0015
 218 #define PGM_TRACE_TABLE                 0x0016
 219 #define PGM_SPACE_SWITCH                0x001c
 220 #define PGM_HFP_SQRT                    0x001d
 221 #define PGM_PC_TRANS_SPEC               0x001f
 222 #define PGM_AFX_TRANS                   0x0020
 223 #define PGM_ASX_TRANS                   0x0021
 224 #define PGM_LX_TRANS                    0x0022
 225 #define PGM_EX_TRANS                    0x0023
 226 #define PGM_PRIM_AUTH                   0x0024
 227 #define PGM_SEC_AUTH                    0x0025
 228 #define PGM_ALET_SPEC                   0x0028
 229 #define PGM_ALEN_SPEC                   0x0029
 230 #define PGM_ALE_SEQ                     0x002a
 231 #define PGM_ASTE_VALID                  0x002b
 232 #define PGM_ASTE_SEQ                    0x002c
 233 #define PGM_EXT_AUTH                    0x002d
 234 #define PGM_STACK_FULL                  0x0030
 235 #define PGM_STACK_EMPTY                 0x0031
 236 #define PGM_STACK_SPEC                  0x0032
 237 #define PGM_STACK_TYPE                  0x0033
 238 #define PGM_STACK_OP                    0x0034
 239 #define PGM_ASCE_TYPE                   0x0038
 240 #define PGM_REG_FIRST_TRANS             0x0039
 241 #define PGM_REG_SEC_TRANS               0x003a
 242 #define PGM_REG_THIRD_TRANS             0x003b
 243 #define PGM_MONITOR                     0x0040
 244 #define PGM_PER                         0x0080
 245 #define PGM_CRYPTO                      0x0119
 246
 247 /* External Interrupts */
 248 #define EXT_INTERRUPT_KEY               0x0040
 249 #define EXT_CLOCK_COMP                  0x1004
 250 #define EXT_CPU_TIMER                   0x1005
 251 #define EXT_MALFUNCTION                 0x1200
 252 #define EXT_EMERGENCY                   0x1201
 253 #define EXT_EXTERNAL_CALL               0x1202
 254 #define EXT_ETR                         0x1406
 255 #define EXT_SERVICE                     0x2401
 256 #define EXT_VIRTIO                      0x2603
 257
 258 /* PSW defines */
 259 #undef PSW_MASK_PER
 260 #undef PSW_MASK_DAT
 261 #undef PSW_MASK_IO
 262 #undef PSW_MASK_EXT
 263 #undef PSW_MASK_KEY
 264 #undef PSW_SHIFT_KEY
 265 #undef PSW_MASK_MCHECK
 266 #undef PSW_MASK_WAIT
 267 #undef PSW_MASK_PSTATE
 268 #undef PSW_MASK_ASC
 269 #undef PSW_SHIFT_ASC
 270 #undef PSW_MASK_CC
 271 #undef PSW_MASK_PM
 272 #undef PSW_SHIFT_MASK_PM
 273 #undef PSW_MASK_64
 274 #undef PSW_MASK_32
 275 #undef PSW_MASK_ESA_ADDR
 276
 277 #define PSW_MASK_PER            0x4000000000000000ULL
 278 #define PSW_MASK_DAT            0x0400000000000000ULL
 279 #define PSW_MASK_IO             0x0200000000000000ULL
 280 #define PSW_MASK_EXT            0x0100000000000000ULL
 281 #define PSW_MASK_KEY            0x00F0000000000000ULL
 282 #define PSW_SHIFT_KEY           52
 283 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 284 #define PSW_MASK_WAIT           0x0002000000000000ULL
 285 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 286 #define PSW_MASK_ASC            0x0000C00000000000ULL
 287 #define PSW_SHIFT_ASC           46
 288 #define PSW_MASK_CC             0x0000300000000000ULL
 289 #define PSW_MASK_PM             0x00000F0000000000ULL
 290 #define PSW_SHIFT_MASK_PM       40
 291 #define PSW_MASK_64             0x0000000100000000ULL
 292 #define PSW_MASK_32             0x0000000080000000ULL
 293 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 294
 295 #undef PSW_ASC_PRIMARY
 296 #undef PSW_ASC_ACCREG
 297 #undef PSW_ASC_SECONDARY
 298 #undef PSW_ASC_HOME
 299
 300 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 301 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 302 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 303 #define PSW_ASC_HOME            0x0000C00000000000ULL
 304
 305 /* the address space values shifted */
 306 #define AS_PRIMARY              0
 307 #define AS_ACCREG               1
 308 #define AS_SECONDARY            2
 309 #define AS_HOME                 3
 310
 311 /* tb flags */
 312
 313 #define FLAG_MASK_PSW_SHIFT     31
 314 #define FLAG_MASK_PER           (PSW_MASK_PER    >> FLAG_MASK_PSW_SHIFT)
 315 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> FLAG_MASK_PSW_SHIFT)
 316 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
 317 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> FLAG_MASK_PSW_SHIFT)
 318 #define FLAG_MASK_64            (PSW_MASK_64     >> FLAG_MASK_PSW_SHIFT)
 319 #define FLAG_MASK_32            (PSW_MASK_32     >> FLAG_MASK_PSW_SHIFT)
 320 #define FLAG_MASK_PSW           (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
 321                                 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
 322
 323 /* Control register 0 bits */
 324 #define CR0_LOWPROT             0x0000000010000000ULL
 325 #define CR0_SECONDARY           0x0000000004000000ULL
 326 #define CR0_EDAT                0x0000000000800000ULL
 327 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
 328 #define CR0_EXTERNAL_CALL_SC    0x0000000000002000ULL
 329 #define CR0_CKC_SC              0x0000000000000800ULL
 330 #define CR0_CPU_TIMER_SC        0x0000000000000400ULL
 331 #define CR0_SERVICE_SC          0x0000000000000200ULL
 332
 333 /* Control register 14 bits */
 334 #define CR14_CHANNEL_REPORT_SC  0x0000000010000000ULL
 335
 336 /* MMU */
 337 #define MMU_PRIMARY_IDX         0
 338 #define MMU_SECONDARY_IDX       1
 339 #define MMU_HOME_IDX            2
 340 #define MMU_REAL_IDX            3
 341
 342 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
 343 {
 344     if (!(env->psw.mask & PSW_MASK_DAT)) {
 345         return MMU_REAL_IDX;
 346     }
 347
 348     switch (env->psw.mask & PSW_MASK_ASC) {
 349     case PSW_ASC_PRIMARY:
 350         return MMU_PRIMARY_IDX;
 351     case PSW_ASC_SECONDARY:
 352         return MMU_SECONDARY_IDX;
 353     case PSW_ASC_HOME:
 354         return MMU_HOME_IDX;
 355     case PSW_ASC_ACCREG:
 356         /* Fallthrough: access register mode is not yet supported */
 357     default:
 358         abort();
 359     }
 360 }
 361
 362 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 363                                         target_ulong *cs_base, uint32_t *flags)
 364 {
 365     *pc = env->psw.addr;
 366     *cs_base = env->ex_value;
 367     *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
 368 }
 369
 370 /* PER bits from control register 9 */
 371 #define PER_CR9_EVENT_BRANCH           0x80000000
 372 #define PER_CR9_EVENT_IFETCH           0x40000000
 373 #define PER_CR9_EVENT_STORE            0x20000000
 374 #define PER_CR9_EVENT_STORE_REAL       0x08000000
 375 #define PER_CR9_EVENT_NULLIFICATION    0x01000000
 376 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
 377 #define PER_CR9_CONTROL_ALTERATION     0x00200000
 378
 379 /* PER bits from the PER CODE/ATMID/AI in lowcore */
 380 #define PER_CODE_EVENT_BRANCH          0x8000
 381 #define PER_CODE_EVENT_IFETCH          0x4000
 382 #define PER_CODE_EVENT_STORE           0x2000
 383 #define PER_CODE_EVENT_STORE_REAL      0x0800
 384 #define PER_CODE_EVENT_NULLIFICATION   0x0100
 385
 386 #define EXCP_EXT 1 /* external interrupt */
 387 #define EXCP_SVC 2 /* supervisor call (syscall) */
 388 #define EXCP_PGM 3 /* program interruption */
 389 #define EXCP_RESTART 4 /* restart interrupt */
 390 #define EXCP_STOP 5 /* stop interrupt */
 391 #define EXCP_IO  7 /* I/O interrupt */
 392 #define EXCP_MCHK 8 /* machine check */
 393
 394 #define INTERRUPT_EXT_CPU_TIMER          (1 << 3)
 395 #define INTERRUPT_EXT_CLOCK_COMPARATOR   (1 << 4)
 396 #define INTERRUPT_EXTERNAL_CALL          (1 << 5)
 397 #define INTERRUPT_EMERGENCY_SIGNAL       (1 << 6)
 398 #define INTERRUPT_RESTART                (1 << 7)
 399 #define INTERRUPT_STOP                   (1 << 8)
 400
 401 /* Program Status Word.  */
 402 #define S390_PSWM_REGNUM 0
 403 #define S390_PSWA_REGNUM 1
 404 /* General Purpose Registers.  */
 405 #define S390_R0_REGNUM 2
 406 #define S390_R1_REGNUM 3
 407 #define S390_R2_REGNUM 4
 408 #define S390_R3_REGNUM 5
 409 #define S390_R4_REGNUM 6
 410 #define S390_R5_REGNUM 7
 411 #define S390_R6_REGNUM 8
 412 #define S390_R7_REGNUM 9
 413 #define S390_R8_REGNUM 10
 414 #define S390_R9_REGNUM 11
 415 #define S390_R10_REGNUM 12
 416 #define S390_R11_REGNUM 13
 417 #define S390_R12_REGNUM 14
 418 #define S390_R13_REGNUM 15
 419 #define S390_R14_REGNUM 16
 420 #define S390_R15_REGNUM 17
 421 /* Total Core Registers. */
 422 #define S390_NUM_CORE_REGS 18
 423
 424 static inline void setcc(S390CPU *cpu, uint64_t cc)
 425 {
 426     CPUS390XState *env = &cpu->env;
 427
 428     env->psw.mask &= ~(3ull << 44);
 429     env->psw.mask |= (cc & 3) << 44;
 430     env->cc_op = cc;
 431 }
 432
 433 /* STSI */
 434 #define STSI_R0_FC_MASK         0x00000000f0000000ULL
 435 #define STSI_R0_FC_CURRENT      0x0000000000000000ULL
 436 #define STSI_R0_FC_LEVEL_1      0x0000000010000000ULL
 437 #define STSI_R0_FC_LEVEL_2      0x0000000020000000ULL
 438 #define STSI_R0_FC_LEVEL_3      0x0000000030000000ULL
 439 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 440 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 441 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 442 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 443
 444 /* Basic Machine Configuration */
 445 typedef struct SysIB_111 {
 446     uint8_t  res1[32];
 447     uint8_t  manuf[16];
 448     uint8_t  type[4];
 449     uint8_t  res2[12];
 450     uint8_t  model[16];
 451     uint8_t  sequence[16];
 452     uint8_t  plant[4];
 453     uint8_t  res3[3996];
 454 } SysIB_111;
 455 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
 456
 457 /* Basic Machine CPU */
 458 typedef struct SysIB_121 {
 459     uint8_t  res1[80];
 460     uint8_t  sequence[16];
 461     uint8_t  plant[4];
 462     uint8_t  res2[2];
 463     uint16_t cpu_addr;
 464     uint8_t  res3[3992];
 465 } SysIB_121;
 466 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
 467
 468 /* Basic Machine CPUs */
 469 typedef struct SysIB_122 {
 470     uint8_t res1[32];
 471     uint32_t capability;
 472     uint16_t total_cpus;
 473     uint16_t conf_cpus;
 474     uint16_t standby_cpus;
 475     uint16_t reserved_cpus;
 476     uint16_t adjustments[2026];
 477 } SysIB_122;
 478 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
 479
 480 /* LPAR CPU */
 481 typedef struct SysIB_221 {
 482     uint8_t  res1[80];
 483     uint8_t  sequence[16];
 484     uint8_t  plant[4];
 485     uint16_t cpu_id;
 486     uint16_t cpu_addr;
 487     uint8_t  res3[3992];
 488 } SysIB_221;
 489 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
 490
 491 /* LPAR CPUs */
 492 typedef struct SysIB_222 {
 493     uint8_t  res1[32];
 494     uint16_t lpar_num;
 495     uint8_t  res2;
 496     uint8_t  lcpuc;
 497     uint16_t total_cpus;
 498     uint16_t conf_cpus;
 499     uint16_t standby_cpus;
 500     uint16_t reserved_cpus;
 501     uint8_t  name[8];
 502     uint32_t caf;
 503     uint8_t  res3[16];
 504     uint16_t dedicated_cpus;
 505     uint16_t shared_cpus;
 506     uint8_t  res4[4020];
 507 } SysIB_222;
 508 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
 509
 510 /* VM CPUs */
 511 typedef struct SysIB_322 {
 512     uint8_t  res1[31];
 513     uint8_t  count;
 514     struct {
 515         uint8_t  res2[4];
 516         uint16_t total_cpus;
 517         uint16_t conf_cpus;
 518         uint16_t standby_cpus;
 519         uint16_t reserved_cpus;
 520         uint8_t  name[8];
 521         uint32_t caf;
 522         uint8_t  cpi[16];
 523         uint8_t res5[3];
 524         uint8_t ext_name_encoding;
 525         uint32_t res3;
 526         uint8_t uuid[16];
 527     } vm[8];
 528     uint8_t res4[1504];
 529     uint8_t ext_names[8][256];
 530 } SysIB_322;
 531 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
 532
 533 typedef union SysIB {
 534     SysIB_111 sysib_111;
 535     SysIB_121 sysib_121;
 536     SysIB_122 sysib_122;
 537     SysIB_221 sysib_221;
 538     SysIB_222 sysib_222;
 539     SysIB_322 sysib_322;
 540 } SysIB;
 541 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
 542
 543 /* MMU defines */
 544 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 545 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 546 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 547 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 548 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 549 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 550 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 551 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 552 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 553 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 554 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 555 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 556
 557 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 558 #define _REGION_ENTRY_RO        0x200     /* region/segment protection bit    */
 559 #define _REGION_ENTRY_TF        0xc0      /* region/segment table offset      */
 560 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 561 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 562 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 563 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 564 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 565 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 566
 567 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 568 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 569 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 570 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 571
 572 #define VADDR_PX                0xff000   /* page index bits                  */
 573
 574 #define _PAGE_RO        0x200            /* HW read-only bit  */
 575 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 576 #define _PAGE_RES0      0x800            /* bit must be zero  */
 577
 578 #define SK_C                    (0x1 << 1)
 579 #define SK_R                    (0x1 << 2)
 580 #define SK_F                    (0x1 << 3)
 581 #define SK_ACC_MASK             (0xf << 4)
 582
 583 /* SIGP order codes */
 584 #define SIGP_SENSE             0x01
 585 #define SIGP_EXTERNAL_CALL     0x02
 586 #define SIGP_EMERGENCY         0x03
 587 #define SIGP_START             0x04
 588 #define SIGP_STOP              0x05
 589 #define SIGP_RESTART           0x06
 590 #define SIGP_STOP_STORE_STATUS 0x09
 591 #define SIGP_INITIAL_CPU_RESET 0x0b
 592 #define SIGP_CPU_RESET         0x0c
 593 #define SIGP_SET_PREFIX        0x0d
 594 #define SIGP_STORE_STATUS_ADDR 0x0e
 595 #define SIGP_SET_ARCH          0x12
 596 #define SIGP_COND_EMERGENCY    0x13
 597 #define SIGP_SENSE_RUNNING     0x15
 598 #define SIGP_STORE_ADTL_STATUS 0x17
 599
 600 /* SIGP condition codes */
 601 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
 602 #define SIGP_CC_STATUS_STORED       1
 603 #define SIGP_CC_BUSY                2
 604 #define SIGP_CC_NOT_OPERATIONAL     3
 605
 606 /* SIGP status bits */
 607 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 608 #define SIGP_STAT_NOT_RUNNING       0x00000400UL
 609 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 610 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 611 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 612 #define SIGP_STAT_STOPPED           0x00000040UL
 613 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 614 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 615 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 616 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 617 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 618
 619 /* SIGP SET ARCHITECTURE modes */
 620 #define SIGP_MODE_ESA_S390 0
 621 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
 622 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
 623
 624 /* SIGP order code mask corresponding to bit positions 56-63 */
 625 #define SIGP_ORDER_MASK 0x000000ff
 626
 627 /* from s390-virtio-ccw */
 628 #define MEM_SECTION_SIZE             0x10000000UL
 629 #define MAX_AVAIL_SLOTS              32
 630
 631 /* machine check interruption code */
 632
 633 /* subclasses */
 634 #define MCIC_SC_SD 0x8000000000000000ULL
 635 #define MCIC_SC_PD 0x4000000000000000ULL
 636 #define MCIC_SC_SR 0x2000000000000000ULL
 637 #define MCIC_SC_CD 0x0800000000000000ULL
 638 #define MCIC_SC_ED 0x0400000000000000ULL
 639 #define MCIC_SC_DG 0x0100000000000000ULL
 640 #define MCIC_SC_W  0x0080000000000000ULL
 641 #define MCIC_SC_CP 0x0040000000000000ULL
 642 #define MCIC_SC_SP 0x0020000000000000ULL
 643 #define MCIC_SC_CK 0x0010000000000000ULL
 644
 645 /* subclass modifiers */
 646 #define MCIC_SCM_B  0x0002000000000000ULL
 647 #define MCIC_SCM_DA 0x0000000020000000ULL
 648 #define MCIC_SCM_AP 0x0000000000080000ULL
 649
 650 /* storage errors */
 651 #define MCIC_SE_SE 0x0000800000000000ULL
 652 #define MCIC_SE_SC 0x0000400000000000ULL
 653 #define MCIC_SE_KE 0x0000200000000000ULL
 654 #define MCIC_SE_DS 0x0000100000000000ULL
 655 #define MCIC_SE_IE 0x0000000080000000ULL
 656
 657 /* validity bits */
 658 #define MCIC_VB_WP 0x0000080000000000ULL
 659 #define MCIC_VB_MS 0x0000040000000000ULL
 660 #define MCIC_VB_PM 0x0000020000000000ULL
 661 #define MCIC_VB_IA 0x0000010000000000ULL
 662 #define MCIC_VB_FA 0x0000008000000000ULL
 663 #define MCIC_VB_VR 0x0000004000000000ULL
 664 #define MCIC_VB_EC 0x0000002000000000ULL
 665 #define MCIC_VB_FP 0x0000001000000000ULL
 666 #define MCIC_VB_GR 0x0000000800000000ULL
 667 #define MCIC_VB_CR 0x0000000400000000ULL
 668 #define MCIC_VB_ST 0x0000000100000000ULL
 669 #define MCIC_VB_AR 0x0000000040000000ULL
 670 #define MCIC_VB_GS 0x0000000008000000ULL
 671 #define MCIC_VB_PR 0x0000000000200000ULL
 672 #define MCIC_VB_FC 0x0000000000100000ULL
 673 #define MCIC_VB_CT 0x0000000000020000ULL
 674 #define MCIC_VB_CC 0x0000000000010000ULL
 675
 676 static inline uint64_t s390_build_validity_mcic(void)
 677 {
 678     uint64_t mcic;
 679
 680     /*
 681      * Indicate all validity bits (no damage) only. Other bits have to be
 682      * added by the caller. (storage errors, subclasses and subclass modifiers)
 683      */
 684     mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
 685            MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
 686            MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
 687     if (s390_has_feat(S390_FEAT_VECTOR)) {
 688         mcic |= MCIC_VB_VR;
 689     }
 690     if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
 691         mcic |= MCIC_VB_GS;
 692     }
 693     return mcic;
 694 }
 695
 696
 697 /* cpu.c */
 698 int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low);
 699 int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low);
 700 void s390_crypto_reset(void);
 701 bool s390_get_squash_mcss(void);
 702 int s390_get_memslot_count(void);
 703 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
 704 void s390_cmma_reset(void);
 705 void s390_enable_css_support(S390CPU *cpu);
 706 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
 707                                 int vq, bool assign);
 708 #ifndef CONFIG_USER_ONLY
 709 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 710 #else
 711 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 712 {
 713     return 0;
 714 }
 715 #endif /* CONFIG_USER_ONLY */
 716 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 717 {
 718     return cpu->env.cpu_state;
 719 }
 720
 721
 722 /* cpu_models.c */
 723 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 724 #define cpu_list s390_cpu_list
 725 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
 726                              const S390FeatInit feat_init);
 727
 728
 729 /* helper.c */
 730 #define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model)
 731
 732 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
 733 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
 734
 735 /* you can call this signal handler from your SIGBUS and SIGSEGV
 736    signal handlers to inform the virtual CPU of exceptions. non zero
 737    is returned if the signal was handled by the virtual CPU.  */
 738 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
 739 #define cpu_signal_handler cpu_s390x_signal_handler
 740
 741
 742 /* interrupt.c */
 743 void s390_crw_mchk(void);
 744 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
 745                        uint32_t io_int_parm, uint32_t io_int_word);
 746 /* automatically detect the instruction length */
 747 #define ILEN_AUTO                   0xff
 748 #define RA_IGNORED                  0
 749 void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen,
 750                             uintptr_t ra);
 751 /* service interrupts are floating therefore we must not pass an cpustate */
 752 void s390_sclp_extint(uint32_t parm);
 753
 754 /* mmu_helper.c */
 755 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 756                          int len, bool is_write);
 757 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
 758         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
 759 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
 760         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
 761 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len)   \
 762         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
 763 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
 764         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
 765 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
 766
 767
 768 /* sigp.c */
 769 int s390_cpu_restart(S390CPU *cpu);
 770 void s390_init_sigp(void);
 771
 772
 773 /* outside of target/s390x/ */
 774 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 775
 776 #endif