hw/mips/mips_int.c

   1 /*
   2  * QEMU MIPS interrupt support
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "hw/hw.h"
  25 #include "hw/mips/cpudevs.h"
  26 #include "cpu.h"
  27 #include "sysemu/kvm.h"
  28 #include "kvm_mips.h"
  29
  30 static void cpu_mips_irq_request(void *opaque, int irq, int level)
  31 {
  32     MIPSCPU *cpu = opaque;
  33     CPUMIPSState *env = &cpu->env;
  34     CPUState *cs = CPU(cpu);
  35
  36     if (irq < 0 || irq > 7)
  37         return;
  38
  39     if (level) {
  40         env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
  41
  42         if (kvm_enabled() && irq == 2) {
  43             kvm_mips_set_interrupt(cpu, irq, level);
  44         }
  45
  46     } else {
  47         env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
  48
  49         if (kvm_enabled() && irq == 2) {
  50             kvm_mips_set_interrupt(cpu, irq, level);
  51         }
  52     }
  53
  54     if (env->CP0_Cause & CP0Ca_IP_mask) {
  55         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  56     } else {
  57         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  58     }
  59 }
  60
  61 void cpu_mips_irq_init_cpu(MIPSCPU *cpu)
  62 {
  63     CPUMIPSState *env = &cpu->env;
  64     qemu_irq *qi;
  65     int i;
  66
  67     qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env), 8);
  68     for (i = 0; i < 8; i++) {
  69         env->irq[i] = qi[i];
  70     }
  71 }
  72
  73 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
  74 {
  75     if (irq < 0 || irq > 2) {
  76         return;
  77     }
  78
  79     qemu_set_irq(env->irq[irq], level);
  80 }