target-s390x/mmu_helper.c

   1 /*
   2  * S390x MMU related functions
   3  *
   4  * Copyright (c) 2011 Alexander Graf
   5  * Copyright (c) 2015 Thomas Huth, IBM Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include "qemu/error-report.h"
  19 #include "exec/address-spaces.h"
  20 #include "cpu.h"
  21 #include "sysemu/kvm.h"
  22 #include "trace.h"
  23 #include "hw/s390x/storage-keys.h"
  24
  25 /* #define DEBUG_S390 */
  26 /* #define DEBUG_S390_PTE */
  27 /* #define DEBUG_S390_STDOUT */
  28
  29 #ifdef DEBUG_S390
  30 #ifdef DEBUG_S390_STDOUT
  31 #define DPRINTF(fmt, ...) \
  32     do { fprintf(stderr, fmt, ## __VA_ARGS__); \
  33          if (qemu_log_separate()) qemu_log(fmt, ##__VA_ARGS__); } while (0)
  34 #else
  35 #define DPRINTF(fmt, ...) \
  36     do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
  37 #endif
  38 #else
  39 #define DPRINTF(fmt, ...) \
  40     do { } while (0)
  41 #endif
  42
  43 #ifdef DEBUG_S390_PTE
  44 #define PTE_DPRINTF DPRINTF
  45 #else
  46 #define PTE_DPRINTF(fmt, ...) \
  47     do { } while (0)
  48 #endif
  49
  50 /* Fetch/store bits in the translation exception code: */
  51 #define FS_READ  0x800
  52 #define FS_WRITE 0x400
  53
  54 static void trigger_access_exception(CPUS390XState *env, uint32_t type,
  55                                      uint32_t ilen, uint64_t tec)
  56 {
  57     S390CPU *cpu = s390_env_get_cpu(env);
  58
  59     if (kvm_enabled()) {
  60         kvm_s390_access_exception(cpu, type, tec);
  61     } else {
  62         CPUState *cs = CPU(cpu);
  63         stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
  64         trigger_pgm_exception(env, type, ilen);
  65     }
  66 }
  67
  68 static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
  69                                uint64_t asc, int rw, bool exc)
  70 {
  71     uint64_t tec;
  72
  73     tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | 4 | asc >> 46;
  74
  75     DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
  76
  77     if (!exc) {
  78         return;
  79     }
  80
  81     trigger_access_exception(env, PGM_PROTECTION, ILEN_LATER_INC, tec);
  82 }
  83
  84 static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
  85                                uint32_t type, uint64_t asc, int rw, bool exc)
  86 {
  87     int ilen = ILEN_LATER;
  88     uint64_t tec;
  89
  90     tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | asc >> 46;
  91
  92     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
  93
  94     if (!exc) {
  95         return;
  96     }
  97
  98     /* Code accesses have an undefined ilc.  */
  99     if (rw == MMU_INST_FETCH) {
 100         ilen = 2;
 101     }
 102
 103     trigger_access_exception(env, type, ilen, tec);
 104 }
 105
 106 /**
 107  * Translate real address to absolute (= physical)
 108  * address by taking care of the prefix mapping.
 109  */
 110 static target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
 111 {
 112     if (raddr < 0x2000) {
 113         return raddr + env->psa;    /* Map the lowcore. */
 114     } else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
 115         return raddr - env->psa;    /* Map the 0 page. */
 116     }
 117     return raddr;
 118 }
 119
 120 /* Decode page table entry (normal 4KB page) */
 121 static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
 122                              uint64_t asc, uint64_t pt_entry,
 123                              target_ulong *raddr, int *flags, int rw, bool exc)
 124 {
 125     if (pt_entry & _PAGE_INVALID) {
 126         DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, pt_entry);
 127         trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw, exc);
 128         return -1;
 129     }
 130     if (pt_entry & _PAGE_RES0) {
 131         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
 132         return -1;
 133     }
 134     if (pt_entry & _PAGE_RO) {
 135         *flags &= ~PAGE_WRITE;
 136     }
 137
 138     *raddr = pt_entry & _ASCE_ORIGIN;
 139
 140     PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, pt_entry);
 141
 142     return 0;
 143 }
 144
 145 #define VADDR_PX    0xff000         /* Page index bits */
 146
 147 /* Decode segment table entry */
 148 static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
 149                                  uint64_t asc, uint64_t st_entry,
 150                                  target_ulong *raddr, int *flags, int rw,
 151                                  bool exc)
 152 {
 153     CPUState *cs = CPU(s390_env_get_cpu(env));
 154     uint64_t origin, offs, pt_entry;
 155
 156     if (st_entry & _SEGMENT_ENTRY_RO) {
 157         *flags &= ~PAGE_WRITE;
 158     }
 159
 160     if ((st_entry & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
 161         /* Decode EDAT1 segment frame absolute address (1MB page) */
 162         *raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);
 163         PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry);
 164         return 0;
 165     }
 166
 167     /* Look up 4KB page entry */
 168     origin = st_entry & _SEGMENT_ENTRY_ORIGIN;
 169     offs  = (vaddr & VADDR_PX) >> 9;
 170     pt_entry = ldq_phys(cs->as, origin + offs);
 171     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 172                 __func__, origin, offs, pt_entry);
 173     return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc);
 174 }
 175
 176 /* Decode region table entries */
 177 static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
 178                                 uint64_t asc, uint64_t entry, int level,
 179                                 target_ulong *raddr, int *flags, int rw,
 180                                 bool exc)
 181 {
 182     CPUState *cs = CPU(s390_env_get_cpu(env));
 183     uint64_t origin, offs, new_entry;
 184     const int pchks[4] = {
 185         PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
 186         PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS
 187     };
 188
 189     PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry);
 190
 191     origin = entry & _REGION_ENTRY_ORIGIN;
 192     offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
 193
 194     new_entry = ldq_phys(cs->as, origin + offs);
 195     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 196                 __func__, origin, offs, new_entry);
 197
 198     if ((new_entry & _REGION_ENTRY_INV) != 0) {
 199         DPRINTF("%s: invalid region\n", __func__);
 200         trigger_page_fault(env, vaddr, pchks[level / 4], asc, rw, exc);
 201         return -1;
 202     }
 203
 204     if ((new_entry & _REGION_ENTRY_TYPE_MASK) != level) {
 205         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
 206         return -1;
 207     }
 208
 209     if (level == _ASCE_TYPE_SEGMENT) {
 210         return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags,
 211                                      rw, exc);
 212     }
 213
 214     /* Check region table offset and length */
 215     offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3;
 216     if (offs < ((new_entry & _REGION_ENTRY_TF) >> 6)
 217         || offs > (new_entry & _REGION_ENTRY_LENGTH)) {
 218         DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry);
 219         trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw, exc);
 220         return -1;
 221     }
 222
 223     if ((env->cregs[0] & CR0_EDAT) && (new_entry & _REGION_ENTRY_RO)) {
 224         *flags &= ~PAGE_WRITE;
 225     }
 226
 227     /* yet another region */
 228     return mmu_translate_region(env, vaddr, asc, new_entry, level - 4,
 229                                 raddr, flags, rw, exc);
 230 }
 231
 232 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
 233                               uint64_t asc, uint64_t asce, target_ulong *raddr,
 234                               int *flags, int rw, bool exc)
 235 {
 236     int level;
 237     int r;
 238
 239     if (asce & _ASCE_REAL_SPACE) {
 240         /* direct mapping */
 241         *raddr = vaddr;
 242         return 0;
 243     }
 244
 245     level = asce & _ASCE_TYPE_MASK;
 246     switch (level) {
 247     case _ASCE_TYPE_REGION1:
 248         if ((vaddr >> 62) > (asce & _ASCE_TABLE_LENGTH)) {
 249             trigger_page_fault(env, vaddr, PGM_REG_FIRST_TRANS, asc, rw, exc);
 250             return -1;
 251         }
 252         break;
 253     case _ASCE_TYPE_REGION2:
 254         if (vaddr & 0xffe0000000000000ULL) {
 255             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 256                     " 0xffe0000000000000ULL\n", __func__, vaddr);
 257             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 258             return -1;
 259         }
 260         if ((vaddr >> 51 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 261             trigger_page_fault(env, vaddr, PGM_REG_SEC_TRANS, asc, rw, exc);
 262             return -1;
 263         }
 264         break;
 265     case _ASCE_TYPE_REGION3:
 266         if (vaddr & 0xfffffc0000000000ULL) {
 267             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 268                     " 0xfffffc0000000000ULL\n", __func__, vaddr);
 269             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 270             return -1;
 271         }
 272         if ((vaddr >> 40 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 273             trigger_page_fault(env, vaddr, PGM_REG_THIRD_TRANS, asc, rw, exc);
 274             return -1;
 275         }
 276         break;
 277     case _ASCE_TYPE_SEGMENT:
 278         if (vaddr & 0xffffffff80000000ULL) {
 279             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 280                     " 0xffffffff80000000ULL\n", __func__, vaddr);
 281             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 282             return -1;
 283         }
 284         if ((vaddr >> 29 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 285             trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc);
 286             return -1;
 287         }
 288         break;
 289     }
 290
 291     r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw,
 292                              exc);
 293     if (rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE)) {
 294         trigger_prot_fault(env, vaddr, asc, rw, exc);
 295         return -1;
 296     }
 297
 298     return r;
 299 }
 300
 301 /**
 302  * Translate a virtual (logical) address into a physical (absolute) address.
 303  * @param vaddr  the virtual address
 304  * @param rw     0 = read, 1 = write, 2 = code fetch
 305  * @param asc    address space control (one of the PSW_ASC_* modes)
 306  * @param raddr  the translated address is stored to this pointer
 307  * @param flags  the PAGE_READ/WRITE/EXEC flags are stored to this pointer
 308  * @param exc    true = inject a program check if a fault occurred
 309  * @return       0 if the translation was successful, -1 if a fault occurred
 310  */
 311 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 312                   target_ulong *raddr, int *flags, bool exc)
 313 {
 314     static S390SKeysState *ss;
 315     static S390SKeysClass *skeyclass;
 316     int r = -1;
 317     uint8_t key;
 318
 319     if (unlikely(!ss)) {
 320         ss = s390_get_skeys_device();
 321         skeyclass = S390_SKEYS_GET_CLASS(ss);
 322     }
 323
 324     *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 325     vaddr &= TARGET_PAGE_MASK;
 326
 327     if (!(env->psw.mask & PSW_MASK_DAT)) {
 328         *raddr = vaddr;
 329         r = 0;
 330         goto out;
 331     }
 332
 333     switch (asc) {
 334     case PSW_ASC_PRIMARY:
 335         PTE_DPRINTF("%s: asc=primary\n", __func__);
 336         r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,
 337                                rw, exc);
 338         break;
 339     case PSW_ASC_HOME:
 340         PTE_DPRINTF("%s: asc=home\n", __func__);
 341         r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,
 342                                rw, exc);
 343         break;
 344     case PSW_ASC_SECONDARY:
 345         PTE_DPRINTF("%s: asc=secondary\n", __func__);
 346         /*
 347          * Instruction: Primary
 348          * Data: Secondary
 349          */
 350         if (rw == MMU_INST_FETCH) {
 351             r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
 352                                    raddr, flags, rw, exc);
 353             *flags &= ~(PAGE_READ | PAGE_WRITE);
 354         } else {
 355             r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7],
 356                                    raddr, flags, rw, exc);
 357             *flags &= ~(PAGE_EXEC);
 358         }
 359         break;
 360     case PSW_ASC_ACCREG:
 361     default:
 362         hw_error("guest switched to unknown asc mode\n");
 363         break;
 364     }
 365
 366  out:
 367     /* Convert real address -> absolute address */
 368     *raddr = mmu_real2abs(env, *raddr);
 369
 370     if (r == 0 && *raddr < ram_size) {
 371         if (skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) {
 372             trace_get_skeys_nonzero(r);
 373             return 0;
 374         }
 375
 376         if (*flags & PAGE_READ) {
 377             key |= SK_R;
 378         }
 379
 380         if (*flags & PAGE_WRITE) {
 381             key |= SK_C;
 382         }
 383
 384         if (skeyclass->set_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) {
 385             trace_set_skeys_nonzero(r);
 386             return 0;
 387         }
 388     }
 389
 390     return r;
 391 }
 392
 393 /**
 394  * lowprot_enabled: Check whether low-address protection is enabled
 395  */
 396 static bool lowprot_enabled(const CPUS390XState *env)
 397 {
 398     if (!(env->cregs[0] & CR0_LOWPROT)) {
 399         return false;
 400     }
 401     if (!(env->psw.mask & PSW_MASK_DAT)) {
 402         return true;
 403     }
 404
 405     /* Check the private-space control bit */
 406     switch (env->psw.mask & PSW_MASK_ASC) {
 407     case PSW_ASC_PRIMARY:
 408         return !(env->cregs[1] & _ASCE_PRIVATE_SPACE);
 409     case PSW_ASC_SECONDARY:
 410         return !(env->cregs[7] & _ASCE_PRIVATE_SPACE);
 411     case PSW_ASC_HOME:
 412         return !(env->cregs[13] & _ASCE_PRIVATE_SPACE);
 413     default:
 414         /* We don't support access register mode */
 415         error_report("unsupported addressing mode");
 416         exit(1);
 417     }
 418 }
 419
 420 /**
 421  * translate_pages: Translate a set of consecutive logical page addresses
 422  * to absolute addresses
 423  */
 424 static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
 425                            target_ulong *pages, bool is_write)
 426 {
 427     bool lowprot = is_write && lowprot_enabled(&cpu->env);
 428     uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
 429     CPUS390XState *env = &cpu->env;
 430     int ret, i, pflags;
 431
 432     for (i = 0; i < nr_pages; i++) {
 433         /* Low-address protection? */
 434         if (lowprot && (addr < 512 || (addr >= 4096 && addr < 4096 + 512))) {
 435             trigger_access_exception(env, PGM_PROTECTION, ILEN_LATER_INC, 0);
 436             return -EACCES;
 437         }
 438         ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, true);
 439         if (ret) {
 440             return ret;
 441         }
 442         if (!address_space_access_valid(&address_space_memory, pages[i],
 443                                         TARGET_PAGE_SIZE, is_write)) {
 444             program_interrupt(env, PGM_ADDRESSING, 0);
 445             return -EFAULT;
 446         }
 447         addr += TARGET_PAGE_SIZE;
 448     }
 449
 450     return 0;
 451 }
 452
 453 /**
 454  * s390_cpu_virt_mem_rw:
 455  * @laddr:     the logical start address
 456  * @ar:        the access register number
 457  * @hostbuf:   buffer in host memory. NULL = do only checks w/o copying
 458  * @len:       length that should be transferred
 459  * @is_write:  true = write, false = read
 460  * Returns:    0 on success, non-zero if an exception occurred
 461  *
 462  * Copy from/to guest memory using logical addresses. Note that we inject a
 463  * program interrupt in case there is an error while accessing the memory.
 464  */
 465 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 466                          int len, bool is_write)
 467 {
 468     int currlen, nr_pages, i;
 469     target_ulong *pages;
 470     int ret;
 471
 472     if (kvm_enabled()) {
 473         ret = kvm_s390_mem_op(cpu, laddr, ar, hostbuf, len, is_write);
 474         if (ret >= 0) {
 475             return ret;
 476         }
 477     }
 478
 479     nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS)
 480                + 1;
 481     pages = g_malloc(nr_pages * sizeof(*pages));
 482
 483     ret = translate_pages(cpu, laddr, nr_pages, pages, is_write);
 484     if (ret == 0 && hostbuf != NULL) {
 485         /* Copy data by stepping through the area page by page */
 486         for (i = 0; i < nr_pages; i++) {
 487             currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE));
 488             cpu_physical_memory_rw(pages[i] | (laddr & ~TARGET_PAGE_MASK),
 489                                    hostbuf, currlen, is_write);
 490             laddr += currlen;
 491             hostbuf += currlen;
 492             len -= currlen;
 493         }
 494     }
 495
 496     g_free(pages);
 497     return ret;
 498 }