4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
26 #include "translate.h"
27 #include "internals.h"
28 #include "qemu/host-utils.h"
30 #include "exec/semihost.h"
31 #include "exec/gen-icount.h"
33 #include "exec/helper-proto.h"
34 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
39 static TCGv_i64 cpu_X
[32];
40 static TCGv_i64 cpu_pc
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_high
;
44 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
46 static const char *regnames
[] = {
47 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
48 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
49 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
50 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
54 A64_SHIFT_TYPE_LSL
= 0,
55 A64_SHIFT_TYPE_LSR
= 1,
56 A64_SHIFT_TYPE_ASR
= 2,
57 A64_SHIFT_TYPE_ROR
= 3
60 /* Table based decoder typedefs - used when the relevant bits for decode
61 * are too awkwardly scattered across the instruction (eg SIMD).
63 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
65 typedef struct AArch64DecodeTable
{
68 AArch64DecodeFn
*disas_fn
;
71 /* Function prototype for gen_ functions for calling Neon helpers */
72 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
73 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
74 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
76 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
78 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
79 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
80 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
82 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
83 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
84 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
86 /* initialize TCG globals. */
87 void a64_translate_init(void)
91 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
92 offsetof(CPUARMState
, pc
),
94 for (i
= 0; i
< 32; i
++) {
95 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, xregs
[i
]),
100 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
104 static inline int get_a64_user_mem_index(DisasContext
*s
)
106 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
107 * if EL1, access as if EL0; otherwise access at current EL
111 switch (s
->mmu_idx
) {
112 case ARMMMUIdx_S12NSE1
:
113 useridx
= ARMMMUIdx_S12NSE0
;
115 case ARMMMUIdx_S1SE1
:
116 useridx
= ARMMMUIdx_S1SE0
;
119 g_assert_not_reached();
121 useridx
= s
->mmu_idx
;
124 return arm_to_core_mmu_idx(useridx
);
127 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
128 fprintf_function cpu_fprintf
, int flags
)
130 ARMCPU
*cpu
= ARM_CPU(cs
);
131 CPUARMState
*env
= &cpu
->env
;
132 uint32_t psr
= pstate_read(env
);
134 int el
= arm_current_el(env
);
135 const char *ns_status
;
137 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
138 env
->pc
, env
->xregs
[31]);
139 for (i
= 0; i
< 31; i
++) {
140 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
142 cpu_fprintf(f
, "\n");
148 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
149 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
154 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
156 psr
& PSTATE_N
? 'N' : '-',
157 psr
& PSTATE_Z
? 'Z' : '-',
158 psr
& PSTATE_C
? 'C' : '-',
159 psr
& PSTATE_V
? 'V' : '-',
162 psr
& PSTATE_SP
? 'h' : 't');
164 if (flags
& CPU_DUMP_FPU
) {
166 for (i
= 0; i
< numvfpregs
; i
+= 2) {
167 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
168 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
169 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
171 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
172 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
173 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
176 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
177 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
181 void gen_a64_set_pc_im(uint64_t val
)
183 tcg_gen_movi_i64(cpu_pc
, val
);
186 /* Load the PC from a generic TCG variable.
188 * If address tagging is enabled via the TCR TBI bits, then loading
189 * an address into the PC will clear out any tag in the it:
190 * + for EL2 and EL3 there is only one TBI bit, and if it is set
191 * then the address is zero-extended, clearing bits [63:56]
192 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
193 * and TBI1 controls addressses with bit 55 == 1.
194 * If the appropriate TBI bit is set for the address then
195 * the address is sign-extended from bit 55 into bits [63:56]
197 * We can avoid doing this for relative-branches, because the
198 * PC + offset can never overflow into the tag bits (assuming
199 * that virtual addresses are less than 56 bits wide, as they
200 * are currently), but we must handle it for branch-to-register.
202 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
205 if (s
->current_el
<= 1) {
206 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
207 * examine bit 55 of address, can just generate code.
208 * If mixed, then test via generated code
210 if (s
->tbi0
&& s
->tbi1
) {
211 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
212 /* Both bits set, sign extension from bit 55 into [63:56] will
215 tcg_gen_shli_i64(tmp_reg
, src
, 8);
216 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
217 tcg_temp_free_i64(tmp_reg
);
218 } else if (!s
->tbi0
&& !s
->tbi1
) {
219 /* Neither bit set, just load it as-is */
220 tcg_gen_mov_i64(cpu_pc
, src
);
222 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
223 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
224 TCGv_i64 tcg_zero
= tcg_const_i64(0);
226 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
229 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
230 tcg_gen_andi_i64(tcg_tmpval
, src
,
231 0x00FFFFFFFFFFFFFFull
);
232 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
235 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
236 tcg_gen_ori_i64(tcg_tmpval
, src
,
237 0xFF00000000000000ull
);
238 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
241 tcg_temp_free_i64(tcg_zero
);
242 tcg_temp_free_i64(tcg_bit55
);
243 tcg_temp_free_i64(tcg_tmpval
);
245 } else { /* EL > 1 */
247 /* Force tag byte to all zero */
248 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
250 /* Load unmodified address */
251 tcg_gen_mov_i64(cpu_pc
, src
);
256 typedef struct DisasCompare64
{
261 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
265 arm_test_cc(&c32
, cc
);
267 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
268 * properly. The NE/EQ comparisons are also fine with this choice. */
269 c64
->cond
= c32
.cond
;
270 c64
->value
= tcg_temp_new_i64();
271 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
276 static void a64_free_cc(DisasCompare64
*c64
)
278 tcg_temp_free_i64(c64
->value
);
281 static void gen_exception_internal(int excp
)
283 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
285 assert(excp_is_internal(excp
));
286 gen_helper_exception_internal(cpu_env
, tcg_excp
);
287 tcg_temp_free_i32(tcg_excp
);
290 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
292 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
293 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
294 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
296 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
298 tcg_temp_free_i32(tcg_el
);
299 tcg_temp_free_i32(tcg_syn
);
300 tcg_temp_free_i32(tcg_excp
);
303 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
305 gen_a64_set_pc_im(s
->pc
- offset
);
306 gen_exception_internal(excp
);
307 s
->base
.is_jmp
= DISAS_NORETURN
;
310 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
311 uint32_t syndrome
, uint32_t target_el
)
313 gen_a64_set_pc_im(s
->pc
- offset
);
314 gen_exception(excp
, syndrome
, target_el
);
315 s
->base
.is_jmp
= DISAS_NORETURN
;
318 static void gen_ss_advance(DisasContext
*s
)
320 /* If the singlestep state is Active-not-pending, advance to
325 gen_helper_clear_pstate_ss(cpu_env
);
329 static void gen_step_complete_exception(DisasContext
*s
)
331 /* We just completed step of an insn. Move from Active-not-pending
332 * to Active-pending, and then also take the swstep exception.
333 * This corresponds to making the (IMPDEF) choice to prioritize
334 * swstep exceptions over asynchronous exceptions taken to an exception
335 * level where debug is disabled. This choice has the advantage that
336 * we do not need to maintain internal state corresponding to the
337 * ISV/EX syndrome bits between completion of the step and generation
338 * of the exception, and our syndrome information is always correct.
341 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
342 default_exception_el(s
));
343 s
->base
.is_jmp
= DISAS_NORETURN
;
346 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
348 /* No direct tb linking with singlestep (either QEMU's or the ARM
349 * debug architecture kind) or deterministic io
351 if (s
->base
.singlestep_enabled
|| s
->ss_active
|| (s
->base
.tb
->cflags
& CF_LAST_IO
)) {
355 #ifndef CONFIG_USER_ONLY
356 /* Only link tbs from inside the same guest page */
357 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
365 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
367 TranslationBlock
*tb
;
370 if (use_goto_tb(s
, n
, dest
)) {
372 gen_a64_set_pc_im(dest
);
373 tcg_gen_exit_tb((intptr_t)tb
+ n
);
374 s
->base
.is_jmp
= DISAS_NORETURN
;
376 gen_a64_set_pc_im(dest
);
378 gen_step_complete_exception(s
);
379 } else if (s
->base
.singlestep_enabled
) {
380 gen_exception_internal(EXCP_DEBUG
);
382 tcg_gen_lookup_and_goto_ptr(cpu_pc
);
383 s
->base
.is_jmp
= DISAS_NORETURN
;
388 static void unallocated_encoding(DisasContext
*s
)
390 /* Unallocated and reserved encodings are uncategorized */
391 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
392 default_exception_el(s
));
395 #define unsupported_encoding(s, insn) \
397 qemu_log_mask(LOG_UNIMP, \
398 "%s:%d: unsupported instruction encoding 0x%08x " \
399 "at pc=%016" PRIx64 "\n", \
400 __FILE__, __LINE__, insn, s->pc - 4); \
401 unallocated_encoding(s); \
404 static void init_tmp_a64_array(DisasContext
*s
)
406 #ifdef CONFIG_DEBUG_TCG
408 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
409 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
412 s
->tmp_a64_count
= 0;
415 static void free_tmp_a64(DisasContext
*s
)
418 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
419 tcg_temp_free_i64(s
->tmp_a64
[i
]);
421 init_tmp_a64_array(s
);
424 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
426 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
427 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
430 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
432 TCGv_i64 t
= new_tmp_a64(s
);
433 tcg_gen_movi_i64(t
, 0);
438 * Register access functions
440 * These functions are used for directly accessing a register in where
441 * changes to the final register value are likely to be made. If you
442 * need to use a register for temporary calculation (e.g. index type
443 * operations) use the read_* form.
445 * B1.2.1 Register mappings
447 * In instruction register encoding 31 can refer to ZR (zero register) or
448 * the SP (stack pointer) depending on context. In QEMU's case we map SP
449 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
450 * This is the point of the _sp forms.
452 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
455 return new_tmp_a64_zero(s
);
461 /* register access for when 31 == SP */
462 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
467 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
468 * representing the register contents. This TCGv is an auto-freed
469 * temporary so it need not be explicitly freed, and may be modified.
471 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
473 TCGv_i64 v
= new_tmp_a64(s
);
476 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
478 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
481 tcg_gen_movi_i64(v
, 0);
486 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
488 TCGv_i64 v
= new_tmp_a64(s
);
490 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
492 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
497 /* We should have at some point before trying to access an FP register
498 * done the necessary access check, so assert that
499 * (a) we did the check and
500 * (b) we didn't then just plough ahead anyway if it failed.
501 * Print the instruction pattern in the abort message so we can figure
502 * out what we need to fix if a user encounters this problem in the wild.
504 static inline void assert_fp_access_checked(DisasContext
*s
)
506 #ifdef CONFIG_DEBUG_TCG
507 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
508 fprintf(stderr
, "target-arm: FP access check missing for "
509 "instruction 0x%08x\n", s
->insn
);
515 /* Return the offset into CPUARMState of an element of specified
516 * size, 'element' places in from the least significant end of
517 * the FP/vector register Qn.
519 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
520 int element
, TCGMemOp size
)
523 #ifdef HOST_WORDS_BIGENDIAN
524 /* This is complicated slightly because vfp.regs[2n] is
525 * still the low half and vfp.regs[2n+1] the high half
526 * of the 128 bit vector, even on big endian systems.
527 * Calculate the offset assuming a fully bigendian 128 bits,
528 * then XOR to account for the order of the two 64 bit halves.
530 offs
+= (16 - ((element
+ 1) * (1 << size
)));
533 offs
+= element
* (1 << size
);
535 offs
+= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
536 assert_fp_access_checked(s
);
540 /* Return the offset into CPUARMState of a slice (from
541 * the least significant end) of FP register Qn (ie
543 * (Note that this is not the same mapping as for A32; see cpu.h)
545 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
547 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
548 #ifdef HOST_WORDS_BIGENDIAN
549 offs
+= (8 - (1 << size
));
551 assert_fp_access_checked(s
);
555 /* Offset of the high half of the 128 bit vector Qn */
556 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
558 assert_fp_access_checked(s
);
559 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
562 /* Convenience accessors for reading and writing single and double
563 * FP registers. Writing clears the upper parts of the associated
564 * 128 bit vector register, as required by the architecture.
565 * Note that unlike the GP register accessors, the values returned
566 * by the read functions must be manually freed.
568 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
570 TCGv_i64 v
= tcg_temp_new_i64();
572 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
576 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
578 TCGv_i32 v
= tcg_temp_new_i32();
580 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
584 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
586 TCGv_i64 tcg_zero
= tcg_const_i64(0);
588 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
589 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
590 tcg_temp_free_i64(tcg_zero
);
593 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
595 TCGv_i64 tmp
= tcg_temp_new_i64();
597 tcg_gen_extu_i32_i64(tmp
, v
);
598 write_fp_dreg(s
, reg
, tmp
);
599 tcg_temp_free_i64(tmp
);
602 static TCGv_ptr
get_fpstatus_ptr(void)
604 TCGv_ptr statusptr
= tcg_temp_new_ptr();
607 /* In A64 all instructions (both FP and Neon) use the FPCR;
608 * there is no equivalent of the A32 Neon "standard FPSCR value"
609 * and all operations use vfp.fp_status.
611 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
612 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
616 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
617 * than the 32 bit equivalent.
619 static inline void gen_set_NZ64(TCGv_i64 result
)
621 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
622 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
625 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
626 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
629 gen_set_NZ64(result
);
631 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
632 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
634 tcg_gen_movi_i32(cpu_CF
, 0);
635 tcg_gen_movi_i32(cpu_VF
, 0);
638 /* dest = T0 + T1; compute C, N, V and Z flags */
639 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
642 TCGv_i64 result
, flag
, tmp
;
643 result
= tcg_temp_new_i64();
644 flag
= tcg_temp_new_i64();
645 tmp
= tcg_temp_new_i64();
647 tcg_gen_movi_i64(tmp
, 0);
648 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
650 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
652 gen_set_NZ64(result
);
654 tcg_gen_xor_i64(flag
, result
, t0
);
655 tcg_gen_xor_i64(tmp
, t0
, t1
);
656 tcg_gen_andc_i64(flag
, flag
, tmp
);
657 tcg_temp_free_i64(tmp
);
658 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
660 tcg_gen_mov_i64(dest
, result
);
661 tcg_temp_free_i64(result
);
662 tcg_temp_free_i64(flag
);
664 /* 32 bit arithmetic */
665 TCGv_i32 t0_32
= tcg_temp_new_i32();
666 TCGv_i32 t1_32
= tcg_temp_new_i32();
667 TCGv_i32 tmp
= tcg_temp_new_i32();
669 tcg_gen_movi_i32(tmp
, 0);
670 tcg_gen_extrl_i64_i32(t0_32
, t0
);
671 tcg_gen_extrl_i64_i32(t1_32
, t1
);
672 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
673 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
674 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
675 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
676 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
677 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
679 tcg_temp_free_i32(tmp
);
680 tcg_temp_free_i32(t0_32
);
681 tcg_temp_free_i32(t1_32
);
685 /* dest = T0 - T1; compute C, N, V and Z flags */
686 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
689 /* 64 bit arithmetic */
690 TCGv_i64 result
, flag
, tmp
;
692 result
= tcg_temp_new_i64();
693 flag
= tcg_temp_new_i64();
694 tcg_gen_sub_i64(result
, t0
, t1
);
696 gen_set_NZ64(result
);
698 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
699 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
701 tcg_gen_xor_i64(flag
, result
, t0
);
702 tmp
= tcg_temp_new_i64();
703 tcg_gen_xor_i64(tmp
, t0
, t1
);
704 tcg_gen_and_i64(flag
, flag
, tmp
);
705 tcg_temp_free_i64(tmp
);
706 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
707 tcg_gen_mov_i64(dest
, result
);
708 tcg_temp_free_i64(flag
);
709 tcg_temp_free_i64(result
);
711 /* 32 bit arithmetic */
712 TCGv_i32 t0_32
= tcg_temp_new_i32();
713 TCGv_i32 t1_32
= tcg_temp_new_i32();
716 tcg_gen_extrl_i64_i32(t0_32
, t0
);
717 tcg_gen_extrl_i64_i32(t1_32
, t1
);
718 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
719 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
720 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
721 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
722 tmp
= tcg_temp_new_i32();
723 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
724 tcg_temp_free_i32(t0_32
);
725 tcg_temp_free_i32(t1_32
);
726 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
727 tcg_temp_free_i32(tmp
);
728 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
732 /* dest = T0 + T1 + CF; do not compute flags. */
733 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
735 TCGv_i64 flag
= tcg_temp_new_i64();
736 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
737 tcg_gen_add_i64(dest
, t0
, t1
);
738 tcg_gen_add_i64(dest
, dest
, flag
);
739 tcg_temp_free_i64(flag
);
742 tcg_gen_ext32u_i64(dest
, dest
);
746 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
747 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
750 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
751 result
= tcg_temp_new_i64();
752 cf_64
= tcg_temp_new_i64();
753 vf_64
= tcg_temp_new_i64();
754 tmp
= tcg_const_i64(0);
756 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
757 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
758 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
759 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
760 gen_set_NZ64(result
);
762 tcg_gen_xor_i64(vf_64
, result
, t0
);
763 tcg_gen_xor_i64(tmp
, t0
, t1
);
764 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
765 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
767 tcg_gen_mov_i64(dest
, result
);
769 tcg_temp_free_i64(tmp
);
770 tcg_temp_free_i64(vf_64
);
771 tcg_temp_free_i64(cf_64
);
772 tcg_temp_free_i64(result
);
774 TCGv_i32 t0_32
, t1_32
, tmp
;
775 t0_32
= tcg_temp_new_i32();
776 t1_32
= tcg_temp_new_i32();
777 tmp
= tcg_const_i32(0);
779 tcg_gen_extrl_i64_i32(t0_32
, t0
);
780 tcg_gen_extrl_i64_i32(t1_32
, t1
);
781 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
782 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
784 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
785 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
786 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
787 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
788 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
790 tcg_temp_free_i32(tmp
);
791 tcg_temp_free_i32(t1_32
);
792 tcg_temp_free_i32(t0_32
);
797 * Load/Store generators
801 * Store from GPR register to memory.
803 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
804 TCGv_i64 tcg_addr
, int size
, int memidx
,
806 unsigned int iss_srt
,
807 bool iss_sf
, bool iss_ar
)
810 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
815 syn
= syn_data_abort_with_iss(0,
821 0, 0, 0, 0, 0, false);
822 disas_set_insn_syndrome(s
, syn
);
826 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
827 TCGv_i64 tcg_addr
, int size
,
829 unsigned int iss_srt
,
830 bool iss_sf
, bool iss_ar
)
832 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
833 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
837 * Load from memory to GPR register
839 static void do_gpr_ld_memidx(DisasContext
*s
,
840 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
841 int size
, bool is_signed
,
842 bool extend
, int memidx
,
843 bool iss_valid
, unsigned int iss_srt
,
844 bool iss_sf
, bool iss_ar
)
846 TCGMemOp memop
= s
->be_data
+ size
;
854 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
856 if (extend
&& is_signed
) {
858 tcg_gen_ext32u_i64(dest
, dest
);
864 syn
= syn_data_abort_with_iss(0,
870 0, 0, 0, 0, 0, false);
871 disas_set_insn_syndrome(s
, syn
);
875 static void do_gpr_ld(DisasContext
*s
,
876 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
877 int size
, bool is_signed
, bool extend
,
878 bool iss_valid
, unsigned int iss_srt
,
879 bool iss_sf
, bool iss_ar
)
881 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
883 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
887 * Store from FP register to memory
889 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
891 /* This writes the bottom N bits of a 128 bit wide vector to memory */
892 TCGv_i64 tmp
= tcg_temp_new_i64();
893 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
895 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
898 bool be
= s
->be_data
== MO_BE
;
899 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
901 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
902 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
904 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
905 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
907 tcg_temp_free_i64(tcg_hiaddr
);
910 tcg_temp_free_i64(tmp
);
914 * Load from memory to FP register
916 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
918 /* This always zero-extends and writes to a full 128 bit wide vector */
919 TCGv_i64 tmplo
= tcg_temp_new_i64();
923 TCGMemOp memop
= s
->be_data
+ size
;
924 tmphi
= tcg_const_i64(0);
925 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
927 bool be
= s
->be_data
== MO_BE
;
930 tmphi
= tcg_temp_new_i64();
931 tcg_hiaddr
= tcg_temp_new_i64();
933 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
934 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
936 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
938 tcg_temp_free_i64(tcg_hiaddr
);
941 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
942 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
944 tcg_temp_free_i64(tmplo
);
945 tcg_temp_free_i64(tmphi
);
949 * Vector load/store helpers.
951 * The principal difference between this and a FP load is that we don't
952 * zero extend as we are filling a partial chunk of the vector register.
953 * These functions don't support 128 bit loads/stores, which would be
954 * normal load/store operations.
956 * The _i32 versions are useful when operating on 32 bit quantities
957 * (eg for floating point single or using Neon helper functions).
960 /* Get value of an element within a vector register */
961 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
962 int element
, TCGMemOp memop
)
964 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
967 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
970 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
973 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
976 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
979 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
982 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
986 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
989 g_assert_not_reached();
993 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
994 int element
, TCGMemOp memop
)
996 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
999 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1002 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1005 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1008 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1012 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1015 g_assert_not_reached();
1019 /* Set value of an element within a vector register */
1020 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1021 int element
, TCGMemOp memop
)
1023 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1026 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1029 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1032 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1035 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1038 g_assert_not_reached();
1042 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1043 int destidx
, int element
, TCGMemOp memop
)
1045 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1048 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1051 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1054 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1057 g_assert_not_reached();
1061 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
1062 * vector ops all need to do this).
1064 static void clear_vec_high(DisasContext
*s
, int rd
)
1066 TCGv_i64 tcg_zero
= tcg_const_i64(0);
1068 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
1069 tcg_temp_free_i64(tcg_zero
);
1072 /* Store from vector register to memory */
1073 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1074 TCGv_i64 tcg_addr
, int size
)
1076 TCGMemOp memop
= s
->be_data
+ size
;
1077 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1079 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1080 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1082 tcg_temp_free_i64(tcg_tmp
);
1085 /* Load from memory to vector register */
1086 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1087 TCGv_i64 tcg_addr
, int size
)
1089 TCGMemOp memop
= s
->be_data
+ size
;
1090 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1092 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1093 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1095 tcg_temp_free_i64(tcg_tmp
);
1098 /* Check that FP/Neon access is enabled. If it is, return
1099 * true. If not, emit code to generate an appropriate exception,
1100 * and return false; the caller should not emit any code for
1101 * the instruction. Note that this check must happen after all
1102 * unallocated-encoding checks (otherwise the syndrome information
1103 * for the resulting exception will be incorrect).
1105 static inline bool fp_access_check(DisasContext
*s
)
1107 assert(!s
->fp_access_checked
);
1108 s
->fp_access_checked
= true;
1110 if (!s
->fp_excp_el
) {
1114 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1120 * This utility function is for doing register extension with an
1121 * optional shift. You will likely want to pass a temporary for the
1122 * destination register. See DecodeRegExtend() in the ARM ARM.
1124 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1125 int option
, unsigned int shift
)
1127 int extsize
= extract32(option
, 0, 2);
1128 bool is_signed
= extract32(option
, 2, 1);
1133 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1136 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1139 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1142 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1148 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1151 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1154 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1157 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1163 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1167 static inline void gen_check_sp_alignment(DisasContext
*s
)
1169 /* The AArch64 architecture mandates that (if enabled via PSTATE
1170 * or SCTLR bits) there is a check that SP is 16-aligned on every
1171 * SP-relative load or store (with an exception generated if it is not).
1172 * In line with general QEMU practice regarding misaligned accesses,
1173 * we omit these checks for the sake of guest program performance.
1174 * This function is provided as a hook so we can more easily add these
1175 * checks in future (possibly as a "favour catching guest program bugs
1176 * over speed" user selectable option).
1181 * This provides a simple table based table lookup decoder. It is
1182 * intended to be used when the relevant bits for decode are too
1183 * awkwardly placed and switch/if based logic would be confusing and
1184 * deeply nested. Since it's a linear search through the table, tables
1185 * should be kept small.
1187 * It returns the first handler where insn & mask == pattern, or
1188 * NULL if there is no match.
1189 * The table is terminated by an empty mask (i.e. 0)
1191 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1194 const AArch64DecodeTable
*tptr
= table
;
1196 while (tptr
->mask
) {
1197 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1198 return tptr
->disas_fn
;
1206 * The instruction disassembly implemented here matches
1207 * the instruction encoding classifications in chapter C4
1208 * of the ARM Architecture Reference Manual (DDI0487B_a);
1209 * classification names and decode diagrams here should generally
1210 * match up with those in the manual.
1213 /* Unconditional branch (immediate)
1215 * +----+-----------+-------------------------------------+
1216 * | op | 0 0 1 0 1 | imm26 |
1217 * +----+-----------+-------------------------------------+
1219 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1221 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1223 if (insn
& (1U << 31)) {
1224 /* BL Branch with link */
1225 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1228 /* B Branch / BL Branch with link */
1229 gen_goto_tb(s
, 0, addr
);
1232 /* Compare and branch (immediate)
1233 * 31 30 25 24 23 5 4 0
1234 * +----+-------------+----+---------------------+--------+
1235 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1236 * +----+-------------+----+---------------------+--------+
1238 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1240 unsigned int sf
, op
, rt
;
1242 TCGLabel
*label_match
;
1245 sf
= extract32(insn
, 31, 1);
1246 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1247 rt
= extract32(insn
, 0, 5);
1248 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1250 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1251 label_match
= gen_new_label();
1253 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1254 tcg_cmp
, 0, label_match
);
1256 gen_goto_tb(s
, 0, s
->pc
);
1257 gen_set_label(label_match
);
1258 gen_goto_tb(s
, 1, addr
);
1261 /* Test and branch (immediate)
1262 * 31 30 25 24 23 19 18 5 4 0
1263 * +----+-------------+----+-------+-------------+------+
1264 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1265 * +----+-------------+----+-------+-------------+------+
1267 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1269 unsigned int bit_pos
, op
, rt
;
1271 TCGLabel
*label_match
;
1274 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1275 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1276 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1277 rt
= extract32(insn
, 0, 5);
1279 tcg_cmp
= tcg_temp_new_i64();
1280 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1281 label_match
= gen_new_label();
1282 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1283 tcg_cmp
, 0, label_match
);
1284 tcg_temp_free_i64(tcg_cmp
);
1285 gen_goto_tb(s
, 0, s
->pc
);
1286 gen_set_label(label_match
);
1287 gen_goto_tb(s
, 1, addr
);
1290 /* Conditional branch (immediate)
1291 * 31 25 24 23 5 4 3 0
1292 * +---------------+----+---------------------+----+------+
1293 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1294 * +---------------+----+---------------------+----+------+
1296 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1301 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1302 unallocated_encoding(s
);
1305 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1306 cond
= extract32(insn
, 0, 4);
1309 /* genuinely conditional branches */
1310 TCGLabel
*label_match
= gen_new_label();
1311 arm_gen_test_cc(cond
, label_match
);
1312 gen_goto_tb(s
, 0, s
->pc
);
1313 gen_set_label(label_match
);
1314 gen_goto_tb(s
, 1, addr
);
1316 /* 0xe and 0xf are both "always" conditions */
1317 gen_goto_tb(s
, 0, addr
);
1321 /* HINT instruction group, including various allocated HINTs */
1322 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1323 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1325 unsigned int selector
= crm
<< 3 | op2
;
1328 unallocated_encoding(s
);
1336 s
->base
.is_jmp
= DISAS_WFI
;
1339 if (!parallel_cpus
) {
1340 s
->base
.is_jmp
= DISAS_YIELD
;
1344 if (!parallel_cpus
) {
1345 s
->base
.is_jmp
= DISAS_WFE
;
1350 /* we treat all as NOP at least for now */
1353 /* default specified as NOP equivalent */
1358 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1360 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1363 /* CLREX, DSB, DMB, ISB */
1364 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1365 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1370 unallocated_encoding(s
);
1381 case 1: /* MBReqTypes_Reads */
1382 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1384 case 2: /* MBReqTypes_Writes */
1385 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1387 default: /* MBReqTypes_All */
1388 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1394 /* We need to break the TB after this insn to execute
1395 * a self-modified code correctly and also to take
1396 * any pending interrupts immediately.
1398 gen_goto_tb(s
, 0, s
->pc
);
1401 unallocated_encoding(s
);
1406 /* MSR (immediate) - move immediate to processor state field */
1407 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1408 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1410 int op
= op1
<< 3 | op2
;
1412 case 0x05: /* SPSel */
1413 if (s
->current_el
== 0) {
1414 unallocated_encoding(s
);
1418 case 0x1e: /* DAIFSet */
1419 case 0x1f: /* DAIFClear */
1421 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1422 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1423 gen_a64_set_pc_im(s
->pc
- 4);
1424 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1425 tcg_temp_free_i32(tcg_imm
);
1426 tcg_temp_free_i32(tcg_op
);
1427 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1428 gen_a64_set_pc_im(s
->pc
);
1429 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1433 unallocated_encoding(s
);
1438 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1440 TCGv_i32 tmp
= tcg_temp_new_i32();
1441 TCGv_i32 nzcv
= tcg_temp_new_i32();
1443 /* build bit 31, N */
1444 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1445 /* build bit 30, Z */
1446 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1447 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1448 /* build bit 29, C */
1449 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1450 /* build bit 28, V */
1451 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1452 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1453 /* generate result */
1454 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1456 tcg_temp_free_i32(nzcv
);
1457 tcg_temp_free_i32(tmp
);
1460 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1463 TCGv_i32 nzcv
= tcg_temp_new_i32();
1465 /* take NZCV from R[t] */
1466 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1469 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1471 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1472 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1474 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1475 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1477 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1478 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1479 tcg_temp_free_i32(nzcv
);
1482 /* MRS - move from system register
1483 * MSR (register) - move to system register
1486 * These are all essentially the same insn in 'read' and 'write'
1487 * versions, with varying op0 fields.
1489 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1490 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1491 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1493 const ARMCPRegInfo
*ri
;
1496 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1497 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1498 crn
, crm
, op0
, op1
, op2
));
1501 /* Unknown register; this might be a guest error or a QEMU
1502 * unimplemented feature.
1504 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1505 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1506 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1507 unallocated_encoding(s
);
1511 /* Check access permissions */
1512 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1513 unallocated_encoding(s
);
1518 /* Emit code to perform further access permissions checks at
1519 * runtime; this may result in an exception.
1522 TCGv_i32 tcg_syn
, tcg_isread
;
1525 gen_a64_set_pc_im(s
->pc
- 4);
1526 tmpptr
= tcg_const_ptr(ri
);
1527 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1528 tcg_syn
= tcg_const_i32(syndrome
);
1529 tcg_isread
= tcg_const_i32(isread
);
1530 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1531 tcg_temp_free_ptr(tmpptr
);
1532 tcg_temp_free_i32(tcg_syn
);
1533 tcg_temp_free_i32(tcg_isread
);
1536 /* Handle special cases first */
1537 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1541 tcg_rt
= cpu_reg(s
, rt
);
1543 gen_get_nzcv(tcg_rt
);
1545 gen_set_nzcv(tcg_rt
);
1548 case ARM_CP_CURRENTEL
:
1549 /* Reads as current EL value from pstate, which is
1550 * guaranteed to be constant by the tb flags.
1552 tcg_rt
= cpu_reg(s
, rt
);
1553 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1556 /* Writes clear the aligned block of memory which rt points into. */
1557 tcg_rt
= cpu_reg(s
, rt
);
1558 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1564 if ((s
->base
.tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1568 tcg_rt
= cpu_reg(s
, rt
);
1571 if (ri
->type
& ARM_CP_CONST
) {
1572 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1573 } else if (ri
->readfn
) {
1575 tmpptr
= tcg_const_ptr(ri
);
1576 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1577 tcg_temp_free_ptr(tmpptr
);
1579 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1582 if (ri
->type
& ARM_CP_CONST
) {
1583 /* If not forbidden by access permissions, treat as WI */
1585 } else if (ri
->writefn
) {
1587 tmpptr
= tcg_const_ptr(ri
);
1588 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1589 tcg_temp_free_ptr(tmpptr
);
1591 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1595 if ((s
->base
.tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1596 /* I/O operations must end the TB here (whether read or write) */
1598 s
->base
.is_jmp
= DISAS_UPDATE
;
1599 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1600 /* We default to ending the TB on a coprocessor register write,
1601 * but allow this to be suppressed by the register definition
1602 * (usually only necessary to work around guest bugs).
1604 s
->base
.is_jmp
= DISAS_UPDATE
;
1609 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1610 * +---------------------+---+-----+-----+-------+-------+-----+------+
1611 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1612 * +---------------------+---+-----+-----+-------+-------+-----+------+
1614 static void disas_system(DisasContext
*s
, uint32_t insn
)
1616 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1617 l
= extract32(insn
, 21, 1);
1618 op0
= extract32(insn
, 19, 2);
1619 op1
= extract32(insn
, 16, 3);
1620 crn
= extract32(insn
, 12, 4);
1621 crm
= extract32(insn
, 8, 4);
1622 op2
= extract32(insn
, 5, 3);
1623 rt
= extract32(insn
, 0, 5);
1626 if (l
|| rt
!= 31) {
1627 unallocated_encoding(s
);
1631 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1632 handle_hint(s
, insn
, op1
, op2
, crm
);
1634 case 3: /* CLREX, DSB, DMB, ISB */
1635 handle_sync(s
, insn
, op1
, op2
, crm
);
1637 case 4: /* MSR (immediate) */
1638 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1641 unallocated_encoding(s
);
1646 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1649 /* Exception generation
1651 * 31 24 23 21 20 5 4 2 1 0
1652 * +-----------------+-----+------------------------+-----+----+
1653 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1654 * +-----------------------+------------------------+----------+
1656 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1658 int opc
= extract32(insn
, 21, 3);
1659 int op2_ll
= extract32(insn
, 0, 5);
1660 int imm16
= extract32(insn
, 5, 16);
1665 /* For SVC, HVC and SMC we advance the single-step state
1666 * machine before taking the exception. This is architecturally
1667 * mandated, to ensure that single-stepping a system call
1668 * instruction works properly.
1673 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1674 default_exception_el(s
));
1677 if (s
->current_el
== 0) {
1678 unallocated_encoding(s
);
1681 /* The pre HVC helper handles cases when HVC gets trapped
1682 * as an undefined insn by runtime configuration.
1684 gen_a64_set_pc_im(s
->pc
- 4);
1685 gen_helper_pre_hvc(cpu_env
);
1687 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1690 if (s
->current_el
== 0) {
1691 unallocated_encoding(s
);
1694 gen_a64_set_pc_im(s
->pc
- 4);
1695 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1696 gen_helper_pre_smc(cpu_env
, tmp
);
1697 tcg_temp_free_i32(tmp
);
1699 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1702 unallocated_encoding(s
);
1708 unallocated_encoding(s
);
1712 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1713 default_exception_el(s
));
1717 unallocated_encoding(s
);
1720 /* HLT. This has two purposes.
1721 * Architecturally, it is an external halting debug instruction.
1722 * Since QEMU doesn't implement external debug, we treat this as
1723 * it is required for halting debug disabled: it will UNDEF.
1724 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1726 if (semihosting_enabled() && imm16
== 0xf000) {
1727 #ifndef CONFIG_USER_ONLY
1728 /* In system mode, don't allow userspace access to semihosting,
1729 * to provide some semblance of security (and for consistency
1730 * with our 32-bit semihosting).
1732 if (s
->current_el
== 0) {
1733 unsupported_encoding(s
, insn
);
1737 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1739 unsupported_encoding(s
, insn
);
1743 if (op2_ll
< 1 || op2_ll
> 3) {
1744 unallocated_encoding(s
);
1747 /* DCPS1, DCPS2, DCPS3 */
1748 unsupported_encoding(s
, insn
);
1751 unallocated_encoding(s
);
1756 /* Unconditional branch (register)
1757 * 31 25 24 21 20 16 15 10 9 5 4 0
1758 * +---------------+-------+-------+-------+------+-------+
1759 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1760 * +---------------+-------+-------+-------+------+-------+
1762 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1764 unsigned int opc
, op2
, op3
, rn
, op4
;
1766 opc
= extract32(insn
, 21, 4);
1767 op2
= extract32(insn
, 16, 5);
1768 op3
= extract32(insn
, 10, 6);
1769 rn
= extract32(insn
, 5, 5);
1770 op4
= extract32(insn
, 0, 5);
1772 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1773 unallocated_encoding(s
);
1781 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1782 /* BLR also needs to load return address */
1784 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1788 if (s
->current_el
== 0) {
1789 unallocated_encoding(s
);
1792 gen_helper_exception_return(cpu_env
);
1793 /* Must exit loop to check un-masked IRQs */
1794 s
->base
.is_jmp
= DISAS_EXIT
;
1798 unallocated_encoding(s
);
1800 unsupported_encoding(s
, insn
);
1804 unallocated_encoding(s
);
1808 s
->base
.is_jmp
= DISAS_JUMP
;
1811 /* Branches, exception generating and system instructions */
1812 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1814 switch (extract32(insn
, 25, 7)) {
1815 case 0x0a: case 0x0b:
1816 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1817 disas_uncond_b_imm(s
, insn
);
1819 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1820 disas_comp_b_imm(s
, insn
);
1822 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1823 disas_test_b_imm(s
, insn
);
1825 case 0x2a: /* Conditional branch (immediate) */
1826 disas_cond_b_imm(s
, insn
);
1828 case 0x6a: /* Exception generation / System */
1829 if (insn
& (1 << 24)) {
1830 disas_system(s
, insn
);
1835 case 0x6b: /* Unconditional branch (register) */
1836 disas_uncond_b_reg(s
, insn
);
1839 unallocated_encoding(s
);
1845 * Load/Store exclusive instructions are implemented by remembering
1846 * the value/address loaded, and seeing if these are the same
1847 * when the store is performed. This is not actually the architecturally
1848 * mandated semantics, but it works for typical guest code sequences
1849 * and avoids having to monitor regular stores.
1851 * The store exclusive uses the atomic cmpxchg primitives to avoid
1852 * races in multi-threaded linux-user and when MTTCG softmmu is
1855 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1856 TCGv_i64 addr
, int size
, bool is_pair
)
1858 int idx
= get_mem_index(s
);
1859 TCGMemOp memop
= s
->be_data
;
1861 g_assert(size
<= 3);
1863 g_assert(size
>= 2);
1865 /* The pair must be single-copy atomic for the doubleword. */
1866 memop
|= MO_64
| MO_ALIGN
;
1867 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
1868 if (s
->be_data
== MO_LE
) {
1869 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
1870 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
1872 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
1873 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
1876 /* The pair must be single-copy atomic for *each* doubleword, not
1877 the entire quadword, however it must be quadword aligned. */
1879 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
1880 memop
| MO_ALIGN_16
);
1882 TCGv_i64 addr2
= tcg_temp_new_i64();
1883 tcg_gen_addi_i64(addr2
, addr
, 8);
1884 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
1885 tcg_temp_free_i64(addr2
);
1887 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
1888 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
1891 memop
|= size
| MO_ALIGN
;
1892 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
1893 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
1895 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1898 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1899 TCGv_i64 addr
, int size
, int is_pair
)
1901 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1902 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1905 * [addr + datasize] = {Rt2};
1911 * env->exclusive_addr = -1;
1913 TCGLabel
*fail_label
= gen_new_label();
1914 TCGLabel
*done_label
= gen_new_label();
1917 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1919 tmp
= tcg_temp_new_i64();
1922 if (s
->be_data
== MO_LE
) {
1923 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1925 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
1927 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
1928 cpu_exclusive_val
, tmp
,
1930 MO_64
| MO_ALIGN
| s
->be_data
);
1931 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1932 } else if (s
->be_data
== MO_LE
) {
1933 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
1934 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1936 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
1937 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1940 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
1941 cpu_reg(s
, rt
), get_mem_index(s
),
1942 size
| MO_ALIGN
| s
->be_data
);
1943 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1945 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
1946 tcg_temp_free_i64(tmp
);
1947 tcg_gen_br(done_label
);
1949 gen_set_label(fail_label
);
1950 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1951 gen_set_label(done_label
);
1952 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1955 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
1956 * from the ARMv8 specs for LDR (Shared decode for all encodings).
1958 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
1960 int opc0
= extract32(opc
, 0, 1);
1964 regsize
= opc0
? 32 : 64;
1966 regsize
= size
== 3 ? 64 : 32;
1968 return regsize
== 64;
1971 /* Load/store exclusive
1973 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1974 * +-----+-------------+----+---+----+------+----+-------+------+------+
1975 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1976 * +-----+-------------+----+---+----+------+----+-------+------+------+
1978 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1979 * L: 0 -> store, 1 -> load
1980 * o2: 0 -> exclusive, 1 -> not
1981 * o1: 0 -> single register, 1 -> register pair
1982 * o0: 1 -> load-acquire/store-release, 0 -> not
1984 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1986 int rt
= extract32(insn
, 0, 5);
1987 int rn
= extract32(insn
, 5, 5);
1988 int rt2
= extract32(insn
, 10, 5);
1989 int is_lasr
= extract32(insn
, 15, 1);
1990 int rs
= extract32(insn
, 16, 5);
1991 int is_pair
= extract32(insn
, 21, 1);
1992 int is_store
= !extract32(insn
, 22, 1);
1993 int is_excl
= !extract32(insn
, 23, 1);
1994 int size
= extract32(insn
, 30, 2);
1997 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
1998 (!is_excl
&& is_pair
) ||
1999 (is_pair
&& size
< 2)) {
2000 unallocated_encoding(s
);
2005 gen_check_sp_alignment(s
);
2007 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2009 /* Note that since TCG is single threaded load-acquire/store-release
2010 * semantics require no extra if (is_lasr) { ... } handling.
2016 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2018 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2022 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2024 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2027 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2028 bool iss_sf
= disas_ldst_compute_iss_sf(size
, false, 0);
2030 /* Generate ISS for non-exclusive accesses including LASR. */
2033 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2035 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2036 true, rt
, iss_sf
, is_lasr
);
2038 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false,
2039 true, rt
, iss_sf
, is_lasr
);
2041 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2048 * Load register (literal)
2050 * 31 30 29 27 26 25 24 23 5 4 0
2051 * +-----+-------+---+-----+-------------------+-------+
2052 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2053 * +-----+-------+---+-----+-------------------+-------+
2055 * V: 1 -> vector (simd/fp)
2056 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2057 * 10-> 32 bit signed, 11 -> prefetch
2058 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2060 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2062 int rt
= extract32(insn
, 0, 5);
2063 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2064 bool is_vector
= extract32(insn
, 26, 1);
2065 int opc
= extract32(insn
, 30, 2);
2066 bool is_signed
= false;
2068 TCGv_i64 tcg_rt
, tcg_addr
;
2072 unallocated_encoding(s
);
2076 if (!fp_access_check(s
)) {
2081 /* PRFM (literal) : prefetch */
2084 size
= 2 + extract32(opc
, 0, 1);
2085 is_signed
= extract32(opc
, 1, 1);
2088 tcg_rt
= cpu_reg(s
, rt
);
2090 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2092 do_fp_ld(s
, rt
, tcg_addr
, size
);
2094 /* Only unsigned 32bit loads target 32bit registers. */
2095 bool iss_sf
= opc
!= 0;
2097 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2098 true, rt
, iss_sf
, false);
2100 tcg_temp_free_i64(tcg_addr
);
2104 * LDNP (Load Pair - non-temporal hint)
2105 * LDP (Load Pair - non vector)
2106 * LDPSW (Load Pair Signed Word - non vector)
2107 * STNP (Store Pair - non-temporal hint)
2108 * STP (Store Pair - non vector)
2109 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2110 * LDP (Load Pair of SIMD&FP)
2111 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2112 * STP (Store Pair of SIMD&FP)
2114 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2115 * +-----+-------+---+---+-------+---+-----------------------------+
2116 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2117 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2119 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2121 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2122 * V: 0 -> GPR, 1 -> Vector
2123 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2124 * 10 -> signed offset, 11 -> pre-index
2125 * L: 0 -> Store 1 -> Load
2127 * Rt, Rt2 = GPR or SIMD registers to be stored
2128 * Rn = general purpose register containing address
2129 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2131 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2133 int rt
= extract32(insn
, 0, 5);
2134 int rn
= extract32(insn
, 5, 5);
2135 int rt2
= extract32(insn
, 10, 5);
2136 uint64_t offset
= sextract64(insn
, 15, 7);
2137 int index
= extract32(insn
, 23, 2);
2138 bool is_vector
= extract32(insn
, 26, 1);
2139 bool is_load
= extract32(insn
, 22, 1);
2140 int opc
= extract32(insn
, 30, 2);
2142 bool is_signed
= false;
2143 bool postindex
= false;
2146 TCGv_i64 tcg_addr
; /* calculated address */
2150 unallocated_encoding(s
);
2157 size
= 2 + extract32(opc
, 1, 1);
2158 is_signed
= extract32(opc
, 0, 1);
2159 if (!is_load
&& is_signed
) {
2160 unallocated_encoding(s
);
2166 case 1: /* post-index */
2171 /* signed offset with "non-temporal" hint. Since we don't emulate
2172 * caches we don't care about hints to the cache system about
2173 * data access patterns, and handle this identically to plain
2177 /* There is no non-temporal-hint version of LDPSW */
2178 unallocated_encoding(s
);
2183 case 2: /* signed offset, rn not updated */
2186 case 3: /* pre-index */
2192 if (is_vector
&& !fp_access_check(s
)) {
2199 gen_check_sp_alignment(s
);
2202 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2205 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2210 do_fp_ld(s
, rt
, tcg_addr
, size
);
2212 do_fp_st(s
, rt
, tcg_addr
, size
);
2214 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2216 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2218 do_fp_st(s
, rt2
, tcg_addr
, size
);
2221 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2222 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2225 TCGv_i64 tmp
= tcg_temp_new_i64();
2227 /* Do not modify tcg_rt before recognizing any exception
2228 * from the second load.
2230 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2231 false, 0, false, false);
2232 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2233 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2234 false, 0, false, false);
2236 tcg_gen_mov_i64(tcg_rt
, tmp
);
2237 tcg_temp_free_i64(tmp
);
2239 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2240 false, 0, false, false);
2241 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2242 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2243 false, 0, false, false);
2249 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2251 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2253 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2258 * Load/store (immediate post-indexed)
2259 * Load/store (immediate pre-indexed)
2260 * Load/store (unscaled immediate)
2262 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2263 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2264 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2265 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2267 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2269 * V = 0 -> non-vector
2270 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2271 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2273 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2279 int rn
= extract32(insn
, 5, 5);
2280 int imm9
= sextract32(insn
, 12, 9);
2281 int idx
= extract32(insn
, 10, 2);
2282 bool is_signed
= false;
2283 bool is_store
= false;
2284 bool is_extended
= false;
2285 bool is_unpriv
= (idx
== 2);
2286 bool iss_valid
= !is_vector
;
2293 size
|= (opc
& 2) << 1;
2294 if (size
> 4 || is_unpriv
) {
2295 unallocated_encoding(s
);
2298 is_store
= ((opc
& 1) == 0);
2299 if (!fp_access_check(s
)) {
2303 if (size
== 3 && opc
== 2) {
2304 /* PRFM - prefetch */
2306 unallocated_encoding(s
);
2311 if (opc
== 3 && size
> 1) {
2312 unallocated_encoding(s
);
2315 is_store
= (opc
== 0);
2316 is_signed
= extract32(opc
, 1, 1);
2317 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2337 gen_check_sp_alignment(s
);
2339 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2342 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2347 do_fp_st(s
, rt
, tcg_addr
, size
);
2349 do_fp_ld(s
, rt
, tcg_addr
, size
);
2352 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2353 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2354 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2357 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2358 iss_valid
, rt
, iss_sf
, false);
2360 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2361 is_signed
, is_extended
, memidx
,
2362 iss_valid
, rt
, iss_sf
, false);
2367 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2369 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2371 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2376 * Load/store (register offset)
2378 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2379 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2380 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2381 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2384 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2385 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2387 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2388 * opc<0>: 0 -> store, 1 -> load
2389 * V: 1 -> vector/simd
2390 * opt: extend encoding (see DecodeRegExtend)
2391 * S: if S=1 then scale (essentially index by sizeof(size))
2392 * Rt: register to transfer into/out of
2393 * Rn: address register or SP for base
2394 * Rm: offset register or ZR for offset
2396 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2402 int rn
= extract32(insn
, 5, 5);
2403 int shift
= extract32(insn
, 12, 1);
2404 int rm
= extract32(insn
, 16, 5);
2405 int opt
= extract32(insn
, 13, 3);
2406 bool is_signed
= false;
2407 bool is_store
= false;
2408 bool is_extended
= false;
2413 if (extract32(opt
, 1, 1) == 0) {
2414 unallocated_encoding(s
);
2419 size
|= (opc
& 2) << 1;
2421 unallocated_encoding(s
);
2424 is_store
= !extract32(opc
, 0, 1);
2425 if (!fp_access_check(s
)) {
2429 if (size
== 3 && opc
== 2) {
2430 /* PRFM - prefetch */
2433 if (opc
== 3 && size
> 1) {
2434 unallocated_encoding(s
);
2437 is_store
= (opc
== 0);
2438 is_signed
= extract32(opc
, 1, 1);
2439 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2443 gen_check_sp_alignment(s
);
2445 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2447 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2448 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2450 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2454 do_fp_st(s
, rt
, tcg_addr
, size
);
2456 do_fp_ld(s
, rt
, tcg_addr
, size
);
2459 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2460 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2462 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2463 true, rt
, iss_sf
, false);
2465 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2466 is_signed
, is_extended
,
2467 true, rt
, iss_sf
, false);
2473 * Load/store (unsigned immediate)
2475 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2476 * +----+-------+---+-----+-----+------------+-------+------+
2477 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2478 * +----+-------+---+-----+-----+------------+-------+------+
2481 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2482 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2484 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2485 * opc<0>: 0 -> store, 1 -> load
2486 * Rn: base address register (inc SP)
2487 * Rt: target register
2489 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2495 int rn
= extract32(insn
, 5, 5);
2496 unsigned int imm12
= extract32(insn
, 10, 12);
2497 unsigned int offset
;
2502 bool is_signed
= false;
2503 bool is_extended
= false;
2506 size
|= (opc
& 2) << 1;
2508 unallocated_encoding(s
);
2511 is_store
= !extract32(opc
, 0, 1);
2512 if (!fp_access_check(s
)) {
2516 if (size
== 3 && opc
== 2) {
2517 /* PRFM - prefetch */
2520 if (opc
== 3 && size
> 1) {
2521 unallocated_encoding(s
);
2524 is_store
= (opc
== 0);
2525 is_signed
= extract32(opc
, 1, 1);
2526 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2530 gen_check_sp_alignment(s
);
2532 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2533 offset
= imm12
<< size
;
2534 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2538 do_fp_st(s
, rt
, tcg_addr
, size
);
2540 do_fp_ld(s
, rt
, tcg_addr
, size
);
2543 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2544 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2546 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2547 true, rt
, iss_sf
, false);
2549 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2550 true, rt
, iss_sf
, false);
2555 /* Load/store register (all forms) */
2556 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2558 int rt
= extract32(insn
, 0, 5);
2559 int opc
= extract32(insn
, 22, 2);
2560 bool is_vector
= extract32(insn
, 26, 1);
2561 int size
= extract32(insn
, 30, 2);
2563 switch (extract32(insn
, 24, 2)) {
2565 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2566 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2568 /* Load/store register (unscaled immediate)
2569 * Load/store immediate pre/post-indexed
2570 * Load/store register unprivileged
2572 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2576 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2579 unallocated_encoding(s
);
2584 /* AdvSIMD load/store multiple structures
2586 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2587 * +---+---+---------------+---+-------------+--------+------+------+------+
2588 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2589 * +---+---+---------------+---+-------------+--------+------+------+------+
2591 * AdvSIMD load/store multiple structures (post-indexed)
2593 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2594 * +---+---+---------------+---+---+---------+--------+------+------+------+
2595 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2596 * +---+---+---------------+---+---+---------+--------+------+------+------+
2598 * Rt: first (or only) SIMD&FP register to be transferred
2599 * Rn: base address or SP
2600 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2602 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2604 int rt
= extract32(insn
, 0, 5);
2605 int rn
= extract32(insn
, 5, 5);
2606 int size
= extract32(insn
, 10, 2);
2607 int opcode
= extract32(insn
, 12, 4);
2608 bool is_store
= !extract32(insn
, 22, 1);
2609 bool is_postidx
= extract32(insn
, 23, 1);
2610 bool is_q
= extract32(insn
, 30, 1);
2611 TCGv_i64 tcg_addr
, tcg_rn
;
2613 int ebytes
= 1 << size
;
2614 int elements
= (is_q
? 128 : 64) / (8 << size
);
2615 int rpt
; /* num iterations */
2616 int selem
; /* structure elements */
2619 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2620 unallocated_encoding(s
);
2624 /* From the shared decode logic */
2655 unallocated_encoding(s
);
2659 if (size
== 3 && !is_q
&& selem
!= 1) {
2661 unallocated_encoding(s
);
2665 if (!fp_access_check(s
)) {
2670 gen_check_sp_alignment(s
);
2673 tcg_rn
= cpu_reg_sp(s
, rn
);
2674 tcg_addr
= tcg_temp_new_i64();
2675 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2677 for (r
= 0; r
< rpt
; r
++) {
2679 for (e
= 0; e
< elements
; e
++) {
2680 int tt
= (rt
+ r
) % 32;
2682 for (xs
= 0; xs
< selem
; xs
++) {
2684 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2686 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2688 /* For non-quad operations, setting a slice of the low
2689 * 64 bits of the register clears the high 64 bits (in
2690 * the ARM ARM pseudocode this is implicit in the fact
2691 * that 'rval' is a 64 bit wide variable). We optimize
2692 * by noticing that we only need to do this the first
2693 * time we touch a register.
2695 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2696 clear_vec_high(s
, tt
);
2699 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2706 int rm
= extract32(insn
, 16, 5);
2708 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2710 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2713 tcg_temp_free_i64(tcg_addr
);
2716 /* AdvSIMD load/store single structure
2718 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2719 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2720 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2721 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2723 * AdvSIMD load/store single structure (post-indexed)
2725 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2726 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2727 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2728 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2730 * Rt: first (or only) SIMD&FP register to be transferred
2731 * Rn: base address or SP
2732 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2733 * index = encoded in Q:S:size dependent on size
2735 * lane_size = encoded in R, opc
2736 * transfer width = encoded in opc, S, size
2738 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2740 int rt
= extract32(insn
, 0, 5);
2741 int rn
= extract32(insn
, 5, 5);
2742 int size
= extract32(insn
, 10, 2);
2743 int S
= extract32(insn
, 12, 1);
2744 int opc
= extract32(insn
, 13, 3);
2745 int R
= extract32(insn
, 21, 1);
2746 int is_load
= extract32(insn
, 22, 1);
2747 int is_postidx
= extract32(insn
, 23, 1);
2748 int is_q
= extract32(insn
, 30, 1);
2750 int scale
= extract32(opc
, 1, 2);
2751 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2752 bool replicate
= false;
2753 int index
= is_q
<< 3 | S
<< 2 | size
;
2755 TCGv_i64 tcg_addr
, tcg_rn
;
2759 if (!is_load
|| S
) {
2760 unallocated_encoding(s
);
2769 if (extract32(size
, 0, 1)) {
2770 unallocated_encoding(s
);
2776 if (extract32(size
, 1, 1)) {
2777 unallocated_encoding(s
);
2780 if (!extract32(size
, 0, 1)) {
2784 unallocated_encoding(s
);
2792 g_assert_not_reached();
2795 if (!fp_access_check(s
)) {
2799 ebytes
= 1 << scale
;
2802 gen_check_sp_alignment(s
);
2805 tcg_rn
= cpu_reg_sp(s
, rn
);
2806 tcg_addr
= tcg_temp_new_i64();
2807 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2809 for (xs
= 0; xs
< selem
; xs
++) {
2811 /* Load and replicate to all elements */
2813 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2815 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2816 get_mem_index(s
), s
->be_data
+ scale
);
2819 mulconst
= 0x0101010101010101ULL
;
2822 mulconst
= 0x0001000100010001ULL
;
2825 mulconst
= 0x0000000100000001ULL
;
2831 g_assert_not_reached();
2834 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2836 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2838 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2840 clear_vec_high(s
, rt
);
2842 tcg_temp_free_i64(tcg_tmp
);
2844 /* Load/store one element per register */
2846 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
2848 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
2851 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2856 int rm
= extract32(insn
, 16, 5);
2858 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2860 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2863 tcg_temp_free_i64(tcg_addr
);
2866 /* Loads and stores */
2867 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2869 switch (extract32(insn
, 24, 6)) {
2870 case 0x08: /* Load/store exclusive */
2871 disas_ldst_excl(s
, insn
);
2873 case 0x18: case 0x1c: /* Load register (literal) */
2874 disas_ld_lit(s
, insn
);
2876 case 0x28: case 0x29:
2877 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2878 disas_ldst_pair(s
, insn
);
2880 case 0x38: case 0x39:
2881 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2882 disas_ldst_reg(s
, insn
);
2884 case 0x0c: /* AdvSIMD load/store multiple structures */
2885 disas_ldst_multiple_struct(s
, insn
);
2887 case 0x0d: /* AdvSIMD load/store single structure */
2888 disas_ldst_single_struct(s
, insn
);
2891 unallocated_encoding(s
);
2896 /* PC-rel. addressing
2897 * 31 30 29 28 24 23 5 4 0
2898 * +----+-------+-----------+-------------------+------+
2899 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2900 * +----+-------+-----------+-------------------+------+
2902 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2904 unsigned int page
, rd
;
2908 page
= extract32(insn
, 31, 1);
2909 /* SignExtend(immhi:immlo) -> offset */
2910 offset
= sextract64(insn
, 5, 19);
2911 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2912 rd
= extract32(insn
, 0, 5);
2916 /* ADRP (page based) */
2921 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2925 * Add/subtract (immediate)
2927 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2928 * +--+--+--+-----------+-----+-------------+-----+-----+
2929 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2930 * +--+--+--+-----------+-----+-------------+-----+-----+
2932 * sf: 0 -> 32bit, 1 -> 64bit
2933 * op: 0 -> add , 1 -> sub
2935 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2937 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2939 int rd
= extract32(insn
, 0, 5);
2940 int rn
= extract32(insn
, 5, 5);
2941 uint64_t imm
= extract32(insn
, 10, 12);
2942 int shift
= extract32(insn
, 22, 2);
2943 bool setflags
= extract32(insn
, 29, 1);
2944 bool sub_op
= extract32(insn
, 30, 1);
2945 bool is_64bit
= extract32(insn
, 31, 1);
2947 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2948 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2949 TCGv_i64 tcg_result
;
2958 unallocated_encoding(s
);
2962 tcg_result
= tcg_temp_new_i64();
2965 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2967 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2970 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2972 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2974 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2976 tcg_temp_free_i64(tcg_imm
);
2980 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2982 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2985 tcg_temp_free_i64(tcg_result
);
2988 /* The input should be a value in the bottom e bits (with higher
2989 * bits zero); returns that value replicated into every element
2990 * of size e in a 64 bit integer.
2992 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3002 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3003 static inline uint64_t bitmask64(unsigned int length
)
3005 assert(length
> 0 && length
<= 64);
3006 return ~0ULL >> (64 - length
);
3009 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3010 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3011 * value (ie should cause a guest UNDEF exception), and true if they are
3012 * valid, in which case the decoded bit pattern is written to result.
3014 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3015 unsigned int imms
, unsigned int immr
)
3018 unsigned e
, levels
, s
, r
;
3021 assert(immn
< 2 && imms
< 64 && immr
< 64);
3023 /* The bit patterns we create here are 64 bit patterns which
3024 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3025 * 64 bits each. Each element contains the same value: a run
3026 * of between 1 and e-1 non-zero bits, rotated within the
3027 * element by between 0 and e-1 bits.
3029 * The element size and run length are encoded into immn (1 bit)
3030 * and imms (6 bits) as follows:
3031 * 64 bit elements: immn = 1, imms = <length of run - 1>
3032 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3033 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3034 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3035 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3036 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3037 * Notice that immn = 0, imms = 11111x is the only combination
3038 * not covered by one of the above options; this is reserved.
3039 * Further, <length of run - 1> all-ones is a reserved pattern.
3041 * In all cases the rotation is by immr % e (and immr is 6 bits).
3044 /* First determine the element size */
3045 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3047 /* This is the immn == 0, imms == 0x11111x case */
3057 /* <length of run - 1> mustn't be all-ones. */
3061 /* Create the value of one element: s+1 set bits rotated
3062 * by r within the element (which is e bits wide)...
3064 mask
= bitmask64(s
+ 1);
3066 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3067 mask
&= bitmask64(e
);
3069 /* ...then replicate the element over the whole 64 bit value */
3070 mask
= bitfield_replicate(mask
, e
);
3075 /* Logical (immediate)
3076 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3077 * +----+-----+-------------+---+------+------+------+------+
3078 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3079 * +----+-----+-------------+---+------+------+------+------+
3081 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3083 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3084 TCGv_i64 tcg_rd
, tcg_rn
;
3086 bool is_and
= false;
3088 sf
= extract32(insn
, 31, 1);
3089 opc
= extract32(insn
, 29, 2);
3090 is_n
= extract32(insn
, 22, 1);
3091 immr
= extract32(insn
, 16, 6);
3092 imms
= extract32(insn
, 10, 6);
3093 rn
= extract32(insn
, 5, 5);
3094 rd
= extract32(insn
, 0, 5);
3097 unallocated_encoding(s
);
3101 if (opc
== 0x3) { /* ANDS */
3102 tcg_rd
= cpu_reg(s
, rd
);
3104 tcg_rd
= cpu_reg_sp(s
, rd
);
3106 tcg_rn
= cpu_reg(s
, rn
);
3108 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3109 /* some immediate field values are reserved */
3110 unallocated_encoding(s
);
3115 wmask
&= 0xffffffff;
3119 case 0x3: /* ANDS */
3121 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3125 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3128 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3131 assert(FALSE
); /* must handle all above */
3135 if (!sf
&& !is_and
) {
3136 /* zero extend final result; we know we can skip this for AND
3137 * since the immediate had the high 32 bits clear.
3139 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3142 if (opc
== 3) { /* ANDS */
3143 gen_logic_CC(sf
, tcg_rd
);
3148 * Move wide (immediate)
3150 * 31 30 29 28 23 22 21 20 5 4 0
3151 * +--+-----+-------------+-----+----------------+------+
3152 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3153 * +--+-----+-------------+-----+----------------+------+
3155 * sf: 0 -> 32 bit, 1 -> 64 bit
3156 * opc: 00 -> N, 10 -> Z, 11 -> K
3157 * hw: shift/16 (0,16, and sf only 32, 48)
3159 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3161 int rd
= extract32(insn
, 0, 5);
3162 uint64_t imm
= extract32(insn
, 5, 16);
3163 int sf
= extract32(insn
, 31, 1);
3164 int opc
= extract32(insn
, 29, 2);
3165 int pos
= extract32(insn
, 21, 2) << 4;
3166 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3169 if (!sf
&& (pos
>= 32)) {
3170 unallocated_encoding(s
);
3184 tcg_gen_movi_i64(tcg_rd
, imm
);
3187 tcg_imm
= tcg_const_i64(imm
);
3188 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3189 tcg_temp_free_i64(tcg_imm
);
3191 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3195 unallocated_encoding(s
);
3201 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3202 * +----+-----+-------------+---+------+------+------+------+
3203 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3204 * +----+-----+-------------+---+------+------+------+------+
3206 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3208 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3209 TCGv_i64 tcg_rd
, tcg_tmp
;
3211 sf
= extract32(insn
, 31, 1);
3212 opc
= extract32(insn
, 29, 2);
3213 n
= extract32(insn
, 22, 1);
3214 ri
= extract32(insn
, 16, 6);
3215 si
= extract32(insn
, 10, 6);
3216 rn
= extract32(insn
, 5, 5);
3217 rd
= extract32(insn
, 0, 5);
3218 bitsize
= sf
? 64 : 32;
3220 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3221 unallocated_encoding(s
);
3225 tcg_rd
= cpu_reg(s
, rd
);
3227 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3228 to be smaller than bitsize, we'll never reference data outside the
3229 low 32-bits anyway. */
3230 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3232 /* Recognize simple(r) extractions. */
3234 /* Wd<s-r:0> = Wn<s:r> */
3235 len
= (si
- ri
) + 1;
3236 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3237 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3239 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3240 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3243 /* opc == 1, BXFIL fall through to deposit */
3244 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3247 /* Handle the ri > si case with a deposit
3248 * Wd<32+s-r,32-r> = Wn<s:0>
3251 pos
= (bitsize
- ri
) & (bitsize
- 1);
3254 if (opc
== 0 && len
< ri
) {
3255 /* SBFM: sign extend the destination field from len to fill
3256 the balance of the word. Let the deposit below insert all
3257 of those sign bits. */
3258 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3262 if (opc
== 1) { /* BFM, BXFIL */
3263 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3265 /* SBFM or UBFM: We start with zero, and we haven't modified
3266 any bits outside bitsize, therefore the zero-extension
3267 below is unneeded. */
3268 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3273 if (!sf
) { /* zero extend final result */
3274 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3279 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3280 * +----+------+-------------+---+----+------+--------+------+------+
3281 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3282 * +----+------+-------------+---+----+------+--------+------+------+
3284 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3286 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3288 sf
= extract32(insn
, 31, 1);
3289 n
= extract32(insn
, 22, 1);
3290 rm
= extract32(insn
, 16, 5);
3291 imm
= extract32(insn
, 10, 6);
3292 rn
= extract32(insn
, 5, 5);
3293 rd
= extract32(insn
, 0, 5);
3294 op21
= extract32(insn
, 29, 2);
3295 op0
= extract32(insn
, 21, 1);
3296 bitsize
= sf
? 64 : 32;
3298 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3299 unallocated_encoding(s
);
3301 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3303 tcg_rd
= cpu_reg(s
, rd
);
3305 if (unlikely(imm
== 0)) {
3306 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3307 * so an extract from bit 0 is a special case.
3310 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3312 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3314 } else if (rm
== rn
) { /* ROR */
3315 tcg_rm
= cpu_reg(s
, rm
);
3317 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3319 TCGv_i32 tmp
= tcg_temp_new_i32();
3320 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3321 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3322 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3323 tcg_temp_free_i32(tmp
);
3326 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3327 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3328 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3329 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3330 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3332 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3338 /* Data processing - immediate */
3339 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3341 switch (extract32(insn
, 23, 6)) {
3342 case 0x20: case 0x21: /* PC-rel. addressing */
3343 disas_pc_rel_adr(s
, insn
);
3345 case 0x22: case 0x23: /* Add/subtract (immediate) */
3346 disas_add_sub_imm(s
, insn
);
3348 case 0x24: /* Logical (immediate) */
3349 disas_logic_imm(s
, insn
);
3351 case 0x25: /* Move wide (immediate) */
3352 disas_movw_imm(s
, insn
);
3354 case 0x26: /* Bitfield */
3355 disas_bitfield(s
, insn
);
3357 case 0x27: /* Extract */
3358 disas_extract(s
, insn
);
3361 unallocated_encoding(s
);
3366 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3367 * Note that it is the caller's responsibility to ensure that the
3368 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3369 * mandated semantics for out of range shifts.
3371 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3372 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3374 switch (shift_type
) {
3375 case A64_SHIFT_TYPE_LSL
:
3376 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3378 case A64_SHIFT_TYPE_LSR
:
3379 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3381 case A64_SHIFT_TYPE_ASR
:
3383 tcg_gen_ext32s_i64(dst
, src
);
3385 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3387 case A64_SHIFT_TYPE_ROR
:
3389 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3392 t0
= tcg_temp_new_i32();
3393 t1
= tcg_temp_new_i32();
3394 tcg_gen_extrl_i64_i32(t0
, src
);
3395 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3396 tcg_gen_rotr_i32(t0
, t0
, t1
);
3397 tcg_gen_extu_i32_i64(dst
, t0
);
3398 tcg_temp_free_i32(t0
);
3399 tcg_temp_free_i32(t1
);
3403 assert(FALSE
); /* all shift types should be handled */
3407 if (!sf
) { /* zero extend final result */
3408 tcg_gen_ext32u_i64(dst
, dst
);
3412 /* Shift a TCGv src by immediate, put result in dst.
3413 * The shift amount must be in range (this should always be true as the
3414 * relevant instructions will UNDEF on bad shift immediates).
3416 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3417 enum a64_shift_type shift_type
, unsigned int shift_i
)
3419 assert(shift_i
< (sf
? 64 : 32));
3422 tcg_gen_mov_i64(dst
, src
);
3424 TCGv_i64 shift_const
;
3426 shift_const
= tcg_const_i64(shift_i
);
3427 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3428 tcg_temp_free_i64(shift_const
);
3432 /* Logical (shifted register)
3433 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3434 * +----+-----+-----------+-------+---+------+--------+------+------+
3435 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3436 * +----+-----+-----------+-------+---+------+--------+------+------+
3438 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3440 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3441 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3443 sf
= extract32(insn
, 31, 1);
3444 opc
= extract32(insn
, 29, 2);
3445 shift_type
= extract32(insn
, 22, 2);
3446 invert
= extract32(insn
, 21, 1);
3447 rm
= extract32(insn
, 16, 5);
3448 shift_amount
= extract32(insn
, 10, 6);
3449 rn
= extract32(insn
, 5, 5);
3450 rd
= extract32(insn
, 0, 5);
3452 if (!sf
&& (shift_amount
& (1 << 5))) {
3453 unallocated_encoding(s
);
3457 tcg_rd
= cpu_reg(s
, rd
);
3459 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3460 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3461 * register-register MOV and MVN, so it is worth special casing.
3463 tcg_rm
= cpu_reg(s
, rm
);
3465 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3467 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3471 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3473 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3479 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3482 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3485 tcg_rn
= cpu_reg(s
, rn
);
3487 switch (opc
| (invert
<< 2)) {
3490 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3493 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3496 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3500 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3503 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3506 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3514 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3518 gen_logic_CC(sf
, tcg_rd
);
3523 * Add/subtract (extended register)
3525 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3526 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3527 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3528 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3530 * sf: 0 -> 32bit, 1 -> 64bit
3531 * op: 0 -> add , 1 -> sub
3534 * option: extension type (see DecodeRegExtend)
3535 * imm3: optional shift to Rm
3537 * Rd = Rn + LSL(extend(Rm), amount)
3539 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3541 int rd
= extract32(insn
, 0, 5);
3542 int rn
= extract32(insn
, 5, 5);
3543 int imm3
= extract32(insn
, 10, 3);
3544 int option
= extract32(insn
, 13, 3);
3545 int rm
= extract32(insn
, 16, 5);
3546 bool setflags
= extract32(insn
, 29, 1);
3547 bool sub_op
= extract32(insn
, 30, 1);
3548 bool sf
= extract32(insn
, 31, 1);
3550 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3552 TCGv_i64 tcg_result
;
3555 unallocated_encoding(s
);
3559 /* non-flag setting ops may use SP */
3561 tcg_rd
= cpu_reg_sp(s
, rd
);
3563 tcg_rd
= cpu_reg(s
, rd
);
3565 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3567 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3568 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3570 tcg_result
= tcg_temp_new_i64();
3574 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3576 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3580 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3582 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3587 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3589 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3592 tcg_temp_free_i64(tcg_result
);
3596 * Add/subtract (shifted register)
3598 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3599 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3600 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3601 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3603 * sf: 0 -> 32bit, 1 -> 64bit
3604 * op: 0 -> add , 1 -> sub
3606 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3607 * imm6: Shift amount to apply to Rm before the add/sub
3609 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3611 int rd
= extract32(insn
, 0, 5);
3612 int rn
= extract32(insn
, 5, 5);
3613 int imm6
= extract32(insn
, 10, 6);
3614 int rm
= extract32(insn
, 16, 5);
3615 int shift_type
= extract32(insn
, 22, 2);
3616 bool setflags
= extract32(insn
, 29, 1);
3617 bool sub_op
= extract32(insn
, 30, 1);
3618 bool sf
= extract32(insn
, 31, 1);
3620 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3621 TCGv_i64 tcg_rn
, tcg_rm
;
3622 TCGv_i64 tcg_result
;
3624 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3625 unallocated_encoding(s
);
3629 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3630 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3632 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3634 tcg_result
= tcg_temp_new_i64();
3638 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3640 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3644 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3646 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3651 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3653 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3656 tcg_temp_free_i64(tcg_result
);
3659 /* Data-processing (3 source)
3661 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3662 * +--+------+-----------+------+------+----+------+------+------+
3663 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3664 * +--+------+-----------+------+------+----+------+------+------+
3666 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3668 int rd
= extract32(insn
, 0, 5);
3669 int rn
= extract32(insn
, 5, 5);
3670 int ra
= extract32(insn
, 10, 5);
3671 int rm
= extract32(insn
, 16, 5);
3672 int op_id
= (extract32(insn
, 29, 3) << 4) |
3673 (extract32(insn
, 21, 3) << 1) |
3674 extract32(insn
, 15, 1);
3675 bool sf
= extract32(insn
, 31, 1);
3676 bool is_sub
= extract32(op_id
, 0, 1);
3677 bool is_high
= extract32(op_id
, 2, 1);
3678 bool is_signed
= false;
3683 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3685 case 0x42: /* SMADDL */
3686 case 0x43: /* SMSUBL */
3687 case 0x44: /* SMULH */
3690 case 0x0: /* MADD (32bit) */
3691 case 0x1: /* MSUB (32bit) */
3692 case 0x40: /* MADD (64bit) */
3693 case 0x41: /* MSUB (64bit) */
3694 case 0x4a: /* UMADDL */
3695 case 0x4b: /* UMSUBL */
3696 case 0x4c: /* UMULH */
3699 unallocated_encoding(s
);
3704 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3705 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3706 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3707 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3710 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3712 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3715 tcg_temp_free_i64(low_bits
);
3719 tcg_op1
= tcg_temp_new_i64();
3720 tcg_op2
= tcg_temp_new_i64();
3721 tcg_tmp
= tcg_temp_new_i64();
3724 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3725 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3728 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3729 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3731 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3732 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3736 if (ra
== 31 && !is_sub
) {
3737 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3738 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3740 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3742 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3744 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3749 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3752 tcg_temp_free_i64(tcg_op1
);
3753 tcg_temp_free_i64(tcg_op2
);
3754 tcg_temp_free_i64(tcg_tmp
);
3757 /* Add/subtract (with carry)
3758 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3759 * +--+--+--+------------------------+------+---------+------+-----+
3760 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3761 * +--+--+--+------------------------+------+---------+------+-----+
3765 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3767 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3768 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3770 if (extract32(insn
, 10, 6) != 0) {
3771 unallocated_encoding(s
);
3775 sf
= extract32(insn
, 31, 1);
3776 op
= extract32(insn
, 30, 1);
3777 setflags
= extract32(insn
, 29, 1);
3778 rm
= extract32(insn
, 16, 5);
3779 rn
= extract32(insn
, 5, 5);
3780 rd
= extract32(insn
, 0, 5);
3782 tcg_rd
= cpu_reg(s
, rd
);
3783 tcg_rn
= cpu_reg(s
, rn
);
3786 tcg_y
= new_tmp_a64(s
);
3787 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3789 tcg_y
= cpu_reg(s
, rm
);
3793 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3795 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3799 /* Conditional compare (immediate / register)
3800 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3801 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3802 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3803 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3806 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3808 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3809 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3810 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3813 if (!extract32(insn
, 29, 1)) {
3814 unallocated_encoding(s
);
3817 if (insn
& (1 << 10 | 1 << 4)) {
3818 unallocated_encoding(s
);
3821 sf
= extract32(insn
, 31, 1);
3822 op
= extract32(insn
, 30, 1);
3823 is_imm
= extract32(insn
, 11, 1);
3824 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3825 cond
= extract32(insn
, 12, 4);
3826 rn
= extract32(insn
, 5, 5);
3827 nzcv
= extract32(insn
, 0, 4);
3829 /* Set T0 = !COND. */
3830 tcg_t0
= tcg_temp_new_i32();
3831 arm_test_cc(&c
, cond
);
3832 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3835 /* Load the arguments for the new comparison. */
3837 tcg_y
= new_tmp_a64(s
);
3838 tcg_gen_movi_i64(tcg_y
, y
);
3840 tcg_y
= cpu_reg(s
, y
);
3842 tcg_rn
= cpu_reg(s
, rn
);
3844 /* Set the flags for the new comparison. */
3845 tcg_tmp
= tcg_temp_new_i64();
3847 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3849 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3851 tcg_temp_free_i64(tcg_tmp
);
3853 /* If COND was false, force the flags to #nzcv. Compute two masks
3854 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3855 * For tcg hosts that support ANDC, we can make do with just T1.
3856 * In either case, allow the tcg optimizer to delete any unused mask.
3858 tcg_t1
= tcg_temp_new_i32();
3859 tcg_t2
= tcg_temp_new_i32();
3860 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3861 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3863 if (nzcv
& 8) { /* N */
3864 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3866 if (TCG_TARGET_HAS_andc_i32
) {
3867 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3869 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3872 if (nzcv
& 4) { /* Z */
3873 if (TCG_TARGET_HAS_andc_i32
) {
3874 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3876 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3879 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3881 if (nzcv
& 2) { /* C */
3882 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3884 if (TCG_TARGET_HAS_andc_i32
) {
3885 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3887 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3890 if (nzcv
& 1) { /* V */
3891 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3893 if (TCG_TARGET_HAS_andc_i32
) {
3894 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3896 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3899 tcg_temp_free_i32(tcg_t0
);
3900 tcg_temp_free_i32(tcg_t1
);
3901 tcg_temp_free_i32(tcg_t2
);
3904 /* Conditional select
3905 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3906 * +----+----+---+-----------------+------+------+-----+------+------+
3907 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3908 * +----+----+---+-----------------+------+------+-----+------+------+
3910 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3912 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3913 TCGv_i64 tcg_rd
, zero
;
3916 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3917 /* S == 1 or op2<1> == 1 */
3918 unallocated_encoding(s
);
3921 sf
= extract32(insn
, 31, 1);
3922 else_inv
= extract32(insn
, 30, 1);
3923 rm
= extract32(insn
, 16, 5);
3924 cond
= extract32(insn
, 12, 4);
3925 else_inc
= extract32(insn
, 10, 1);
3926 rn
= extract32(insn
, 5, 5);
3927 rd
= extract32(insn
, 0, 5);
3929 tcg_rd
= cpu_reg(s
, rd
);
3931 a64_test_cc(&c
, cond
);
3932 zero
= tcg_const_i64(0);
3934 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3936 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3938 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3941 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3942 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3943 if (else_inv
&& else_inc
) {
3944 tcg_gen_neg_i64(t_false
, t_false
);
3945 } else if (else_inv
) {
3946 tcg_gen_not_i64(t_false
, t_false
);
3947 } else if (else_inc
) {
3948 tcg_gen_addi_i64(t_false
, t_false
, 1);
3950 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3953 tcg_temp_free_i64(zero
);
3957 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3961 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3962 unsigned int rn
, unsigned int rd
)
3964 TCGv_i64 tcg_rd
, tcg_rn
;
3965 tcg_rd
= cpu_reg(s
, rd
);
3966 tcg_rn
= cpu_reg(s
, rn
);
3969 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
3971 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3972 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3973 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
3974 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3975 tcg_temp_free_i32(tcg_tmp32
);
3979 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3980 unsigned int rn
, unsigned int rd
)
3982 TCGv_i64 tcg_rd
, tcg_rn
;
3983 tcg_rd
= cpu_reg(s
, rd
);
3984 tcg_rn
= cpu_reg(s
, rn
);
3987 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
3989 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3990 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3991 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
3992 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3993 tcg_temp_free_i32(tcg_tmp32
);
3997 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3998 unsigned int rn
, unsigned int rd
)
4000 TCGv_i64 tcg_rd
, tcg_rn
;
4001 tcg_rd
= cpu_reg(s
, rd
);
4002 tcg_rn
= cpu_reg(s
, rn
);
4005 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4007 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4008 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4009 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4010 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4011 tcg_temp_free_i32(tcg_tmp32
);
4015 /* REV with sf==1, opcode==3 ("REV64") */
4016 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4017 unsigned int rn
, unsigned int rd
)
4020 unallocated_encoding(s
);
4023 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4026 /* REV with sf==0, opcode==2
4027 * REV32 (sf==1, opcode==2)
4029 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4030 unsigned int rn
, unsigned int rd
)
4032 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4035 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4036 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4038 /* bswap32_i64 requires zero high word */
4039 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4040 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4041 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4042 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4043 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4045 tcg_temp_free_i64(tcg_tmp
);
4047 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4048 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4052 /* REV16 (opcode==1) */
4053 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4054 unsigned int rn
, unsigned int rd
)
4056 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4057 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4058 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4059 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4061 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4062 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4063 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4064 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4065 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4067 tcg_temp_free_i64(mask
);
4068 tcg_temp_free_i64(tcg_tmp
);
4071 /* Data-processing (1 source)
4072 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4073 * +----+---+---+-----------------+---------+--------+------+------+
4074 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4075 * +----+---+---+-----------------+---------+--------+------+------+
4077 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4079 unsigned int sf
, opcode
, rn
, rd
;
4081 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4082 unallocated_encoding(s
);
4086 sf
= extract32(insn
, 31, 1);
4087 opcode
= extract32(insn
, 10, 6);
4088 rn
= extract32(insn
, 5, 5);
4089 rd
= extract32(insn
, 0, 5);
4093 handle_rbit(s
, sf
, rn
, rd
);
4096 handle_rev16(s
, sf
, rn
, rd
);
4099 handle_rev32(s
, sf
, rn
, rd
);
4102 handle_rev64(s
, sf
, rn
, rd
);
4105 handle_clz(s
, sf
, rn
, rd
);
4108 handle_cls(s
, sf
, rn
, rd
);
4113 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4114 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4116 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4117 tcg_rd
= cpu_reg(s
, rd
);
4119 if (!sf
&& is_signed
) {
4120 tcg_n
= new_tmp_a64(s
);
4121 tcg_m
= new_tmp_a64(s
);
4122 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4123 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4125 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4126 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4130 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4132 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4135 if (!sf
) { /* zero extend final result */
4136 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4140 /* LSLV, LSRV, ASRV, RORV */
4141 static void handle_shift_reg(DisasContext
*s
,
4142 enum a64_shift_type shift_type
, unsigned int sf
,
4143 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4145 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4146 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4147 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4149 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4150 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4151 tcg_temp_free_i64(tcg_shift
);
4154 /* CRC32[BHWX], CRC32C[BHWX] */
4155 static void handle_crc32(DisasContext
*s
,
4156 unsigned int sf
, unsigned int sz
, bool crc32c
,
4157 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4159 TCGv_i64 tcg_acc
, tcg_val
;
4162 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4163 || (sf
== 1 && sz
!= 3)
4164 || (sf
== 0 && sz
== 3)) {
4165 unallocated_encoding(s
);
4170 tcg_val
= cpu_reg(s
, rm
);
4184 g_assert_not_reached();
4186 tcg_val
= new_tmp_a64(s
);
4187 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4190 tcg_acc
= cpu_reg(s
, rn
);
4191 tcg_bytes
= tcg_const_i32(1 << sz
);
4194 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4196 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4199 tcg_temp_free_i32(tcg_bytes
);
4202 /* Data-processing (2 source)
4203 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4204 * +----+---+---+-----------------+------+--------+------+------+
4205 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4206 * +----+---+---+-----------------+------+--------+------+------+
4208 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4210 unsigned int sf
, rm
, opcode
, rn
, rd
;
4211 sf
= extract32(insn
, 31, 1);
4212 rm
= extract32(insn
, 16, 5);
4213 opcode
= extract32(insn
, 10, 6);
4214 rn
= extract32(insn
, 5, 5);
4215 rd
= extract32(insn
, 0, 5);
4217 if (extract32(insn
, 29, 1)) {
4218 unallocated_encoding(s
);
4224 handle_div(s
, false, sf
, rm
, rn
, rd
);
4227 handle_div(s
, true, sf
, rm
, rn
, rd
);
4230 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4233 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4236 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4239 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4248 case 23: /* CRC32 */
4250 int sz
= extract32(opcode
, 0, 2);
4251 bool crc32c
= extract32(opcode
, 2, 1);
4252 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4256 unallocated_encoding(s
);
4261 /* Data processing - register */
4262 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4264 switch (extract32(insn
, 24, 5)) {
4265 case 0x0a: /* Logical (shifted register) */
4266 disas_logic_reg(s
, insn
);
4268 case 0x0b: /* Add/subtract */
4269 if (insn
& (1 << 21)) { /* (extended register) */
4270 disas_add_sub_ext_reg(s
, insn
);
4272 disas_add_sub_reg(s
, insn
);
4275 case 0x1b: /* Data-processing (3 source) */
4276 disas_data_proc_3src(s
, insn
);
4279 switch (extract32(insn
, 21, 3)) {
4280 case 0x0: /* Add/subtract (with carry) */
4281 disas_adc_sbc(s
, insn
);
4283 case 0x2: /* Conditional compare */
4284 disas_cc(s
, insn
); /* both imm and reg forms */
4286 case 0x4: /* Conditional select */
4287 disas_cond_select(s
, insn
);
4289 case 0x6: /* Data-processing */
4290 if (insn
& (1 << 30)) { /* (1 source) */
4291 disas_data_proc_1src(s
, insn
);
4292 } else { /* (2 source) */
4293 disas_data_proc_2src(s
, insn
);
4297 unallocated_encoding(s
);
4302 unallocated_encoding(s
);
4307 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4308 unsigned int rn
, unsigned int rm
,
4309 bool cmp_with_zero
, bool signal_all_nans
)
4311 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4312 TCGv_ptr fpst
= get_fpstatus_ptr();
4315 TCGv_i64 tcg_vn
, tcg_vm
;
4317 tcg_vn
= read_fp_dreg(s
, rn
);
4318 if (cmp_with_zero
) {
4319 tcg_vm
= tcg_const_i64(0);
4321 tcg_vm
= read_fp_dreg(s
, rm
);
4323 if (signal_all_nans
) {
4324 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4326 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4328 tcg_temp_free_i64(tcg_vn
);
4329 tcg_temp_free_i64(tcg_vm
);
4331 TCGv_i32 tcg_vn
, tcg_vm
;
4333 tcg_vn
= read_fp_sreg(s
, rn
);
4334 if (cmp_with_zero
) {
4335 tcg_vm
= tcg_const_i32(0);
4337 tcg_vm
= read_fp_sreg(s
, rm
);
4339 if (signal_all_nans
) {
4340 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4342 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4344 tcg_temp_free_i32(tcg_vn
);
4345 tcg_temp_free_i32(tcg_vm
);
4348 tcg_temp_free_ptr(fpst
);
4350 gen_set_nzcv(tcg_flags
);
4352 tcg_temp_free_i64(tcg_flags
);
4355 /* Floating point compare
4356 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4357 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4358 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4359 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4361 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4363 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4365 mos
= extract32(insn
, 29, 3);
4366 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4367 rm
= extract32(insn
, 16, 5);
4368 op
= extract32(insn
, 14, 2);
4369 rn
= extract32(insn
, 5, 5);
4370 opc
= extract32(insn
, 3, 2);
4371 op2r
= extract32(insn
, 0, 3);
4373 if (mos
|| op
|| op2r
|| type
> 1) {
4374 unallocated_encoding(s
);
4378 if (!fp_access_check(s
)) {
4382 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4385 /* Floating point conditional compare
4386 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4387 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4388 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4389 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4391 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4393 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4395 TCGLabel
*label_continue
= NULL
;
4397 mos
= extract32(insn
, 29, 3);
4398 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4399 rm
= extract32(insn
, 16, 5);
4400 cond
= extract32(insn
, 12, 4);
4401 rn
= extract32(insn
, 5, 5);
4402 op
= extract32(insn
, 4, 1);
4403 nzcv
= extract32(insn
, 0, 4);
4405 if (mos
|| type
> 1) {
4406 unallocated_encoding(s
);
4410 if (!fp_access_check(s
)) {
4414 if (cond
< 0x0e) { /* not always */
4415 TCGLabel
*label_match
= gen_new_label();
4416 label_continue
= gen_new_label();
4417 arm_gen_test_cc(cond
, label_match
);
4419 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4420 gen_set_nzcv(tcg_flags
);
4421 tcg_temp_free_i64(tcg_flags
);
4422 tcg_gen_br(label_continue
);
4423 gen_set_label(label_match
);
4426 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4429 gen_set_label(label_continue
);
4433 /* Floating point conditional select
4434 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4435 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4436 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4437 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4439 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4441 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4442 TCGv_i64 t_true
, t_false
, t_zero
;
4445 mos
= extract32(insn
, 29, 3);
4446 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4447 rm
= extract32(insn
, 16, 5);
4448 cond
= extract32(insn
, 12, 4);
4449 rn
= extract32(insn
, 5, 5);
4450 rd
= extract32(insn
, 0, 5);
4452 if (mos
|| type
> 1) {
4453 unallocated_encoding(s
);
4457 if (!fp_access_check(s
)) {
4461 /* Zero extend sreg inputs to 64 bits now. */
4462 t_true
= tcg_temp_new_i64();
4463 t_false
= tcg_temp_new_i64();
4464 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4465 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4467 a64_test_cc(&c
, cond
);
4468 t_zero
= tcg_const_i64(0);
4469 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4470 tcg_temp_free_i64(t_zero
);
4471 tcg_temp_free_i64(t_false
);
4474 /* Note that sregs write back zeros to the high bits,
4475 and we've already done the zero-extension. */
4476 write_fp_dreg(s
, rd
, t_true
);
4477 tcg_temp_free_i64(t_true
);
4480 /* Floating-point data-processing (1 source) - single precision */
4481 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4487 fpst
= get_fpstatus_ptr();
4488 tcg_op
= read_fp_sreg(s
, rn
);
4489 tcg_res
= tcg_temp_new_i32();
4492 case 0x0: /* FMOV */
4493 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4495 case 0x1: /* FABS */
4496 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4498 case 0x2: /* FNEG */
4499 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4501 case 0x3: /* FSQRT */
4502 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4504 case 0x8: /* FRINTN */
4505 case 0x9: /* FRINTP */
4506 case 0xa: /* FRINTM */
4507 case 0xb: /* FRINTZ */
4508 case 0xc: /* FRINTA */
4510 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4512 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4513 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4515 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4516 tcg_temp_free_i32(tcg_rmode
);
4519 case 0xe: /* FRINTX */
4520 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4522 case 0xf: /* FRINTI */
4523 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4529 write_fp_sreg(s
, rd
, tcg_res
);
4531 tcg_temp_free_ptr(fpst
);
4532 tcg_temp_free_i32(tcg_op
);
4533 tcg_temp_free_i32(tcg_res
);
4536 /* Floating-point data-processing (1 source) - double precision */
4537 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4543 fpst
= get_fpstatus_ptr();
4544 tcg_op
= read_fp_dreg(s
, rn
);
4545 tcg_res
= tcg_temp_new_i64();
4548 case 0x0: /* FMOV */
4549 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4551 case 0x1: /* FABS */
4552 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4554 case 0x2: /* FNEG */
4555 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4557 case 0x3: /* FSQRT */
4558 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4560 case 0x8: /* FRINTN */
4561 case 0x9: /* FRINTP */
4562 case 0xa: /* FRINTM */
4563 case 0xb: /* FRINTZ */
4564 case 0xc: /* FRINTA */
4566 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4568 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4569 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4571 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4572 tcg_temp_free_i32(tcg_rmode
);
4575 case 0xe: /* FRINTX */
4576 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4578 case 0xf: /* FRINTI */
4579 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4585 write_fp_dreg(s
, rd
, tcg_res
);
4587 tcg_temp_free_ptr(fpst
);
4588 tcg_temp_free_i64(tcg_op
);
4589 tcg_temp_free_i64(tcg_res
);
4592 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4593 int rd
, int rn
, int dtype
, int ntype
)
4598 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4600 /* Single to double */
4601 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4602 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4603 write_fp_dreg(s
, rd
, tcg_rd
);
4604 tcg_temp_free_i64(tcg_rd
);
4606 /* Single to half */
4607 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4608 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4609 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4610 write_fp_sreg(s
, rd
, tcg_rd
);
4611 tcg_temp_free_i32(tcg_rd
);
4613 tcg_temp_free_i32(tcg_rn
);
4618 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4619 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4621 /* Double to single */
4622 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4624 /* Double to half */
4625 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4626 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4628 write_fp_sreg(s
, rd
, tcg_rd
);
4629 tcg_temp_free_i32(tcg_rd
);
4630 tcg_temp_free_i64(tcg_rn
);
4635 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4636 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4638 /* Half to single */
4639 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4640 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4641 write_fp_sreg(s
, rd
, tcg_rd
);
4642 tcg_temp_free_i32(tcg_rd
);
4644 /* Half to double */
4645 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4646 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4647 write_fp_dreg(s
, rd
, tcg_rd
);
4648 tcg_temp_free_i64(tcg_rd
);
4650 tcg_temp_free_i32(tcg_rn
);
4658 /* Floating point data-processing (1 source)
4659 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4660 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4661 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4662 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4664 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4666 int type
= extract32(insn
, 22, 2);
4667 int opcode
= extract32(insn
, 15, 6);
4668 int rn
= extract32(insn
, 5, 5);
4669 int rd
= extract32(insn
, 0, 5);
4672 case 0x4: case 0x5: case 0x7:
4674 /* FCVT between half, single and double precision */
4675 int dtype
= extract32(opcode
, 0, 2);
4676 if (type
== 2 || dtype
== type
) {
4677 unallocated_encoding(s
);
4680 if (!fp_access_check(s
)) {
4684 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4690 /* 32-to-32 and 64-to-64 ops */
4693 if (!fp_access_check(s
)) {
4697 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4700 if (!fp_access_check(s
)) {
4704 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4707 unallocated_encoding(s
);
4711 unallocated_encoding(s
);
4716 /* Floating-point data-processing (2 source) - single precision */
4717 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4718 int rd
, int rn
, int rm
)
4725 tcg_res
= tcg_temp_new_i32();
4726 fpst
= get_fpstatus_ptr();
4727 tcg_op1
= read_fp_sreg(s
, rn
);
4728 tcg_op2
= read_fp_sreg(s
, rm
);
4731 case 0x0: /* FMUL */
4732 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4734 case 0x1: /* FDIV */
4735 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4737 case 0x2: /* FADD */
4738 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4740 case 0x3: /* FSUB */
4741 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4743 case 0x4: /* FMAX */
4744 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4746 case 0x5: /* FMIN */
4747 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4749 case 0x6: /* FMAXNM */
4750 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4752 case 0x7: /* FMINNM */
4753 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4755 case 0x8: /* FNMUL */
4756 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4757 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4761 write_fp_sreg(s
, rd
, tcg_res
);
4763 tcg_temp_free_ptr(fpst
);
4764 tcg_temp_free_i32(tcg_op1
);
4765 tcg_temp_free_i32(tcg_op2
);
4766 tcg_temp_free_i32(tcg_res
);
4769 /* Floating-point data-processing (2 source) - double precision */
4770 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4771 int rd
, int rn
, int rm
)
4778 tcg_res
= tcg_temp_new_i64();
4779 fpst
= get_fpstatus_ptr();
4780 tcg_op1
= read_fp_dreg(s
, rn
);
4781 tcg_op2
= read_fp_dreg(s
, rm
);
4784 case 0x0: /* FMUL */
4785 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4787 case 0x1: /* FDIV */
4788 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4790 case 0x2: /* FADD */
4791 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4793 case 0x3: /* FSUB */
4794 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4796 case 0x4: /* FMAX */
4797 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4799 case 0x5: /* FMIN */
4800 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4802 case 0x6: /* FMAXNM */
4803 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4805 case 0x7: /* FMINNM */
4806 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4808 case 0x8: /* FNMUL */
4809 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4810 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4814 write_fp_dreg(s
, rd
, tcg_res
);
4816 tcg_temp_free_ptr(fpst
);
4817 tcg_temp_free_i64(tcg_op1
);
4818 tcg_temp_free_i64(tcg_op2
);
4819 tcg_temp_free_i64(tcg_res
);
4822 /* Floating point data-processing (2 source)
4823 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4824 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4825 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4826 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4828 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4830 int type
= extract32(insn
, 22, 2);
4831 int rd
= extract32(insn
, 0, 5);
4832 int rn
= extract32(insn
, 5, 5);
4833 int rm
= extract32(insn
, 16, 5);
4834 int opcode
= extract32(insn
, 12, 4);
4837 unallocated_encoding(s
);
4843 if (!fp_access_check(s
)) {
4846 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4849 if (!fp_access_check(s
)) {
4852 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4855 unallocated_encoding(s
);
4859 /* Floating-point data-processing (3 source) - single precision */
4860 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4861 int rd
, int rn
, int rm
, int ra
)
4863 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4864 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4865 TCGv_ptr fpst
= get_fpstatus_ptr();
4867 tcg_op1
= read_fp_sreg(s
, rn
);
4868 tcg_op2
= read_fp_sreg(s
, rm
);
4869 tcg_op3
= read_fp_sreg(s
, ra
);
4871 /* These are fused multiply-add, and must be done as one
4872 * floating point operation with no rounding between the
4873 * multiplication and addition steps.
4874 * NB that doing the negations here as separate steps is
4875 * correct : an input NaN should come out with its sign bit
4876 * flipped if it is a negated-input.
4879 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4883 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4886 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4888 write_fp_sreg(s
, rd
, tcg_res
);
4890 tcg_temp_free_ptr(fpst
);
4891 tcg_temp_free_i32(tcg_op1
);
4892 tcg_temp_free_i32(tcg_op2
);
4893 tcg_temp_free_i32(tcg_op3
);
4894 tcg_temp_free_i32(tcg_res
);
4897 /* Floating-point data-processing (3 source) - double precision */
4898 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4899 int rd
, int rn
, int rm
, int ra
)
4901 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4902 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4903 TCGv_ptr fpst
= get_fpstatus_ptr();
4905 tcg_op1
= read_fp_dreg(s
, rn
);
4906 tcg_op2
= read_fp_dreg(s
, rm
);
4907 tcg_op3
= read_fp_dreg(s
, ra
);
4909 /* These are fused multiply-add, and must be done as one
4910 * floating point operation with no rounding between the
4911 * multiplication and addition steps.
4912 * NB that doing the negations here as separate steps is
4913 * correct : an input NaN should come out with its sign bit
4914 * flipped if it is a negated-input.
4917 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4921 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4924 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4926 write_fp_dreg(s
, rd
, tcg_res
);
4928 tcg_temp_free_ptr(fpst
);
4929 tcg_temp_free_i64(tcg_op1
);
4930 tcg_temp_free_i64(tcg_op2
);
4931 tcg_temp_free_i64(tcg_op3
);
4932 tcg_temp_free_i64(tcg_res
);
4935 /* Floating point data-processing (3 source)
4936 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4937 * +---+---+---+-----------+------+----+------+----+------+------+------+
4938 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4939 * +---+---+---+-----------+------+----+------+----+------+------+------+
4941 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4943 int type
= extract32(insn
, 22, 2);
4944 int rd
= extract32(insn
, 0, 5);
4945 int rn
= extract32(insn
, 5, 5);
4946 int ra
= extract32(insn
, 10, 5);
4947 int rm
= extract32(insn
, 16, 5);
4948 bool o0
= extract32(insn
, 15, 1);
4949 bool o1
= extract32(insn
, 21, 1);
4953 if (!fp_access_check(s
)) {
4956 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4959 if (!fp_access_check(s
)) {
4962 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4965 unallocated_encoding(s
);
4969 /* Floating point immediate
4970 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4971 * +---+---+---+-----------+------+---+------------+-------+------+------+
4972 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4973 * +---+---+---+-----------+------+---+------------+-------+------+------+
4975 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4977 int rd
= extract32(insn
, 0, 5);
4978 int imm8
= extract32(insn
, 13, 8);
4979 int is_double
= extract32(insn
, 22, 2);
4983 if (is_double
> 1) {
4984 unallocated_encoding(s
);
4988 if (!fp_access_check(s
)) {
4992 /* The imm8 encodes the sign bit, enough bits to represent
4993 * an exponent in the range 01....1xx to 10....0xx,
4994 * and the most significant 4 bits of the mantissa; see
4995 * VFPExpandImm() in the v8 ARM ARM.
4998 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4999 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
5000 extract32(imm8
, 0, 6);
5003 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5004 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5005 (extract32(imm8
, 0, 6) << 3);
5009 tcg_res
= tcg_const_i64(imm
);
5010 write_fp_dreg(s
, rd
, tcg_res
);
5011 tcg_temp_free_i64(tcg_res
);
5014 /* Handle floating point <=> fixed point conversions. Note that we can
5015 * also deal with fp <=> integer conversions as a special case (scale == 64)
5016 * OPTME: consider handling that special case specially or at least skipping
5017 * the call to scalbn in the helpers for zero shifts.
5019 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5020 bool itof
, int rmode
, int scale
, int sf
, int type
)
5022 bool is_signed
= !(opcode
& 1);
5023 bool is_double
= type
;
5024 TCGv_ptr tcg_fpstatus
;
5027 tcg_fpstatus
= get_fpstatus_ptr();
5029 tcg_shift
= tcg_const_i32(64 - scale
);
5032 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5034 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5037 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5039 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5042 tcg_int
= tcg_extend
;
5046 TCGv_i64 tcg_double
= tcg_temp_new_i64();
5048 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5049 tcg_shift
, tcg_fpstatus
);
5051 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5052 tcg_shift
, tcg_fpstatus
);
5054 write_fp_dreg(s
, rd
, tcg_double
);
5055 tcg_temp_free_i64(tcg_double
);
5057 TCGv_i32 tcg_single
= tcg_temp_new_i32();
5059 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5060 tcg_shift
, tcg_fpstatus
);
5062 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5063 tcg_shift
, tcg_fpstatus
);
5065 write_fp_sreg(s
, rd
, tcg_single
);
5066 tcg_temp_free_i32(tcg_single
);
5069 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5072 if (extract32(opcode
, 2, 1)) {
5073 /* There are too many rounding modes to all fit into rmode,
5074 * so FCVTA[US] is a special case.
5076 rmode
= FPROUNDING_TIEAWAY
;
5079 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5081 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5084 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
5087 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5088 tcg_shift
, tcg_fpstatus
);
5090 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5091 tcg_shift
, tcg_fpstatus
);
5095 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5096 tcg_shift
, tcg_fpstatus
);
5098 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5099 tcg_shift
, tcg_fpstatus
);
5102 tcg_temp_free_i64(tcg_double
);
5104 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
5107 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5108 tcg_shift
, tcg_fpstatus
);
5110 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5111 tcg_shift
, tcg_fpstatus
);
5114 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5116 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5117 tcg_shift
, tcg_fpstatus
);
5119 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5120 tcg_shift
, tcg_fpstatus
);
5122 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5123 tcg_temp_free_i32(tcg_dest
);
5125 tcg_temp_free_i32(tcg_single
);
5128 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5129 tcg_temp_free_i32(tcg_rmode
);
5132 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5136 tcg_temp_free_ptr(tcg_fpstatus
);
5137 tcg_temp_free_i32(tcg_shift
);
5140 /* Floating point <-> fixed point conversions
5141 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5142 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5143 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5144 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5146 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5148 int rd
= extract32(insn
, 0, 5);
5149 int rn
= extract32(insn
, 5, 5);
5150 int scale
= extract32(insn
, 10, 6);
5151 int opcode
= extract32(insn
, 16, 3);
5152 int rmode
= extract32(insn
, 19, 2);
5153 int type
= extract32(insn
, 22, 2);
5154 bool sbit
= extract32(insn
, 29, 1);
5155 bool sf
= extract32(insn
, 31, 1);
5158 if (sbit
|| (type
> 1)
5159 || (!sf
&& scale
< 32)) {
5160 unallocated_encoding(s
);
5164 switch ((rmode
<< 3) | opcode
) {
5165 case 0x2: /* SCVTF */
5166 case 0x3: /* UCVTF */
5169 case 0x18: /* FCVTZS */
5170 case 0x19: /* FCVTZU */
5174 unallocated_encoding(s
);
5178 if (!fp_access_check(s
)) {
5182 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5185 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5187 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5188 * without conversion.
5192 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5198 TCGv_i64 tmp
= tcg_temp_new_i64();
5199 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5200 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5201 tcg_gen_movi_i64(tmp
, 0);
5202 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5203 tcg_temp_free_i64(tmp
);
5209 TCGv_i64 tmp
= tcg_const_i64(0);
5210 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5211 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5212 tcg_temp_free_i64(tmp
);
5216 /* 64 bit to top half. */
5217 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5221 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5226 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5230 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5233 /* 64 bits from top half */
5234 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5240 /* Floating point <-> integer conversions
5241 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5242 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5243 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5244 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5246 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5248 int rd
= extract32(insn
, 0, 5);
5249 int rn
= extract32(insn
, 5, 5);
5250 int opcode
= extract32(insn
, 16, 3);
5251 int rmode
= extract32(insn
, 19, 2);
5252 int type
= extract32(insn
, 22, 2);
5253 bool sbit
= extract32(insn
, 29, 1);
5254 bool sf
= extract32(insn
, 31, 1);
5257 unallocated_encoding(s
);
5263 bool itof
= opcode
& 1;
5266 unallocated_encoding(s
);
5270 switch (sf
<< 3 | type
<< 1 | rmode
) {
5271 case 0x0: /* 32 bit */
5272 case 0xa: /* 64 bit */
5273 case 0xd: /* 64 bit to top half of quad */
5276 /* all other sf/type/rmode combinations are invalid */
5277 unallocated_encoding(s
);
5281 if (!fp_access_check(s
)) {
5284 handle_fmov(s
, rd
, rn
, type
, itof
);
5286 /* actual FP conversions */
5287 bool itof
= extract32(opcode
, 1, 1);
5289 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5290 unallocated_encoding(s
);
5294 if (!fp_access_check(s
)) {
5297 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5301 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5302 * 31 30 29 28 25 24 0
5303 * +---+---+---+---------+-----------------------------+
5304 * | | 0 | | 1 1 1 1 | |
5305 * +---+---+---+---------+-----------------------------+
5307 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5309 if (extract32(insn
, 24, 1)) {
5310 /* Floating point data-processing (3 source) */
5311 disas_fp_3src(s
, insn
);
5312 } else if (extract32(insn
, 21, 1) == 0) {
5313 /* Floating point to fixed point conversions */
5314 disas_fp_fixed_conv(s
, insn
);
5316 switch (extract32(insn
, 10, 2)) {
5318 /* Floating point conditional compare */
5319 disas_fp_ccomp(s
, insn
);
5322 /* Floating point data-processing (2 source) */
5323 disas_fp_2src(s
, insn
);
5326 /* Floating point conditional select */
5327 disas_fp_csel(s
, insn
);
5330 switch (ctz32(extract32(insn
, 12, 4))) {
5331 case 0: /* [15:12] == xxx1 */
5332 /* Floating point immediate */
5333 disas_fp_imm(s
, insn
);
5335 case 1: /* [15:12] == xx10 */
5336 /* Floating point compare */
5337 disas_fp_compare(s
, insn
);
5339 case 2: /* [15:12] == x100 */
5340 /* Floating point data-processing (1 source) */
5341 disas_fp_1src(s
, insn
);
5343 case 3: /* [15:12] == 1000 */
5344 unallocated_encoding(s
);
5346 default: /* [15:12] == 0000 */
5347 /* Floating point <-> integer conversions */
5348 disas_fp_int_conv(s
, insn
);
5356 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5359 /* Extract 64 bits from the middle of two concatenated 64 bit
5360 * vector register slices left:right. The extracted bits start
5361 * at 'pos' bits into the right (least significant) side.
5362 * We return the result in tcg_right, and guarantee not to
5365 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5366 assert(pos
> 0 && pos
< 64);
5368 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5369 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5370 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5372 tcg_temp_free_i64(tcg_tmp
);
5376 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5377 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5378 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5379 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5381 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5383 int is_q
= extract32(insn
, 30, 1);
5384 int op2
= extract32(insn
, 22, 2);
5385 int imm4
= extract32(insn
, 11, 4);
5386 int rm
= extract32(insn
, 16, 5);
5387 int rn
= extract32(insn
, 5, 5);
5388 int rd
= extract32(insn
, 0, 5);
5389 int pos
= imm4
<< 3;
5390 TCGv_i64 tcg_resl
, tcg_resh
;
5392 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5393 unallocated_encoding(s
);
5397 if (!fp_access_check(s
)) {
5401 tcg_resh
= tcg_temp_new_i64();
5402 tcg_resl
= tcg_temp_new_i64();
5404 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5405 * either extracting 128 bits from a 128:128 concatenation, or
5406 * extracting 64 bits from a 64:64 concatenation.
5409 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5411 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5412 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5414 tcg_gen_movi_i64(tcg_resh
, 0);
5421 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5422 EltPosns
*elt
= eltposns
;
5429 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5431 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5434 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5435 tcg_hh
= tcg_temp_new_i64();
5436 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5437 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5438 tcg_temp_free_i64(tcg_hh
);
5442 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5443 tcg_temp_free_i64(tcg_resl
);
5444 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5445 tcg_temp_free_i64(tcg_resh
);
5449 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5450 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5451 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5452 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5454 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5456 int op2
= extract32(insn
, 22, 2);
5457 int is_q
= extract32(insn
, 30, 1);
5458 int rm
= extract32(insn
, 16, 5);
5459 int rn
= extract32(insn
, 5, 5);
5460 int rd
= extract32(insn
, 0, 5);
5461 int is_tblx
= extract32(insn
, 12, 1);
5462 int len
= extract32(insn
, 13, 2);
5463 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5464 TCGv_i32 tcg_regno
, tcg_numregs
;
5467 unallocated_encoding(s
);
5471 if (!fp_access_check(s
)) {
5475 /* This does a table lookup: for every byte element in the input
5476 * we index into a table formed from up to four vector registers,
5477 * and then the output is the result of the lookups. Our helper
5478 * function does the lookup operation for a single 64 bit part of
5481 tcg_resl
= tcg_temp_new_i64();
5482 tcg_resh
= tcg_temp_new_i64();
5485 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5487 tcg_gen_movi_i64(tcg_resl
, 0);
5489 if (is_tblx
&& is_q
) {
5490 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5492 tcg_gen_movi_i64(tcg_resh
, 0);
5495 tcg_idx
= tcg_temp_new_i64();
5496 tcg_regno
= tcg_const_i32(rn
);
5497 tcg_numregs
= tcg_const_i32(len
+ 1);
5498 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5499 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5500 tcg_regno
, tcg_numregs
);
5502 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5503 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5504 tcg_regno
, tcg_numregs
);
5506 tcg_temp_free_i64(tcg_idx
);
5507 tcg_temp_free_i32(tcg_regno
);
5508 tcg_temp_free_i32(tcg_numregs
);
5510 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5511 tcg_temp_free_i64(tcg_resl
);
5512 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5513 tcg_temp_free_i64(tcg_resh
);
5517 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5518 * +---+---+-------------+------+---+------+---+------------------+------+
5519 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5520 * +---+---+-------------+------+---+------+---+------------------+------+
5522 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5524 int rd
= extract32(insn
, 0, 5);
5525 int rn
= extract32(insn
, 5, 5);
5526 int rm
= extract32(insn
, 16, 5);
5527 int size
= extract32(insn
, 22, 2);
5528 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5529 * bit 2 indicates 1 vs 2 variant of the insn.
5531 int opcode
= extract32(insn
, 12, 2);
5532 bool part
= extract32(insn
, 14, 1);
5533 bool is_q
= extract32(insn
, 30, 1);
5534 int esize
= 8 << size
;
5536 int datasize
= is_q
? 128 : 64;
5537 int elements
= datasize
/ esize
;
5538 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5540 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5541 unallocated_encoding(s
);
5545 if (!fp_access_check(s
)) {
5549 tcg_resl
= tcg_const_i64(0);
5550 tcg_resh
= tcg_const_i64(0);
5551 tcg_res
= tcg_temp_new_i64();
5553 for (i
= 0; i
< elements
; i
++) {
5555 case 1: /* UZP1/2 */
5557 int midpoint
= elements
/ 2;
5559 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5561 read_vec_element(s
, tcg_res
, rm
,
5562 2 * (i
- midpoint
) + part
, size
);
5566 case 2: /* TRN1/2 */
5568 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5570 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5573 case 3: /* ZIP1/2 */
5575 int base
= part
* elements
/ 2;
5577 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5579 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5584 g_assert_not_reached();
5589 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5590 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5592 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5593 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5597 tcg_temp_free_i64(tcg_res
);
5599 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5600 tcg_temp_free_i64(tcg_resl
);
5601 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5602 tcg_temp_free_i64(tcg_resh
);
5605 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5606 int opc
, bool is_min
, TCGv_ptr fpst
)
5608 /* Helper function for disas_simd_across_lanes: do a single precision
5609 * min/max operation on the specified two inputs,
5610 * and return the result in tcg_elt1.
5614 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5616 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5621 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5623 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5628 /* AdvSIMD across lanes
5629 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5630 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5631 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5632 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5634 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5636 int rd
= extract32(insn
, 0, 5);
5637 int rn
= extract32(insn
, 5, 5);
5638 int size
= extract32(insn
, 22, 2);
5639 int opcode
= extract32(insn
, 12, 5);
5640 bool is_q
= extract32(insn
, 30, 1);
5641 bool is_u
= extract32(insn
, 29, 1);
5643 bool is_min
= false;
5647 TCGv_i64 tcg_res
, tcg_elt
;
5650 case 0x1b: /* ADDV */
5652 unallocated_encoding(s
);
5656 case 0x3: /* SADDLV, UADDLV */
5657 case 0xa: /* SMAXV, UMAXV */
5658 case 0x1a: /* SMINV, UMINV */
5659 if (size
== 3 || (size
== 2 && !is_q
)) {
5660 unallocated_encoding(s
);
5664 case 0xc: /* FMAXNMV, FMINNMV */
5665 case 0xf: /* FMAXV, FMINV */
5666 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5667 unallocated_encoding(s
);
5670 /* Bit 1 of size field encodes min vs max, and actual size is always
5671 * 32 bits: adjust the size variable so following code can rely on it
5673 is_min
= extract32(size
, 1, 1);
5678 unallocated_encoding(s
);
5682 if (!fp_access_check(s
)) {
5687 elements
= (is_q
? 128 : 64) / esize
;
5689 tcg_res
= tcg_temp_new_i64();
5690 tcg_elt
= tcg_temp_new_i64();
5692 /* These instructions operate across all lanes of a vector
5693 * to produce a single result. We can guarantee that a 64
5694 * bit intermediate is sufficient:
5695 * + for [US]ADDLV the maximum element size is 32 bits, and
5696 * the result type is 64 bits
5697 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5698 * same as the element size, which is 32 bits at most
5699 * For the integer operations we can choose to work at 64
5700 * or 32 bits and truncate at the end; for simplicity
5701 * we use 64 bits always. The floating point
5702 * ops do require 32 bit intermediates, though.
5705 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5707 for (i
= 1; i
< elements
; i
++) {
5708 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5711 case 0x03: /* SADDLV / UADDLV */
5712 case 0x1b: /* ADDV */
5713 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5715 case 0x0a: /* SMAXV / UMAXV */
5716 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5718 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5720 case 0x1a: /* SMINV / UMINV */
5721 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5723 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5727 g_assert_not_reached();
5732 /* Floating point ops which work on 32 bit (single) intermediates.
5733 * Note that correct NaN propagation requires that we do these
5734 * operations in exactly the order specified by the pseudocode.
5736 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5737 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5738 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5739 TCGv_ptr fpst
= get_fpstatus_ptr();
5741 assert(esize
== 32);
5742 assert(elements
== 4);
5744 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5745 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5746 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5747 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5749 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5751 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5752 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5753 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5754 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5756 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5758 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5760 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5761 tcg_temp_free_i32(tcg_elt1
);
5762 tcg_temp_free_i32(tcg_elt2
);
5763 tcg_temp_free_i32(tcg_elt3
);
5764 tcg_temp_free_ptr(fpst
);
5767 tcg_temp_free_i64(tcg_elt
);
5769 /* Now truncate the result to the width required for the final output */
5770 if (opcode
== 0x03) {
5771 /* SADDLV, UADDLV: result is 2*esize */
5777 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5780 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5783 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5788 g_assert_not_reached();
5791 write_fp_dreg(s
, rd
, tcg_res
);
5792 tcg_temp_free_i64(tcg_res
);
5795 /* DUP (Element, Vector)
5797 * 31 30 29 21 20 16 15 10 9 5 4 0
5798 * +---+---+-------------------+--------+-------------+------+------+
5799 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5800 * +---+---+-------------------+--------+-------------+------+------+
5802 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5804 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5807 int size
= ctz32(imm5
);
5808 int esize
= 8 << size
;
5809 int elements
= (is_q
? 128 : 64) / esize
;
5813 if (size
> 3 || (size
== 3 && !is_q
)) {
5814 unallocated_encoding(s
);
5818 if (!fp_access_check(s
)) {
5822 index
= imm5
>> (size
+ 1);
5824 tmp
= tcg_temp_new_i64();
5825 read_vec_element(s
, tmp
, rn
, index
, size
);
5827 for (i
= 0; i
< elements
; i
++) {
5828 write_vec_element(s
, tmp
, rd
, i
, size
);
5832 clear_vec_high(s
, rd
);
5835 tcg_temp_free_i64(tmp
);
5838 /* DUP (element, scalar)
5839 * 31 21 20 16 15 10 9 5 4 0
5840 * +-----------------------+--------+-------------+------+------+
5841 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5842 * +-----------------------+--------+-------------+------+------+
5844 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5847 int size
= ctz32(imm5
);
5852 unallocated_encoding(s
);
5856 if (!fp_access_check(s
)) {
5860 index
= imm5
>> (size
+ 1);
5862 /* This instruction just extracts the specified element and
5863 * zero-extends it into the bottom of the destination register.
5865 tmp
= tcg_temp_new_i64();
5866 read_vec_element(s
, tmp
, rn
, index
, size
);
5867 write_fp_dreg(s
, rd
, tmp
);
5868 tcg_temp_free_i64(tmp
);
5873 * 31 30 29 21 20 16 15 10 9 5 4 0
5874 * +---+---+-------------------+--------+-------------+------+------+
5875 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5876 * +---+---+-------------------+--------+-------------+------+------+
5878 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5880 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5883 int size
= ctz32(imm5
);
5884 int esize
= 8 << size
;
5885 int elements
= (is_q
? 128 : 64)/esize
;
5888 if (size
> 3 || ((size
== 3) && !is_q
)) {
5889 unallocated_encoding(s
);
5893 if (!fp_access_check(s
)) {
5897 for (i
= 0; i
< elements
; i
++) {
5898 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5901 clear_vec_high(s
, rd
);
5907 * 31 21 20 16 15 14 11 10 9 5 4 0
5908 * +-----------------------+--------+------------+---+------+------+
5909 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5910 * +-----------------------+--------+------------+---+------+------+
5912 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5913 * index: encoded in imm5<4:size+1>
5915 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5918 int size
= ctz32(imm5
);
5919 int src_index
, dst_index
;
5923 unallocated_encoding(s
);
5927 if (!fp_access_check(s
)) {
5931 dst_index
= extract32(imm5
, 1+size
, 5);
5932 src_index
= extract32(imm4
, size
, 4);
5934 tmp
= tcg_temp_new_i64();
5936 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5937 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5939 tcg_temp_free_i64(tmp
);
5945 * 31 21 20 16 15 10 9 5 4 0
5946 * +-----------------------+--------+-------------+------+------+
5947 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5948 * +-----------------------+--------+-------------+------+------+
5950 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5951 * index: encoded in imm5<4:size+1>
5953 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5955 int size
= ctz32(imm5
);
5959 unallocated_encoding(s
);
5963 if (!fp_access_check(s
)) {
5967 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5968 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5975 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5976 * +---+---+-------------------+--------+-------------+------+------+
5977 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5978 * +---+---+-------------------+--------+-------------+------+------+
5980 * U: unsigned when set
5981 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5983 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5984 int rn
, int rd
, int imm5
)
5986 int size
= ctz32(imm5
);
5990 /* Check for UnallocatedEncodings */
5992 if (size
> 2 || (size
== 2 && !is_q
)) {
5993 unallocated_encoding(s
);
5998 || (size
< 3 && is_q
)
5999 || (size
== 3 && !is_q
)) {
6000 unallocated_encoding(s
);
6005 if (!fp_access_check(s
)) {
6009 element
= extract32(imm5
, 1+size
, 4);
6011 tcg_rd
= cpu_reg(s
, rd
);
6012 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6013 if (is_signed
&& !is_q
) {
6014 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6019 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6020 * +---+---+----+-----------------+------+---+------+---+------+------+
6021 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6022 * +---+---+----+-----------------+------+---+------+---+------+------+
6024 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6026 int rd
= extract32(insn
, 0, 5);
6027 int rn
= extract32(insn
, 5, 5);
6028 int imm4
= extract32(insn
, 11, 4);
6029 int op
= extract32(insn
, 29, 1);
6030 int is_q
= extract32(insn
, 30, 1);
6031 int imm5
= extract32(insn
, 16, 5);
6036 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6038 unallocated_encoding(s
);
6043 /* DUP (element - vector) */
6044 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6048 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6053 handle_simd_insg(s
, rd
, rn
, imm5
);
6055 unallocated_encoding(s
);
6060 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6061 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6064 unallocated_encoding(s
);
6070 /* AdvSIMD modified immediate
6071 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6072 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6073 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6074 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6076 * There are a number of operations that can be carried out here:
6077 * MOVI - move (shifted) imm into register
6078 * MVNI - move inverted (shifted) imm into register
6079 * ORR - bitwise OR of (shifted) imm with register
6080 * BIC - bitwise clear of (shifted) imm with register
6082 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6084 int rd
= extract32(insn
, 0, 5);
6085 int cmode
= extract32(insn
, 12, 4);
6086 int cmode_3_1
= extract32(cmode
, 1, 3);
6087 int cmode_0
= extract32(cmode
, 0, 1);
6088 int o2
= extract32(insn
, 11, 1);
6089 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6090 bool is_neg
= extract32(insn
, 29, 1);
6091 bool is_q
= extract32(insn
, 30, 1);
6093 TCGv_i64 tcg_rd
, tcg_imm
;
6096 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6097 unallocated_encoding(s
);
6101 if (!fp_access_check(s
)) {
6105 /* See AdvSIMDExpandImm() in ARM ARM */
6106 switch (cmode_3_1
) {
6107 case 0: /* Replicate(Zeros(24):imm8, 2) */
6108 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6109 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6110 case 3: /* Replicate(imm8:Zeros(24), 2) */
6112 int shift
= cmode_3_1
* 8;
6113 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6116 case 4: /* Replicate(Zeros(8):imm8, 4) */
6117 case 5: /* Replicate(imm8:Zeros(8), 4) */
6119 int shift
= (cmode_3_1
& 0x1) * 8;
6120 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6125 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6126 imm
= (abcdefgh
<< 16) | 0xffff;
6128 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6129 imm
= (abcdefgh
<< 8) | 0xff;
6131 imm
= bitfield_replicate(imm
, 32);
6134 if (!cmode_0
&& !is_neg
) {
6135 imm
= bitfield_replicate(abcdefgh
, 8);
6136 } else if (!cmode_0
&& is_neg
) {
6139 for (i
= 0; i
< 8; i
++) {
6140 if ((abcdefgh
) & (1 << i
)) {
6141 imm
|= 0xffULL
<< (i
* 8);
6144 } else if (cmode_0
) {
6146 imm
= (abcdefgh
& 0x3f) << 48;
6147 if (abcdefgh
& 0x80) {
6148 imm
|= 0x8000000000000000ULL
;
6150 if (abcdefgh
& 0x40) {
6151 imm
|= 0x3fc0000000000000ULL
;
6153 imm
|= 0x4000000000000000ULL
;
6156 imm
= (abcdefgh
& 0x3f) << 19;
6157 if (abcdefgh
& 0x80) {
6160 if (abcdefgh
& 0x40) {
6171 if (cmode_3_1
!= 7 && is_neg
) {
6175 tcg_imm
= tcg_const_i64(imm
);
6176 tcg_rd
= new_tmp_a64(s
);
6178 for (i
= 0; i
< 2; i
++) {
6179 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6181 if (i
== 1 && !is_q
) {
6182 /* non-quad ops clear high half of vector */
6183 tcg_gen_movi_i64(tcg_rd
, 0);
6184 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6185 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6188 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6191 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6195 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6197 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6200 tcg_temp_free_i64(tcg_imm
);
6203 /* AdvSIMD scalar copy
6204 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6205 * +-----+----+-----------------+------+---+------+---+------+------+
6206 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6207 * +-----+----+-----------------+------+---+------+---+------+------+
6209 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6211 int rd
= extract32(insn
, 0, 5);
6212 int rn
= extract32(insn
, 5, 5);
6213 int imm4
= extract32(insn
, 11, 4);
6214 int imm5
= extract32(insn
, 16, 5);
6215 int op
= extract32(insn
, 29, 1);
6217 if (op
!= 0 || imm4
!= 0) {
6218 unallocated_encoding(s
);
6222 /* DUP (element, scalar) */
6223 handle_simd_dupes(s
, rd
, rn
, imm5
);
6226 /* AdvSIMD scalar pairwise
6227 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6228 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6229 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6230 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6232 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6234 int u
= extract32(insn
, 29, 1);
6235 int size
= extract32(insn
, 22, 2);
6236 int opcode
= extract32(insn
, 12, 5);
6237 int rn
= extract32(insn
, 5, 5);
6238 int rd
= extract32(insn
, 0, 5);
6241 /* For some ops (the FP ones), size[1] is part of the encoding.
6242 * For ADDP strictly it is not but size[1] is always 1 for valid
6245 opcode
|= (extract32(size
, 1, 1) << 5);
6248 case 0x3b: /* ADDP */
6249 if (u
|| size
!= 3) {
6250 unallocated_encoding(s
);
6253 if (!fp_access_check(s
)) {
6257 TCGV_UNUSED_PTR(fpst
);
6259 case 0xc: /* FMAXNMP */
6260 case 0xd: /* FADDP */
6261 case 0xf: /* FMAXP */
6262 case 0x2c: /* FMINNMP */
6263 case 0x2f: /* FMINP */
6264 /* FP op, size[0] is 32 or 64 bit */
6266 unallocated_encoding(s
);
6269 if (!fp_access_check(s
)) {
6273 size
= extract32(size
, 0, 1) ? 3 : 2;
6274 fpst
= get_fpstatus_ptr();
6277 unallocated_encoding(s
);
6282 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6283 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6284 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6286 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6287 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6290 case 0x3b: /* ADDP */
6291 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6293 case 0xc: /* FMAXNMP */
6294 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6296 case 0xd: /* FADDP */
6297 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6299 case 0xf: /* FMAXP */
6300 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6302 case 0x2c: /* FMINNMP */
6303 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6305 case 0x2f: /* FMINP */
6306 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6309 g_assert_not_reached();
6312 write_fp_dreg(s
, rd
, tcg_res
);
6314 tcg_temp_free_i64(tcg_op1
);
6315 tcg_temp_free_i64(tcg_op2
);
6316 tcg_temp_free_i64(tcg_res
);
6318 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6319 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6320 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6322 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6323 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6326 case 0xc: /* FMAXNMP */
6327 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6329 case 0xd: /* FADDP */
6330 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6332 case 0xf: /* FMAXP */
6333 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6335 case 0x2c: /* FMINNMP */
6336 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6338 case 0x2f: /* FMINP */
6339 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6342 g_assert_not_reached();
6345 write_fp_sreg(s
, rd
, tcg_res
);
6347 tcg_temp_free_i32(tcg_op1
);
6348 tcg_temp_free_i32(tcg_op2
);
6349 tcg_temp_free_i32(tcg_res
);
6352 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6353 tcg_temp_free_ptr(fpst
);
6358 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6360 * This code is handles the common shifting code and is used by both
6361 * the vector and scalar code.
6363 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6364 TCGv_i64 tcg_rnd
, bool accumulate
,
6365 bool is_u
, int size
, int shift
)
6367 bool extended_result
= false;
6368 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6370 TCGv_i64 tcg_src_hi
;
6372 if (round
&& size
== 3) {
6373 extended_result
= true;
6374 ext_lshift
= 64 - shift
;
6375 tcg_src_hi
= tcg_temp_new_i64();
6376 } else if (shift
== 64) {
6377 if (!accumulate
&& is_u
) {
6378 /* result is zero */
6379 tcg_gen_movi_i64(tcg_res
, 0);
6384 /* Deal with the rounding step */
6386 if (extended_result
) {
6387 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6389 /* take care of sign extending tcg_res */
6390 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6391 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6392 tcg_src
, tcg_src_hi
,
6395 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6399 tcg_temp_free_i64(tcg_zero
);
6401 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6405 /* Now do the shift right */
6406 if (round
&& extended_result
) {
6407 /* extended case, >64 bit precision required */
6408 if (ext_lshift
== 0) {
6409 /* special case, only high bits matter */
6410 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6412 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6413 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6414 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6419 /* essentially shifting in 64 zeros */
6420 tcg_gen_movi_i64(tcg_src
, 0);
6422 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6426 /* effectively extending the sign-bit */
6427 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6429 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6435 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6437 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6440 if (extended_result
) {
6441 tcg_temp_free_i64(tcg_src_hi
);
6445 /* Common SHL/SLI - Shift left with an optional insert */
6446 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6447 bool insert
, int shift
)
6449 if (insert
) { /* SLI */
6450 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6452 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6456 /* SRI: shift right with insert */
6457 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6458 int size
, int shift
)
6460 int esize
= 8 << size
;
6462 /* shift count same as element size is valid but does nothing;
6463 * special case to avoid potential shift by 64.
6465 if (shift
!= esize
) {
6466 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6467 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6471 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6472 static void handle_scalar_simd_shri(DisasContext
*s
,
6473 bool is_u
, int immh
, int immb
,
6474 int opcode
, int rn
, int rd
)
6477 int immhb
= immh
<< 3 | immb
;
6478 int shift
= 2 * (8 << size
) - immhb
;
6479 bool accumulate
= false;
6481 bool insert
= false;
6486 if (!extract32(immh
, 3, 1)) {
6487 unallocated_encoding(s
);
6491 if (!fp_access_check(s
)) {
6496 case 0x02: /* SSRA / USRA (accumulate) */
6499 case 0x04: /* SRSHR / URSHR (rounding) */
6502 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6503 accumulate
= round
= true;
6505 case 0x08: /* SRI */
6511 uint64_t round_const
= 1ULL << (shift
- 1);
6512 tcg_round
= tcg_const_i64(round_const
);
6514 TCGV_UNUSED_I64(tcg_round
);
6517 tcg_rn
= read_fp_dreg(s
, rn
);
6518 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6521 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6523 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6524 accumulate
, is_u
, size
, shift
);
6527 write_fp_dreg(s
, rd
, tcg_rd
);
6529 tcg_temp_free_i64(tcg_rn
);
6530 tcg_temp_free_i64(tcg_rd
);
6532 tcg_temp_free_i64(tcg_round
);
6536 /* SHL/SLI - Scalar shift left */
6537 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6538 int immh
, int immb
, int opcode
,
6541 int size
= 32 - clz32(immh
) - 1;
6542 int immhb
= immh
<< 3 | immb
;
6543 int shift
= immhb
- (8 << size
);
6544 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6545 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6547 if (!extract32(immh
, 3, 1)) {
6548 unallocated_encoding(s
);
6552 if (!fp_access_check(s
)) {
6556 tcg_rn
= read_fp_dreg(s
, rn
);
6557 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6559 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6561 write_fp_dreg(s
, rd
, tcg_rd
);
6563 tcg_temp_free_i64(tcg_rn
);
6564 tcg_temp_free_i64(tcg_rd
);
6567 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6568 * (signed/unsigned) narrowing */
6569 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6570 bool is_u_shift
, bool is_u_narrow
,
6571 int immh
, int immb
, int opcode
,
6574 int immhb
= immh
<< 3 | immb
;
6575 int size
= 32 - clz32(immh
) - 1;
6576 int esize
= 8 << size
;
6577 int shift
= (2 * esize
) - immhb
;
6578 int elements
= is_scalar
? 1 : (64 / esize
);
6579 bool round
= extract32(opcode
, 0, 1);
6580 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6581 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6582 TCGv_i32 tcg_rd_narrowed
;
6585 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6586 { gen_helper_neon_narrow_sat_s8
,
6587 gen_helper_neon_unarrow_sat8
},
6588 { gen_helper_neon_narrow_sat_s16
,
6589 gen_helper_neon_unarrow_sat16
},
6590 { gen_helper_neon_narrow_sat_s32
,
6591 gen_helper_neon_unarrow_sat32
},
6594 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6595 gen_helper_neon_narrow_sat_u8
,
6596 gen_helper_neon_narrow_sat_u16
,
6597 gen_helper_neon_narrow_sat_u32
,
6600 NeonGenNarrowEnvFn
*narrowfn
;
6606 if (extract32(immh
, 3, 1)) {
6607 unallocated_encoding(s
);
6611 if (!fp_access_check(s
)) {
6616 narrowfn
= unsigned_narrow_fns
[size
];
6618 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6621 tcg_rn
= tcg_temp_new_i64();
6622 tcg_rd
= tcg_temp_new_i64();
6623 tcg_rd_narrowed
= tcg_temp_new_i32();
6624 tcg_final
= tcg_const_i64(0);
6627 uint64_t round_const
= 1ULL << (shift
- 1);
6628 tcg_round
= tcg_const_i64(round_const
);
6630 TCGV_UNUSED_I64(tcg_round
);
6633 for (i
= 0; i
< elements
; i
++) {
6634 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6635 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6636 false, is_u_shift
, size
+1, shift
);
6637 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6638 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6639 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6643 clear_vec_high(s
, rd
);
6644 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6646 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6650 tcg_temp_free_i64(tcg_round
);
6652 tcg_temp_free_i64(tcg_rn
);
6653 tcg_temp_free_i64(tcg_rd
);
6654 tcg_temp_free_i32(tcg_rd_narrowed
);
6655 tcg_temp_free_i64(tcg_final
);
6659 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6660 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6661 bool src_unsigned
, bool dst_unsigned
,
6662 int immh
, int immb
, int rn
, int rd
)
6664 int immhb
= immh
<< 3 | immb
;
6665 int size
= 32 - clz32(immh
) - 1;
6666 int shift
= immhb
- (8 << size
);
6670 assert(!(scalar
&& is_q
));
6673 if (!is_q
&& extract32(immh
, 3, 1)) {
6674 unallocated_encoding(s
);
6678 /* Since we use the variable-shift helpers we must
6679 * replicate the shift count into each element of
6680 * the tcg_shift value.
6684 shift
|= shift
<< 8;
6687 shift
|= shift
<< 16;
6693 g_assert_not_reached();
6697 if (!fp_access_check(s
)) {
6702 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6703 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6704 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6705 { NULL
, gen_helper_neon_qshl_u64
},
6707 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6708 int maxpass
= is_q
? 2 : 1;
6710 for (pass
= 0; pass
< maxpass
; pass
++) {
6711 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6713 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6714 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6715 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6717 tcg_temp_free_i64(tcg_op
);
6719 tcg_temp_free_i64(tcg_shift
);
6722 clear_vec_high(s
, rd
);
6725 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6726 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6728 { gen_helper_neon_qshl_s8
,
6729 gen_helper_neon_qshl_s16
,
6730 gen_helper_neon_qshl_s32
},
6731 { gen_helper_neon_qshlu_s8
,
6732 gen_helper_neon_qshlu_s16
,
6733 gen_helper_neon_qshlu_s32
}
6735 { NULL
, NULL
, NULL
},
6736 { gen_helper_neon_qshl_u8
,
6737 gen_helper_neon_qshl_u16
,
6738 gen_helper_neon_qshl_u32
}
6741 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6742 TCGMemOp memop
= scalar
? size
: MO_32
;
6743 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6745 for (pass
= 0; pass
< maxpass
; pass
++) {
6746 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6748 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6749 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6753 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6756 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6761 g_assert_not_reached();
6763 write_fp_sreg(s
, rd
, tcg_op
);
6765 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6768 tcg_temp_free_i32(tcg_op
);
6770 tcg_temp_free_i32(tcg_shift
);
6772 if (!is_q
&& !scalar
) {
6773 clear_vec_high(s
, rd
);
6778 /* Common vector code for handling integer to FP conversion */
6779 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6780 int elements
, int is_signed
,
6781 int fracbits
, int size
)
6783 bool is_double
= size
== 3 ? true : false;
6784 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6785 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6786 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6787 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6790 for (pass
= 0; pass
< elements
; pass
++) {
6791 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6794 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6796 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6797 tcg_shift
, tcg_fpst
);
6799 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6800 tcg_shift
, tcg_fpst
);
6802 if (elements
== 1) {
6803 write_fp_dreg(s
, rd
, tcg_double
);
6805 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6807 tcg_temp_free_i64(tcg_double
);
6809 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6811 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6812 tcg_shift
, tcg_fpst
);
6814 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6815 tcg_shift
, tcg_fpst
);
6817 if (elements
== 1) {
6818 write_fp_sreg(s
, rd
, tcg_single
);
6820 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6822 tcg_temp_free_i32(tcg_single
);
6826 if (!is_double
&& elements
== 2) {
6827 clear_vec_high(s
, rd
);
6830 tcg_temp_free_i64(tcg_int
);
6831 tcg_temp_free_ptr(tcg_fpst
);
6832 tcg_temp_free_i32(tcg_shift
);
6835 /* UCVTF/SCVTF - Integer to FP conversion */
6836 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6837 bool is_q
, bool is_u
,
6838 int immh
, int immb
, int opcode
,
6841 bool is_double
= extract32(immh
, 3, 1);
6842 int size
= is_double
? MO_64
: MO_32
;
6844 int immhb
= immh
<< 3 | immb
;
6845 int fracbits
= (is_double
? 128 : 64) - immhb
;
6847 if (!extract32(immh
, 2, 2)) {
6848 unallocated_encoding(s
);
6855 elements
= is_double
? 2 : is_q
? 4 : 2;
6856 if (is_double
&& !is_q
) {
6857 unallocated_encoding(s
);
6862 if (!fp_access_check(s
)) {
6866 /* immh == 0 would be a failure of the decode logic */
6869 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6872 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6873 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6874 bool is_q
, bool is_u
,
6875 int immh
, int immb
, int rn
, int rd
)
6877 bool is_double
= extract32(immh
, 3, 1);
6878 int immhb
= immh
<< 3 | immb
;
6879 int fracbits
= (is_double
? 128 : 64) - immhb
;
6881 TCGv_ptr tcg_fpstatus
;
6882 TCGv_i32 tcg_rmode
, tcg_shift
;
6884 if (!extract32(immh
, 2, 2)) {
6885 unallocated_encoding(s
);
6889 if (!is_scalar
&& !is_q
&& is_double
) {
6890 unallocated_encoding(s
);
6894 if (!fp_access_check(s
)) {
6898 assert(!(is_scalar
&& is_q
));
6900 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6901 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6902 tcg_fpstatus
= get_fpstatus_ptr();
6903 tcg_shift
= tcg_const_i32(fracbits
);
6906 int maxpass
= is_scalar
? 1 : 2;
6908 for (pass
= 0; pass
< maxpass
; pass
++) {
6909 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6911 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6913 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6915 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6917 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6918 tcg_temp_free_i64(tcg_op
);
6921 clear_vec_high(s
, rd
);
6924 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6925 for (pass
= 0; pass
< maxpass
; pass
++) {
6926 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6928 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6930 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6932 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6935 write_fp_sreg(s
, rd
, tcg_op
);
6937 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6939 tcg_temp_free_i32(tcg_op
);
6941 if (!is_q
&& !is_scalar
) {
6942 clear_vec_high(s
, rd
);
6946 tcg_temp_free_ptr(tcg_fpstatus
);
6947 tcg_temp_free_i32(tcg_shift
);
6948 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6949 tcg_temp_free_i32(tcg_rmode
);
6952 /* AdvSIMD scalar shift by immediate
6953 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6954 * +-----+---+-------------+------+------+--------+---+------+------+
6955 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6956 * +-----+---+-------------+------+------+--------+---+------+------+
6958 * This is the scalar version so it works on a fixed sized registers
6960 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6962 int rd
= extract32(insn
, 0, 5);
6963 int rn
= extract32(insn
, 5, 5);
6964 int opcode
= extract32(insn
, 11, 5);
6965 int immb
= extract32(insn
, 16, 3);
6966 int immh
= extract32(insn
, 19, 4);
6967 bool is_u
= extract32(insn
, 29, 1);
6970 unallocated_encoding(s
);
6975 case 0x08: /* SRI */
6977 unallocated_encoding(s
);
6981 case 0x00: /* SSHR / USHR */
6982 case 0x02: /* SSRA / USRA */
6983 case 0x04: /* SRSHR / URSHR */
6984 case 0x06: /* SRSRA / URSRA */
6985 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6987 case 0x0a: /* SHL / SLI */
6988 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6990 case 0x1c: /* SCVTF, UCVTF */
6991 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6994 case 0x10: /* SQSHRUN, SQSHRUN2 */
6995 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6997 unallocated_encoding(s
);
7000 handle_vec_simd_sqshrn(s
, true, false, false, true,
7001 immh
, immb
, opcode
, rn
, rd
);
7003 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7004 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7005 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7006 immh
, immb
, opcode
, rn
, rd
);
7008 case 0xc: /* SQSHLU */
7010 unallocated_encoding(s
);
7013 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7015 case 0xe: /* SQSHL, UQSHL */
7016 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7018 case 0x1f: /* FCVTZS, FCVTZU */
7019 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7022 unallocated_encoding(s
);
7027 /* AdvSIMD scalar three different
7028 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7029 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7030 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7031 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7033 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7035 bool is_u
= extract32(insn
, 29, 1);
7036 int size
= extract32(insn
, 22, 2);
7037 int opcode
= extract32(insn
, 12, 4);
7038 int rm
= extract32(insn
, 16, 5);
7039 int rn
= extract32(insn
, 5, 5);
7040 int rd
= extract32(insn
, 0, 5);
7043 unallocated_encoding(s
);
7048 case 0x9: /* SQDMLAL, SQDMLAL2 */
7049 case 0xb: /* SQDMLSL, SQDMLSL2 */
7050 case 0xd: /* SQDMULL, SQDMULL2 */
7051 if (size
== 0 || size
== 3) {
7052 unallocated_encoding(s
);
7057 unallocated_encoding(s
);
7061 if (!fp_access_check(s
)) {
7066 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7067 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7068 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7070 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7071 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7073 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7074 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7077 case 0xd: /* SQDMULL, SQDMULL2 */
7079 case 0xb: /* SQDMLSL, SQDMLSL2 */
7080 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7082 case 0x9: /* SQDMLAL, SQDMLAL2 */
7083 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7084 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7088 g_assert_not_reached();
7091 write_fp_dreg(s
, rd
, tcg_res
);
7093 tcg_temp_free_i64(tcg_op1
);
7094 tcg_temp_free_i64(tcg_op2
);
7095 tcg_temp_free_i64(tcg_res
);
7097 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7098 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7099 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7101 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
7102 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
7104 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7105 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7108 case 0xd: /* SQDMULL, SQDMULL2 */
7110 case 0xb: /* SQDMLSL, SQDMLSL2 */
7111 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
7113 case 0x9: /* SQDMLAL, SQDMLAL2 */
7115 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
7116 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
7117 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
7119 tcg_temp_free_i64(tcg_op3
);
7123 g_assert_not_reached();
7126 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7127 write_fp_dreg(s
, rd
, tcg_res
);
7129 tcg_temp_free_i32(tcg_op1
);
7130 tcg_temp_free_i32(tcg_op2
);
7131 tcg_temp_free_i64(tcg_res
);
7135 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
7136 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
7138 /* Handle 64x64->64 opcodes which are shared between the scalar
7139 * and vector 3-same groups. We cover every opcode where size == 3
7140 * is valid in either the three-reg-same (integer, not pairwise)
7141 * or scalar-three-reg-same groups. (Some opcodes are not yet
7147 case 0x1: /* SQADD */
7149 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7151 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7154 case 0x5: /* SQSUB */
7156 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7158 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7161 case 0x6: /* CMGT, CMHI */
7162 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
7163 * We implement this using setcond (test) and then negating.
7165 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
7167 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
7168 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7170 case 0x7: /* CMGE, CMHS */
7171 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
7173 case 0x11: /* CMTST, CMEQ */
7178 /* CMTST : test is "if (X & Y != 0)". */
7179 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7180 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7181 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7183 case 0x8: /* SSHL, USHL */
7185 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7187 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7190 case 0x9: /* SQSHL, UQSHL */
7192 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7194 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7197 case 0xa: /* SRSHL, URSHL */
7199 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7201 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7204 case 0xb: /* SQRSHL, UQRSHL */
7206 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7208 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7211 case 0x10: /* ADD, SUB */
7213 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7215 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7219 g_assert_not_reached();
7223 /* Handle the 3-same-operands float operations; shared by the scalar
7224 * and vector encodings. The caller must filter out any encodings
7225 * not allocated for the encoding it is dealing with.
7227 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7228 int fpopcode
, int rd
, int rn
, int rm
)
7231 TCGv_ptr fpst
= get_fpstatus_ptr();
7233 for (pass
= 0; pass
< elements
; pass
++) {
7236 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7237 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7238 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7240 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7241 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7244 case 0x39: /* FMLS */
7245 /* As usual for ARM, separate negation for fused multiply-add */
7246 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7248 case 0x19: /* FMLA */
7249 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7250 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7253 case 0x18: /* FMAXNM */
7254 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7256 case 0x1a: /* FADD */
7257 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7259 case 0x1b: /* FMULX */
7260 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7262 case 0x1c: /* FCMEQ */
7263 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7265 case 0x1e: /* FMAX */
7266 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7268 case 0x1f: /* FRECPS */
7269 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7271 case 0x38: /* FMINNM */
7272 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7274 case 0x3a: /* FSUB */
7275 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7277 case 0x3e: /* FMIN */
7278 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7280 case 0x3f: /* FRSQRTS */
7281 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7283 case 0x5b: /* FMUL */
7284 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7286 case 0x5c: /* FCMGE */
7287 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7289 case 0x5d: /* FACGE */
7290 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7292 case 0x5f: /* FDIV */
7293 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7295 case 0x7a: /* FABD */
7296 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7297 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7299 case 0x7c: /* FCMGT */
7300 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7302 case 0x7d: /* FACGT */
7303 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7306 g_assert_not_reached();
7309 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7311 tcg_temp_free_i64(tcg_res
);
7312 tcg_temp_free_i64(tcg_op1
);
7313 tcg_temp_free_i64(tcg_op2
);
7316 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7317 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7318 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7320 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7321 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7324 case 0x39: /* FMLS */
7325 /* As usual for ARM, separate negation for fused multiply-add */
7326 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7328 case 0x19: /* FMLA */
7329 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7330 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7333 case 0x1a: /* FADD */
7334 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7336 case 0x1b: /* FMULX */
7337 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7339 case 0x1c: /* FCMEQ */
7340 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7342 case 0x1e: /* FMAX */
7343 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7345 case 0x1f: /* FRECPS */
7346 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7348 case 0x18: /* FMAXNM */
7349 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7351 case 0x38: /* FMINNM */
7352 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7354 case 0x3a: /* FSUB */
7355 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7357 case 0x3e: /* FMIN */
7358 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7360 case 0x3f: /* FRSQRTS */
7361 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7363 case 0x5b: /* FMUL */
7364 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7366 case 0x5c: /* FCMGE */
7367 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7369 case 0x5d: /* FACGE */
7370 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7372 case 0x5f: /* FDIV */
7373 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7375 case 0x7a: /* FABD */
7376 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7377 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7379 case 0x7c: /* FCMGT */
7380 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7382 case 0x7d: /* FACGT */
7383 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7386 g_assert_not_reached();
7389 if (elements
== 1) {
7390 /* scalar single so clear high part */
7391 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7393 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7394 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7395 tcg_temp_free_i64(tcg_tmp
);
7397 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7400 tcg_temp_free_i32(tcg_res
);
7401 tcg_temp_free_i32(tcg_op1
);
7402 tcg_temp_free_i32(tcg_op2
);
7406 tcg_temp_free_ptr(fpst
);
7408 if ((elements
<< size
) < 4) {
7409 /* scalar, or non-quad vector op */
7410 clear_vec_high(s
, rd
);
7414 /* AdvSIMD scalar three same
7415 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7416 * +-----+---+-----------+------+---+------+--------+---+------+------+
7417 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7418 * +-----+---+-----------+------+---+------+--------+---+------+------+
7420 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7422 int rd
= extract32(insn
, 0, 5);
7423 int rn
= extract32(insn
, 5, 5);
7424 int opcode
= extract32(insn
, 11, 5);
7425 int rm
= extract32(insn
, 16, 5);
7426 int size
= extract32(insn
, 22, 2);
7427 bool u
= extract32(insn
, 29, 1);
7430 if (opcode
>= 0x18) {
7431 /* Floating point: U, size[1] and opcode indicate operation */
7432 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7434 case 0x1b: /* FMULX */
7435 case 0x1f: /* FRECPS */
7436 case 0x3f: /* FRSQRTS */
7437 case 0x5d: /* FACGE */
7438 case 0x7d: /* FACGT */
7439 case 0x1c: /* FCMEQ */
7440 case 0x5c: /* FCMGE */
7441 case 0x7c: /* FCMGT */
7442 case 0x7a: /* FABD */
7445 unallocated_encoding(s
);
7449 if (!fp_access_check(s
)) {
7453 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7458 case 0x1: /* SQADD, UQADD */
7459 case 0x5: /* SQSUB, UQSUB */
7460 case 0x9: /* SQSHL, UQSHL */
7461 case 0xb: /* SQRSHL, UQRSHL */
7463 case 0x8: /* SSHL, USHL */
7464 case 0xa: /* SRSHL, URSHL */
7465 case 0x6: /* CMGT, CMHI */
7466 case 0x7: /* CMGE, CMHS */
7467 case 0x11: /* CMTST, CMEQ */
7468 case 0x10: /* ADD, SUB (vector) */
7470 unallocated_encoding(s
);
7474 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7475 if (size
!= 1 && size
!= 2) {
7476 unallocated_encoding(s
);
7481 unallocated_encoding(s
);
7485 if (!fp_access_check(s
)) {
7489 tcg_rd
= tcg_temp_new_i64();
7492 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7493 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7495 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7496 tcg_temp_free_i64(tcg_rn
);
7497 tcg_temp_free_i64(tcg_rm
);
7499 /* Do a single operation on the lowest element in the vector.
7500 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7501 * no side effects for all these operations.
7502 * OPTME: special-purpose helpers would avoid doing some
7503 * unnecessary work in the helper for the 8 and 16 bit cases.
7505 NeonGenTwoOpEnvFn
*genenvfn
;
7506 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7507 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7508 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7510 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7511 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7514 case 0x1: /* SQADD, UQADD */
7516 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7517 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7518 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7519 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7521 genenvfn
= fns
[size
][u
];
7524 case 0x5: /* SQSUB, UQSUB */
7526 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7527 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7528 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7529 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7531 genenvfn
= fns
[size
][u
];
7534 case 0x9: /* SQSHL, UQSHL */
7536 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7537 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7538 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7539 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7541 genenvfn
= fns
[size
][u
];
7544 case 0xb: /* SQRSHL, UQRSHL */
7546 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7547 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7548 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7549 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7551 genenvfn
= fns
[size
][u
];
7554 case 0x16: /* SQDMULH, SQRDMULH */
7556 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7557 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7558 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7560 assert(size
== 1 || size
== 2);
7561 genenvfn
= fns
[size
- 1][u
];
7565 g_assert_not_reached();
7568 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7569 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7570 tcg_temp_free_i32(tcg_rd32
);
7571 tcg_temp_free_i32(tcg_rn
);
7572 tcg_temp_free_i32(tcg_rm
);
7575 write_fp_dreg(s
, rd
, tcg_rd
);
7577 tcg_temp_free_i64(tcg_rd
);
7580 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7581 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7582 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7584 /* Handle 64->64 opcodes which are shared between the scalar and
7585 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7586 * is valid in either group and also the double-precision fp ops.
7587 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7593 case 0x4: /* CLS, CLZ */
7595 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
7597 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
7601 /* This opcode is shared with CNT and RBIT but we have earlier
7602 * enforced that size == 3 if and only if this is the NOT insn.
7604 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7606 case 0x7: /* SQABS, SQNEG */
7608 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7610 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7613 case 0xa: /* CMLT */
7614 /* 64 bit integer comparison against zero, result is
7615 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7620 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7621 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7623 case 0x8: /* CMGT, CMGE */
7624 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7626 case 0x9: /* CMEQ, CMLE */
7627 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7629 case 0xb: /* ABS, NEG */
7631 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7633 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7634 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7635 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7637 tcg_temp_free_i64(tcg_zero
);
7640 case 0x2f: /* FABS */
7641 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7643 case 0x6f: /* FNEG */
7644 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7646 case 0x7f: /* FSQRT */
7647 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7649 case 0x1a: /* FCVTNS */
7650 case 0x1b: /* FCVTMS */
7651 case 0x1c: /* FCVTAS */
7652 case 0x3a: /* FCVTPS */
7653 case 0x3b: /* FCVTZS */
7655 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7656 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7657 tcg_temp_free_i32(tcg_shift
);
7660 case 0x5a: /* FCVTNU */
7661 case 0x5b: /* FCVTMU */
7662 case 0x5c: /* FCVTAU */
7663 case 0x7a: /* FCVTPU */
7664 case 0x7b: /* FCVTZU */
7666 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7667 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7668 tcg_temp_free_i32(tcg_shift
);
7671 case 0x18: /* FRINTN */
7672 case 0x19: /* FRINTM */
7673 case 0x38: /* FRINTP */
7674 case 0x39: /* FRINTZ */
7675 case 0x58: /* FRINTA */
7676 case 0x79: /* FRINTI */
7677 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7679 case 0x59: /* FRINTX */
7680 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7683 g_assert_not_reached();
7687 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7688 bool is_scalar
, bool is_u
, bool is_q
,
7689 int size
, int rn
, int rd
)
7691 bool is_double
= (size
== 3);
7694 if (!fp_access_check(s
)) {
7698 fpst
= get_fpstatus_ptr();
7701 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7702 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7703 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7704 NeonGenTwoDoubleOPFn
*genfn
;
7709 case 0x2e: /* FCMLT (zero) */
7712 case 0x2c: /* FCMGT (zero) */
7713 genfn
= gen_helper_neon_cgt_f64
;
7715 case 0x2d: /* FCMEQ (zero) */
7716 genfn
= gen_helper_neon_ceq_f64
;
7718 case 0x6d: /* FCMLE (zero) */
7721 case 0x6c: /* FCMGE (zero) */
7722 genfn
= gen_helper_neon_cge_f64
;
7725 g_assert_not_reached();
7728 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7729 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7731 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7733 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7735 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7738 clear_vec_high(s
, rd
);
7741 tcg_temp_free_i64(tcg_res
);
7742 tcg_temp_free_i64(tcg_zero
);
7743 tcg_temp_free_i64(tcg_op
);
7745 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7746 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7747 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7748 NeonGenTwoSingleOPFn
*genfn
;
7750 int pass
, maxpasses
;
7753 case 0x2e: /* FCMLT (zero) */
7756 case 0x2c: /* FCMGT (zero) */
7757 genfn
= gen_helper_neon_cgt_f32
;
7759 case 0x2d: /* FCMEQ (zero) */
7760 genfn
= gen_helper_neon_ceq_f32
;
7762 case 0x6d: /* FCMLE (zero) */
7765 case 0x6c: /* FCMGE (zero) */
7766 genfn
= gen_helper_neon_cge_f32
;
7769 g_assert_not_reached();
7775 maxpasses
= is_q
? 4 : 2;
7778 for (pass
= 0; pass
< maxpasses
; pass
++) {
7779 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7781 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7783 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7786 write_fp_sreg(s
, rd
, tcg_res
);
7788 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7791 tcg_temp_free_i32(tcg_res
);
7792 tcg_temp_free_i32(tcg_zero
);
7793 tcg_temp_free_i32(tcg_op
);
7794 if (!is_q
&& !is_scalar
) {
7795 clear_vec_high(s
, rd
);
7799 tcg_temp_free_ptr(fpst
);
7802 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7803 bool is_scalar
, bool is_u
, bool is_q
,
7804 int size
, int rn
, int rd
)
7806 bool is_double
= (size
== 3);
7807 TCGv_ptr fpst
= get_fpstatus_ptr();
7810 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7811 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7814 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7815 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7817 case 0x3d: /* FRECPE */
7818 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7820 case 0x3f: /* FRECPX */
7821 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7823 case 0x7d: /* FRSQRTE */
7824 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7827 g_assert_not_reached();
7829 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7832 clear_vec_high(s
, rd
);
7835 tcg_temp_free_i64(tcg_res
);
7836 tcg_temp_free_i64(tcg_op
);
7838 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7839 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7840 int pass
, maxpasses
;
7845 maxpasses
= is_q
? 4 : 2;
7848 for (pass
= 0; pass
< maxpasses
; pass
++) {
7849 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7852 case 0x3c: /* URECPE */
7853 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7855 case 0x3d: /* FRECPE */
7856 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7858 case 0x3f: /* FRECPX */
7859 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7861 case 0x7d: /* FRSQRTE */
7862 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7865 g_assert_not_reached();
7869 write_fp_sreg(s
, rd
, tcg_res
);
7871 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7874 tcg_temp_free_i32(tcg_res
);
7875 tcg_temp_free_i32(tcg_op
);
7876 if (!is_q
&& !is_scalar
) {
7877 clear_vec_high(s
, rd
);
7880 tcg_temp_free_ptr(fpst
);
7883 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7884 int opcode
, bool u
, bool is_q
,
7885 int size
, int rn
, int rd
)
7887 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7888 * in the source becomes a size element in the destination).
7891 TCGv_i32 tcg_res
[2];
7892 int destelt
= is_q
? 2 : 0;
7893 int passes
= scalar
? 1 : 2;
7896 tcg_res
[1] = tcg_const_i32(0);
7899 for (pass
= 0; pass
< passes
; pass
++) {
7900 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7901 NeonGenNarrowFn
*genfn
= NULL
;
7902 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7905 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7907 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7909 tcg_res
[pass
] = tcg_temp_new_i32();
7912 case 0x12: /* XTN, SQXTUN */
7914 static NeonGenNarrowFn
* const xtnfns
[3] = {
7915 gen_helper_neon_narrow_u8
,
7916 gen_helper_neon_narrow_u16
,
7917 tcg_gen_extrl_i64_i32
,
7919 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7920 gen_helper_neon_unarrow_sat8
,
7921 gen_helper_neon_unarrow_sat16
,
7922 gen_helper_neon_unarrow_sat32
,
7925 genenvfn
= sqxtunfns
[size
];
7927 genfn
= xtnfns
[size
];
7931 case 0x14: /* SQXTN, UQXTN */
7933 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7934 { gen_helper_neon_narrow_sat_s8
,
7935 gen_helper_neon_narrow_sat_u8
},
7936 { gen_helper_neon_narrow_sat_s16
,
7937 gen_helper_neon_narrow_sat_u16
},
7938 { gen_helper_neon_narrow_sat_s32
,
7939 gen_helper_neon_narrow_sat_u32
},
7941 genenvfn
= fns
[size
][u
];
7944 case 0x16: /* FCVTN, FCVTN2 */
7945 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7947 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7949 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7950 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7951 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7952 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7953 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7954 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7955 tcg_temp_free_i32(tcg_lo
);
7956 tcg_temp_free_i32(tcg_hi
);
7959 case 0x56: /* FCVTXN, FCVTXN2 */
7960 /* 64 bit to 32 bit float conversion
7961 * with von Neumann rounding (round to odd)
7964 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7967 g_assert_not_reached();
7971 genfn(tcg_res
[pass
], tcg_op
);
7972 } else if (genenvfn
) {
7973 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7976 tcg_temp_free_i64(tcg_op
);
7979 for (pass
= 0; pass
< 2; pass
++) {
7980 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7981 tcg_temp_free_i32(tcg_res
[pass
]);
7984 clear_vec_high(s
, rd
);
7988 /* Remaining saturating accumulating ops */
7989 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7990 bool is_q
, int size
, int rn
, int rd
)
7992 bool is_double
= (size
== 3);
7995 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7996 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7999 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8000 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
8001 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8003 if (is_u
) { /* USQADD */
8004 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8005 } else { /* SUQADD */
8006 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8008 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8011 clear_vec_high(s
, rd
);
8014 tcg_temp_free_i64(tcg_rd
);
8015 tcg_temp_free_i64(tcg_rn
);
8017 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8018 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8019 int pass
, maxpasses
;
8024 maxpasses
= is_q
? 4 : 2;
8027 for (pass
= 0; pass
< maxpasses
; pass
++) {
8029 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
8030 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
8032 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
8033 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8036 if (is_u
) { /* USQADD */
8039 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8042 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8045 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8048 g_assert_not_reached();
8050 } else { /* SUQADD */
8053 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8056 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8059 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8062 g_assert_not_reached();
8067 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8068 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
8069 tcg_temp_free_i64(tcg_zero
);
8071 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8075 clear_vec_high(s
, rd
);
8078 tcg_temp_free_i32(tcg_rd
);
8079 tcg_temp_free_i32(tcg_rn
);
8083 /* AdvSIMD scalar two reg misc
8084 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8085 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8086 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8087 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8089 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8091 int rd
= extract32(insn
, 0, 5);
8092 int rn
= extract32(insn
, 5, 5);
8093 int opcode
= extract32(insn
, 12, 5);
8094 int size
= extract32(insn
, 22, 2);
8095 bool u
= extract32(insn
, 29, 1);
8096 bool is_fcvt
= false;
8099 TCGv_ptr tcg_fpstatus
;
8102 case 0x3: /* USQADD / SUQADD*/
8103 if (!fp_access_check(s
)) {
8106 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
8108 case 0x7: /* SQABS / SQNEG */
8110 case 0xa: /* CMLT */
8112 unallocated_encoding(s
);
8116 case 0x8: /* CMGT, CMGE */
8117 case 0x9: /* CMEQ, CMLE */
8118 case 0xb: /* ABS, NEG */
8120 unallocated_encoding(s
);
8124 case 0x12: /* SQXTUN */
8126 unallocated_encoding(s
);
8130 case 0x14: /* SQXTN, UQXTN */
8132 unallocated_encoding(s
);
8135 if (!fp_access_check(s
)) {
8138 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
8143 /* Floating point: U, size[1] and opcode indicate operation;
8144 * size[0] indicates single or double precision.
8146 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8147 size
= extract32(size
, 0, 1) ? 3 : 2;
8149 case 0x2c: /* FCMGT (zero) */
8150 case 0x2d: /* FCMEQ (zero) */
8151 case 0x2e: /* FCMLT (zero) */
8152 case 0x6c: /* FCMGE (zero) */
8153 case 0x6d: /* FCMLE (zero) */
8154 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
8156 case 0x1d: /* SCVTF */
8157 case 0x5d: /* UCVTF */
8159 bool is_signed
= (opcode
== 0x1d);
8160 if (!fp_access_check(s
)) {
8163 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
8166 case 0x3d: /* FRECPE */
8167 case 0x3f: /* FRECPX */
8168 case 0x7d: /* FRSQRTE */
8169 if (!fp_access_check(s
)) {
8172 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
8174 case 0x1a: /* FCVTNS */
8175 case 0x1b: /* FCVTMS */
8176 case 0x3a: /* FCVTPS */
8177 case 0x3b: /* FCVTZS */
8178 case 0x5a: /* FCVTNU */
8179 case 0x5b: /* FCVTMU */
8180 case 0x7a: /* FCVTPU */
8181 case 0x7b: /* FCVTZU */
8183 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8185 case 0x1c: /* FCVTAS */
8186 case 0x5c: /* FCVTAU */
8187 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8189 rmode
= FPROUNDING_TIEAWAY
;
8191 case 0x56: /* FCVTXN, FCVTXN2 */
8193 unallocated_encoding(s
);
8196 if (!fp_access_check(s
)) {
8199 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8202 unallocated_encoding(s
);
8207 unallocated_encoding(s
);
8211 if (!fp_access_check(s
)) {
8216 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8217 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8218 tcg_fpstatus
= get_fpstatus_ptr();
8220 TCGV_UNUSED_I32(tcg_rmode
);
8221 TCGV_UNUSED_PTR(tcg_fpstatus
);
8225 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8226 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8228 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8229 write_fp_dreg(s
, rd
, tcg_rd
);
8230 tcg_temp_free_i64(tcg_rd
);
8231 tcg_temp_free_i64(tcg_rn
);
8233 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8234 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8236 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8239 case 0x7: /* SQABS, SQNEG */
8241 NeonGenOneOpEnvFn
*genfn
;
8242 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8243 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8244 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8245 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8247 genfn
= fns
[size
][u
];
8248 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8251 case 0x1a: /* FCVTNS */
8252 case 0x1b: /* FCVTMS */
8253 case 0x1c: /* FCVTAS */
8254 case 0x3a: /* FCVTPS */
8255 case 0x3b: /* FCVTZS */
8257 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8258 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8259 tcg_temp_free_i32(tcg_shift
);
8262 case 0x5a: /* FCVTNU */
8263 case 0x5b: /* FCVTMU */
8264 case 0x5c: /* FCVTAU */
8265 case 0x7a: /* FCVTPU */
8266 case 0x7b: /* FCVTZU */
8268 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8269 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8270 tcg_temp_free_i32(tcg_shift
);
8274 g_assert_not_reached();
8277 write_fp_sreg(s
, rd
, tcg_rd
);
8278 tcg_temp_free_i32(tcg_rd
);
8279 tcg_temp_free_i32(tcg_rn
);
8283 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8284 tcg_temp_free_i32(tcg_rmode
);
8285 tcg_temp_free_ptr(tcg_fpstatus
);
8289 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8290 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8291 int immh
, int immb
, int opcode
, int rn
, int rd
)
8293 int size
= 32 - clz32(immh
) - 1;
8294 int immhb
= immh
<< 3 | immb
;
8295 int shift
= 2 * (8 << size
) - immhb
;
8296 bool accumulate
= false;
8298 bool insert
= false;
8299 int dsize
= is_q
? 128 : 64;
8300 int esize
= 8 << size
;
8301 int elements
= dsize
/esize
;
8302 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8303 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8304 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8308 if (extract32(immh
, 3, 1) && !is_q
) {
8309 unallocated_encoding(s
);
8313 if (size
> 3 && !is_q
) {
8314 unallocated_encoding(s
);
8318 if (!fp_access_check(s
)) {
8323 case 0x02: /* SSRA / USRA (accumulate) */
8326 case 0x04: /* SRSHR / URSHR (rounding) */
8329 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8330 accumulate
= round
= true;
8332 case 0x08: /* SRI */
8338 uint64_t round_const
= 1ULL << (shift
- 1);
8339 tcg_round
= tcg_const_i64(round_const
);
8341 TCGV_UNUSED_I64(tcg_round
);
8344 for (i
= 0; i
< elements
; i
++) {
8345 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8346 if (accumulate
|| insert
) {
8347 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8351 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8353 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8354 accumulate
, is_u
, size
, shift
);
8357 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8361 clear_vec_high(s
, rd
);
8365 tcg_temp_free_i64(tcg_round
);
8369 /* SHL/SLI - Vector shift left */
8370 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8371 int immh
, int immb
, int opcode
, int rn
, int rd
)
8373 int size
= 32 - clz32(immh
) - 1;
8374 int immhb
= immh
<< 3 | immb
;
8375 int shift
= immhb
- (8 << size
);
8376 int dsize
= is_q
? 128 : 64;
8377 int esize
= 8 << size
;
8378 int elements
= dsize
/esize
;
8379 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8380 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8383 if (extract32(immh
, 3, 1) && !is_q
) {
8384 unallocated_encoding(s
);
8388 if (size
> 3 && !is_q
) {
8389 unallocated_encoding(s
);
8393 if (!fp_access_check(s
)) {
8397 for (i
= 0; i
< elements
; i
++) {
8398 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8400 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8403 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8405 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8409 clear_vec_high(s
, rd
);
8413 /* USHLL/SHLL - Vector shift left with widening */
8414 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8415 int immh
, int immb
, int opcode
, int rn
, int rd
)
8417 int size
= 32 - clz32(immh
) - 1;
8418 int immhb
= immh
<< 3 | immb
;
8419 int shift
= immhb
- (8 << size
);
8421 int esize
= 8 << size
;
8422 int elements
= dsize
/esize
;
8423 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8424 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8428 unallocated_encoding(s
);
8432 if (!fp_access_check(s
)) {
8436 /* For the LL variants the store is larger than the load,
8437 * so if rd == rn we would overwrite parts of our input.
8438 * So load everything right now and use shifts in the main loop.
8440 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8442 for (i
= 0; i
< elements
; i
++) {
8443 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8444 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8445 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8446 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8450 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8451 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8452 int immh
, int immb
, int opcode
, int rn
, int rd
)
8454 int immhb
= immh
<< 3 | immb
;
8455 int size
= 32 - clz32(immh
) - 1;
8457 int esize
= 8 << size
;
8458 int elements
= dsize
/esize
;
8459 int shift
= (2 * esize
) - immhb
;
8460 bool round
= extract32(opcode
, 0, 1);
8461 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8465 if (extract32(immh
, 3, 1)) {
8466 unallocated_encoding(s
);
8470 if (!fp_access_check(s
)) {
8474 tcg_rn
= tcg_temp_new_i64();
8475 tcg_rd
= tcg_temp_new_i64();
8476 tcg_final
= tcg_temp_new_i64();
8477 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8480 uint64_t round_const
= 1ULL << (shift
- 1);
8481 tcg_round
= tcg_const_i64(round_const
);
8483 TCGV_UNUSED_I64(tcg_round
);
8486 for (i
= 0; i
< elements
; i
++) {
8487 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8488 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8489 false, true, size
+1, shift
);
8491 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8495 clear_vec_high(s
, rd
);
8496 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8498 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8502 tcg_temp_free_i64(tcg_round
);
8504 tcg_temp_free_i64(tcg_rn
);
8505 tcg_temp_free_i64(tcg_rd
);
8506 tcg_temp_free_i64(tcg_final
);
8511 /* AdvSIMD shift by immediate
8512 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8513 * +---+---+---+-------------+------+------+--------+---+------+------+
8514 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8515 * +---+---+---+-------------+------+------+--------+---+------+------+
8517 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8519 int rd
= extract32(insn
, 0, 5);
8520 int rn
= extract32(insn
, 5, 5);
8521 int opcode
= extract32(insn
, 11, 5);
8522 int immb
= extract32(insn
, 16, 3);
8523 int immh
= extract32(insn
, 19, 4);
8524 bool is_u
= extract32(insn
, 29, 1);
8525 bool is_q
= extract32(insn
, 30, 1);
8528 case 0x08: /* SRI */
8530 unallocated_encoding(s
);
8534 case 0x00: /* SSHR / USHR */
8535 case 0x02: /* SSRA / USRA (accumulate) */
8536 case 0x04: /* SRSHR / URSHR (rounding) */
8537 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8538 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8540 case 0x0a: /* SHL / SLI */
8541 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8543 case 0x10: /* SHRN */
8544 case 0x11: /* RSHRN / SQRSHRUN */
8546 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8549 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8552 case 0x12: /* SQSHRN / UQSHRN */
8553 case 0x13: /* SQRSHRN / UQRSHRN */
8554 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8557 case 0x14: /* SSHLL / USHLL */
8558 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8560 case 0x1c: /* SCVTF / UCVTF */
8561 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8564 case 0xc: /* SQSHLU */
8566 unallocated_encoding(s
);
8569 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8571 case 0xe: /* SQSHL, UQSHL */
8572 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8574 case 0x1f: /* FCVTZS/ FCVTZU */
8575 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8578 unallocated_encoding(s
);
8583 /* Generate code to do a "long" addition or subtraction, ie one done in
8584 * TCGv_i64 on vector lanes twice the width specified by size.
8586 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8587 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8589 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8590 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8591 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8592 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8594 NeonGenTwo64OpFn
*genfn
;
8597 genfn
= fns
[size
][is_sub
];
8598 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8601 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8602 int opcode
, int rd
, int rn
, int rm
)
8604 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8605 TCGv_i64 tcg_res
[2];
8608 tcg_res
[0] = tcg_temp_new_i64();
8609 tcg_res
[1] = tcg_temp_new_i64();
8611 /* Does this op do an adding accumulate, a subtracting accumulate,
8612 * or no accumulate at all?
8630 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8631 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8634 /* size == 2 means two 32x32->64 operations; this is worth special
8635 * casing because we can generally handle it inline.
8638 for (pass
= 0; pass
< 2; pass
++) {
8639 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8640 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8641 TCGv_i64 tcg_passres
;
8642 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8644 int elt
= pass
+ is_q
* 2;
8646 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8647 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8650 tcg_passres
= tcg_res
[pass
];
8652 tcg_passres
= tcg_temp_new_i64();
8656 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8657 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8659 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8660 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8662 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8663 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8665 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8666 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8668 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8669 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8670 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8672 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8673 tcg_temp_free_i64(tcg_tmp1
);
8674 tcg_temp_free_i64(tcg_tmp2
);
8677 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8678 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8679 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8680 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8682 case 9: /* SQDMLAL, SQDMLAL2 */
8683 case 11: /* SQDMLSL, SQDMLSL2 */
8684 case 13: /* SQDMULL, SQDMULL2 */
8685 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8686 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8687 tcg_passres
, tcg_passres
);
8690 g_assert_not_reached();
8693 if (opcode
== 9 || opcode
== 11) {
8694 /* saturating accumulate ops */
8696 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8698 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8699 tcg_res
[pass
], tcg_passres
);
8700 } else if (accop
> 0) {
8701 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8702 } else if (accop
< 0) {
8703 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8707 tcg_temp_free_i64(tcg_passres
);
8710 tcg_temp_free_i64(tcg_op1
);
8711 tcg_temp_free_i64(tcg_op2
);
8714 /* size 0 or 1, generally helper functions */
8715 for (pass
= 0; pass
< 2; pass
++) {
8716 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8717 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8718 TCGv_i64 tcg_passres
;
8719 int elt
= pass
+ is_q
* 2;
8721 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8722 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8725 tcg_passres
= tcg_res
[pass
];
8727 tcg_passres
= tcg_temp_new_i64();
8731 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8732 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8734 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8735 static NeonGenWidenFn
* const widenfns
[2][2] = {
8736 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8737 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8739 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8741 widenfn(tcg_op2_64
, tcg_op2
);
8742 widenfn(tcg_passres
, tcg_op1
);
8743 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8744 tcg_passres
, tcg_op2_64
);
8745 tcg_temp_free_i64(tcg_op2_64
);
8748 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8749 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8752 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8754 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8758 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8760 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8764 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8765 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8766 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8769 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8771 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8775 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8777 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8781 case 9: /* SQDMLAL, SQDMLAL2 */
8782 case 11: /* SQDMLSL, SQDMLSL2 */
8783 case 13: /* SQDMULL, SQDMULL2 */
8785 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8786 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8787 tcg_passres
, tcg_passres
);
8789 case 14: /* PMULL */
8791 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8794 g_assert_not_reached();
8796 tcg_temp_free_i32(tcg_op1
);
8797 tcg_temp_free_i32(tcg_op2
);
8800 if (opcode
== 9 || opcode
== 11) {
8801 /* saturating accumulate ops */
8803 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8805 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8809 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8810 tcg_res
[pass
], tcg_passres
);
8812 tcg_temp_free_i64(tcg_passres
);
8817 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8818 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8819 tcg_temp_free_i64(tcg_res
[0]);
8820 tcg_temp_free_i64(tcg_res
[1]);
8823 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8824 int opcode
, int rd
, int rn
, int rm
)
8826 TCGv_i64 tcg_res
[2];
8827 int part
= is_q
? 2 : 0;
8830 for (pass
= 0; pass
< 2; pass
++) {
8831 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8832 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8833 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8834 static NeonGenWidenFn
* const widenfns
[3][2] = {
8835 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8836 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8837 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8839 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8841 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8842 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8843 widenfn(tcg_op2_wide
, tcg_op2
);
8844 tcg_temp_free_i32(tcg_op2
);
8845 tcg_res
[pass
] = tcg_temp_new_i64();
8846 gen_neon_addl(size
, (opcode
== 3),
8847 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8848 tcg_temp_free_i64(tcg_op1
);
8849 tcg_temp_free_i64(tcg_op2_wide
);
8852 for (pass
= 0; pass
< 2; pass
++) {
8853 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8854 tcg_temp_free_i64(tcg_res
[pass
]);
8858 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8860 tcg_gen_addi_i64(in
, in
, 1U << 31);
8861 tcg_gen_extrh_i64_i32(res
, in
);
8864 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8865 int opcode
, int rd
, int rn
, int rm
)
8867 TCGv_i32 tcg_res
[2];
8868 int part
= is_q
? 2 : 0;
8871 for (pass
= 0; pass
< 2; pass
++) {
8872 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8873 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8874 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8875 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8876 { gen_helper_neon_narrow_high_u8
,
8877 gen_helper_neon_narrow_round_high_u8
},
8878 { gen_helper_neon_narrow_high_u16
,
8879 gen_helper_neon_narrow_round_high_u16
},
8880 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8882 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8884 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8885 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8887 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8889 tcg_temp_free_i64(tcg_op1
);
8890 tcg_temp_free_i64(tcg_op2
);
8892 tcg_res
[pass
] = tcg_temp_new_i32();
8893 gennarrow(tcg_res
[pass
], tcg_wideres
);
8894 tcg_temp_free_i64(tcg_wideres
);
8897 for (pass
= 0; pass
< 2; pass
++) {
8898 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8899 tcg_temp_free_i32(tcg_res
[pass
]);
8902 clear_vec_high(s
, rd
);
8906 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8908 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8909 * is the only three-reg-diff instruction which produces a
8910 * 128-bit wide result from a single operation. However since
8911 * it's possible to calculate the two halves more or less
8912 * separately we just use two helper calls.
8914 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8915 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8916 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8918 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8919 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8920 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8921 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8922 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8923 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8925 tcg_temp_free_i64(tcg_op1
);
8926 tcg_temp_free_i64(tcg_op2
);
8927 tcg_temp_free_i64(tcg_res
);
8930 /* AdvSIMD three different
8931 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8932 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8933 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8934 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8936 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8938 /* Instructions in this group fall into three basic classes
8939 * (in each case with the operation working on each element in
8940 * the input vectors):
8941 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8943 * (2) wide 64 x 128 -> 128
8944 * (3) narrowing 128 x 128 -> 64
8945 * Here we do initial decode, catch unallocated cases and
8946 * dispatch to separate functions for each class.
8948 int is_q
= extract32(insn
, 30, 1);
8949 int is_u
= extract32(insn
, 29, 1);
8950 int size
= extract32(insn
, 22, 2);
8951 int opcode
= extract32(insn
, 12, 4);
8952 int rm
= extract32(insn
, 16, 5);
8953 int rn
= extract32(insn
, 5, 5);
8954 int rd
= extract32(insn
, 0, 5);
8957 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8958 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8959 /* 64 x 128 -> 128 */
8961 unallocated_encoding(s
);
8964 if (!fp_access_check(s
)) {
8967 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8969 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8970 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8971 /* 128 x 128 -> 64 */
8973 unallocated_encoding(s
);
8976 if (!fp_access_check(s
)) {
8979 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8981 case 14: /* PMULL, PMULL2 */
8982 if (is_u
|| size
== 1 || size
== 2) {
8983 unallocated_encoding(s
);
8987 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8988 unallocated_encoding(s
);
8991 if (!fp_access_check(s
)) {
8994 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8998 case 9: /* SQDMLAL, SQDMLAL2 */
8999 case 11: /* SQDMLSL, SQDMLSL2 */
9000 case 13: /* SQDMULL, SQDMULL2 */
9001 if (is_u
|| size
== 0) {
9002 unallocated_encoding(s
);
9006 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9007 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9008 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9009 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9010 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9011 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9012 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
9013 /* 64 x 64 -> 128 */
9015 unallocated_encoding(s
);
9019 if (!fp_access_check(s
)) {
9023 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9026 /* opcode 15 not allocated */
9027 unallocated_encoding(s
);
9032 /* Logic op (opcode == 3) subgroup of C3.6.16. */
9033 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
9035 int rd
= extract32(insn
, 0, 5);
9036 int rn
= extract32(insn
, 5, 5);
9037 int rm
= extract32(insn
, 16, 5);
9038 int size
= extract32(insn
, 22, 2);
9039 bool is_u
= extract32(insn
, 29, 1);
9040 bool is_q
= extract32(insn
, 30, 1);
9041 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
9044 if (!fp_access_check(s
)) {
9048 tcg_op1
= tcg_temp_new_i64();
9049 tcg_op2
= tcg_temp_new_i64();
9050 tcg_res
[0] = tcg_temp_new_i64();
9051 tcg_res
[1] = tcg_temp_new_i64();
9053 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9054 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9055 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9060 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9063 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9066 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9069 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9074 /* B* ops need res loaded to operate on */
9075 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9080 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9082 case 1: /* BSL bitwise select */
9083 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9084 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9085 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
9087 case 2: /* BIT, bitwise insert if true */
9088 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9089 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9090 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9092 case 3: /* BIF, bitwise insert if false */
9093 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9094 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9095 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9101 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9103 tcg_gen_movi_i64(tcg_res
[1], 0);
9105 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9107 tcg_temp_free_i64(tcg_op1
);
9108 tcg_temp_free_i64(tcg_op2
);
9109 tcg_temp_free_i64(tcg_res
[0]);
9110 tcg_temp_free_i64(tcg_res
[1]);
9113 /* Helper functions for 32 bit comparisons */
9114 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9116 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
9119 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9121 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
9124 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9126 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
9129 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9131 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
9134 /* Pairwise op subgroup of C3.6.16.
9136 * This is called directly or via the handle_3same_float for float pairwise
9137 * operations where the opcode and size are calculated differently.
9139 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
9140 int size
, int rn
, int rm
, int rd
)
9145 /* Floating point operations need fpst */
9146 if (opcode
>= 0x58) {
9147 fpst
= get_fpstatus_ptr();
9149 TCGV_UNUSED_PTR(fpst
);
9152 if (!fp_access_check(s
)) {
9156 /* These operations work on the concatenated rm:rn, with each pair of
9157 * adjacent elements being operated on to produce an element in the result.
9160 TCGv_i64 tcg_res
[2];
9162 for (pass
= 0; pass
< 2; pass
++) {
9163 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9164 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9165 int passreg
= (pass
== 0) ? rn
: rm
;
9167 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
9168 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
9169 tcg_res
[pass
] = tcg_temp_new_i64();
9172 case 0x17: /* ADDP */
9173 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9175 case 0x58: /* FMAXNMP */
9176 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9178 case 0x5a: /* FADDP */
9179 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9181 case 0x5e: /* FMAXP */
9182 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9184 case 0x78: /* FMINNMP */
9185 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9187 case 0x7e: /* FMINP */
9188 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9191 g_assert_not_reached();
9194 tcg_temp_free_i64(tcg_op1
);
9195 tcg_temp_free_i64(tcg_op2
);
9198 for (pass
= 0; pass
< 2; pass
++) {
9199 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9200 tcg_temp_free_i64(tcg_res
[pass
]);
9203 int maxpass
= is_q
? 4 : 2;
9204 TCGv_i32 tcg_res
[4];
9206 for (pass
= 0; pass
< maxpass
; pass
++) {
9207 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9208 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9209 NeonGenTwoOpFn
*genfn
= NULL
;
9210 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9211 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9213 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9214 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9215 tcg_res
[pass
] = tcg_temp_new_i32();
9218 case 0x17: /* ADDP */
9220 static NeonGenTwoOpFn
* const fns
[3] = {
9221 gen_helper_neon_padd_u8
,
9222 gen_helper_neon_padd_u16
,
9228 case 0x14: /* SMAXP, UMAXP */
9230 static NeonGenTwoOpFn
* const fns
[3][2] = {
9231 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9232 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9233 { gen_max_s32
, gen_max_u32
},
9235 genfn
= fns
[size
][u
];
9238 case 0x15: /* SMINP, UMINP */
9240 static NeonGenTwoOpFn
* const fns
[3][2] = {
9241 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9242 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9243 { gen_min_s32
, gen_min_u32
},
9245 genfn
= fns
[size
][u
];
9248 /* The FP operations are all on single floats (32 bit) */
9249 case 0x58: /* FMAXNMP */
9250 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9252 case 0x5a: /* FADDP */
9253 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9255 case 0x5e: /* FMAXP */
9256 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9258 case 0x78: /* FMINNMP */
9259 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9261 case 0x7e: /* FMINP */
9262 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9265 g_assert_not_reached();
9268 /* FP ops called directly, otherwise call now */
9270 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9273 tcg_temp_free_i32(tcg_op1
);
9274 tcg_temp_free_i32(tcg_op2
);
9277 for (pass
= 0; pass
< maxpass
; pass
++) {
9278 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9279 tcg_temp_free_i32(tcg_res
[pass
]);
9282 clear_vec_high(s
, rd
);
9286 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9287 tcg_temp_free_ptr(fpst
);
9291 /* Floating point op subgroup of C3.6.16. */
9292 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9294 /* For floating point ops, the U, size[1] and opcode bits
9295 * together indicate the operation. size[0] indicates single
9298 int fpopcode
= extract32(insn
, 11, 5)
9299 | (extract32(insn
, 23, 1) << 5)
9300 | (extract32(insn
, 29, 1) << 6);
9301 int is_q
= extract32(insn
, 30, 1);
9302 int size
= extract32(insn
, 22, 1);
9303 int rm
= extract32(insn
, 16, 5);
9304 int rn
= extract32(insn
, 5, 5);
9305 int rd
= extract32(insn
, 0, 5);
9307 int datasize
= is_q
? 128 : 64;
9308 int esize
= 32 << size
;
9309 int elements
= datasize
/ esize
;
9311 if (size
== 1 && !is_q
) {
9312 unallocated_encoding(s
);
9317 case 0x58: /* FMAXNMP */
9318 case 0x5a: /* FADDP */
9319 case 0x5e: /* FMAXP */
9320 case 0x78: /* FMINNMP */
9321 case 0x7e: /* FMINP */
9322 if (size
&& !is_q
) {
9323 unallocated_encoding(s
);
9326 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9329 case 0x1b: /* FMULX */
9330 case 0x1f: /* FRECPS */
9331 case 0x3f: /* FRSQRTS */
9332 case 0x5d: /* FACGE */
9333 case 0x7d: /* FACGT */
9334 case 0x19: /* FMLA */
9335 case 0x39: /* FMLS */
9336 case 0x18: /* FMAXNM */
9337 case 0x1a: /* FADD */
9338 case 0x1c: /* FCMEQ */
9339 case 0x1e: /* FMAX */
9340 case 0x38: /* FMINNM */
9341 case 0x3a: /* FSUB */
9342 case 0x3e: /* FMIN */
9343 case 0x5b: /* FMUL */
9344 case 0x5c: /* FCMGE */
9345 case 0x5f: /* FDIV */
9346 case 0x7a: /* FABD */
9347 case 0x7c: /* FCMGT */
9348 if (!fp_access_check(s
)) {
9352 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9355 unallocated_encoding(s
);
9360 /* Integer op subgroup of C3.6.16. */
9361 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9363 int is_q
= extract32(insn
, 30, 1);
9364 int u
= extract32(insn
, 29, 1);
9365 int size
= extract32(insn
, 22, 2);
9366 int opcode
= extract32(insn
, 11, 5);
9367 int rm
= extract32(insn
, 16, 5);
9368 int rn
= extract32(insn
, 5, 5);
9369 int rd
= extract32(insn
, 0, 5);
9373 case 0x13: /* MUL, PMUL */
9374 if (u
&& size
!= 0) {
9375 unallocated_encoding(s
);
9379 case 0x0: /* SHADD, UHADD */
9380 case 0x2: /* SRHADD, URHADD */
9381 case 0x4: /* SHSUB, UHSUB */
9382 case 0xc: /* SMAX, UMAX */
9383 case 0xd: /* SMIN, UMIN */
9384 case 0xe: /* SABD, UABD */
9385 case 0xf: /* SABA, UABA */
9386 case 0x12: /* MLA, MLS */
9388 unallocated_encoding(s
);
9392 case 0x16: /* SQDMULH, SQRDMULH */
9393 if (size
== 0 || size
== 3) {
9394 unallocated_encoding(s
);
9399 if (size
== 3 && !is_q
) {
9400 unallocated_encoding(s
);
9406 if (!fp_access_check(s
)) {
9412 for (pass
= 0; pass
< 2; pass
++) {
9413 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9414 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9415 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9417 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9418 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9420 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9422 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9424 tcg_temp_free_i64(tcg_res
);
9425 tcg_temp_free_i64(tcg_op1
);
9426 tcg_temp_free_i64(tcg_op2
);
9429 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9430 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9431 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9432 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9433 NeonGenTwoOpFn
*genfn
= NULL
;
9434 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9436 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9437 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9440 case 0x0: /* SHADD, UHADD */
9442 static NeonGenTwoOpFn
* const fns
[3][2] = {
9443 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9444 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9445 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9447 genfn
= fns
[size
][u
];
9450 case 0x1: /* SQADD, UQADD */
9452 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9453 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9454 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9455 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9457 genenvfn
= fns
[size
][u
];
9460 case 0x2: /* SRHADD, URHADD */
9462 static NeonGenTwoOpFn
* const fns
[3][2] = {
9463 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9464 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9465 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9467 genfn
= fns
[size
][u
];
9470 case 0x4: /* SHSUB, UHSUB */
9472 static NeonGenTwoOpFn
* const fns
[3][2] = {
9473 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9474 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9475 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9477 genfn
= fns
[size
][u
];
9480 case 0x5: /* SQSUB, UQSUB */
9482 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9483 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9484 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9485 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9487 genenvfn
= fns
[size
][u
];
9490 case 0x6: /* CMGT, CMHI */
9492 static NeonGenTwoOpFn
* const fns
[3][2] = {
9493 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9494 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9495 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9497 genfn
= fns
[size
][u
];
9500 case 0x7: /* CMGE, CMHS */
9502 static NeonGenTwoOpFn
* const fns
[3][2] = {
9503 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9504 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9505 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9507 genfn
= fns
[size
][u
];
9510 case 0x8: /* SSHL, USHL */
9512 static NeonGenTwoOpFn
* const fns
[3][2] = {
9513 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9514 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9515 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9517 genfn
= fns
[size
][u
];
9520 case 0x9: /* SQSHL, UQSHL */
9522 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9523 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9524 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9525 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9527 genenvfn
= fns
[size
][u
];
9530 case 0xa: /* SRSHL, URSHL */
9532 static NeonGenTwoOpFn
* const fns
[3][2] = {
9533 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9534 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9535 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9537 genfn
= fns
[size
][u
];
9540 case 0xb: /* SQRSHL, UQRSHL */
9542 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9543 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9544 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9545 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9547 genenvfn
= fns
[size
][u
];
9550 case 0xc: /* SMAX, UMAX */
9552 static NeonGenTwoOpFn
* const fns
[3][2] = {
9553 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9554 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9555 { gen_max_s32
, gen_max_u32
},
9557 genfn
= fns
[size
][u
];
9561 case 0xd: /* SMIN, UMIN */
9563 static NeonGenTwoOpFn
* const fns
[3][2] = {
9564 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9565 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9566 { gen_min_s32
, gen_min_u32
},
9568 genfn
= fns
[size
][u
];
9571 case 0xe: /* SABD, UABD */
9572 case 0xf: /* SABA, UABA */
9574 static NeonGenTwoOpFn
* const fns
[3][2] = {
9575 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9576 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9577 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9579 genfn
= fns
[size
][u
];
9582 case 0x10: /* ADD, SUB */
9584 static NeonGenTwoOpFn
* const fns
[3][2] = {
9585 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9586 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9587 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9589 genfn
= fns
[size
][u
];
9592 case 0x11: /* CMTST, CMEQ */
9594 static NeonGenTwoOpFn
* const fns
[3][2] = {
9595 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9596 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9597 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9599 genfn
= fns
[size
][u
];
9602 case 0x13: /* MUL, PMUL */
9606 genfn
= gen_helper_neon_mul_p8
;
9609 /* fall through : MUL */
9610 case 0x12: /* MLA, MLS */
9612 static NeonGenTwoOpFn
* const fns
[3] = {
9613 gen_helper_neon_mul_u8
,
9614 gen_helper_neon_mul_u16
,
9620 case 0x16: /* SQDMULH, SQRDMULH */
9622 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9623 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9624 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9626 assert(size
== 1 || size
== 2);
9627 genenvfn
= fns
[size
- 1][u
];
9631 g_assert_not_reached();
9635 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9637 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9640 if (opcode
== 0xf || opcode
== 0x12) {
9641 /* SABA, UABA, MLA, MLS: accumulating ops */
9642 static NeonGenTwoOpFn
* const fns
[3][2] = {
9643 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9644 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9645 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9647 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9649 genfn
= fns
[size
][is_sub
];
9650 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9651 genfn(tcg_res
, tcg_op1
, tcg_res
);
9654 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9656 tcg_temp_free_i32(tcg_res
);
9657 tcg_temp_free_i32(tcg_op1
);
9658 tcg_temp_free_i32(tcg_op2
);
9663 clear_vec_high(s
, rd
);
9667 /* AdvSIMD three same
9668 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9669 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9670 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9671 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9673 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9675 int opcode
= extract32(insn
, 11, 5);
9678 case 0x3: /* logic ops */
9679 disas_simd_3same_logic(s
, insn
);
9681 case 0x17: /* ADDP */
9682 case 0x14: /* SMAXP, UMAXP */
9683 case 0x15: /* SMINP, UMINP */
9685 /* Pairwise operations */
9686 int is_q
= extract32(insn
, 30, 1);
9687 int u
= extract32(insn
, 29, 1);
9688 int size
= extract32(insn
, 22, 2);
9689 int rm
= extract32(insn
, 16, 5);
9690 int rn
= extract32(insn
, 5, 5);
9691 int rd
= extract32(insn
, 0, 5);
9692 if (opcode
== 0x17) {
9693 if (u
|| (size
== 3 && !is_q
)) {
9694 unallocated_encoding(s
);
9699 unallocated_encoding(s
);
9703 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9707 /* floating point ops, sz[1] and U are part of opcode */
9708 disas_simd_3same_float(s
, insn
);
9711 disas_simd_3same_int(s
, insn
);
9716 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9717 int size
, int rn
, int rd
)
9719 /* Handle 2-reg-misc ops which are widening (so each size element
9720 * in the source becomes a 2*size element in the destination.
9721 * The only instruction like this is FCVTL.
9726 /* 32 -> 64 bit fp conversion */
9727 TCGv_i64 tcg_res
[2];
9728 int srcelt
= is_q
? 2 : 0;
9730 for (pass
= 0; pass
< 2; pass
++) {
9731 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9732 tcg_res
[pass
] = tcg_temp_new_i64();
9734 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9735 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9736 tcg_temp_free_i32(tcg_op
);
9738 for (pass
= 0; pass
< 2; pass
++) {
9739 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9740 tcg_temp_free_i64(tcg_res
[pass
]);
9743 /* 16 -> 32 bit fp conversion */
9744 int srcelt
= is_q
? 4 : 0;
9745 TCGv_i32 tcg_res
[4];
9747 for (pass
= 0; pass
< 4; pass
++) {
9748 tcg_res
[pass
] = tcg_temp_new_i32();
9750 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9751 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9754 for (pass
= 0; pass
< 4; pass
++) {
9755 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9756 tcg_temp_free_i32(tcg_res
[pass
]);
9761 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9762 bool is_q
, int size
, int rn
, int rd
)
9764 int op
= (opcode
<< 1) | u
;
9765 int opsz
= op
+ size
;
9766 int grp_size
= 3 - opsz
;
9767 int dsize
= is_q
? 128 : 64;
9771 unallocated_encoding(s
);
9775 if (!fp_access_check(s
)) {
9780 /* Special case bytes, use bswap op on each group of elements */
9781 int groups
= dsize
/ (8 << grp_size
);
9783 for (i
= 0; i
< groups
; i
++) {
9784 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9786 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9789 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9792 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9795 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9798 g_assert_not_reached();
9800 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9801 tcg_temp_free_i64(tcg_tmp
);
9804 clear_vec_high(s
, rd
);
9807 int revmask
= (1 << grp_size
) - 1;
9808 int esize
= 8 << size
;
9809 int elements
= dsize
/ esize
;
9810 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9811 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9812 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9814 for (i
= 0; i
< elements
; i
++) {
9815 int e_rev
= (i
& 0xf) ^ revmask
;
9816 int off
= e_rev
* esize
;
9817 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9819 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9820 tcg_rn
, off
- 64, esize
);
9822 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9825 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9826 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9828 tcg_temp_free_i64(tcg_rd_hi
);
9829 tcg_temp_free_i64(tcg_rd
);
9830 tcg_temp_free_i64(tcg_rn
);
9834 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9835 bool is_q
, int size
, int rn
, int rd
)
9837 /* Implement the pairwise operations from 2-misc:
9838 * SADDLP, UADDLP, SADALP, UADALP.
9839 * These all add pairs of elements in the input to produce a
9840 * double-width result element in the output (possibly accumulating).
9842 bool accum
= (opcode
== 0x6);
9843 int maxpass
= is_q
? 2 : 1;
9845 TCGv_i64 tcg_res
[2];
9848 /* 32 + 32 -> 64 op */
9849 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9851 for (pass
= 0; pass
< maxpass
; pass
++) {
9852 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9853 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9855 tcg_res
[pass
] = tcg_temp_new_i64();
9857 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9858 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9859 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9861 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9862 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9865 tcg_temp_free_i64(tcg_op1
);
9866 tcg_temp_free_i64(tcg_op2
);
9869 for (pass
= 0; pass
< maxpass
; pass
++) {
9870 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9871 NeonGenOneOpFn
*genfn
;
9872 static NeonGenOneOpFn
* const fns
[2][2] = {
9873 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9874 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9877 genfn
= fns
[size
][u
];
9879 tcg_res
[pass
] = tcg_temp_new_i64();
9881 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9882 genfn(tcg_res
[pass
], tcg_op
);
9885 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9887 gen_helper_neon_addl_u16(tcg_res
[pass
],
9888 tcg_res
[pass
], tcg_op
);
9890 gen_helper_neon_addl_u32(tcg_res
[pass
],
9891 tcg_res
[pass
], tcg_op
);
9894 tcg_temp_free_i64(tcg_op
);
9898 tcg_res
[1] = tcg_const_i64(0);
9900 for (pass
= 0; pass
< 2; pass
++) {
9901 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9902 tcg_temp_free_i64(tcg_res
[pass
]);
9906 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9908 /* Implement SHLL and SHLL2 */
9910 int part
= is_q
? 2 : 0;
9911 TCGv_i64 tcg_res
[2];
9913 for (pass
= 0; pass
< 2; pass
++) {
9914 static NeonGenWidenFn
* const widenfns
[3] = {
9915 gen_helper_neon_widen_u8
,
9916 gen_helper_neon_widen_u16
,
9917 tcg_gen_extu_i32_i64
,
9919 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9920 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9922 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9923 tcg_res
[pass
] = tcg_temp_new_i64();
9924 widenfn(tcg_res
[pass
], tcg_op
);
9925 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9927 tcg_temp_free_i32(tcg_op
);
9930 for (pass
= 0; pass
< 2; pass
++) {
9931 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9932 tcg_temp_free_i64(tcg_res
[pass
]);
9936 /* AdvSIMD two reg misc
9937 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9938 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9939 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9940 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9942 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9944 int size
= extract32(insn
, 22, 2);
9945 int opcode
= extract32(insn
, 12, 5);
9946 bool u
= extract32(insn
, 29, 1);
9947 bool is_q
= extract32(insn
, 30, 1);
9948 int rn
= extract32(insn
, 5, 5);
9949 int rd
= extract32(insn
, 0, 5);
9950 bool need_fpstatus
= false;
9951 bool need_rmode
= false;
9954 TCGv_ptr tcg_fpstatus
;
9957 case 0x0: /* REV64, REV32 */
9958 case 0x1: /* REV16 */
9959 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9961 case 0x5: /* CNT, NOT, RBIT */
9962 if (u
&& size
== 0) {
9963 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9966 } else if (u
&& size
== 1) {
9969 } else if (!u
&& size
== 0) {
9973 unallocated_encoding(s
);
9975 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9976 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9978 unallocated_encoding(s
);
9981 if (!fp_access_check(s
)) {
9985 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9987 case 0x4: /* CLS, CLZ */
9989 unallocated_encoding(s
);
9993 case 0x2: /* SADDLP, UADDLP */
9994 case 0x6: /* SADALP, UADALP */
9996 unallocated_encoding(s
);
9999 if (!fp_access_check(s
)) {
10002 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
10004 case 0x13: /* SHLL, SHLL2 */
10005 if (u
== 0 || size
== 3) {
10006 unallocated_encoding(s
);
10009 if (!fp_access_check(s
)) {
10012 handle_shll(s
, is_q
, size
, rn
, rd
);
10014 case 0xa: /* CMLT */
10016 unallocated_encoding(s
);
10020 case 0x8: /* CMGT, CMGE */
10021 case 0x9: /* CMEQ, CMLE */
10022 case 0xb: /* ABS, NEG */
10023 if (size
== 3 && !is_q
) {
10024 unallocated_encoding(s
);
10028 case 0x3: /* SUQADD, USQADD */
10029 if (size
== 3 && !is_q
) {
10030 unallocated_encoding(s
);
10033 if (!fp_access_check(s
)) {
10036 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
10038 case 0x7: /* SQABS, SQNEG */
10039 if (size
== 3 && !is_q
) {
10040 unallocated_encoding(s
);
10045 case 0x16 ... 0x1d:
10048 /* Floating point: U, size[1] and opcode indicate operation;
10049 * size[0] indicates single or double precision.
10051 int is_double
= extract32(size
, 0, 1);
10052 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10053 size
= is_double
? 3 : 2;
10055 case 0x2f: /* FABS */
10056 case 0x6f: /* FNEG */
10057 if (size
== 3 && !is_q
) {
10058 unallocated_encoding(s
);
10062 case 0x1d: /* SCVTF */
10063 case 0x5d: /* UCVTF */
10065 bool is_signed
= (opcode
== 0x1d) ? true : false;
10066 int elements
= is_double
? 2 : is_q
? 4 : 2;
10067 if (is_double
&& !is_q
) {
10068 unallocated_encoding(s
);
10071 if (!fp_access_check(s
)) {
10074 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
10077 case 0x2c: /* FCMGT (zero) */
10078 case 0x2d: /* FCMEQ (zero) */
10079 case 0x2e: /* FCMLT (zero) */
10080 case 0x6c: /* FCMGE (zero) */
10081 case 0x6d: /* FCMLE (zero) */
10082 if (size
== 3 && !is_q
) {
10083 unallocated_encoding(s
);
10086 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10088 case 0x7f: /* FSQRT */
10089 if (size
== 3 && !is_q
) {
10090 unallocated_encoding(s
);
10094 case 0x1a: /* FCVTNS */
10095 case 0x1b: /* FCVTMS */
10096 case 0x3a: /* FCVTPS */
10097 case 0x3b: /* FCVTZS */
10098 case 0x5a: /* FCVTNU */
10099 case 0x5b: /* FCVTMU */
10100 case 0x7a: /* FCVTPU */
10101 case 0x7b: /* FCVTZU */
10102 need_fpstatus
= true;
10104 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10105 if (size
== 3 && !is_q
) {
10106 unallocated_encoding(s
);
10110 case 0x5c: /* FCVTAU */
10111 case 0x1c: /* FCVTAS */
10112 need_fpstatus
= true;
10114 rmode
= FPROUNDING_TIEAWAY
;
10115 if (size
== 3 && !is_q
) {
10116 unallocated_encoding(s
);
10120 case 0x3c: /* URECPE */
10122 unallocated_encoding(s
);
10126 case 0x3d: /* FRECPE */
10127 case 0x7d: /* FRSQRTE */
10128 if (size
== 3 && !is_q
) {
10129 unallocated_encoding(s
);
10132 if (!fp_access_check(s
)) {
10135 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10137 case 0x56: /* FCVTXN, FCVTXN2 */
10139 unallocated_encoding(s
);
10143 case 0x16: /* FCVTN, FCVTN2 */
10144 /* handle_2misc_narrow does a 2*size -> size operation, but these
10145 * instructions encode the source size rather than dest size.
10147 if (!fp_access_check(s
)) {
10150 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
10152 case 0x17: /* FCVTL, FCVTL2 */
10153 if (!fp_access_check(s
)) {
10156 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
10158 case 0x18: /* FRINTN */
10159 case 0x19: /* FRINTM */
10160 case 0x38: /* FRINTP */
10161 case 0x39: /* FRINTZ */
10163 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10165 case 0x59: /* FRINTX */
10166 case 0x79: /* FRINTI */
10167 need_fpstatus
= true;
10168 if (size
== 3 && !is_q
) {
10169 unallocated_encoding(s
);
10173 case 0x58: /* FRINTA */
10175 rmode
= FPROUNDING_TIEAWAY
;
10176 need_fpstatus
= true;
10177 if (size
== 3 && !is_q
) {
10178 unallocated_encoding(s
);
10182 case 0x7c: /* URSQRTE */
10184 unallocated_encoding(s
);
10187 need_fpstatus
= true;
10190 unallocated_encoding(s
);
10196 unallocated_encoding(s
);
10200 if (!fp_access_check(s
)) {
10204 if (need_fpstatus
) {
10205 tcg_fpstatus
= get_fpstatus_ptr();
10207 TCGV_UNUSED_PTR(tcg_fpstatus
);
10210 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10211 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10213 TCGV_UNUSED_I32(tcg_rmode
);
10217 /* All 64-bit element operations can be shared with scalar 2misc */
10220 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10221 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10222 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10224 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10226 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10227 tcg_rmode
, tcg_fpstatus
);
10229 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10231 tcg_temp_free_i64(tcg_res
);
10232 tcg_temp_free_i64(tcg_op
);
10237 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10238 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10239 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10242 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10245 /* Special cases for 32 bit elements */
10247 case 0xa: /* CMLT */
10248 /* 32 bit integer comparison against zero, result is
10249 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10252 cond
= TCG_COND_LT
;
10254 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10255 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10257 case 0x8: /* CMGT, CMGE */
10258 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10260 case 0x9: /* CMEQ, CMLE */
10261 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10263 case 0x4: /* CLS */
10265 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
10267 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
10270 case 0x7: /* SQABS, SQNEG */
10272 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10274 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10277 case 0xb: /* ABS, NEG */
10279 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10281 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10282 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10283 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10284 tcg_zero
, tcg_op
, tcg_res
);
10285 tcg_temp_free_i32(tcg_zero
);
10288 case 0x2f: /* FABS */
10289 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10291 case 0x6f: /* FNEG */
10292 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10294 case 0x7f: /* FSQRT */
10295 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10297 case 0x1a: /* FCVTNS */
10298 case 0x1b: /* FCVTMS */
10299 case 0x1c: /* FCVTAS */
10300 case 0x3a: /* FCVTPS */
10301 case 0x3b: /* FCVTZS */
10303 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10304 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10305 tcg_shift
, tcg_fpstatus
);
10306 tcg_temp_free_i32(tcg_shift
);
10309 case 0x5a: /* FCVTNU */
10310 case 0x5b: /* FCVTMU */
10311 case 0x5c: /* FCVTAU */
10312 case 0x7a: /* FCVTPU */
10313 case 0x7b: /* FCVTZU */
10315 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10316 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10317 tcg_shift
, tcg_fpstatus
);
10318 tcg_temp_free_i32(tcg_shift
);
10321 case 0x18: /* FRINTN */
10322 case 0x19: /* FRINTM */
10323 case 0x38: /* FRINTP */
10324 case 0x39: /* FRINTZ */
10325 case 0x58: /* FRINTA */
10326 case 0x79: /* FRINTI */
10327 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10329 case 0x59: /* FRINTX */
10330 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10332 case 0x7c: /* URSQRTE */
10333 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10336 g_assert_not_reached();
10339 /* Use helpers for 8 and 16 bit elements */
10341 case 0x5: /* CNT, RBIT */
10342 /* For these two insns size is part of the opcode specifier
10343 * (handled earlier); they always operate on byte elements.
10346 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10348 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10351 case 0x7: /* SQABS, SQNEG */
10353 NeonGenOneOpEnvFn
*genfn
;
10354 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10355 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10356 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10358 genfn
= fns
[size
][u
];
10359 genfn(tcg_res
, cpu_env
, tcg_op
);
10362 case 0x8: /* CMGT, CMGE */
10363 case 0x9: /* CMEQ, CMLE */
10364 case 0xa: /* CMLT */
10366 static NeonGenTwoOpFn
* const fns
[3][2] = {
10367 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10368 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10369 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10371 NeonGenTwoOpFn
*genfn
;
10374 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10376 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10377 comp
= (opcode
- 0x8) * 2 + u
;
10378 /* ...but LE, LT are implemented as reverse GE, GT */
10379 reverse
= (comp
> 2);
10383 genfn
= fns
[comp
][size
];
10385 genfn(tcg_res
, tcg_zero
, tcg_op
);
10387 genfn(tcg_res
, tcg_op
, tcg_zero
);
10389 tcg_temp_free_i32(tcg_zero
);
10392 case 0xb: /* ABS, NEG */
10394 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10396 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10398 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10400 tcg_temp_free_i32(tcg_zero
);
10403 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10405 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10409 case 0x4: /* CLS, CLZ */
10412 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10414 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10418 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10420 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10425 g_assert_not_reached();
10429 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10431 tcg_temp_free_i32(tcg_res
);
10432 tcg_temp_free_i32(tcg_op
);
10436 clear_vec_high(s
, rd
);
10440 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10441 tcg_temp_free_i32(tcg_rmode
);
10443 if (need_fpstatus
) {
10444 tcg_temp_free_ptr(tcg_fpstatus
);
10448 /* AdvSIMD scalar x indexed element
10449 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10450 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10451 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10452 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10453 * AdvSIMD vector x indexed element
10454 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10455 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10456 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10457 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10459 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10461 /* This encoding has two kinds of instruction:
10462 * normal, where we perform elt x idxelt => elt for each
10463 * element in the vector
10464 * long, where we perform elt x idxelt and generate a result of
10465 * double the width of the input element
10466 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10468 bool is_scalar
= extract32(insn
, 28, 1);
10469 bool is_q
= extract32(insn
, 30, 1);
10470 bool u
= extract32(insn
, 29, 1);
10471 int size
= extract32(insn
, 22, 2);
10472 int l
= extract32(insn
, 21, 1);
10473 int m
= extract32(insn
, 20, 1);
10474 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10475 int rm
= extract32(insn
, 16, 4);
10476 int opcode
= extract32(insn
, 12, 4);
10477 int h
= extract32(insn
, 11, 1);
10478 int rn
= extract32(insn
, 5, 5);
10479 int rd
= extract32(insn
, 0, 5);
10480 bool is_long
= false;
10481 bool is_fp
= false;
10486 case 0x0: /* MLA */
10487 case 0x4: /* MLS */
10488 if (!u
|| is_scalar
) {
10489 unallocated_encoding(s
);
10493 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10494 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10495 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10497 unallocated_encoding(s
);
10502 case 0x3: /* SQDMLAL, SQDMLAL2 */
10503 case 0x7: /* SQDMLSL, SQDMLSL2 */
10504 case 0xb: /* SQDMULL, SQDMULL2 */
10507 case 0xc: /* SQDMULH */
10508 case 0xd: /* SQRDMULH */
10510 unallocated_encoding(s
);
10514 case 0x8: /* MUL */
10515 if (u
|| is_scalar
) {
10516 unallocated_encoding(s
);
10520 case 0x1: /* FMLA */
10521 case 0x5: /* FMLS */
10523 unallocated_encoding(s
);
10527 case 0x9: /* FMUL, FMULX */
10528 if (!extract32(size
, 1, 1)) {
10529 unallocated_encoding(s
);
10535 unallocated_encoding(s
);
10540 /* low bit of size indicates single/double */
10541 size
= extract32(size
, 0, 1) ? 3 : 2;
10543 index
= h
<< 1 | l
;
10546 unallocated_encoding(s
);
10555 index
= h
<< 2 | l
<< 1 | m
;
10558 index
= h
<< 1 | l
;
10562 unallocated_encoding(s
);
10567 if (!fp_access_check(s
)) {
10572 fpst
= get_fpstatus_ptr();
10574 TCGV_UNUSED_PTR(fpst
);
10578 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10581 assert(is_fp
&& is_q
&& !is_long
);
10583 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10585 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10586 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10587 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10589 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10592 case 0x5: /* FMLS */
10593 /* As usual for ARM, separate negation for fused multiply-add */
10594 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10596 case 0x1: /* FMLA */
10597 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10598 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10600 case 0x9: /* FMUL, FMULX */
10602 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10604 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10608 g_assert_not_reached();
10611 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10612 tcg_temp_free_i64(tcg_op
);
10613 tcg_temp_free_i64(tcg_res
);
10617 clear_vec_high(s
, rd
);
10620 tcg_temp_free_i64(tcg_idx
);
10621 } else if (!is_long
) {
10622 /* 32 bit floating point, or 16 or 32 bit integer.
10623 * For the 16 bit scalar case we use the usual Neon helpers and
10624 * rely on the fact that 0 op 0 == 0 with no side effects.
10626 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10627 int pass
, maxpasses
;
10632 maxpasses
= is_q
? 4 : 2;
10635 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10637 if (size
== 1 && !is_scalar
) {
10638 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10639 * the index into both halves of the 32 bit tcg_idx and then use
10640 * the usual Neon helpers.
10642 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10645 for (pass
= 0; pass
< maxpasses
; pass
++) {
10646 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10647 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10649 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10652 case 0x0: /* MLA */
10653 case 0x4: /* MLS */
10654 case 0x8: /* MUL */
10656 static NeonGenTwoOpFn
* const fns
[2][2] = {
10657 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10658 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10660 NeonGenTwoOpFn
*genfn
;
10661 bool is_sub
= opcode
== 0x4;
10664 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10666 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10668 if (opcode
== 0x8) {
10671 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10672 genfn
= fns
[size
- 1][is_sub
];
10673 genfn(tcg_res
, tcg_op
, tcg_res
);
10676 case 0x5: /* FMLS */
10677 /* As usual for ARM, separate negation for fused multiply-add */
10678 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10680 case 0x1: /* FMLA */
10681 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10682 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10684 case 0x9: /* FMUL, FMULX */
10686 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10688 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10691 case 0xc: /* SQDMULH */
10693 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10696 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10700 case 0xd: /* SQRDMULH */
10702 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10705 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10710 g_assert_not_reached();
10714 write_fp_sreg(s
, rd
, tcg_res
);
10716 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10719 tcg_temp_free_i32(tcg_op
);
10720 tcg_temp_free_i32(tcg_res
);
10723 tcg_temp_free_i32(tcg_idx
);
10726 clear_vec_high(s
, rd
);
10729 /* long ops: 16x16->32 or 32x32->64 */
10730 TCGv_i64 tcg_res
[2];
10732 bool satop
= extract32(opcode
, 0, 1);
10733 TCGMemOp memop
= MO_32
;
10740 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10742 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10744 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10745 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10746 TCGv_i64 tcg_passres
;
10752 passelt
= pass
+ (is_q
* 2);
10755 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10757 tcg_res
[pass
] = tcg_temp_new_i64();
10759 if (opcode
== 0xa || opcode
== 0xb) {
10760 /* Non-accumulating ops */
10761 tcg_passres
= tcg_res
[pass
];
10763 tcg_passres
= tcg_temp_new_i64();
10766 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10767 tcg_temp_free_i64(tcg_op
);
10770 /* saturating, doubling */
10771 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10772 tcg_passres
, tcg_passres
);
10775 if (opcode
== 0xa || opcode
== 0xb) {
10779 /* Accumulating op: handle accumulate step */
10780 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10783 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10784 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10786 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10787 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10789 case 0x7: /* SQDMLSL, SQDMLSL2 */
10790 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10792 case 0x3: /* SQDMLAL, SQDMLAL2 */
10793 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10798 g_assert_not_reached();
10800 tcg_temp_free_i64(tcg_passres
);
10802 tcg_temp_free_i64(tcg_idx
);
10805 clear_vec_high(s
, rd
);
10808 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10811 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10814 /* The simplest way to handle the 16x16 indexed ops is to
10815 * duplicate the index into both halves of the 32 bit tcg_idx
10816 * and then use the usual Neon helpers.
10818 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10821 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10822 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10823 TCGv_i64 tcg_passres
;
10826 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10828 read_vec_element_i32(s
, tcg_op
, rn
,
10829 pass
+ (is_q
* 2), MO_32
);
10832 tcg_res
[pass
] = tcg_temp_new_i64();
10834 if (opcode
== 0xa || opcode
== 0xb) {
10835 /* Non-accumulating ops */
10836 tcg_passres
= tcg_res
[pass
];
10838 tcg_passres
= tcg_temp_new_i64();
10841 if (memop
& MO_SIGN
) {
10842 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10844 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10847 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10848 tcg_passres
, tcg_passres
);
10850 tcg_temp_free_i32(tcg_op
);
10852 if (opcode
== 0xa || opcode
== 0xb) {
10856 /* Accumulating op: handle accumulate step */
10857 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10860 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10861 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10864 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10865 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10868 case 0x7: /* SQDMLSL, SQDMLSL2 */
10869 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10871 case 0x3: /* SQDMLAL, SQDMLAL2 */
10872 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10877 g_assert_not_reached();
10879 tcg_temp_free_i64(tcg_passres
);
10881 tcg_temp_free_i32(tcg_idx
);
10884 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10889 tcg_res
[1] = tcg_const_i64(0);
10892 for (pass
= 0; pass
< 2; pass
++) {
10893 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10894 tcg_temp_free_i64(tcg_res
[pass
]);
10898 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10899 tcg_temp_free_ptr(fpst
);
10904 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10905 * +-----------------+------+-----------+--------+-----+------+------+
10906 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10907 * +-----------------+------+-----------+--------+-----+------+------+
10909 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10911 int size
= extract32(insn
, 22, 2);
10912 int opcode
= extract32(insn
, 12, 5);
10913 int rn
= extract32(insn
, 5, 5);
10914 int rd
= extract32(insn
, 0, 5);
10916 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10917 CryptoThreeOpEnvFn
*genfn
;
10919 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10921 unallocated_encoding(s
);
10926 case 0x4: /* AESE */
10928 genfn
= gen_helper_crypto_aese
;
10930 case 0x6: /* AESMC */
10932 genfn
= gen_helper_crypto_aesmc
;
10934 case 0x5: /* AESD */
10936 genfn
= gen_helper_crypto_aese
;
10938 case 0x7: /* AESIMC */
10940 genfn
= gen_helper_crypto_aesmc
;
10943 unallocated_encoding(s
);
10947 if (!fp_access_check(s
)) {
10951 /* Note that we convert the Vx register indexes into the
10952 * index within the vfp.regs[] array, so we can share the
10953 * helper with the AArch32 instructions.
10955 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10956 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10957 tcg_decrypt
= tcg_const_i32(decrypt
);
10959 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10961 tcg_temp_free_i32(tcg_rd_regno
);
10962 tcg_temp_free_i32(tcg_rn_regno
);
10963 tcg_temp_free_i32(tcg_decrypt
);
10966 /* Crypto three-reg SHA
10967 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10968 * +-----------------+------+---+------+---+--------+-----+------+------+
10969 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10970 * +-----------------+------+---+------+---+--------+-----+------+------+
10972 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10974 int size
= extract32(insn
, 22, 2);
10975 int opcode
= extract32(insn
, 12, 3);
10976 int rm
= extract32(insn
, 16, 5);
10977 int rn
= extract32(insn
, 5, 5);
10978 int rd
= extract32(insn
, 0, 5);
10979 CryptoThreeOpEnvFn
*genfn
;
10980 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10981 int feature
= ARM_FEATURE_V8_SHA256
;
10984 unallocated_encoding(s
);
10989 case 0: /* SHA1C */
10990 case 1: /* SHA1P */
10991 case 2: /* SHA1M */
10992 case 3: /* SHA1SU0 */
10994 feature
= ARM_FEATURE_V8_SHA1
;
10996 case 4: /* SHA256H */
10997 genfn
= gen_helper_crypto_sha256h
;
10999 case 5: /* SHA256H2 */
11000 genfn
= gen_helper_crypto_sha256h2
;
11002 case 6: /* SHA256SU1 */
11003 genfn
= gen_helper_crypto_sha256su1
;
11006 unallocated_encoding(s
);
11010 if (!arm_dc_feature(s
, feature
)) {
11011 unallocated_encoding(s
);
11015 if (!fp_access_check(s
)) {
11019 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11020 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11021 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
11024 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
11026 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
11028 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
11029 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
11030 tcg_temp_free_i32(tcg_opcode
);
11033 tcg_temp_free_i32(tcg_rd_regno
);
11034 tcg_temp_free_i32(tcg_rn_regno
);
11035 tcg_temp_free_i32(tcg_rm_regno
);
11038 /* Crypto two-reg SHA
11039 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
11040 * +-----------------+------+-----------+--------+-----+------+------+
11041 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
11042 * +-----------------+------+-----------+--------+-----+------+------+
11044 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
11046 int size
= extract32(insn
, 22, 2);
11047 int opcode
= extract32(insn
, 12, 5);
11048 int rn
= extract32(insn
, 5, 5);
11049 int rd
= extract32(insn
, 0, 5);
11050 CryptoTwoOpEnvFn
*genfn
;
11052 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
11055 unallocated_encoding(s
);
11060 case 0: /* SHA1H */
11061 feature
= ARM_FEATURE_V8_SHA1
;
11062 genfn
= gen_helper_crypto_sha1h
;
11064 case 1: /* SHA1SU1 */
11065 feature
= ARM_FEATURE_V8_SHA1
;
11066 genfn
= gen_helper_crypto_sha1su1
;
11068 case 2: /* SHA256SU0 */
11069 feature
= ARM_FEATURE_V8_SHA256
;
11070 genfn
= gen_helper_crypto_sha256su0
;
11073 unallocated_encoding(s
);
11077 if (!arm_dc_feature(s
, feature
)) {
11078 unallocated_encoding(s
);
11082 if (!fp_access_check(s
)) {
11086 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11087 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11089 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
11091 tcg_temp_free_i32(tcg_rd_regno
);
11092 tcg_temp_free_i32(tcg_rn_regno
);
11095 /* C3.6 Data processing - SIMD, inc Crypto
11097 * As the decode gets a little complex we are using a table based
11098 * approach for this part of the decode.
11100 static const AArch64DecodeTable data_proc_simd
[] = {
11101 /* pattern , mask , fn */
11102 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
11103 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
11104 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
11105 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
11106 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
11107 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
11108 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
11109 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
11110 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
11111 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
11112 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
11113 { 0x2e000000, 0xbf208400, disas_simd_ext
},
11114 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
11115 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
11116 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
11117 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
11118 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
11119 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
11120 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
11121 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
11122 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
11123 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
11124 { 0x00000000, 0x00000000, NULL
}
11127 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
11129 /* Note that this is called with all non-FP cases from
11130 * table C3-6 so it must UNDEF for entries not specifically
11131 * allocated to instructions in that table.
11133 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
11137 unallocated_encoding(s
);
11141 /* C3.6 Data processing - SIMD and floating point */
11142 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
11144 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
11145 disas_data_proc_fp(s
, insn
);
11147 /* SIMD, including crypto */
11148 disas_data_proc_simd(s
, insn
);
11152 /* C3.1 A64 instruction index by encoding */
11153 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
11157 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
11161 s
->fp_access_checked
= false;
11163 switch (extract32(insn
, 25, 4)) {
11164 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
11165 unallocated_encoding(s
);
11167 case 0x8: case 0x9: /* Data processing - immediate */
11168 disas_data_proc_imm(s
, insn
);
11170 case 0xa: case 0xb: /* Branch, exception generation and system insns */
11171 disas_b_exc_sys(s
, insn
);
11176 case 0xe: /* Loads and stores */
11177 disas_ldst(s
, insn
);
11180 case 0xd: /* Data processing - register */
11181 disas_data_proc_reg(s
, insn
);
11184 case 0xf: /* Data processing - SIMD and floating point */
11185 disas_data_proc_simd_fp(s
, insn
);
11188 assert(FALSE
); /* all 15 cases should be handled above */
11192 /* if we allocated any temporaries, free them here */
11196 static int aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
11197 CPUState
*cpu
, int max_insns
)
11199 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11200 CPUARMState
*env
= cpu
->env_ptr
;
11201 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
11204 dc
->pc
= dc
->base
.pc_first
;
11208 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11209 * there is no secure EL1, so we route exceptions to EL3.
11211 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11212 !arm_el_is_aa64(env
, 3);
11215 dc
->be_data
= ARM_TBFLAG_BE_DATA(dc
->base
.tb
->flags
) ? MO_BE
: MO_LE
;
11216 dc
->condexec_mask
= 0;
11217 dc
->condexec_cond
= 0;
11218 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(dc
->base
.tb
->flags
));
11219 dc
->tbi0
= ARM_TBFLAG_TBI0(dc
->base
.tb
->flags
);
11220 dc
->tbi1
= ARM_TBFLAG_TBI1(dc
->base
.tb
->flags
);
11221 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11222 #if !defined(CONFIG_USER_ONLY)
11223 dc
->user
= (dc
->current_el
== 0);
11225 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(dc
->base
.tb
->flags
);
11227 dc
->vec_stride
= 0;
11228 dc
->cp_regs
= arm_cpu
->cp_regs
;
11229 dc
->features
= env
->features
;
11231 /* Single step state. The code-generation logic here is:
11233 * generate code with no special handling for single-stepping (except
11234 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11235 * this happens anyway because those changes are all system register or
11237 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11238 * emit code for one insn
11239 * emit code to clear PSTATE.SS
11240 * emit code to generate software step exception for completed step
11241 * end TB (as usual for having generated an exception)
11242 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11243 * emit code to generate a software step exception
11246 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(dc
->base
.tb
->flags
);
11247 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(dc
->base
.tb
->flags
);
11248 dc
->is_ldex
= false;
11249 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11251 /* Bound the number of insns to execute to those left on the page. */
11252 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
11254 /* If architectural single step active, limit to 1. */
11255 if (dc
->ss_active
) {
11258 max_insns
= MIN(max_insns
, bound
);
11260 init_tmp_a64_array(dc
);
11265 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
11267 tcg_clear_temp_count();
11270 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
11272 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11274 dc
->insn_start_idx
= tcg_op_buf_count();
11275 tcg_gen_insn_start(dc
->pc
, 0, 0);
11278 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
11279 const CPUBreakpoint
*bp
)
11281 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11283 if (bp
->flags
& BP_CPU
) {
11284 gen_a64_set_pc_im(dc
->pc
);
11285 gen_helper_check_breakpoints(cpu_env
);
11286 /* End the TB early; it likely won't be executed */
11287 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
11289 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11290 /* The address covered by the breakpoint must be
11291 included in [tb->pc, tb->pc + tb->size) in order
11292 to for it to be properly cleared -- thus we
11293 increment the PC here so that the logic setting
11294 tb->size below does the right thing. */
11296 dc
->base
.is_jmp
= DISAS_NORETURN
;
11302 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
11304 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11305 CPUARMState
*env
= cpu
->env_ptr
;
11307 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11308 /* Singlestep state is Active-pending.
11309 * If we're in this state at the start of a TB then either
11310 * a) we just took an exception to an EL which is being debugged
11311 * and this is the first insn in the exception handler
11312 * b) debug exceptions were masked and we just unmasked them
11313 * without changing EL (eg by clearing PSTATE.D)
11314 * In either case we're going to take a swstep exception in the
11315 * "did not step an insn" case, and so the syndrome ISV and EX
11316 * bits should be zero.
11318 assert(dc
->base
.num_insns
== 1);
11319 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11320 default_exception_el(dc
));
11321 dc
->base
.is_jmp
= DISAS_NORETURN
;
11323 disas_a64_insn(env
, dc
);
11326 dc
->base
.pc_next
= dc
->pc
;
11327 translator_loop_temp_check(&dc
->base
);
11330 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
11332 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11334 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
11335 /* Note that this means single stepping WFI doesn't halt the CPU.
11336 * For conditional branch insns this is harmless unreachable code as
11337 * gen_goto_tb() has already handled emitting the debug exception
11338 * (and thus a tb-jump is not possible when singlestepping).
11340 switch (dc
->base
.is_jmp
) {
11342 gen_a64_set_pc_im(dc
->pc
);
11346 if (dc
->base
.singlestep_enabled
) {
11347 gen_exception_internal(EXCP_DEBUG
);
11349 gen_step_complete_exception(dc
);
11352 case DISAS_NORETURN
:
11356 switch (dc
->base
.is_jmp
) {
11358 case DISAS_TOO_MANY
:
11359 gen_goto_tb(dc
, 1, dc
->pc
);
11363 gen_a64_set_pc_im(dc
->pc
);
11366 tcg_gen_lookup_and_goto_ptr(cpu_pc
);
11369 tcg_gen_exit_tb(0);
11371 case DISAS_NORETURN
:
11375 gen_a64_set_pc_im(dc
->pc
);
11376 gen_helper_wfe(cpu_env
);
11379 gen_a64_set_pc_im(dc
->pc
);
11380 gen_helper_yield(cpu_env
);
11383 /* This is a special case because we don't want to just halt the CPU
11384 * if trying to debug across a WFI.
11386 gen_a64_set_pc_im(dc
->pc
);
11387 gen_helper_wfi(cpu_env
);
11388 /* The helper doesn't necessarily throw an exception, but we
11389 * must go back to the main loop to check for interrupts anyway.
11391 tcg_gen_exit_tb(0);
11396 /* Functions above can change dc->pc, so re-align db->pc_next */
11397 dc
->base
.pc_next
= dc
->pc
;
11400 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
11403 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11405 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
11406 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
,
11407 4 | (bswap_code(dc
->sctlr_b
) ? 2 : 0));
11410 const TranslatorOps aarch64_translator_ops
= {
11411 .init_disas_context
= aarch64_tr_init_disas_context
,
11412 .tb_start
= aarch64_tr_tb_start
,
11413 .insn_start
= aarch64_tr_insn_start
,
11414 .breakpoint_check
= aarch64_tr_breakpoint_check
,
11415 .translate_insn
= aarch64_tr_translate_insn
,
11416 .tb_stop
= aarch64_tr_tb_stop
,
11417 .disas_log
= aarch64_tr_disas_log
,