target/arm/machine.c

   1 #include "qemu/osdep.h"
   2 #include "qemu-common.h"
   3 #include "cpu.h"
   4 #include "hw/hw.h"
   5 #include "hw/boards.h"
   6 #include "qemu/error-report.h"
   7 #include "sysemu/kvm.h"
   8 #include "kvm_arm.h"
   9 #include "internals.h"
  10 #include "migration/cpu.h"
  11
  12 static bool vfp_needed(void *opaque)
  13 {
  14     ARMCPU *cpu = opaque;
  15     CPUARMState *env = &cpu->env;
  16
  17     return arm_feature(env, ARM_FEATURE_VFP);
  18 }
  19
  20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
  21                      VMStateField *field)
  22 {
  23     ARMCPU *cpu = opaque;
  24     CPUARMState *env = &cpu->env;
  25     uint32_t val = qemu_get_be32(f);
  26
  27     vfp_set_fpscr(env, val);
  28     return 0;
  29 }
  30
  31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size,
  32                      VMStateField *field, QJSON *vmdesc)
  33 {
  34     ARMCPU *cpu = opaque;
  35     CPUARMState *env = &cpu->env;
  36
  37     qemu_put_be32(f, vfp_get_fpscr(env));
  38     return 0;
  39 }
  40
  41 static const VMStateInfo vmstate_fpscr = {
  42     .name = "fpscr",
  43     .get = get_fpscr,
  44     .put = put_fpscr,
  45 };
  46
  47 static const VMStateDescription vmstate_vfp = {
  48     .name = "cpu/vfp",
  49     .version_id = 3,
  50     .minimum_version_id = 3,
  51     .needed = vfp_needed,
  52     .fields = (VMStateField[]) {
  53         VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
  54         /* The xregs array is a little awkward because element 1 (FPSCR)
  55          * requires a specific accessor, so we have to split it up in
  56          * the vmstate:
  57          */
  58         VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
  59         VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
  60         {
  61             .name = "fpscr",
  62             .version_id = 0,
  63             .size = sizeof(uint32_t),
  64             .info = &vmstate_fpscr,
  65             .flags = VMS_SINGLE,
  66             .offset = 0,
  67         },
  68         VMSTATE_END_OF_LIST()
  69     }
  70 };
  71
  72 static bool iwmmxt_needed(void *opaque)
  73 {
  74     ARMCPU *cpu = opaque;
  75     CPUARMState *env = &cpu->env;
  76
  77     return arm_feature(env, ARM_FEATURE_IWMMXT);
  78 }
  79
  80 static const VMStateDescription vmstate_iwmmxt = {
  81     .name = "cpu/iwmmxt",
  82     .version_id = 1,
  83     .minimum_version_id = 1,
  84     .needed = iwmmxt_needed,
  85     .fields = (VMStateField[]) {
  86         VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
  87         VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
  88         VMSTATE_END_OF_LIST()
  89     }
  90 };
  91
  92 static bool m_needed(void *opaque)
  93 {
  94     ARMCPU *cpu = opaque;
  95     CPUARMState *env = &cpu->env;
  96
  97     return arm_feature(env, ARM_FEATURE_M);
  98 }
  99
 100 static const VMStateDescription vmstate_m_faultmask_primask = {
 101     .name = "cpu/m/faultmask-primask",
 102     .version_id = 1,
 103     .minimum_version_id = 1,
 104     .fields = (VMStateField[]) {
 105         VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU),
 106         VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU),
 107         VMSTATE_END_OF_LIST()
 108     }
 109 };
 110
 111 static const VMStateDescription vmstate_m = {
 112     .name = "cpu/m",
 113     .version_id = 4,
 114     .minimum_version_id = 4,
 115     .needed = m_needed,
 116     .fields = (VMStateField[]) {
 117         VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU),
 118         VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),
 119         VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU),
 120         VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU),
 121         VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU),
 122         VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
 123         VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
 124         VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU),
 125         VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
 126         VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU),
 127         VMSTATE_INT32(env.v7m.exception, ARMCPU),
 128         VMSTATE_END_OF_LIST()
 129     },
 130     .subsections = (const VMStateDescription*[]) {
 131         &vmstate_m_faultmask_primask,
 132         NULL
 133     }
 134 };
 135
 136 static bool thumb2ee_needed(void *opaque)
 137 {
 138     ARMCPU *cpu = opaque;
 139     CPUARMState *env = &cpu->env;
 140
 141     return arm_feature(env, ARM_FEATURE_THUMB2EE);
 142 }
 143
 144 static const VMStateDescription vmstate_thumb2ee = {
 145     .name = "cpu/thumb2ee",
 146     .version_id = 1,
 147     .minimum_version_id = 1,
 148     .needed = thumb2ee_needed,
 149     .fields = (VMStateField[]) {
 150         VMSTATE_UINT32(env.teecr, ARMCPU),
 151         VMSTATE_UINT32(env.teehbr, ARMCPU),
 152         VMSTATE_END_OF_LIST()
 153     }
 154 };
 155
 156 static bool pmsav7_needed(void *opaque)
 157 {
 158     ARMCPU *cpu = opaque;
 159     CPUARMState *env = &cpu->env;
 160
 161     return arm_feature(env, ARM_FEATURE_PMSA) &&
 162            arm_feature(env, ARM_FEATURE_V7) &&
 163            !arm_feature(env, ARM_FEATURE_V8);
 164 }
 165
 166 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
 167 {
 168     ARMCPU *cpu = opaque;
 169
 170     return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion;
 171 }
 172
 173 static const VMStateDescription vmstate_pmsav7 = {
 174     .name = "cpu/pmsav7",
 175     .version_id = 1,
 176     .minimum_version_id = 1,
 177     .needed = pmsav7_needed,
 178     .fields = (VMStateField[]) {
 179         VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
 180                               vmstate_info_uint32, uint32_t),
 181         VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
 182                               vmstate_info_uint32, uint32_t),
 183         VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
 184                               vmstate_info_uint32, uint32_t),
 185         VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
 186         VMSTATE_END_OF_LIST()
 187     }
 188 };
 189
 190 static bool pmsav7_rnr_needed(void *opaque)
 191 {
 192     ARMCPU *cpu = opaque;
 193     CPUARMState *env = &cpu->env;
 194
 195     /* For R profile cores pmsav7.rnr is migrated via the cpreg
 196      * "RGNR" definition in helper.h. For M profile we have to
 197      * migrate it separately.
 198      */
 199     return arm_feature(env, ARM_FEATURE_M);
 200 }
 201
 202 static const VMStateDescription vmstate_pmsav7_rnr = {
 203     .name = "cpu/pmsav7-rnr",
 204     .version_id = 1,
 205     .minimum_version_id = 1,
 206     .needed = pmsav7_rnr_needed,
 207     .fields = (VMStateField[]) {
 208         VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU),
 209         VMSTATE_END_OF_LIST()
 210     }
 211 };
 212
 213 static bool pmsav8_needed(void *opaque)
 214 {
 215     ARMCPU *cpu = opaque;
 216     CPUARMState *env = &cpu->env;
 217
 218     return arm_feature(env, ARM_FEATURE_PMSA) &&
 219         arm_feature(env, ARM_FEATURE_V8);
 220 }
 221
 222 static const VMStateDescription vmstate_pmsav8 = {
 223     .name = "cpu/pmsav8",
 224     .version_id = 1,
 225     .minimum_version_id = 1,
 226     .needed = pmsav8_needed,
 227     .fields = (VMStateField[]) {
 228         VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion,
 229                               0, vmstate_info_uint32, uint32_t),
 230         VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion,
 231                               0, vmstate_info_uint32, uint32_t),
 232         VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
 233         VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
 234         VMSTATE_END_OF_LIST()
 235     }
 236 };
 237
 238 static bool s_rnr_vmstate_validate(void *opaque, int version_id)
 239 {
 240     ARMCPU *cpu = opaque;
 241
 242     return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion;
 243 }
 244
 245 static bool m_security_needed(void *opaque)
 246 {
 247     ARMCPU *cpu = opaque;
 248     CPUARMState *env = &cpu->env;
 249
 250     return arm_feature(env, ARM_FEATURE_M_SECURITY);
 251 }
 252
 253 static const VMStateDescription vmstate_m_security = {
 254     .name = "cpu/m-security",
 255     .version_id = 1,
 256     .minimum_version_id = 1,
 257     .needed = m_security_needed,
 258     .fields = (VMStateField[]) {
 259         VMSTATE_UINT32(env.v7m.secure, ARMCPU),
 260         VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU),
 261         VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU),
 262         VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU),
 263         VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),
 264         VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),
 265         VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU),
 266         VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),
 267         VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU),
 268         VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU),
 269         VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion,
 270                               0, vmstate_info_uint32, uint32_t),
 271         VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion,
 272                               0, vmstate_info_uint32, uint32_t),
 273         VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU),
 274         VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),
 275         VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),
 276         VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU),
 277         VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU),
 278         VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU),
 279         VMSTATE_END_OF_LIST()
 280     }
 281 };
 282
 283 static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
 284                     VMStateField *field)
 285 {
 286     ARMCPU *cpu = opaque;
 287     CPUARMState *env = &cpu->env;
 288     uint32_t val = qemu_get_be32(f);
 289
 290     if (arm_feature(env, ARM_FEATURE_M)) {
 291         if (val & XPSR_EXCP) {
 292             /* This is a CPSR format value from an older QEMU. (We can tell
 293              * because values transferred in XPSR format always have zero
 294              * for the EXCP field, and CPSR format will always have bit 4
 295              * set in CPSR_M.) Rearrange it into XPSR format. The significant
 296              * differences are that the T bit is not in the same place, the
 297              * primask/faultmask info may be in the CPSR I and F bits, and
 298              * we do not want the mode bits.
 299              * We know that this cleanup happened before v8M, so there
 300              * is no complication with banked primask/faultmask.
 301              */
 302             uint32_t newval = val;
 303
 304             assert(!arm_feature(env, ARM_FEATURE_M_SECURITY));
 305
 306             newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE);
 307             if (val & CPSR_T) {
 308                 newval |= XPSR_T;
 309             }
 310             /* If the I or F bits are set then this is a migration from
 311              * an old QEMU which still stored the M profile FAULTMASK
 312              * and PRIMASK in env->daif. For a new QEMU, the data is
 313              * transferred using the vmstate_m_faultmask_primask subsection.
 314              */
 315             if (val & CPSR_F) {
 316                 env->v7m.faultmask[M_REG_NS] = 1;
 317             }
 318             if (val & CPSR_I) {
 319                 env->v7m.primask[M_REG_NS] = 1;
 320             }
 321             val = newval;
 322         }
 323         /* Ignore the low bits, they are handled by vmstate_m. */
 324         xpsr_write(env, val, ~XPSR_EXCP);
 325         return 0;
 326     }
 327
 328     env->aarch64 = ((val & PSTATE_nRW) == 0);
 329
 330     if (is_a64(env)) {
 331         pstate_write(env, val);
 332         return 0;
 333     }
 334
 335     cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
 336     return 0;
 337 }
 338
 339 static int put_cpsr(QEMUFile *f, void *opaque, size_t size,
 340                     VMStateField *field, QJSON *vmdesc)
 341 {
 342     ARMCPU *cpu = opaque;
 343     CPUARMState *env = &cpu->env;
 344     uint32_t val;
 345
 346     if (arm_feature(env, ARM_FEATURE_M)) {
 347         /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */
 348         val = xpsr_read(env) & ~XPSR_EXCP;
 349     } else if (is_a64(env)) {
 350         val = pstate_read(env);
 351     } else {
 352         val = cpsr_read(env);
 353     }
 354
 355     qemu_put_be32(f, val);
 356     return 0;
 357 }
 358
 359 static const VMStateInfo vmstate_cpsr = {
 360     .name = "cpsr",
 361     .get = get_cpsr,
 362     .put = put_cpsr,
 363 };
 364
 365 static int get_power(QEMUFile *f, void *opaque, size_t size,
 366                     VMStateField *field)
 367 {
 368     ARMCPU *cpu = opaque;
 369     bool powered_off = qemu_get_byte(f);
 370     cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON;
 371     return 0;
 372 }
 373
 374 static int put_power(QEMUFile *f, void *opaque, size_t size,
 375                     VMStateField *field, QJSON *vmdesc)
 376 {
 377     ARMCPU *cpu = opaque;
 378
 379     /* Migration should never happen while we transition power states */
 380
 381     if (cpu->power_state == PSCI_ON ||
 382         cpu->power_state == PSCI_OFF) {
 383         bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false;
 384         qemu_put_byte(f, powered_off);
 385         return 0;
 386     } else {
 387         return 1;
 388     }
 389 }
 390
 391 static const VMStateInfo vmstate_powered_off = {
 392     .name = "powered_off",
 393     .get = get_power,
 394     .put = put_power,
 395 };
 396
 397 static void cpu_pre_save(void *opaque)
 398 {
 399     ARMCPU *cpu = opaque;
 400
 401     if (kvm_enabled()) {
 402         if (!write_kvmstate_to_list(cpu)) {
 403             /* This should never fail */
 404             abort();
 405         }
 406     } else {
 407         if (!write_cpustate_to_list(cpu)) {
 408             /* This should never fail. */
 409             abort();
 410         }
 411     }
 412
 413     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 414     memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
 415            cpu->cpreg_array_len * sizeof(uint64_t));
 416     memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
 417            cpu->cpreg_array_len * sizeof(uint64_t));
 418 }
 419
 420 static int cpu_post_load(void *opaque, int version_id)
 421 {
 422     ARMCPU *cpu = opaque;
 423     int i, v;
 424
 425     /* Update the values list from the incoming migration data.
 426      * Anything in the incoming data which we don't know about is
 427      * a migration failure; anything we know about but the incoming
 428      * data doesn't specify retains its current (reset) value.
 429      * The indexes list remains untouched -- we only inspect the
 430      * incoming migration index list so we can match the values array
 431      * entries with the right slots in our own values array.
 432      */
 433
 434     for (i = 0, v = 0; i < cpu->cpreg_array_len
 435              && v < cpu->cpreg_vmstate_array_len; i++) {
 436         if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
 437             /* register in our list but not incoming : skip it */
 438             continue;
 439         }
 440         if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
 441             /* register in their list but not ours: fail migration */
 442             return -1;
 443         }
 444         /* matching register, copy the value over */
 445         cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
 446         v++;
 447     }
 448
 449     if (kvm_enabled()) {
 450         if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
 451             return -1;
 452         }
 453         /* Note that it's OK for the TCG side not to know about
 454          * every register in the list; KVM is authoritative if
 455          * we're using it.
 456          */
 457         write_list_to_cpustate(cpu);
 458     } else {
 459         if (!write_list_to_cpustate(cpu)) {
 460             return -1;
 461         }
 462     }
 463
 464     hw_breakpoint_update_all(cpu);
 465     hw_watchpoint_update_all(cpu);
 466
 467     return 0;
 468 }
 469
 470 const VMStateDescription vmstate_arm_cpu = {
 471     .name = "cpu",
 472     .version_id = 22,
 473     .minimum_version_id = 22,
 474     .pre_save = cpu_pre_save,
 475     .post_load = cpu_post_load,
 476     .fields = (VMStateField[]) {
 477         VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
 478         VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
 479         VMSTATE_UINT64(env.pc, ARMCPU),
 480         {
 481             .name = "cpsr",
 482             .version_id = 0,
 483             .size = sizeof(uint32_t),
 484             .info = &vmstate_cpsr,
 485             .flags = VMS_SINGLE,
 486             .offset = 0,
 487         },
 488         VMSTATE_UINT32(env.spsr, ARMCPU),
 489         VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
 490         VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
 491         VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
 492         VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
 493         VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
 494         VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
 495         VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
 496         /* The length-check must come before the arrays to avoid
 497          * incoming data possibly overflowing the array.
 498          */
 499         VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
 500         VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
 501                              cpreg_vmstate_array_len,
 502                              0, vmstate_info_uint64, uint64_t),
 503         VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
 504                              cpreg_vmstate_array_len,
 505                              0, vmstate_info_uint64, uint64_t),
 506         VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
 507         VMSTATE_UINT64(env.exclusive_val, ARMCPU),
 508         VMSTATE_UINT64(env.exclusive_high, ARMCPU),
 509         VMSTATE_UINT64(env.features, ARMCPU),
 510         VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
 511         VMSTATE_UINT32(env.exception.fsr, ARMCPU),
 512         VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
 513         VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
 514         VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
 515         {
 516             .name = "power_state",
 517             .version_id = 0,
 518             .size = sizeof(bool),
 519             .info = &vmstate_powered_off,
 520             .flags = VMS_SINGLE,
 521             .offset = 0,
 522         },
 523         VMSTATE_END_OF_LIST()
 524     },
 525     .subsections = (const VMStateDescription*[]) {
 526         &vmstate_vfp,
 527         &vmstate_iwmmxt,
 528         &vmstate_m,
 529         &vmstate_thumb2ee,
 530         /* pmsav7_rnr must come before pmsav7 so that we have the
 531          * region number before we test it in the VMSTATE_VALIDATE
 532          * in vmstate_pmsav7.
 533          */
 534         &vmstate_pmsav7_rnr,
 535         &vmstate_pmsav7,
 536         &vmstate_pmsav8,
 537         &vmstate_m_security,
 538         NULL
 539     }
 540 };