hw/arm/mps2-tz.c

   1 /*
   2  * ARM V2M MPS2 board emulation, trustzone aware FPGA images
   3  *
   4  * Copyright (c) 2017 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
  13  * FPGA but is otherwise the same as the 2). Since the CPU itself
  14  * and most of the devices are in the FPGA, the details of the board
  15  * as seen by the guest depend significantly on the FPGA image.
  16  * This source file covers the following FPGA images, for TrustZone cores:
  17  *  "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
  18  *
  19  * Links to the TRM for the board itself and to the various Application
  20  * Notes which document the FPGA images can be found here:
  21  * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
  22  *
  23  * Board TRM:
  24  * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf
  25  * Application Note AN505:
  26  * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
  27  *
  28  * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
  29  * (ARM ECM0601256) for the details of some of the device layout:
  30  *   http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  31  */
  32
  33 #include "qemu/osdep.h"
  34 #include "qapi/error.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/arm/arm.h"
  37 #include "hw/arm/armv7m.h"
  38 #include "hw/or-irq.h"
  39 #include "hw/boards.h"
  40 #include "exec/address-spaces.h"
  41 #include "sysemu/sysemu.h"
  42 #include "hw/misc/unimp.h"
  43 #include "hw/char/cmsdk-apb-uart.h"
  44 #include "hw/timer/cmsdk-apb-timer.h"
  45 #include "hw/misc/mps2-scc.h"
  46 #include "hw/misc/mps2-fpgaio.h"
  47 #include "hw/misc/tz-mpc.h"
  48 #include "hw/misc/tz-msc.h"
  49 #include "hw/arm/iotkit.h"
  50 #include "hw/dma/pl080.h"
  51 #include "hw/ssi/pl022.h"
  52 #include "hw/devices.h"
  53 #include "net/net.h"
  54 #include "hw/core/split-irq.h"
  55
  56 typedef enum MPS2TZFPGAType {
  57     FPGA_AN505,
  58 } MPS2TZFPGAType;
  59
  60 typedef struct {
  61     MachineClass parent;
  62     MPS2TZFPGAType fpga_type;
  63     uint32_t scc_id;
  64 } MPS2TZMachineClass;
  65
  66 typedef struct {
  67     MachineState parent;
  68
  69     IoTKit iotkit;
  70     MemoryRegion psram;
  71     MemoryRegion ssram[3];
  72     MemoryRegion ssram1_m;
  73     MPS2SCC scc;
  74     MPS2FPGAIO fpgaio;
  75     TZPPC ppc[5];
  76     TZMPC ssram_mpc[3];
  77     PL022State spi[5];
  78     UnimplementedDeviceState i2c[4];
  79     UnimplementedDeviceState i2s_audio;
  80     UnimplementedDeviceState gpio[4];
  81     UnimplementedDeviceState gfx;
  82     PL080State dma[4];
  83     TZMSC msc[4];
  84     CMSDKAPBUART uart[5];
  85     SplitIRQ sec_resp_splitter;
  86     qemu_or_irq uart_irq_orgate;
  87     DeviceState *lan9118;
  88 } MPS2TZMachineState;
  89
  90 #define TYPE_MPS2TZ_MACHINE "mps2tz"
  91 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
  92
  93 #define MPS2TZ_MACHINE(obj) \
  94     OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE)
  95 #define MPS2TZ_MACHINE_GET_CLASS(obj) \
  96     OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE)
  97 #define MPS2TZ_MACHINE_CLASS(klass) \
  98     OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE)
  99
 100 /* Main SYSCLK frequency in Hz */
 101 #define SYSCLK_FRQ 20000000
 102
 103 /* Create an alias of an entire original MemoryRegion @orig
 104  * located at @base in the memory map.
 105  */
 106 static void make_ram_alias(MemoryRegion *mr, const char *name,
 107                            MemoryRegion *orig, hwaddr base)
 108 {
 109     memory_region_init_alias(mr, NULL, name, orig, 0,
 110                              memory_region_size(orig));
 111     memory_region_add_subregion(get_system_memory(), base, mr);
 112 }
 113
 114 /* Most of the devices in the AN505 FPGA image sit behind
 115  * Peripheral Protection Controllers. These data structures
 116  * define the layout of which devices sit behind which PPCs.
 117  * The devfn for each port is a function which creates, configures
 118  * and initializes the device, returning the MemoryRegion which
 119  * needs to be plugged into the downstream end of the PPC port.
 120  */
 121 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque,
 122                                 const char *name, hwaddr size);
 123
 124 typedef struct PPCPortInfo {
 125     const char *name;
 126     MakeDevFn *devfn;
 127     void *opaque;
 128     hwaddr addr;
 129     hwaddr size;
 130 } PPCPortInfo;
 131
 132 typedef struct PPCInfo {
 133     const char *name;
 134     PPCPortInfo ports[TZ_NUM_PORTS];
 135 } PPCInfo;
 136
 137 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
 138                                        void *opaque,
 139                                        const char *name, hwaddr size)
 140 {
 141     /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
 142      * and return a pointer to its MemoryRegion.
 143      */
 144     UnimplementedDeviceState *uds = opaque;
 145
 146     sysbus_init_child_obj(OBJECT(mms), name, uds,
 147                           sizeof(UnimplementedDeviceState),
 148                           TYPE_UNIMPLEMENTED_DEVICE);
 149     qdev_prop_set_string(DEVICE(uds), "name", name);
 150     qdev_prop_set_uint64(DEVICE(uds), "size", size);
 151     object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
 152     return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
 153 }
 154
 155 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
 156                                const char *name, hwaddr size)
 157 {
 158     CMSDKAPBUART *uart = opaque;
 159     int i = uart - &mms->uart[0];
 160     int rxirqno = i * 2;
 161     int txirqno = i * 2 + 1;
 162     int combirqno = i + 10;
 163     SysBusDevice *s;
 164     DeviceState *iotkitdev = DEVICE(&mms->iotkit);
 165     DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
 166
 167     sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
 168                           TYPE_CMSDK_APB_UART);
 169     qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
 170     qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
 171     object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
 172     s = SYS_BUS_DEVICE(uart);
 173     sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev,
 174                                                     "EXP_IRQ", txirqno));
 175     sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev,
 176                                                     "EXP_IRQ", rxirqno));
 177     sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
 178     sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
 179     sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev,
 180                                                     "EXP_IRQ", combirqno));
 181     return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
 182 }
 183
 184 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
 185                               const char *name, hwaddr size)
 186 {
 187     MPS2SCC *scc = opaque;
 188     DeviceState *sccdev;
 189     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
 190
 191     object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC);
 192     sccdev = DEVICE(scc);
 193     qdev_set_parent_bus(sccdev, sysbus_get_default());
 194     qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
 195     qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
 196     qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
 197     object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal);
 198     return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
 199 }
 200
 201 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,
 202                                  const char *name, hwaddr size)
 203 {
 204     MPS2FPGAIO *fpgaio = opaque;
 205
 206     object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO);
 207     qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default());
 208     object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal);
 209     return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);
 210 }
 211
 212 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
 213                                   const char *name, hwaddr size)
 214 {
 215     SysBusDevice *s;
 216     DeviceState *iotkitdev = DEVICE(&mms->iotkit);
 217     NICInfo *nd = &nd_table[0];
 218
 219     /* In hardware this is a LAN9220; the LAN9118 is software compatible
 220      * except that it doesn't support the checksum-offload feature.
 221      */
 222     qemu_check_nic_model(nd, "lan9118");
 223     mms->lan9118 = qdev_create(NULL, "lan9118");
 224     qdev_set_nic_properties(mms->lan9118, nd);
 225     qdev_init_nofail(mms->lan9118);
 226
 227     s = SYS_BUS_DEVICE(mms->lan9118);
 228     sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16));
 229     return sysbus_mmio_get_region(s, 0);
 230 }
 231
 232 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
 233                               const char *name, hwaddr size)
 234 {
 235     TZMPC *mpc = opaque;
 236     int i = mpc - &mms->ssram_mpc[0];
 237     MemoryRegion *ssram = &mms->ssram[i];
 238     MemoryRegion *upstream;
 239     char *mpcname = g_strdup_printf("%s-mpc", name);
 240     static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 };
 241     static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 };
 242
 243     memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
 244
 245     sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]),
 246                           TYPE_TZ_MPC);
 247     object_property_set_link(OBJECT(mpc), OBJECT(ssram),
 248                              "downstream", &error_fatal);
 249     object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
 250     /* Map the upstream end of the MPC into system memory */
 251     upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
 252     memory_region_add_subregion(get_system_memory(), rambase[i], upstream);
 253     /* and connect its interrupt to the IoTKit */
 254     qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
 255                                 qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
 256                                                        "mpcexp_status", i));
 257
 258     /* The first SSRAM is a special case as it has an alias; accesses to
 259      * the alias region at 0x00400000 must also go to the MPC upstream.
 260      */
 261     if (i == 0) {
 262         make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000);
 263     }
 264
 265     g_free(mpcname);
 266     /* Return the register interface MR for our caller to map behind the PPC */
 267     return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
 268 }
 269
 270 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
 271                               const char *name, hwaddr size)
 272 {
 273     PL080State *dma = opaque;
 274     int i = dma - &mms->dma[0];
 275     SysBusDevice *s;
 276     char *mscname = g_strdup_printf("%s-msc", name);
 277     TZMSC *msc = &mms->msc[i];
 278     DeviceState *iotkitdev = DEVICE(&mms->iotkit);
 279     MemoryRegion *msc_upstream;
 280     MemoryRegion *msc_downstream;
 281
 282     /*
 283      * Each DMA device is a PL081 whose transaction master interface
 284      * is guarded by a Master Security Controller. The downstream end of
 285      * the MSC connects to the IoTKit AHB Slave Expansion port, so the
 286      * DMA devices can see all devices and memory that the CPU does.
 287      */
 288     sysbus_init_child_obj(OBJECT(mms), mscname, msc, sizeof(*msc), TYPE_TZ_MSC);
 289     msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0);
 290     object_property_set_link(OBJECT(msc), OBJECT(msc_downstream),
 291                              "downstream", &error_fatal);
 292     object_property_set_link(OBJECT(msc), OBJECT(mms),
 293                              "idau", &error_fatal);
 294     object_property_set_bool(OBJECT(msc), true, "realized", &error_fatal);
 295
 296     qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0,
 297                                 qdev_get_gpio_in_named(iotkitdev,
 298                                                        "mscexp_status", i));
 299     qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i,
 300                                 qdev_get_gpio_in_named(DEVICE(msc),
 301                                                        "irq_clear", 0));
 302     qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i,
 303                                 qdev_get_gpio_in_named(DEVICE(msc),
 304                                                        "cfg_nonsec", 0));
 305     qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter),
 306                           ARRAY_SIZE(mms->ppc) + i,
 307                           qdev_get_gpio_in_named(DEVICE(msc),
 308                                                  "cfg_sec_resp", 0));
 309     msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0);
 310
 311     sysbus_init_child_obj(OBJECT(mms), name, dma, sizeof(*dma), TYPE_PL081);
 312     object_property_set_link(OBJECT(dma), OBJECT(msc_upstream),
 313                              "downstream", &error_fatal);
 314     object_property_set_bool(OBJECT(dma), true, "realized", &error_fatal);
 315
 316     s = SYS_BUS_DEVICE(dma);
 317     /* Wire up DMACINTR, DMACINTERR, DMACINTTC */
 318     sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev,
 319                                                     "EXP_IRQ", 58 + i * 3));
 320     sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev,
 321                                                     "EXP_IRQ", 56 + i * 3));
 322     sysbus_connect_irq(s, 2, qdev_get_gpio_in_named(iotkitdev,
 323                                                     "EXP_IRQ", 57 + i * 3));
 324
 325     g_free(mscname);
 326     return sysbus_mmio_get_region(s, 0);
 327 }
 328
 329 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
 330                               const char *name, hwaddr size)
 331 {
 332     /*
 333      * The AN505 has five PL022 SPI controllers.
 334      * One of these should have the LCD controller behind it; the others
 335      * are connected only to the FPGA's "general purpose SPI connector"
 336      * or "shield" expansion connectors.
 337      * Note that if we do implement devices behind SPI, the chip select
 338      * lines are set via the "MISC" register in the MPS2 FPGAIO device.
 339      */
 340     PL022State *spi = opaque;
 341     int i = spi - &mms->spi[0];
 342     DeviceState *iotkitdev = DEVICE(&mms->iotkit);
 343     SysBusDevice *s;
 344
 345     sysbus_init_child_obj(OBJECT(mms), name, spi, sizeof(mms->spi[0]),
 346                           TYPE_PL022);
 347     object_property_set_bool(OBJECT(spi), true, "realized", &error_fatal);
 348     s = SYS_BUS_DEVICE(spi);
 349     sysbus_connect_irq(s, 0,
 350                        qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 51 + i));
 351     return sysbus_mmio_get_region(s, 0);
 352 }
 353
 354 static void mps2tz_common_init(MachineState *machine)
 355 {
 356     MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
 357     MachineClass *mc = MACHINE_GET_CLASS(machine);
 358     MemoryRegion *system_memory = get_system_memory();
 359     DeviceState *iotkitdev;
 360     DeviceState *dev_splitter;
 361     int i;
 362
 363     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
 364         error_report("This board can only be used with CPU %s",
 365                      mc->default_cpu_type);
 366         exit(1);
 367     }
 368
 369     sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
 370                           sizeof(mms->iotkit), TYPE_IOTKIT);
 371     iotkitdev = DEVICE(&mms->iotkit);
 372     object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
 373                              "memory", &error_abort);
 374     qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92);
 375     qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ);
 376     object_property_set_bool(OBJECT(&mms->iotkit), true, "realized",
 377                              &error_fatal);
 378
 379     /* The sec_resp_cfg output from the IoTKit must be split into multiple
 380      * lines, one for each of the PPCs we create here, plus one per MSC.
 381      */
 382     object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter),
 383                       TYPE_SPLIT_IRQ);
 384     object_property_add_child(OBJECT(machine), "sec-resp-splitter",
 385                               OBJECT(&mms->sec_resp_splitter), &error_abort);
 386     object_property_set_int(OBJECT(&mms->sec_resp_splitter),
 387                             ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc),
 388                             "num-lines", &error_fatal);
 389     object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,
 390                              "realized", &error_fatal);
 391     dev_splitter = DEVICE(&mms->sec_resp_splitter);
 392     qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,
 393                                 qdev_get_gpio_in(dev_splitter, 0));
 394
 395     /* The IoTKit sets up much of the memory layout, including
 396      * the aliases between secure and non-secure regions in the
 397      * address space. The FPGA itself contains:
 398      *
 399      * 0x00000000..0x003fffff  SSRAM1
 400      * 0x00400000..0x007fffff  alias of SSRAM1
 401      * 0x28000000..0x283fffff  4MB SSRAM2 + SSRAM3
 402      * 0x40100000..0x4fffffff  AHB Master Expansion 1 interface devices
 403      * 0x80000000..0x80ffffff  16MB PSRAM
 404      */
 405
 406     /* The FPGA images have an odd combination of different RAMs,
 407      * because in hardware they are different implementations and
 408      * connected to different buses, giving varying performance/size
 409      * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
 410      * call the 16MB our "system memory", as it's the largest lump.
 411      */
 412     memory_region_allocate_system_memory(&mms->psram,
 413                                          NULL, "mps.ram", 0x01000000);
 414     memory_region_add_subregion(system_memory, 0x80000000, &mms->psram);
 415
 416     /* The overflow IRQs for all UARTs are ORed together.
 417      * Tx, Rx and "combined" IRQs are sent to the NVIC separately.
 418      * Create the OR gate for this.
 419      */
 420     object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate),
 421                       TYPE_OR_IRQ);
 422     object_property_add_child(OBJECT(mms), "uart-irq-orgate",
 423                               OBJECT(&mms->uart_irq_orgate), &error_abort);
 424     object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines",
 425                             &error_fatal);
 426     object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true,
 427                              "realized", &error_fatal);
 428     qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
 429                           qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15));
 430
 431     /* Most of the devices in the FPGA are behind Peripheral Protection
 432      * Controllers. The required order for initializing things is:
 433      *  + initialize the PPC
 434      *  + initialize, configure and realize downstream devices
 435      *  + connect downstream device MemoryRegions to the PPC
 436      *  + realize the PPC
 437      *  + map the PPC's MemoryRegions to the places in the address map
 438      *    where the downstream devices should appear
 439      *  + wire up the PPC's control lines to the IoTKit object
 440      */
 441
 442     const PPCInfo ppcs[] = { {
 443             .name = "apb_ppcexp0",
 444             .ports = {
 445                 { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 },
 446                 { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 },
 447                 { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 },
 448             },
 449         }, {
 450             .name = "apb_ppcexp1",
 451             .ports = {
 452                 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 },
 453                 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 },
 454                 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 },
 455                 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 },
 456                 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 },
 457                 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 },
 458                 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 },
 459                 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 },
 460                 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 },
 461                 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 },
 462                 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 },
 463                 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 },
 464                 { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 },
 465                 { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 },
 466             },
 467         }, {
 468             .name = "apb_ppcexp2",
 469             .ports = {
 470                 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 },
 471                 { "i2s-audio", make_unimp_dev, &mms->i2s_audio,
 472                   0x40301000, 0x1000 },
 473                 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 },
 474             },
 475         }, {
 476             .name = "ahb_ppcexp0",
 477             .ports = {
 478                 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 },
 479                 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 },
 480                 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 },
 481                 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 },
 482                 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 },
 483                 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 },
 484             },
 485         }, {
 486             .name = "ahb_ppcexp1",
 487             .ports = {
 488                 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 },
 489                 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 },
 490                 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 },
 491                 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 },
 492             },
 493         },
 494     };
 495
 496     for (i = 0; i < ARRAY_SIZE(ppcs); i++) {
 497         const PPCInfo *ppcinfo = &ppcs[i];
 498         TZPPC *ppc = &mms->ppc[i];
 499         DeviceState *ppcdev;
 500         int port;
 501         char *gpioname;
 502
 503         sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
 504                               sizeof(TZPPC), TYPE_TZ_PPC);
 505         ppcdev = DEVICE(ppc);
 506
 507         for (port = 0; port < TZ_NUM_PORTS; port++) {
 508             const PPCPortInfo *pinfo = &ppcinfo->ports[port];
 509             MemoryRegion *mr;
 510             char *portname;
 511
 512             if (!pinfo->devfn) {
 513                 continue;
 514             }
 515
 516             mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
 517             portname = g_strdup_printf("port[%d]", port);
 518             object_property_set_link(OBJECT(ppc), OBJECT(mr),
 519                                      portname, &error_fatal);
 520             g_free(portname);
 521         }
 522
 523         object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal);
 524
 525         for (port = 0; port < TZ_NUM_PORTS; port++) {
 526             const PPCPortInfo *pinfo = &ppcinfo->ports[port];
 527
 528             if (!pinfo->devfn) {
 529                 continue;
 530             }
 531             sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr);
 532
 533             gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name);
 534             qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
 535                                         qdev_get_gpio_in_named(ppcdev,
 536                                                                "cfg_nonsec",
 537                                                                port));
 538             g_free(gpioname);
 539             gpioname = g_strdup_printf("%s_ap", ppcinfo->name);
 540             qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
 541                                         qdev_get_gpio_in_named(ppcdev,
 542                                                                "cfg_ap", port));
 543             g_free(gpioname);
 544         }
 545
 546         gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name);
 547         qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
 548                                     qdev_get_gpio_in_named(ppcdev,
 549                                                            "irq_enable", 0));
 550         g_free(gpioname);
 551         gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name);
 552         qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
 553                                     qdev_get_gpio_in_named(ppcdev,
 554                                                            "irq_clear", 0));
 555         g_free(gpioname);
 556         gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name);
 557         qdev_connect_gpio_out_named(ppcdev, "irq", 0,
 558                                     qdev_get_gpio_in_named(iotkitdev,
 559                                                            gpioname, 0));
 560         g_free(gpioname);
 561
 562         qdev_connect_gpio_out(dev_splitter, i,
 563                               qdev_get_gpio_in_named(ppcdev,
 564                                                      "cfg_sec_resp", 0));
 565     }
 566
 567     create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
 568
 569     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000);
 570 }
 571
 572 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address,
 573                                int *iregion, bool *exempt, bool *ns, bool *nsc)
 574 {
 575     /*
 576      * The MPS2 TZ FPGA images have IDAUs in them which are connected to
 577      * the Master Security Controllers. Thes have the same logic as
 578      * is used by the IoTKit for the IDAU connected to the CPU, except
 579      * that MSCs don't care about the NSC attribute.
 580      */
 581     int region = extract32(address, 28, 4);
 582
 583     *ns = !(region & 1);
 584     *nsc = false;
 585     /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
 586     *exempt = (address & 0xeff00000) == 0xe0000000;
 587     *iregion = region;
 588 }
 589
 590 static void mps2tz_class_init(ObjectClass *oc, void *data)
 591 {
 592     MachineClass *mc = MACHINE_CLASS(oc);
 593     IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
 594
 595     mc->init = mps2tz_common_init;
 596     mc->max_cpus = 1;
 597     iic->check = mps2_tz_idau_check;
 598 }
 599
 600 static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
 601 {
 602     MachineClass *mc = MACHINE_CLASS(oc);
 603     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 604
 605     mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33";
 606     mmc->fpga_type = FPGA_AN505;
 607     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
 608     mmc->scc_id = 0x41045050;
 609 }
 610
 611 static const TypeInfo mps2tz_info = {
 612     .name = TYPE_MPS2TZ_MACHINE,
 613     .parent = TYPE_MACHINE,
 614     .abstract = true,
 615     .instance_size = sizeof(MPS2TZMachineState),
 616     .class_size = sizeof(MPS2TZMachineClass),
 617     .class_init = mps2tz_class_init,
 618     .interfaces = (InterfaceInfo[]) {
 619         { TYPE_IDAU_INTERFACE },
 620         { }
 621     },
 622 };
 623
 624 static const TypeInfo mps2tz_an505_info = {
 625     .name = TYPE_MPS2TZ_AN505_MACHINE,
 626     .parent = TYPE_MPS2TZ_MACHINE,
 627     .class_init = mps2tz_an505_class_init,
 628 };
 629
 630 static void mps2tz_machine_init(void)
 631 {
 632     type_register_static(&mps2tz_info);
 633     type_register_static(&mps2tz_an505_info);
 634 }
 635
 636 type_init(mps2tz_machine_init);