hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31 #ifdef DEBUG_PCI
  32 # define PCI_DPRINTF(format, ...)       printf(format, __VA_ARGS__)
  33 #else
  34 # define PCI_DPRINTF(format, ...)       do { } while (0)
  35 #endif
  36
  37 struct PCIBus {
  38     BusState qbus;
  39     int bus_num;
  40     int devfn_min;
  41     pci_set_irq_fn set_irq;
  42     pci_map_irq_fn map_irq;
  43     uint32_t config_reg; /* XXX: suppress */
  44     /* low level pic */
  45     SetIRQFunc *low_set_irq;
  46     qemu_irq *irq_opaque;
  47     PCIDevice *devices[256];
  48     PCIDevice *parent_dev;
  49     PCIBus *next;
  50     /* The bus IRQ state is the logical OR of the connected devices.
  51        Keep a count of the number of devices with raised IRQs.  */
  52     int nirq;
  53     int *irq_count;
  54 };
  55
  56 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  57
  58 static struct BusInfo pci_bus_info = {
  59     .name       = "PCI",
  60     .size       = sizeof(PCIBus),
  61     .print_dev  = pcibus_dev_print,
  62     .props      = (Property[]) {
  63         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  64         DEFINE_PROP_END_OF_LIST()
  65     }
  66 };
  67
  68 static void pci_update_mappings(PCIDevice *d);
  69 static void pci_set_irq(void *opaque, int irq_num, int level);
  70
  71 target_phys_addr_t pci_mem_base;
  72 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  73 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  74 static PCIBus *first_bus;
  75
  76 static const VMStateDescription vmstate_pcibus = {
  77     .name = "PCIBUS",
  78     .version_id = 1,
  79     .minimum_version_id = 1,
  80     .minimum_version_id_old = 1,
  81     .fields      = (VMStateField []) {
  82         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  83         VMSTATE_INT32_VARRAY(irq_count, PCIBus, nirq),
  84         VMSTATE_END_OF_LIST()
  85     }
  86 };
  87
  88 static void pci_bus_reset(void *opaque)
  89 {
  90     PCIBus *bus = (PCIBus *)opaque;
  91     int i;
  92
  93     for (i = 0; i < bus->nirq; i++) {
  94         bus->irq_count[i] = 0;
  95     }
  96     for (i = 0; i < 256; i++) {
  97         if (bus->devices[i])
  98             memset(bus->devices[i]->irq_state, 0,
  99                    sizeof(bus->devices[i]->irq_state));
 100     }
 101 }
 102
 103 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 104                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 105                          qemu_irq *pic, int devfn_min, int nirq)
 106 {
 107     PCIBus *bus;
 108     static int nbus = 0;
 109
 110     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name));
 111     bus->set_irq = set_irq;
 112     bus->map_irq = map_irq;
 113     bus->irq_opaque = pic;
 114     bus->devfn_min = devfn_min;
 115     bus->nirq = nirq;
 116     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 117     bus->next = first_bus;
 118     first_bus = bus;
 119     vmstate_register(nbus++, &vmstate_pcibus, bus);
 120     qemu_register_reset(pci_bus_reset, bus);
 121     return bus;
 122 }
 123
 124 static PCIBus *pci_register_secondary_bus(PCIDevice *dev,
 125                                           pci_map_irq_fn map_irq,
 126                                           const char *name)
 127 {
 128     PCIBus *bus;
 129
 130     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, &dev->qdev, name));
 131     bus->map_irq = map_irq;
 132     bus->parent_dev = dev;
 133     bus->next = dev->bus->next;
 134     dev->bus->next = bus;
 135     return bus;
 136 }
 137
 138 int pci_bus_num(PCIBus *s)
 139 {
 140     return s->bus_num;
 141 }
 142
 143 void pci_device_save(PCIDevice *s, QEMUFile *f)
 144 {
 145     int i;
 146
 147     qemu_put_be32(f, s->version_id); /* PCI device version */
 148     qemu_put_buffer(f, s->config, 256);
 149     for (i = 0; i < 4; i++)
 150         qemu_put_be32(f, s->irq_state[i]);
 151 }
 152
 153 int pci_device_load(PCIDevice *s, QEMUFile *f)
 154 {
 155     uint8_t config[PCI_CONFIG_SPACE_SIZE];
 156     uint32_t version_id;
 157     int i;
 158
 159     version_id = qemu_get_be32(f);
 160     if (version_id > 2)
 161         return -EINVAL;
 162     qemu_get_buffer(f, config, sizeof config);
 163     for (i = 0; i < sizeof config; ++i)
 164         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 165             return -EINVAL;
 166     memcpy(s->config, config, sizeof config);
 167
 168     pci_update_mappings(s);
 169
 170     if (version_id >= 2)
 171         for (i = 0; i < 4; i ++)
 172             s->irq_state[i] = qemu_get_be32(f);
 173     return 0;
 174 }
 175
 176 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 177 {
 178     uint16_t *id;
 179
 180     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 181     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 182     id[1] = cpu_to_le16(pci_default_sub_device_id);
 183     return 0;
 184 }
 185
 186 /*
 187  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 188  */
 189 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 190 {
 191     const char *p;
 192     char *e;
 193     unsigned long val;
 194     unsigned long dom = 0, bus = 0;
 195     unsigned slot = 0;
 196
 197     p = addr;
 198     val = strtoul(p, &e, 16);
 199     if (e == p)
 200         return -1;
 201     if (*e == ':') {
 202         bus = val;
 203         p = e + 1;
 204         val = strtoul(p, &e, 16);
 205         if (e == p)
 206             return -1;
 207         if (*e == ':') {
 208             dom = bus;
 209             bus = val;
 210             p = e + 1;
 211             val = strtoul(p, &e, 16);
 212             if (e == p)
 213                 return -1;
 214         }
 215     }
 216
 217     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 218         return -1;
 219
 220     slot = val;
 221
 222     if (*e)
 223         return -1;
 224
 225     /* Note: QEMU doesn't implement domains other than 0 */
 226     if (dom != 0 || pci_find_bus(bus) == NULL)
 227         return -1;
 228
 229     *domp = dom;
 230     *busp = bus;
 231     *slotp = slot;
 232     return 0;
 233 }
 234
 235 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 236                      unsigned *slotp)
 237 {
 238     /* strip legacy tag */
 239     if (!strncmp(addr, "pci_addr=", 9)) {
 240         addr += 9;
 241     }
 242     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 243         monitor_printf(mon, "Invalid pci address\n");
 244         return -1;
 245     }
 246     return 0;
 247 }
 248
 249 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 250 {
 251     int dom, bus;
 252     unsigned slot;
 253
 254     if (!devaddr) {
 255         *devfnp = -1;
 256         return pci_find_bus(0);
 257     }
 258
 259     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 260         return NULL;
 261     }
 262
 263     *devfnp = slot << 3;
 264     return pci_find_bus(bus);
 265 }
 266
 267 static void pci_init_cmask(PCIDevice *dev)
 268 {
 269     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 270     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 271     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 272     dev->cmask[PCI_REVISION_ID] = 0xff;
 273     dev->cmask[PCI_CLASS_PROG] = 0xff;
 274     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 275     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 276     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 277 }
 278
 279 static void pci_init_wmask(PCIDevice *dev)
 280 {
 281     int i;
 282     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 283     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 284     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 285                               | PCI_COMMAND_MASTER;
 286     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 287         dev->wmask[i] = 0xff;
 288 }
 289
 290 /* -1 for devfn means auto assign */
 291 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 292                                          const char *name, int devfn,
 293                                          PCIConfigReadFunc *config_read,
 294                                          PCIConfigWriteFunc *config_write)
 295 {
 296     if (devfn < 0) {
 297         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 298             if (!bus->devices[devfn])
 299                 goto found;
 300         }
 301         return NULL;
 302     found: ;
 303     } else if (bus->devices[devfn]) {
 304         return NULL;
 305     }
 306     pci_dev->bus = bus;
 307     pci_dev->devfn = devfn;
 308     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 309     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 310     pci_set_default_subsystem_id(pci_dev);
 311     pci_init_cmask(pci_dev);
 312     pci_init_wmask(pci_dev);
 313
 314     if (!config_read)
 315         config_read = pci_default_read_config;
 316     if (!config_write)
 317         config_write = pci_default_write_config;
 318     pci_dev->config_read = config_read;
 319     pci_dev->config_write = config_write;
 320     bus->devices[devfn] = pci_dev;
 321     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 322     pci_dev->version_id = 2; /* Current pci device vmstate version */
 323     return pci_dev;
 324 }
 325
 326 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 327                                int instance_size, int devfn,
 328                                PCIConfigReadFunc *config_read,
 329                                PCIConfigWriteFunc *config_write)
 330 {
 331     PCIDevice *pci_dev;
 332
 333     pci_dev = qemu_mallocz(instance_size);
 334     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 335                                      config_read, config_write);
 336     return pci_dev;
 337 }
 338 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 339 {
 340     return addr + pci_mem_base;
 341 }
 342
 343 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 344 {
 345     PCIIORegion *r;
 346     int i;
 347
 348     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 349         r = &pci_dev->io_regions[i];
 350         if (!r->size || r->addr == -1)
 351             continue;
 352         if (r->type == PCI_ADDRESS_SPACE_IO) {
 353             isa_unassign_ioport(r->addr, r->size);
 354         } else {
 355             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 356                                                      r->size,
 357                                                      IO_MEM_UNASSIGNED);
 358         }
 359     }
 360 }
 361
 362 int pci_unregister_device(PCIDevice *pci_dev)
 363 {
 364     int ret = 0;
 365
 366     if (pci_dev->unregister)
 367         ret = pci_dev->unregister(pci_dev);
 368     if (ret)
 369         return ret;
 370
 371     pci_unregister_io_regions(pci_dev);
 372
 373     qemu_free_irqs(pci_dev->irq);
 374     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 375     qdev_free(&pci_dev->qdev);
 376     return 0;
 377 }
 378
 379 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 380                             uint32_t size, int type,
 381                             PCIMapIORegionFunc *map_func)
 382 {
 383     PCIIORegion *r;
 384     uint32_t addr;
 385     uint32_t wmask;
 386
 387     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 388         return;
 389
 390     if (size & (size-1)) {
 391         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 392                     "type=0x%x, size=0x%x\n", type, size);
 393         exit(1);
 394     }
 395
 396     r = &pci_dev->io_regions[region_num];
 397     r->addr = -1;
 398     r->size = size;
 399     r->type = type;
 400     r->map_func = map_func;
 401
 402     wmask = ~(size - 1);
 403     if (region_num == PCI_ROM_SLOT) {
 404         addr = 0x30;
 405         /* ROM enable bit is writeable */
 406         wmask |= 1;
 407     } else {
 408         addr = 0x10 + region_num * 4;
 409     }
 410     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 411     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 412     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 413 }
 414
 415 static void pci_update_mappings(PCIDevice *d)
 416 {
 417     PCIIORegion *r;
 418     int cmd, i;
 419     uint32_t last_addr, new_addr, config_ofs;
 420
 421     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 422     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 423         r = &d->io_regions[i];
 424         if (i == PCI_ROM_SLOT) {
 425             config_ofs = 0x30;
 426         } else {
 427             config_ofs = 0x10 + i * 4;
 428         }
 429         if (r->size != 0) {
 430             if (r->type & PCI_ADDRESS_SPACE_IO) {
 431                 if (cmd & PCI_COMMAND_IO) {
 432                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 433                                                          config_ofs));
 434                     new_addr = new_addr & ~(r->size - 1);
 435                     last_addr = new_addr + r->size - 1;
 436                     /* NOTE: we have only 64K ioports on PC */
 437                     if (last_addr <= new_addr || new_addr == 0 ||
 438                         last_addr >= 0x10000) {
 439                         new_addr = -1;
 440                     }
 441                 } else {
 442                     new_addr = -1;
 443                 }
 444             } else {
 445                 if (cmd & PCI_COMMAND_MEMORY) {
 446                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 447                                                          config_ofs));
 448                     /* the ROM slot has a specific enable bit */
 449                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 450                         goto no_mem_map;
 451                     new_addr = new_addr & ~(r->size - 1);
 452                     last_addr = new_addr + r->size - 1;
 453                     /* NOTE: we do not support wrapping */
 454                     /* XXX: as we cannot support really dynamic
 455                        mappings, we handle specific values as invalid
 456                        mappings. */
 457                     if (last_addr <= new_addr || new_addr == 0 ||
 458                         last_addr == -1) {
 459                         new_addr = -1;
 460                     }
 461                 } else {
 462                 no_mem_map:
 463                     new_addr = -1;
 464                 }
 465             }
 466             /* now do the real mapping */
 467             if (new_addr != r->addr) {
 468                 if (r->addr != -1) {
 469                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 470                         int class;
 471                         /* NOTE: specific hack for IDE in PC case:
 472                            only one byte must be mapped. */
 473                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 474                         if (class == 0x0101 && r->size == 4) {
 475                             isa_unassign_ioport(r->addr + 2, 1);
 476                         } else {
 477                             isa_unassign_ioport(r->addr, r->size);
 478                         }
 479                     } else {
 480                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 481                                                      r->size,
 482                                                      IO_MEM_UNASSIGNED);
 483                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 484                     }
 485                 }
 486                 r->addr = new_addr;
 487                 if (r->addr != -1) {
 488                     r->map_func(d, i, r->addr, r->size, r->type);
 489                 }
 490             }
 491         }
 492     }
 493 }
 494
 495 uint32_t pci_default_read_config(PCIDevice *d,
 496                                  uint32_t address, int len)
 497 {
 498     uint32_t val;
 499
 500     switch(len) {
 501     default:
 502     case 4:
 503         if (address <= 0xfc) {
 504             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 505             break;
 506         }
 507         /* fall through */
 508     case 2:
 509         if (address <= 0xfe) {
 510             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 511             break;
 512         }
 513         /* fall through */
 514     case 1:
 515         val = d->config[address];
 516         break;
 517     }
 518     return val;
 519 }
 520
 521 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 522 {
 523     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 524     int i;
 525
 526     /* not efficient, but simple */
 527     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 528     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 529         uint8_t wmask = d->wmask[addr];
 530         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 531     }
 532     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 533         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 534             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 535         pci_update_mappings(d);
 536 }
 537
 538 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 539 {
 540     PCIBus *s = opaque;
 541     PCIDevice *pci_dev;
 542     int config_addr, bus_num;
 543
 544 #if 0
 545     PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
 546                 addr, val, len);
 547 #endif
 548     bus_num = (addr >> 16) & 0xff;
 549     while (s && s->bus_num != bus_num)
 550         s = s->next;
 551     if (!s)
 552         return;
 553     pci_dev = s->devices[(addr >> 8) & 0xff];
 554     if (!pci_dev)
 555         return;
 556     config_addr = addr & 0xff;
 557     PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 558                 pci_dev->name, config_addr, val, len);
 559     pci_dev->config_write(pci_dev, config_addr, val, len);
 560 }
 561
 562 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 563 {
 564     PCIBus *s = opaque;
 565     PCIDevice *pci_dev;
 566     int config_addr, bus_num;
 567     uint32_t val;
 568
 569     bus_num = (addr >> 16) & 0xff;
 570     while (s && s->bus_num != bus_num)
 571         s= s->next;
 572     if (!s)
 573         goto fail;
 574     pci_dev = s->devices[(addr >> 8) & 0xff];
 575     if (!pci_dev) {
 576     fail:
 577         switch(len) {
 578         case 1:
 579             val = 0xff;
 580             break;
 581         case 2:
 582             val = 0xffff;
 583             break;
 584         default:
 585         case 4:
 586             val = 0xffffffff;
 587             break;
 588         }
 589         goto the_end;
 590     }
 591     config_addr = addr & 0xff;
 592     val = pci_dev->config_read(pci_dev, config_addr, len);
 593     PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 594                 pci_dev->name, config_addr, val, len);
 595  the_end:
 596 #if 0
 597     PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
 598                 addr, val, len);
 599 #endif
 600     return val;
 601 }
 602
 603 /***********************************************************/
 604 /* generic PCI irq support */
 605
 606 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 607 static void pci_set_irq(void *opaque, int irq_num, int level)
 608 {
 609     PCIDevice *pci_dev = (PCIDevice *)opaque;
 610     PCIBus *bus;
 611     int change;
 612
 613     change = level - pci_dev->irq_state[irq_num];
 614     if (!change)
 615         return;
 616
 617     pci_dev->irq_state[irq_num] = level;
 618     for (;;) {
 619         bus = pci_dev->bus;
 620         irq_num = bus->map_irq(pci_dev, irq_num);
 621         if (bus->set_irq)
 622             break;
 623         pci_dev = bus->parent_dev;
 624     }
 625     bus->irq_count[irq_num] += change;
 626     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 627 }
 628
 629 /***********************************************************/
 630 /* monitor info on PCI */
 631
 632 typedef struct {
 633     uint16_t class;
 634     const char *desc;
 635 } pci_class_desc;
 636
 637 static const pci_class_desc pci_class_descriptions[] =
 638 {
 639     { 0x0100, "SCSI controller"},
 640     { 0x0101, "IDE controller"},
 641     { 0x0102, "Floppy controller"},
 642     { 0x0103, "IPI controller"},
 643     { 0x0104, "RAID controller"},
 644     { 0x0106, "SATA controller"},
 645     { 0x0107, "SAS controller"},
 646     { 0x0180, "Storage controller"},
 647     { 0x0200, "Ethernet controller"},
 648     { 0x0201, "Token Ring controller"},
 649     { 0x0202, "FDDI controller"},
 650     { 0x0203, "ATM controller"},
 651     { 0x0280, "Network controller"},
 652     { 0x0300, "VGA controller"},
 653     { 0x0301, "XGA controller"},
 654     { 0x0302, "3D controller"},
 655     { 0x0380, "Display controller"},
 656     { 0x0400, "Video controller"},
 657     { 0x0401, "Audio controller"},
 658     { 0x0402, "Phone"},
 659     { 0x0480, "Multimedia controller"},
 660     { 0x0500, "RAM controller"},
 661     { 0x0501, "Flash controller"},
 662     { 0x0580, "Memory controller"},
 663     { 0x0600, "Host bridge"},
 664     { 0x0601, "ISA bridge"},
 665     { 0x0602, "EISA bridge"},
 666     { 0x0603, "MC bridge"},
 667     { 0x0604, "PCI bridge"},
 668     { 0x0605, "PCMCIA bridge"},
 669     { 0x0606, "NUBUS bridge"},
 670     { 0x0607, "CARDBUS bridge"},
 671     { 0x0608, "RACEWAY bridge"},
 672     { 0x0680, "Bridge"},
 673     { 0x0c03, "USB controller"},
 674     { 0, NULL}
 675 };
 676
 677 static void pci_info_device(PCIDevice *d)
 678 {
 679     Monitor *mon = cur_mon;
 680     int i, class;
 681     PCIIORegion *r;
 682     const pci_class_desc *desc;
 683
 684     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 685                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 686     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 687     monitor_printf(mon, "    ");
 688     desc = pci_class_descriptions;
 689     while (desc->desc && class != desc->class)
 690         desc++;
 691     if (desc->desc) {
 692         monitor_printf(mon, "%s", desc->desc);
 693     } else {
 694         monitor_printf(mon, "Class %04x", class);
 695     }
 696     monitor_printf(mon, ": PCI device %04x:%04x\n",
 697            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 698            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 699
 700     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 701         monitor_printf(mon, "      IRQ %d.\n",
 702                        d->config[PCI_INTERRUPT_LINE]);
 703     }
 704     if (class == 0x0604) {
 705         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 706     }
 707     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 708         r = &d->io_regions[i];
 709         if (r->size != 0) {
 710             monitor_printf(mon, "      BAR%d: ", i);
 711             if (r->type & PCI_ADDRESS_SPACE_IO) {
 712                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 713                                r->addr, r->addr + r->size - 1);
 714             } else {
 715                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 716                                r->addr, r->addr + r->size - 1);
 717             }
 718         }
 719     }
 720     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
 721     if (class == 0x0604 && d->config[0x19] != 0) {
 722         pci_for_each_device(d->config[0x19], pci_info_device);
 723     }
 724 }
 725
 726 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 727 {
 728     PCIBus *bus = first_bus;
 729     PCIDevice *d;
 730     int devfn;
 731
 732     while (bus && bus->bus_num != bus_num)
 733         bus = bus->next;
 734     if (bus) {
 735         for(devfn = 0; devfn < 256; devfn++) {
 736             d = bus->devices[devfn];
 737             if (d)
 738                 fn(d);
 739         }
 740     }
 741 }
 742
 743 void pci_info(Monitor *mon)
 744 {
 745     pci_for_each_device(0, pci_info_device);
 746 }
 747
 748 PCIDevice *pci_create(const char *name, const char *devaddr)
 749 {
 750     PCIBus *bus;
 751     int devfn;
 752     DeviceState *dev;
 753
 754     bus = pci_get_bus_devfn(&devfn, devaddr);
 755     if (!bus) {
 756         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 757                 devaddr, name);
 758         exit(1);
 759     }
 760
 761     dev = qdev_create(&bus->qbus, name);
 762     qdev_prop_set_uint32(dev, "addr", devfn);
 763     return (PCIDevice *)dev;
 764 }
 765
 766 static const char * const pci_nic_models[] = {
 767     "ne2k_pci",
 768     "i82551",
 769     "i82557b",
 770     "i82559er",
 771     "rtl8139",
 772     "e1000",
 773     "pcnet",
 774     "virtio",
 775     NULL
 776 };
 777
 778 static const char * const pci_nic_names[] = {
 779     "ne2k_pci",
 780     "i82551",
 781     "i82557b",
 782     "i82559er",
 783     "rtl8139",
 784     "e1000",
 785     "pcnet",
 786     "virtio-net-pci",
 787     NULL
 788 };
 789
 790 /* Initialize a PCI NIC.  */
 791 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 792                         const char *default_devaddr)
 793 {
 794     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 795     PCIDevice *pci_dev;
 796     DeviceState *dev;
 797     int i;
 798
 799     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 800
 801     for (i = 0; pci_nic_models[i]; i++) {
 802         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 803             pci_dev = pci_create(pci_nic_names[i], devaddr);
 804             dev = &pci_dev->qdev;
 805             if (nd->id)
 806                 dev->id = qemu_strdup(nd->id);
 807             dev->nd = nd;
 808             qdev_init(dev);
 809             nd->private = dev;
 810             return pci_dev;
 811         }
 812     }
 813
 814     return NULL;
 815 }
 816
 817 typedef struct {
 818     PCIDevice dev;
 819     PCIBus *bus;
 820 } PCIBridge;
 821
 822 static void pci_bridge_write_config(PCIDevice *d,
 823                              uint32_t address, uint32_t val, int len)
 824 {
 825     PCIBridge *s = (PCIBridge *)d;
 826
 827     pci_default_write_config(d, address, val, len);
 828     s->bus->bus_num = d->config[PCI_SECONDARY_BUS];
 829 }
 830
 831 PCIBus *pci_find_bus(int bus_num)
 832 {
 833     PCIBus *bus = first_bus;
 834
 835     while (bus && bus->bus_num != bus_num)
 836         bus = bus->next;
 837
 838     return bus;
 839 }
 840
 841 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 842 {
 843     PCIBus *bus = pci_find_bus(bus_num);
 844
 845     if (!bus)
 846         return NULL;
 847
 848     return bus->devices[PCI_DEVFN(slot, function)];
 849 }
 850
 851 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 852                         pci_map_irq_fn map_irq, const char *name)
 853 {
 854     PCIBridge *s;
 855     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 856                                          devfn, NULL, pci_bridge_write_config);
 857
 858     pci_config_set_vendor_id(s->dev.config, vid);
 859     pci_config_set_device_id(s->dev.config, did);
 860
 861     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 862     s->dev.config[0x05] = 0x00;
 863     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 864     s->dev.config[0x07] = 0x00; // status = fast devsel
 865     s->dev.config[0x08] = 0x00; // revision
 866     s->dev.config[0x09] = 0x00; // programming i/f
 867     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 868     s->dev.config[0x0D] = 0x10; // latency_timer
 869     s->dev.config[PCI_HEADER_TYPE] =
 870         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 871     s->dev.config[0x1E] = 0xa0; // secondary status
 872
 873     s->bus = pci_register_secondary_bus(&s->dev, map_irq, name);
 874     return s->bus;
 875 }
 876
 877 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 878 {
 879     PCIDevice *pci_dev = (PCIDevice *)qdev;
 880     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 881     PCIBus *bus;
 882     int devfn;
 883
 884     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 885     devfn = pci_dev->devfn;
 886     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
 887                                      info->config_read, info->config_write);
 888     assert(pci_dev);
 889     info->init(pci_dev);
 890 }
 891
 892 void pci_qdev_register(PCIDeviceInfo *info)
 893 {
 894     info->qdev.init = pci_qdev_init;
 895     info->qdev.bus_info = &pci_bus_info;
 896     qdev_register(&info->qdev);
 897 }
 898
 899 void pci_qdev_register_many(PCIDeviceInfo *info)
 900 {
 901     while (info->qdev.name) {
 902         pci_qdev_register(info);
 903         info++;
 904     }
 905 }
 906
 907 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
 908 {
 909     DeviceState *dev;
 910
 911     dev = qdev_create(&bus->qbus, name);
 912     qdev_prop_set_uint32(dev, "addr", devfn);
 913     qdev_init(dev);
 914
 915     return (PCIDevice *)dev;
 916 }
 917
 918 static int pci_find_space(PCIDevice *pdev, uint8_t size)
 919 {
 920     int offset = PCI_CONFIG_HEADER_SIZE;
 921     int i;
 922     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 923         if (pdev->used[i])
 924             offset = i + 1;
 925         else if (i - offset + 1 == size)
 926             return offset;
 927     return 0;
 928 }
 929
 930 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
 931                                         uint8_t *prev_p)
 932 {
 933     uint8_t next, prev;
 934
 935     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
 936         return 0;
 937
 938     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
 939          prev = next + PCI_CAP_LIST_NEXT)
 940         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
 941             break;
 942
 943     if (prev_p)
 944         *prev_p = prev;
 945     return next;
 946 }
 947
 948 /* Reserve space and add capability to the linked list in pci config space */
 949 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 950 {
 951     uint8_t offset = pci_find_space(pdev, size);
 952     uint8_t *config = pdev->config + offset;
 953     if (!offset)
 954         return -ENOSPC;
 955     config[PCI_CAP_LIST_ID] = cap_id;
 956     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
 957     pdev->config[PCI_CAPABILITY_LIST] = offset;
 958     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
 959     memset(pdev->used + offset, 0xFF, size);
 960     /* Make capability read-only by default */
 961     memset(pdev->wmask + offset, 0, size);
 962     /* Check capability by default */
 963     memset(pdev->cmask + offset, 0xFF, size);
 964     return offset;
 965 }
 966
 967 /* Unlink capability from the pci config space. */
 968 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 969 {
 970     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
 971     if (!offset)
 972         return;
 973     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
 974     /* Make capability writeable again */
 975     memset(pdev->wmask + offset, 0xff, size);
 976     /* Clear cmask as device-specific registers can't be checked */
 977     memset(pdev->cmask + offset, 0, size);
 978     memset(pdev->used + offset, 0, size);
 979
 980     if (!pdev->config[PCI_CAPABILITY_LIST])
 981         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
 982 }
 983
 984 /* Reserve space for capability at a known offset (to call after load). */
 985 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
 986 {
 987     memset(pdev->used + offset, 0xff, size);
 988 }
 989
 990 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
 991 {
 992     return pci_find_capability_list(pdev, cap_id, NULL);
 993 }
 994
 995 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
 996 {
 997     PCIDevice *d = (PCIDevice *)dev;
 998     const pci_class_desc *desc;
 999     char ctxt[64];
1000     PCIIORegion *r;
1001     int i, class;
1002
1003     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1004     desc = pci_class_descriptions;
1005     while (desc->desc && class != desc->class)
1006         desc++;
1007     if (desc->desc) {
1008         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1009     } else {
1010         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1011     }
1012
1013     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1014                    "pci id %04x:%04x (sub %04x:%04x)\n",
1015                    indent, "", ctxt,
1016                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1017                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1018                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1019                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1020                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1021     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1022         r = &d->io_regions[i];
1023         if (!r->size)
1024             continue;
1025         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1026                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1027                        r->addr, r->addr + r->size - 1);
1028     }
1029 }