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exec: remove unused compacted argument
[qemu.git] / hw / sd / omap_mmc.c
blobe934cd36560be88aaff3a140fcbccdeff2868c10
1 /*
2 * OMAP on-chip MMC/SD host emulation.
3 *
4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "hw/hw.h"
21 #include "hw/arm/omap.h"
22 #include "hw/sd/sd.h"
23
24 struct omap_mmc_s {
25 qemu_irq irq;
26 qemu_irq *dma;
27 qemu_irq coverswitch;
28 MemoryRegion iomem;
29 omap_clk clk;
30 SDState *card;
31 uint16_t last_cmd;
32 uint16_t sdio;
33 uint16_t rsp[8];
34 uint32_t arg;
35 int lines;
36 int dw;
37 int mode;
38 int enable;
39 int be;
40 int rev;
41 uint16_t status;
42 uint16_t mask;
43 uint8_t cto;
44 uint16_t dto;
45 int clkdiv;
46 uint16_t fifo[32];
47 int fifo_start;
48 int fifo_len;
49 uint16_t blen;
50 uint16_t blen_counter;
51 uint16_t nblk;
52 uint16_t nblk_counter;
53 int tx_dma;
54 int rx_dma;
55 int af_level;
56 int ae_level;
57
58 int ddir;
59 int transfer;
60
61 int cdet_wakeup;
62 int cdet_enable;
63 int cdet_state;
64 qemu_irq cdet;
65 };
66
67 static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
68 {
69 qemu_set_irq(s->irq, !!(s->status & s->mask));
70 }
71
72 static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
73 {
74 if (!host->transfer && !host->fifo_len) {
75 host->status &= 0xf3ff;
76 return;
77 }
78
79 if (host->fifo_len > host->af_level && host->ddir) {
80 if (host->rx_dma) {
81 host->status &= 0xfbff;
82 qemu_irq_raise(host->dma[1]);
83 } else
84 host->status |= 0x0400;
85 } else {
86 host->status &= 0xfbff;
87 qemu_irq_lower(host->dma[1]);
88 }
89
90 if (host->fifo_len < host->ae_level && !host->ddir) {
91 if (host->tx_dma) {
92 host->status &= 0xf7ff;
93 qemu_irq_raise(host->dma[0]);
94 } else
95 host->status |= 0x0800;
96 } else {
97 qemu_irq_lower(host->dma[0]);
98 host->status &= 0xf7ff;
99 }
100 }
101
102 typedef enum {
103 sd_nore = 0, /* no response */
104 sd_r1, /* normal response command */
105 sd_r2, /* CID, CSD registers */
106 sd_r3, /* OCR register */
107 sd_r6 = 6, /* Published RCA response */
108 sd_r1b = -1,
109 } sd_rsp_type_t;
110
111 static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
112 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
113 {
114 uint32_t rspstatus, mask;
115 int rsplen, timeout;
116 SDRequest request;
117 uint8_t response[16];
118
119 if (init && cmd == 0) {
120 host->status |= 0x0001;
121 return;
122 }
123
124 if (resptype == sd_r1 && busy)
125 resptype = sd_r1b;
126
127 if (type == sd_adtc) {
128 host->fifo_start = 0;
129 host->fifo_len = 0;
130 host->transfer = 1;
131 host->ddir = dir;
132 } else
133 host->transfer = 0;
134 timeout = 0;
135 mask = 0;
136 rspstatus = 0;
137
138 request.cmd = cmd;
139 request.arg = host->arg;
140 request.crc = 0; /* FIXME */
141
142 rsplen = sd_do_command(host->card, &request, response);
143
144 /* TODO: validate CRCs */
145 switch (resptype) {
146 case sd_nore:
147 rsplen = 0;
148 break;
149
150 case sd_r1:
151 case sd_r1b:
152 if (rsplen < 4) {
153 timeout = 1;
154 break;
155 }
156 rsplen = 4;
157
158 mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
159 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
160 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
161 CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
162 CID_CSD_OVERWRITE;
163 if (host->sdio & (1 << 13))
164 mask |= AKE_SEQ_ERROR;
165 rspstatus = (response[0] << 24) | (response[1] << 16) |
166 (response[2] << 8) | (response[3] << 0);
167 break;
168
169 case sd_r2:
170 if (rsplen < 16) {
171 timeout = 1;
172 break;
173 }
174 rsplen = 16;
175 break;
176
177 case sd_r3:
178 if (rsplen < 4) {
179 timeout = 1;
180 break;
181 }
182 rsplen = 4;
183
184 rspstatus = (response[0] << 24) | (response[1] << 16) |
185 (response[2] << 8) | (response[3] << 0);
186 if (rspstatus & 0x80000000)
187 host->status &= 0xe000;
188 else
189 host->status |= 0x1000;
190 break;
191
192 case sd_r6:
193 if (rsplen < 4) {
194 timeout = 1;
195 break;
196 }
197 rsplen = 4;
198
199 mask = 0xe000 | AKE_SEQ_ERROR;
200 rspstatus = (response[2] << 8) | (response[3] << 0);
201 }
202
203 if (rspstatus & mask)
204 host->status |= 0x4000;
205 else
206 host->status &= 0xb000;
207
208 if (rsplen)
209 for (rsplen = 0; rsplen < 8; rsplen ++)
210 host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
211 (response[(rsplen << 1) | 0] << 8);
212
213 if (timeout)
214 host->status |= 0x0080;
215 else if (cmd == 12)
216 host->status |= 0x0005; /* Makes it more real */
217 else
218 host->status |= 0x0001;
219 }
220
221 static void omap_mmc_transfer(struct omap_mmc_s *host)
222 {
223 uint8_t value;
224
225 if (!host->transfer)
226 return;
227
228 while (1) {
229 if (host->ddir) {
230 if (host->fifo_len > host->af_level)
231 break;
232
233 value = sd_read_data(host->card);
234 host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
235 if (-- host->blen_counter) {
236 value = sd_read_data(host->card);
237 host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
238 value << 8;
239 host->blen_counter --;
240 }
241
242 host->fifo_len ++;
243 } else {
244 if (!host->fifo_len)
245 break;
246
247 value = host->fifo[host->fifo_start] & 0xff;
248 sd_write_data(host->card, value);
249 if (-- host->blen_counter) {
250 value = host->fifo[host->fifo_start] >> 8;
251 sd_write_data(host->card, value);
252 host->blen_counter --;
253 }
254
255 host->fifo_start ++;
256 host->fifo_len --;
257 host->fifo_start &= 31;
258 }
259
260 if (host->blen_counter == 0) {
261 host->nblk_counter --;
262 host->blen_counter = host->blen;
263
264 if (host->nblk_counter == 0) {
265 host->nblk_counter = host->nblk;
266 host->transfer = 0;
267 host->status |= 0x0008;
268 break;
269 }
270 }
271 }
272 }
273
274 static void omap_mmc_update(void *opaque)
275 {
276 struct omap_mmc_s *s = opaque;
277 omap_mmc_transfer(s);
278 omap_mmc_fifolevel_update(s);
279 omap_mmc_interrupts_update(s);
280 }
281
282 void omap_mmc_reset(struct omap_mmc_s *host)
283 {
284 host->last_cmd = 0;
285 memset(host->rsp, 0, sizeof(host->rsp));
286 host->arg = 0;
287 host->dw = 0;
288 host->mode = 0;
289 host->enable = 0;
290 host->status = 0;
291 host->mask = 0;
292 host->cto = 0;
293 host->dto = 0;
294 host->fifo_len = 0;
295 host->blen = 0;
296 host->blen_counter = 0;
297 host->nblk = 0;
298 host->nblk_counter = 0;
299 host->tx_dma = 0;
300 host->rx_dma = 0;
301 host->ae_level = 0x00;
302 host->af_level = 0x1f;
303 host->transfer = 0;
304 host->cdet_wakeup = 0;
305 host->cdet_enable = 0;
306 qemu_set_irq(host->coverswitch, host->cdet_state);
307 host->clkdiv = 0;
308 }
309
310 static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
311 unsigned size)
312 {
313 uint16_t i;
314 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
315
316 if (size != 2) {
317 return omap_badwidth_read16(opaque, offset);
318 }
319
320 switch (offset) {
321 case 0x00: /* MMC_CMD */
322 return s->last_cmd;
323
324 case 0x04: /* MMC_ARGL */
325 return s->arg & 0x0000ffff;
326
327 case 0x08: /* MMC_ARGH */
328 return s->arg >> 16;
329
330 case 0x0c: /* MMC_CON */
331 return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) |
332 (s->be << 10) | s->clkdiv;
333
334 case 0x10: /* MMC_STAT */
335 return s->status;
336
337 case 0x14: /* MMC_IE */
338 return s->mask;
339
340 case 0x18: /* MMC_CTO */
341 return s->cto;
342
343 case 0x1c: /* MMC_DTO */
344 return s->dto;
345
346 case 0x20: /* MMC_DATA */
347 /* TODO: support 8-bit access */
348 i = s->fifo[s->fifo_start];
349 if (s->fifo_len == 0) {
350 printf("MMC: FIFO underrun\n");
351 return i;
352 }
353 s->fifo_start ++;
354 s->fifo_len --;
355 s->fifo_start &= 31;
356 omap_mmc_transfer(s);
357 omap_mmc_fifolevel_update(s);
358 omap_mmc_interrupts_update(s);
359 return i;
360
361 case 0x24: /* MMC_BLEN */
362 return s->blen_counter;
363
364 case 0x28: /* MMC_NBLK */
365 return s->nblk_counter;
366
367 case 0x2c: /* MMC_BUF */
368 return (s->rx_dma << 15) | (s->af_level << 8) |
369 (s->tx_dma << 7) | s->ae_level;
370
371 case 0x30: /* MMC_SPI */
372 return 0x0000;
373 case 0x34: /* MMC_SDIO */
374 return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
375 case 0x38: /* MMC_SYST */
376 return 0x0000;
377
378 case 0x3c: /* MMC_REV */
379 return s->rev;
380
381 case 0x40: /* MMC_RSP0 */
382 case 0x44: /* MMC_RSP1 */
383 case 0x48: /* MMC_RSP2 */
384 case 0x4c: /* MMC_RSP3 */
385 case 0x50: /* MMC_RSP4 */
386 case 0x54: /* MMC_RSP5 */
387 case 0x58: /* MMC_RSP6 */
388 case 0x5c: /* MMC_RSP7 */
389 return s->rsp[(offset - 0x40) >> 2];
390
391 /* OMAP2-specific */
392 case 0x60: /* MMC_IOSR */
393 case 0x64: /* MMC_SYSC */
394 return 0;
395 case 0x68: /* MMC_SYSS */
396 return 1; /* RSTD */
397 }
398
399 OMAP_BAD_REG(offset);
400 return 0;
401 }
402
403 static void omap_mmc_write(void *opaque, hwaddr offset,
404 uint64_t value, unsigned size)
405 {
406 int i;
407 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
408
409 if (size != 2) {
410 omap_badwidth_write16(opaque, offset, value);
411 return;
412 }
413
414 switch (offset) {
415 case 0x00: /* MMC_CMD */
416 if (!s->enable)
417 break;
418
419 s->last_cmd = value;
420 for (i = 0; i < 8; i ++)
421 s->rsp[i] = 0x0000;
422 omap_mmc_command(s, value & 63, (value >> 15) & 1,
423 (sd_cmd_type_t) ((value >> 12) & 3),
424 (value >> 11) & 1,
425 (sd_rsp_type_t) ((value >> 8) & 7),
426 (value >> 7) & 1);
427 omap_mmc_update(s);
428 break;
429
430 case 0x04: /* MMC_ARGL */
431 s->arg &= 0xffff0000;
432 s->arg |= 0x0000ffff & value;
433 break;
434
435 case 0x08: /* MMC_ARGH */
436 s->arg &= 0x0000ffff;
437 s->arg |= value << 16;
438 break;
439
440 case 0x0c: /* MMC_CON */
441 s->dw = (value >> 15) & 1;
442 s->mode = (value >> 12) & 3;
443 s->enable = (value >> 11) & 1;
444 s->be = (value >> 10) & 1;
445 s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
446 if (s->mode != 0)
447 printf("SD mode %i unimplemented!\n", s->mode);
448 if (s->be != 0)
449 printf("SD FIFO byte sex unimplemented!\n");
450 if (s->dw != 0 && s->lines < 4)
451 printf("4-bit SD bus enabled\n");
452 if (!s->enable)
453 omap_mmc_reset(s);
454 break;
455
456 case 0x10: /* MMC_STAT */
457 s->status &= ~value;
458 omap_mmc_interrupts_update(s);
459 break;
460
461 case 0x14: /* MMC_IE */
462 s->mask = value & 0x7fff;
463 omap_mmc_interrupts_update(s);
464 break;
465
466 case 0x18: /* MMC_CTO */
467 s->cto = value & 0xff;
468 if (s->cto > 0xfd && s->rev <= 1)
469 printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
470 break;
471
472 case 0x1c: /* MMC_DTO */
473 s->dto = value & 0xffff;
474 break;
475
476 case 0x20: /* MMC_DATA */
477 /* TODO: support 8-bit access */
478 if (s->fifo_len == 32)
479 break;
480 s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
481 s->fifo_len ++;
482 omap_mmc_transfer(s);
483 omap_mmc_fifolevel_update(s);
484 omap_mmc_interrupts_update(s);
485 break;
486
487 case 0x24: /* MMC_BLEN */
488 s->blen = (value & 0x07ff) + 1;
489 s->blen_counter = s->blen;
490 break;
491
492 case 0x28: /* MMC_NBLK */
493 s->nblk = (value & 0x07ff) + 1;
494 s->nblk_counter = s->nblk;
495 s->blen_counter = s->blen;
496 break;
497
498 case 0x2c: /* MMC_BUF */
499 s->rx_dma = (value >> 15) & 1;
500 s->af_level = (value >> 8) & 0x1f;
501 s->tx_dma = (value >> 7) & 1;
502 s->ae_level = value & 0x1f;
503
504 if (s->rx_dma)
505 s->status &= 0xfbff;
506 if (s->tx_dma)
507 s->status &= 0xf7ff;
508 omap_mmc_fifolevel_update(s);
509 omap_mmc_interrupts_update(s);
510 break;
511
512 /* SPI, SDIO and TEST modes unimplemented */
513 case 0x30: /* MMC_SPI (OMAP1 only) */
514 break;
515 case 0x34: /* MMC_SDIO */
516 s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
517 s->cdet_wakeup = (value >> 9) & 1;
518 s->cdet_enable = (value >> 2) & 1;
519 break;
520 case 0x38: /* MMC_SYST */
521 break;
522
523 case 0x3c: /* MMC_REV */
524 case 0x40: /* MMC_RSP0 */
525 case 0x44: /* MMC_RSP1 */
526 case 0x48: /* MMC_RSP2 */
527 case 0x4c: /* MMC_RSP3 */
528 case 0x50: /* MMC_RSP4 */
529 case 0x54: /* MMC_RSP5 */
530 case 0x58: /* MMC_RSP6 */
531 case 0x5c: /* MMC_RSP7 */
532 OMAP_RO_REG(offset);
533 break;
534
535 /* OMAP2-specific */
536 case 0x60: /* MMC_IOSR */
537 if (value & 0xf)
538 printf("MMC: SDIO bits used!\n");
539 break;
540 case 0x64: /* MMC_SYSC */
541 if (value & (1 << 2)) /* SRTS */
542 omap_mmc_reset(s);
543 break;
544 case 0x68: /* MMC_SYSS */
545 OMAP_RO_REG(offset);
546 break;
547
548 default:
549 OMAP_BAD_REG(offset);
550 }
551 }
552
553 static const MemoryRegionOps omap_mmc_ops = {
554 .read = omap_mmc_read,
555 .write = omap_mmc_write,
556 .endianness = DEVICE_NATIVE_ENDIAN,
557 };
558
559 static void omap_mmc_cover_cb(void *opaque, int line, int level)
560 {
561 struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
562
563 if (!host->cdet_state && level) {
564 host->status |= 0x0002;
565 omap_mmc_interrupts_update(host);
566 if (host->cdet_wakeup) {
567 /* TODO: Assert wake-up */
568 }
569 }
570
571 if (host->cdet_state != level) {
572 qemu_set_irq(host->coverswitch, level);
573 host->cdet_state = level;
574 }
575 }
576
577 struct omap_mmc_s *omap_mmc_init(hwaddr base,
578 MemoryRegion *sysmem,
579 BlockBackend *blk,
580 qemu_irq irq, qemu_irq dma[], omap_clk clk)
581 {
582 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
583
584 s->irq = irq;
585 s->dma = dma;
586 s->clk = clk;
587 s->lines = 1; /* TODO: needs to be settable per-board */
588 s->rev = 1;
589
590 omap_mmc_reset(s);
591
592 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
593 memory_region_add_subregion(sysmem, base, &s->iomem);
594
595 /* Instantiate the storage */
596 s->card = sd_init(blk, false);
597 if (s->card == NULL) {
598 exit(1);
599 }
600
601 return s;
602 }
603
604 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
605 BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
606 omap_clk fclk, omap_clk iclk)
607 {
608 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
609
610 s->irq = irq;
611 s->dma = dma;
612 s->clk = fclk;
613 s->lines = 4;
614 s->rev = 2;
615
616 omap_mmc_reset(s);
617
618 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
619 omap_l4_region_size(ta, 0));
620 omap_l4_attach(ta, 0, &s->iomem);
621
622 /* Instantiate the storage */
623 s->card = sd_init(blk, false);
624 if (s->card == NULL) {
625 exit(1);
626 }
627
628 s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
629 sd_set_cb(s->card, NULL, s->cdet);
630
631 return s;
632 }
633
634 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
635 {
636 if (s->cdet) {
637 sd_set_cb(s->card, ro, s->cdet);
638 s->coverswitch = cover;
639 qemu_set_irq(cover, s->cdet_state);
640 } else
641 sd_set_cb(s->card, ro, cover);
642 }
643
644 void omap_mmc_enable(struct omap_mmc_s *s, int enable)
645 {
646 sd_enable(s->card, enable);
647 }
QEmu