4 * Copyright (c) 2019 Yoshinori Sato
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/qemu-print.h"
21 #include "qapi/error.h"
23 #include "migration/vmstate.h"
24 #include "exec/exec-all.h"
25 #include "hw/loader.h"
26 #include "fpu/softfloat.h"
28 static void rx_cpu_set_pc(CPUState
*cs
, vaddr value
)
30 RXCPU
*cpu
= RX_CPU(cs
);
35 static void rx_cpu_synchronize_from_tb(CPUState
*cs
,
36 const TranslationBlock
*tb
)
38 RXCPU
*cpu
= RX_CPU(cs
);
43 static bool rx_cpu_has_work(CPUState
*cs
)
45 return cs
->interrupt_request
&
46 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_FIR
);
49 static void rx_cpu_reset(DeviceState
*dev
)
51 RXCPU
*cpu
= RX_CPU(dev
);
52 RXCPUClass
*rcc
= RX_CPU_GET_CLASS(cpu
);
53 CPURXState
*env
= &cpu
->env
;
56 rcc
->parent_reset(dev
);
58 memset(env
, 0, offsetof(CPURXState
, end_reset_fields
));
60 resetvec
= rom_ptr(0xfffffffc, 4);
62 /* In the case of kernel, it is ignored because it is not set. */
63 env
->pc
= ldl_p(resetvec
);
65 rx_cpu_unpack_psw(env
, 0, 1);
66 env
->regs
[0] = env
->isp
= env
->usp
= 0;
68 set_flush_to_zero(1, &env
->fp_status
);
69 set_flush_inputs_to_zero(1, &env
->fp_status
);
72 static void rx_cpu_list_entry(gpointer data
, gpointer user_data
)
74 ObjectClass
*oc
= data
;
76 qemu_printf(" %s\n", object_class_get_name(oc
));
79 void rx_cpu_list(void)
82 list
= object_class_get_list_sorted(TYPE_RX_CPU
, false);
83 qemu_printf("Available CPUs:\n");
84 g_slist_foreach(list
, rx_cpu_list_entry
, NULL
);
88 static ObjectClass
*rx_cpu_class_by_name(const char *cpu_model
)
93 oc
= object_class_by_name(cpu_model
);
94 if (oc
!= NULL
&& object_class_dynamic_cast(oc
, TYPE_RX_CPU
) != NULL
&&
95 !object_class_is_abstract(oc
)) {
98 typename
= g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model
);
99 oc
= object_class_by_name(typename
);
101 if (oc
!= NULL
&& object_class_is_abstract(oc
)) {
108 static void rx_cpu_realize(DeviceState
*dev
, Error
**errp
)
110 CPUState
*cs
= CPU(dev
);
111 RXCPUClass
*rcc
= RX_CPU_GET_CLASS(dev
);
112 Error
*local_err
= NULL
;
114 cpu_exec_realizefn(cs
, &local_err
);
115 if (local_err
!= NULL
) {
116 error_propagate(errp
, local_err
);
123 rcc
->parent_realize(dev
, errp
);
126 static void rx_cpu_set_irq(void *opaque
, int no
, int request
)
129 CPUState
*cs
= CPU(cpu
);
130 int irq
= request
& 0xff;
132 static const int mask
[] = {
133 [RX_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
134 [RX_CPU_FIR
] = CPU_INTERRUPT_FIR
,
137 cpu
->env
.req_irq
= irq
;
138 cpu
->env
.req_ipl
= (request
>> 8) & 0x0f;
139 cpu_interrupt(cs
, mask
[no
]);
141 cpu_reset_interrupt(cs
, mask
[no
]);
145 static void rx_cpu_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
147 info
->mach
= bfd_mach_rx
;
148 info
->print_insn
= print_insn_rx
;
151 static bool rx_cpu_tlb_fill(CPUState
*cs
, vaddr addr
, int size
,
152 MMUAccessType access_type
, int mmu_idx
,
153 bool probe
, uintptr_t retaddr
)
155 uint32_t address
, physical
, prot
;
158 address
= physical
= addr
& TARGET_PAGE_MASK
;
159 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
160 tlb_set_page(cs
, address
, physical
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
164 static void rx_cpu_init(Object
*obj
)
166 CPUState
*cs
= CPU(obj
);
167 RXCPU
*cpu
= RX_CPU(obj
);
168 CPURXState
*env
= &cpu
->env
;
170 cpu_set_cpustate_pointers(cpu
);
172 qdev_init_gpio_in(DEVICE(cpu
), rx_cpu_set_irq
, 2);
175 #ifndef CONFIG_USER_ONLY
176 #include "hw/core/sysemu-cpu-ops.h"
178 static const struct SysemuCPUOps rx_sysemu_ops
= {
179 .get_phys_page_debug
= rx_cpu_get_phys_page_debug
,
183 #include "hw/core/tcg-cpu-ops.h"
185 static const struct TCGCPUOps rx_tcg_ops
= {
186 .initialize
= rx_translate_init
,
187 .synchronize_from_tb
= rx_cpu_synchronize_from_tb
,
188 .tlb_fill
= rx_cpu_tlb_fill
,
190 #ifndef CONFIG_USER_ONLY
191 .cpu_exec_interrupt
= rx_cpu_exec_interrupt
,
192 .do_interrupt
= rx_cpu_do_interrupt
,
193 #endif /* !CONFIG_USER_ONLY */
196 static void rx_cpu_class_init(ObjectClass
*klass
, void *data
)
198 DeviceClass
*dc
= DEVICE_CLASS(klass
);
199 CPUClass
*cc
= CPU_CLASS(klass
);
200 RXCPUClass
*rcc
= RX_CPU_CLASS(klass
);
202 device_class_set_parent_realize(dc
, rx_cpu_realize
,
203 &rcc
->parent_realize
);
204 device_class_set_parent_reset(dc
, rx_cpu_reset
,
207 cc
->class_by_name
= rx_cpu_class_by_name
;
208 cc
->has_work
= rx_cpu_has_work
;
209 cc
->dump_state
= rx_cpu_dump_state
;
210 cc
->set_pc
= rx_cpu_set_pc
;
212 #ifndef CONFIG_USER_ONLY
213 cc
->sysemu_ops
= &rx_sysemu_ops
;
215 cc
->gdb_read_register
= rx_cpu_gdb_read_register
;
216 cc
->gdb_write_register
= rx_cpu_gdb_write_register
;
217 cc
->disas_set_info
= rx_cpu_disas_set_info
;
219 cc
->gdb_num_core_regs
= 26;
220 cc
->gdb_core_xml_file
= "rx-core.xml";
221 cc
->tcg_ops
= &rx_tcg_ops
;
224 static const TypeInfo rx_cpu_info
= {
227 .instance_size
= sizeof(RXCPU
),
228 .instance_init
= rx_cpu_init
,
230 .class_size
= sizeof(RXCPUClass
),
231 .class_init
= rx_cpu_class_init
,
234 static const TypeInfo rx62n_rx_cpu_info
= {
235 .name
= TYPE_RX62N_CPU
,
236 .parent
= TYPE_RX_CPU
,
239 static void rx_cpu_register_types(void)
241 type_register_static(&rx_cpu_info
);
242 type_register_static(&rx62n_rx_cpu_info
);
245 type_init(rx_cpu_register_types
)