hw/gt64xxx.c

   1 /*
   2  * QEMU GT64120 PCI host
   3  *
   4  * Copyright (c) 2006,2007 Aurelien Jarno
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "pc.h"
  30 #include "exec-memory.h"
  31
  32 //#define DEBUG
  33
  34 #ifdef DEBUG
  35 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  36 #else
  37 #define DPRINTF(fmt, ...)
  38 #endif
  39
  40 #define GT_REGS                 (0x1000 >> 2)
  41
  42 /* CPU Configuration */
  43 #define GT_CPU                  (0x000 >> 2)
  44 #define GT_MULTI                (0x120 >> 2)
  45
  46 /* CPU Address Decode */
  47 #define GT_SCS10LD              (0x008 >> 2)
  48 #define GT_SCS10HD              (0x010 >> 2)
  49 #define GT_SCS32LD              (0x018 >> 2)
  50 #define GT_SCS32HD              (0x020 >> 2)
  51 #define GT_CS20LD               (0x028 >> 2)
  52 #define GT_CS20HD               (0x030 >> 2)
  53 #define GT_CS3BOOTLD            (0x038 >> 2)
  54 #define GT_CS3BOOTHD            (0x040 >> 2)
  55 #define GT_PCI0IOLD             (0x048 >> 2)
  56 #define GT_PCI0IOHD             (0x050 >> 2)
  57 #define GT_PCI0M0LD             (0x058 >> 2)
  58 #define GT_PCI0M0HD             (0x060 >> 2)
  59 #define GT_PCI0M1LD             (0x080 >> 2)
  60 #define GT_PCI0M1HD             (0x088 >> 2)
  61 #define GT_PCI1IOLD             (0x090 >> 2)
  62 #define GT_PCI1IOHD             (0x098 >> 2)
  63 #define GT_PCI1M0LD             (0x0a0 >> 2)
  64 #define GT_PCI1M0HD             (0x0a8 >> 2)
  65 #define GT_PCI1M1LD             (0x0b0 >> 2)
  66 #define GT_PCI1M1HD             (0x0b8 >> 2)
  67 #define GT_ISD                  (0x068 >> 2)
  68
  69 #define GT_SCS10AR              (0x0d0 >> 2)
  70 #define GT_SCS32AR              (0x0d8 >> 2)
  71 #define GT_CS20R                (0x0e0 >> 2)
  72 #define GT_CS3BOOTR             (0x0e8 >> 2)
  73
  74 #define GT_PCI0IOREMAP          (0x0f0 >> 2)
  75 #define GT_PCI0M0REMAP          (0x0f8 >> 2)
  76 #define GT_PCI0M1REMAP          (0x100 >> 2)
  77 #define GT_PCI1IOREMAP          (0x108 >> 2)
  78 #define GT_PCI1M0REMAP          (0x110 >> 2)
  79 #define GT_PCI1M1REMAP          (0x118 >> 2)
  80
  81 /* CPU Error Report */
  82 #define GT_CPUERR_ADDRLO        (0x070 >> 2)
  83 #define GT_CPUERR_ADDRHI        (0x078 >> 2)
  84 #define GT_CPUERR_DATALO        (0x128 >> 2)            /* GT-64120A only  */
  85 #define GT_CPUERR_DATAHI        (0x130 >> 2)            /* GT-64120A only  */
  86 #define GT_CPUERR_PARITY        (0x138 >> 2)            /* GT-64120A only  */
  87
  88 /* CPU Sync Barrier */
  89 #define GT_PCI0SYNC             (0x0c0 >> 2)
  90 #define GT_PCI1SYNC             (0x0c8 >> 2)
  91
  92 /* SDRAM and Device Address Decode */
  93 #define GT_SCS0LD               (0x400 >> 2)
  94 #define GT_SCS0HD               (0x404 >> 2)
  95 #define GT_SCS1LD               (0x408 >> 2)
  96 #define GT_SCS1HD               (0x40c >> 2)
  97 #define GT_SCS2LD               (0x410 >> 2)
  98 #define GT_SCS2HD               (0x414 >> 2)
  99 #define GT_SCS3LD               (0x418 >> 2)
 100 #define GT_SCS3HD               (0x41c >> 2)
 101 #define GT_CS0LD                (0x420 >> 2)
 102 #define GT_CS0HD                (0x424 >> 2)
 103 #define GT_CS1LD                (0x428 >> 2)
 104 #define GT_CS1HD                (0x42c >> 2)
 105 #define GT_CS2LD                (0x430 >> 2)
 106 #define GT_CS2HD                (0x434 >> 2)
 107 #define GT_CS3LD                (0x438 >> 2)
 108 #define GT_CS3HD                (0x43c >> 2)
 109 #define GT_BOOTLD               (0x440 >> 2)
 110 #define GT_BOOTHD               (0x444 >> 2)
 111 #define GT_ADERR                (0x470 >> 2)
 112
 113 /* SDRAM Configuration */
 114 #define GT_SDRAM_CFG            (0x448 >> 2)
 115 #define GT_SDRAM_OPMODE         (0x474 >> 2)
 116 #define GT_SDRAM_BM             (0x478 >> 2)
 117 #define GT_SDRAM_ADDRDECODE     (0x47c >> 2)
 118
 119 /* SDRAM Parameters */
 120 #define GT_SDRAM_B0             (0x44c >> 2)
 121 #define GT_SDRAM_B1             (0x450 >> 2)
 122 #define GT_SDRAM_B2             (0x454 >> 2)
 123 #define GT_SDRAM_B3             (0x458 >> 2)
 124
 125 /* Device Parameters */
 126 #define GT_DEV_B0               (0x45c >> 2)
 127 #define GT_DEV_B1               (0x460 >> 2)
 128 #define GT_DEV_B2               (0x464 >> 2)
 129 #define GT_DEV_B3               (0x468 >> 2)
 130 #define GT_DEV_BOOT             (0x46c >> 2)
 131
 132 /* ECC */
 133 #define GT_ECC_ERRDATALO        (0x480 >> 2)            /* GT-64120A only  */
 134 #define GT_ECC_ERRDATAHI        (0x484 >> 2)            /* GT-64120A only  */
 135 #define GT_ECC_MEM              (0x488 >> 2)            /* GT-64120A only  */
 136 #define GT_ECC_CALC             (0x48c >> 2)            /* GT-64120A only  */
 137 #define GT_ECC_ERRADDR          (0x490 >> 2)            /* GT-64120A only  */
 138
 139 /* DMA Record */
 140 #define GT_DMA0_CNT             (0x800 >> 2)
 141 #define GT_DMA1_CNT             (0x804 >> 2)
 142 #define GT_DMA2_CNT             (0x808 >> 2)
 143 #define GT_DMA3_CNT             (0x80c >> 2)
 144 #define GT_DMA0_SA              (0x810 >> 2)
 145 #define GT_DMA1_SA              (0x814 >> 2)
 146 #define GT_DMA2_SA              (0x818 >> 2)
 147 #define GT_DMA3_SA              (0x81c >> 2)
 148 #define GT_DMA0_DA              (0x820 >> 2)
 149 #define GT_DMA1_DA              (0x824 >> 2)
 150 #define GT_DMA2_DA              (0x828 >> 2)
 151 #define GT_DMA3_DA              (0x82c >> 2)
 152 #define GT_DMA0_NEXT            (0x830 >> 2)
 153 #define GT_DMA1_NEXT            (0x834 >> 2)
 154 #define GT_DMA2_NEXT            (0x838 >> 2)
 155 #define GT_DMA3_NEXT            (0x83c >> 2)
 156 #define GT_DMA0_CUR             (0x870 >> 2)
 157 #define GT_DMA1_CUR             (0x874 >> 2)
 158 #define GT_DMA2_CUR             (0x878 >> 2)
 159 #define GT_DMA3_CUR             (0x87c >> 2)
 160
 161 /* DMA Channel Control */
 162 #define GT_DMA0_CTRL            (0x840 >> 2)
 163 #define GT_DMA1_CTRL            (0x844 >> 2)
 164 #define GT_DMA2_CTRL            (0x848 >> 2)
 165 #define GT_DMA3_CTRL            (0x84c >> 2)
 166
 167 /* DMA Arbiter */
 168 #define GT_DMA_ARB              (0x860 >> 2)
 169
 170 /* Timer/Counter */
 171 #define GT_TC0                  (0x850 >> 2)
 172 #define GT_TC1                  (0x854 >> 2)
 173 #define GT_TC2                  (0x858 >> 2)
 174 #define GT_TC3                  (0x85c >> 2)
 175 #define GT_TC_CONTROL           (0x864 >> 2)
 176
 177 /* PCI Internal */
 178 #define GT_PCI0_CMD             (0xc00 >> 2)
 179 #define GT_PCI0_TOR             (0xc04 >> 2)
 180 #define GT_PCI0_BS_SCS10        (0xc08 >> 2)
 181 #define GT_PCI0_BS_SCS32        (0xc0c >> 2)
 182 #define GT_PCI0_BS_CS20         (0xc10 >> 2)
 183 #define GT_PCI0_BS_CS3BT        (0xc14 >> 2)
 184 #define GT_PCI1_IACK            (0xc30 >> 2)
 185 #define GT_PCI0_IACK            (0xc34 >> 2)
 186 #define GT_PCI0_BARE            (0xc3c >> 2)
 187 #define GT_PCI0_PREFMBR         (0xc40 >> 2)
 188 #define GT_PCI0_SCS10_BAR       (0xc48 >> 2)
 189 #define GT_PCI0_SCS32_BAR       (0xc4c >> 2)
 190 #define GT_PCI0_CS20_BAR        (0xc50 >> 2)
 191 #define GT_PCI0_CS3BT_BAR       (0xc54 >> 2)
 192 #define GT_PCI0_SSCS10_BAR      (0xc58 >> 2)
 193 #define GT_PCI0_SSCS32_BAR      (0xc5c >> 2)
 194 #define GT_PCI0_SCS3BT_BAR      (0xc64 >> 2)
 195 #define GT_PCI1_CMD             (0xc80 >> 2)
 196 #define GT_PCI1_TOR             (0xc84 >> 2)
 197 #define GT_PCI1_BS_SCS10        (0xc88 >> 2)
 198 #define GT_PCI1_BS_SCS32        (0xc8c >> 2)
 199 #define GT_PCI1_BS_CS20         (0xc90 >> 2)
 200 #define GT_PCI1_BS_CS3BT        (0xc94 >> 2)
 201 #define GT_PCI1_BARE            (0xcbc >> 2)
 202 #define GT_PCI1_PREFMBR         (0xcc0 >> 2)
 203 #define GT_PCI1_SCS10_BAR       (0xcc8 >> 2)
 204 #define GT_PCI1_SCS32_BAR       (0xccc >> 2)
 205 #define GT_PCI1_CS20_BAR        (0xcd0 >> 2)
 206 #define GT_PCI1_CS3BT_BAR       (0xcd4 >> 2)
 207 #define GT_PCI1_SSCS10_BAR      (0xcd8 >> 2)
 208 #define GT_PCI1_SSCS32_BAR      (0xcdc >> 2)
 209 #define GT_PCI1_SCS3BT_BAR      (0xce4 >> 2)
 210 #define GT_PCI1_CFGADDR         (0xcf0 >> 2)
 211 #define GT_PCI1_CFGDATA         (0xcf4 >> 2)
 212 #define GT_PCI0_CFGADDR         (0xcf8 >> 2)
 213 #define GT_PCI0_CFGDATA         (0xcfc >> 2)
 214
 215 /* Interrupts */
 216 #define GT_INTRCAUSE            (0xc18 >> 2)
 217 #define GT_INTRMASK             (0xc1c >> 2)
 218 #define GT_PCI0_ICMASK          (0xc24 >> 2)
 219 #define GT_PCI0_SERR0MASK       (0xc28 >> 2)
 220 #define GT_CPU_INTSEL           (0xc70 >> 2)
 221 #define GT_PCI0_INTSEL          (0xc74 >> 2)
 222 #define GT_HINTRCAUSE           (0xc98 >> 2)
 223 #define GT_HINTRMASK            (0xc9c >> 2)
 224 #define GT_PCI0_HICMASK         (0xca4 >> 2)
 225 #define GT_PCI1_SERR1MASK       (0xca8 >> 2)
 226
 227 #define PCI_MAPPING_ENTRY(regname)            \
 228     target_phys_addr_t regname ##_start;      \
 229     target_phys_addr_t regname ##_length;     \
 230     int regname ##_handle
 231
 232 typedef struct GT64120State {
 233     SysBusDevice busdev;
 234     PCIHostState pci;
 235     uint32_t regs[GT_REGS];
 236     PCI_MAPPING_ENTRY(PCI0IO);
 237     PCI_MAPPING_ENTRY(ISD);
 238 } GT64120State;
 239
 240 /* Adjust range to avoid touching space which isn't mappable via PCI */
 241 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
 242                                     0x1fc00000 - 0x1fd00000  */
 243 static void check_reserved_space (target_phys_addr_t *start,
 244                                   target_phys_addr_t *length)
 245 {
 246     target_phys_addr_t begin = *start;
 247     target_phys_addr_t end = *start + *length;
 248
 249     if (end >= 0x1e000000LL && end < 0x1f100000LL)
 250         end = 0x1e000000LL;
 251     if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
 252         begin = 0x1f100000LL;
 253     if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
 254         end = 0x1fc00000LL;
 255     if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
 256         begin = 0x1fd00000LL;
 257     /* XXX: This is broken when a reserved range splits the requested range */
 258     if (end >= 0x1f100000LL && begin < 0x1e000000LL)
 259         end = 0x1e000000LL;
 260     if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
 261         end = 0x1fc00000LL;
 262
 263     *start = begin;
 264     *length = end - begin;
 265 }
 266
 267 static void gt64120_isd_mapping(GT64120State *s)
 268 {
 269     target_phys_addr_t start = s->regs[GT_ISD] << 21;
 270     target_phys_addr_t length = 0x1000;
 271
 272     if (s->ISD_length)
 273         cpu_register_physical_memory(s->ISD_start, s->ISD_length,
 274                                      IO_MEM_UNASSIGNED);
 275     check_reserved_space(&start, &length);
 276     length = 0x1000;
 277     /* Map new address */
 278     DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx" -> "TARGET_FMT_plx"@"TARGET_FMT_plx", %x\n", s->ISD_length, s->ISD_start,
 279             length, start, s->ISD_handle);
 280     s->ISD_start = start;
 281     s->ISD_length = length;
 282     cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
 283 }
 284
 285 static void gt64120_pci_mapping(GT64120State *s)
 286 {
 287     /* Update IO mapping */
 288     if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
 289     {
 290       /* Unmap old IO address */
 291       if (s->PCI0IO_length)
 292       {
 293         cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
 294       }
 295       /* Map new IO address */
 296       s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
 297       s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
 298       isa_mem_base = s->PCI0IO_start;
 299       isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
 300     }
 301 }
 302
 303 static void gt64120_writel (void *opaque, target_phys_addr_t addr,
 304                             uint32_t val)
 305 {
 306     GT64120State *s = opaque;
 307     uint32_t saddr;
 308
 309     if (!(s->regs[GT_CPU] & 0x00001000))
 310         val = bswap32(val);
 311
 312     saddr = (addr & 0xfff) >> 2;
 313     switch (saddr) {
 314
 315     /* CPU Configuration */
 316     case GT_CPU:
 317         s->regs[GT_CPU] = val;
 318         break;
 319     case GT_MULTI:
 320         /* Read-only register as only one GT64xxx is present on the CPU bus */
 321         break;
 322
 323     /* CPU Address Decode */
 324     case GT_PCI0IOLD:
 325         s->regs[GT_PCI0IOLD]    = val & 0x00007fff;
 326         s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
 327         gt64120_pci_mapping(s);
 328         break;
 329     case GT_PCI0M0LD:
 330         s->regs[GT_PCI0M0LD]    = val & 0x00007fff;
 331         s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
 332         break;
 333     case GT_PCI0M1LD:
 334         s->regs[GT_PCI0M1LD]    = val & 0x00007fff;
 335         s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
 336         break;
 337     case GT_PCI1IOLD:
 338         s->regs[GT_PCI1IOLD]    = val & 0x00007fff;
 339         s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
 340         break;
 341     case GT_PCI1M0LD:
 342         s->regs[GT_PCI1M0LD]    = val & 0x00007fff;
 343         s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
 344         break;
 345     case GT_PCI1M1LD:
 346         s->regs[GT_PCI1M1LD]    = val & 0x00007fff;
 347         s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
 348         break;
 349     case GT_PCI0IOHD:
 350         s->regs[saddr] = val & 0x0000007f;
 351         gt64120_pci_mapping(s);
 352         break;
 353     case GT_PCI0M0HD:
 354     case GT_PCI0M1HD:
 355     case GT_PCI1IOHD:
 356     case GT_PCI1M0HD:
 357     case GT_PCI1M1HD:
 358         s->regs[saddr] = val & 0x0000007f;
 359         break;
 360     case GT_ISD:
 361         s->regs[saddr] = val & 0x00007fff;
 362         gt64120_isd_mapping(s);
 363         break;
 364
 365     case GT_PCI0IOREMAP:
 366     case GT_PCI0M0REMAP:
 367     case GT_PCI0M1REMAP:
 368     case GT_PCI1IOREMAP:
 369     case GT_PCI1M0REMAP:
 370     case GT_PCI1M1REMAP:
 371         s->regs[saddr] = val & 0x000007ff;
 372         break;
 373
 374     /* CPU Error Report */
 375     case GT_CPUERR_ADDRLO:
 376     case GT_CPUERR_ADDRHI:
 377     case GT_CPUERR_DATALO:
 378     case GT_CPUERR_DATAHI:
 379     case GT_CPUERR_PARITY:
 380         /* Read-only registers, do nothing */
 381         break;
 382
 383     /* CPU Sync Barrier */
 384     case GT_PCI0SYNC:
 385     case GT_PCI1SYNC:
 386         /* Read-only registers, do nothing */
 387         break;
 388
 389     /* SDRAM and Device Address Decode */
 390     case GT_SCS0LD:
 391     case GT_SCS0HD:
 392     case GT_SCS1LD:
 393     case GT_SCS1HD:
 394     case GT_SCS2LD:
 395     case GT_SCS2HD:
 396     case GT_SCS3LD:
 397     case GT_SCS3HD:
 398     case GT_CS0LD:
 399     case GT_CS0HD:
 400     case GT_CS1LD:
 401     case GT_CS1HD:
 402     case GT_CS2LD:
 403     case GT_CS2HD:
 404     case GT_CS3LD:
 405     case GT_CS3HD:
 406     case GT_BOOTLD:
 407     case GT_BOOTHD:
 408     case GT_ADERR:
 409     /* SDRAM Configuration */
 410     case GT_SDRAM_CFG:
 411     case GT_SDRAM_OPMODE:
 412     case GT_SDRAM_BM:
 413     case GT_SDRAM_ADDRDECODE:
 414         /* Accept and ignore SDRAM interleave configuration */
 415         s->regs[saddr] = val;
 416         break;
 417
 418     /* Device Parameters */
 419     case GT_DEV_B0:
 420     case GT_DEV_B1:
 421     case GT_DEV_B2:
 422     case GT_DEV_B3:
 423     case GT_DEV_BOOT:
 424         /* Not implemented */
 425         DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
 426         break;
 427
 428     /* ECC */
 429     case GT_ECC_ERRDATALO:
 430     case GT_ECC_ERRDATAHI:
 431     case GT_ECC_MEM:
 432     case GT_ECC_CALC:
 433     case GT_ECC_ERRADDR:
 434         /* Read-only registers, do nothing */
 435         break;
 436
 437     /* DMA Record */
 438     case GT_DMA0_CNT:
 439     case GT_DMA1_CNT:
 440     case GT_DMA2_CNT:
 441     case GT_DMA3_CNT:
 442     case GT_DMA0_SA:
 443     case GT_DMA1_SA:
 444     case GT_DMA2_SA:
 445     case GT_DMA3_SA:
 446     case GT_DMA0_DA:
 447     case GT_DMA1_DA:
 448     case GT_DMA2_DA:
 449     case GT_DMA3_DA:
 450     case GT_DMA0_NEXT:
 451     case GT_DMA1_NEXT:
 452     case GT_DMA2_NEXT:
 453     case GT_DMA3_NEXT:
 454     case GT_DMA0_CUR:
 455     case GT_DMA1_CUR:
 456     case GT_DMA2_CUR:
 457     case GT_DMA3_CUR:
 458         /* Not implemented */
 459         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 460         break;
 461
 462     /* DMA Channel Control */
 463     case GT_DMA0_CTRL:
 464     case GT_DMA1_CTRL:
 465     case GT_DMA2_CTRL:
 466     case GT_DMA3_CTRL:
 467         /* Not implemented */
 468         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 469         break;
 470
 471     /* DMA Arbiter */
 472     case GT_DMA_ARB:
 473         /* Not implemented */
 474         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 475         break;
 476
 477     /* Timer/Counter */
 478     case GT_TC0:
 479     case GT_TC1:
 480     case GT_TC2:
 481     case GT_TC3:
 482     case GT_TC_CONTROL:
 483         /* Not implemented */
 484         DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
 485         break;
 486
 487     /* PCI Internal */
 488     case GT_PCI0_CMD:
 489     case GT_PCI1_CMD:
 490         s->regs[saddr] = val & 0x0401fc0f;
 491         break;
 492     case GT_PCI0_TOR:
 493     case GT_PCI0_BS_SCS10:
 494     case GT_PCI0_BS_SCS32:
 495     case GT_PCI0_BS_CS20:
 496     case GT_PCI0_BS_CS3BT:
 497     case GT_PCI1_IACK:
 498     case GT_PCI0_IACK:
 499     case GT_PCI0_BARE:
 500     case GT_PCI0_PREFMBR:
 501     case GT_PCI0_SCS10_BAR:
 502     case GT_PCI0_SCS32_BAR:
 503     case GT_PCI0_CS20_BAR:
 504     case GT_PCI0_CS3BT_BAR:
 505     case GT_PCI0_SSCS10_BAR:
 506     case GT_PCI0_SSCS32_BAR:
 507     case GT_PCI0_SCS3BT_BAR:
 508     case GT_PCI1_TOR:
 509     case GT_PCI1_BS_SCS10:
 510     case GT_PCI1_BS_SCS32:
 511     case GT_PCI1_BS_CS20:
 512     case GT_PCI1_BS_CS3BT:
 513     case GT_PCI1_BARE:
 514     case GT_PCI1_PREFMBR:
 515     case GT_PCI1_SCS10_BAR:
 516     case GT_PCI1_SCS32_BAR:
 517     case GT_PCI1_CS20_BAR:
 518     case GT_PCI1_CS3BT_BAR:
 519     case GT_PCI1_SSCS10_BAR:
 520     case GT_PCI1_SSCS32_BAR:
 521     case GT_PCI1_SCS3BT_BAR:
 522     case GT_PCI1_CFGADDR:
 523     case GT_PCI1_CFGDATA:
 524         /* not implemented */
 525         break;
 526     case GT_PCI0_CFGADDR:
 527         s->pci.config_reg = val & 0x80fffffc;
 528         break;
 529     case GT_PCI0_CFGDATA:
 530         if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800))
 531             val = bswap32(val);
 532         if (s->pci.config_reg & (1u << 31))
 533             pci_data_write(s->pci.bus, s->pci.config_reg, val, 4);
 534         break;
 535
 536     /* Interrupts */
 537     case GT_INTRCAUSE:
 538         /* not really implemented */
 539         s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
 540         s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
 541         DPRINTF("INTRCAUSE %x\n", val);
 542         break;
 543     case GT_INTRMASK:
 544         s->regs[saddr] = val & 0x3c3ffffe;
 545         DPRINTF("INTRMASK %x\n", val);
 546         break;
 547     case GT_PCI0_ICMASK:
 548         s->regs[saddr] = val & 0x03fffffe;
 549         DPRINTF("ICMASK %x\n", val);
 550         break;
 551     case GT_PCI0_SERR0MASK:
 552         s->regs[saddr] = val & 0x0000003f;
 553         DPRINTF("SERR0MASK %x\n", val);
 554         break;
 555
 556     /* Reserved when only PCI_0 is configured. */
 557     case GT_HINTRCAUSE:
 558     case GT_CPU_INTSEL:
 559     case GT_PCI0_INTSEL:
 560     case GT_HINTRMASK:
 561     case GT_PCI0_HICMASK:
 562     case GT_PCI1_SERR1MASK:
 563         /* not implemented */
 564         break;
 565
 566     /* SDRAM Parameters */
 567     case GT_SDRAM_B0:
 568     case GT_SDRAM_B1:
 569     case GT_SDRAM_B2:
 570     case GT_SDRAM_B3:
 571         /* We don't simulate electrical parameters of the SDRAM.
 572            Accept, but ignore the values. */
 573         s->regs[saddr] = val;
 574         break;
 575
 576     default:
 577         DPRINTF ("Bad register offset 0x%x\n", (int)addr);
 578         break;
 579     }
 580 }
 581
 582 static uint32_t gt64120_readl (void *opaque,
 583                                target_phys_addr_t addr)
 584 {
 585     GT64120State *s = opaque;
 586     uint32_t val;
 587     uint32_t saddr;
 588
 589     saddr = (addr & 0xfff) >> 2;
 590     switch (saddr) {
 591
 592     /* CPU Configuration */
 593     case GT_MULTI:
 594         /* Only one GT64xxx is present on the CPU bus, return
 595            the initial value */
 596         val = s->regs[saddr];
 597         break;
 598
 599     /* CPU Error Report */
 600     case GT_CPUERR_ADDRLO:
 601     case GT_CPUERR_ADDRHI:
 602     case GT_CPUERR_DATALO:
 603     case GT_CPUERR_DATAHI:
 604     case GT_CPUERR_PARITY:
 605         /* Emulated memory has no error, always return the initial
 606            values */
 607         val = s->regs[saddr];
 608         break;
 609
 610     /* CPU Sync Barrier */
 611     case GT_PCI0SYNC:
 612     case GT_PCI1SYNC:
 613         /* Reading those register should empty all FIFO on the PCI
 614            bus, which are not emulated. The return value should be
 615            a random value that should be ignored. */
 616         val = 0xc000ffee;
 617         break;
 618
 619     /* ECC */
 620     case GT_ECC_ERRDATALO:
 621     case GT_ECC_ERRDATAHI:
 622     case GT_ECC_MEM:
 623     case GT_ECC_CALC:
 624     case GT_ECC_ERRADDR:
 625         /* Emulated memory has no error, always return the initial
 626            values */
 627         val = s->regs[saddr];
 628         break;
 629
 630     case GT_CPU:
 631     case GT_SCS10LD:
 632     case GT_SCS10HD:
 633     case GT_SCS32LD:
 634     case GT_SCS32HD:
 635     case GT_CS20LD:
 636     case GT_CS20HD:
 637     case GT_CS3BOOTLD:
 638     case GT_CS3BOOTHD:
 639     case GT_SCS10AR:
 640     case GT_SCS32AR:
 641     case GT_CS20R:
 642     case GT_CS3BOOTR:
 643     case GT_PCI0IOLD:
 644     case GT_PCI0M0LD:
 645     case GT_PCI0M1LD:
 646     case GT_PCI1IOLD:
 647     case GT_PCI1M0LD:
 648     case GT_PCI1M1LD:
 649     case GT_PCI0IOHD:
 650     case GT_PCI0M0HD:
 651     case GT_PCI0M1HD:
 652     case GT_PCI1IOHD:
 653     case GT_PCI1M0HD:
 654     case GT_PCI1M1HD:
 655     case GT_PCI0IOREMAP:
 656     case GT_PCI0M0REMAP:
 657     case GT_PCI0M1REMAP:
 658     case GT_PCI1IOREMAP:
 659     case GT_PCI1M0REMAP:
 660     case GT_PCI1M1REMAP:
 661     case GT_ISD:
 662         val = s->regs[saddr];
 663         break;
 664     case GT_PCI0_IACK:
 665         /* Read the IRQ number */
 666         val = pic_read_irq(isa_pic);
 667         break;
 668
 669     /* SDRAM and Device Address Decode */
 670     case GT_SCS0LD:
 671     case GT_SCS0HD:
 672     case GT_SCS1LD:
 673     case GT_SCS1HD:
 674     case GT_SCS2LD:
 675     case GT_SCS2HD:
 676     case GT_SCS3LD:
 677     case GT_SCS3HD:
 678     case GT_CS0LD:
 679     case GT_CS0HD:
 680     case GT_CS1LD:
 681     case GT_CS1HD:
 682     case GT_CS2LD:
 683     case GT_CS2HD:
 684     case GT_CS3LD:
 685     case GT_CS3HD:
 686     case GT_BOOTLD:
 687     case GT_BOOTHD:
 688     case GT_ADERR:
 689         val = s->regs[saddr];
 690         break;
 691
 692     /* SDRAM Configuration */
 693     case GT_SDRAM_CFG:
 694     case GT_SDRAM_OPMODE:
 695     case GT_SDRAM_BM:
 696     case GT_SDRAM_ADDRDECODE:
 697         val = s->regs[saddr];
 698         break;
 699
 700     /* SDRAM Parameters */
 701     case GT_SDRAM_B0:
 702     case GT_SDRAM_B1:
 703     case GT_SDRAM_B2:
 704     case GT_SDRAM_B3:
 705         /* We don't simulate electrical parameters of the SDRAM.
 706            Just return the last written value. */
 707         val = s->regs[saddr];
 708         break;
 709
 710     /* Device Parameters */
 711     case GT_DEV_B0:
 712     case GT_DEV_B1:
 713     case GT_DEV_B2:
 714     case GT_DEV_B3:
 715     case GT_DEV_BOOT:
 716         val = s->regs[saddr];
 717         break;
 718
 719     /* DMA Record */
 720     case GT_DMA0_CNT:
 721     case GT_DMA1_CNT:
 722     case GT_DMA2_CNT:
 723     case GT_DMA3_CNT:
 724     case GT_DMA0_SA:
 725     case GT_DMA1_SA:
 726     case GT_DMA2_SA:
 727     case GT_DMA3_SA:
 728     case GT_DMA0_DA:
 729     case GT_DMA1_DA:
 730     case GT_DMA2_DA:
 731     case GT_DMA3_DA:
 732     case GT_DMA0_NEXT:
 733     case GT_DMA1_NEXT:
 734     case GT_DMA2_NEXT:
 735     case GT_DMA3_NEXT:
 736     case GT_DMA0_CUR:
 737     case GT_DMA1_CUR:
 738     case GT_DMA2_CUR:
 739     case GT_DMA3_CUR:
 740         val = s->regs[saddr];
 741         break;
 742
 743     /* DMA Channel Control */
 744     case GT_DMA0_CTRL:
 745     case GT_DMA1_CTRL:
 746     case GT_DMA2_CTRL:
 747     case GT_DMA3_CTRL:
 748         val = s->regs[saddr];
 749         break;
 750
 751     /* DMA Arbiter */
 752     case GT_DMA_ARB:
 753         val = s->regs[saddr];
 754         break;
 755
 756     /* Timer/Counter */
 757     case GT_TC0:
 758     case GT_TC1:
 759     case GT_TC2:
 760     case GT_TC3:
 761     case GT_TC_CONTROL:
 762         val = s->regs[saddr];
 763         break;
 764
 765     /* PCI Internal */
 766     case GT_PCI0_CFGADDR:
 767         val = s->pci.config_reg;
 768         break;
 769     case GT_PCI0_CFGDATA:
 770         if (!(s->pci.config_reg & (1 << 31)))
 771             val = 0xffffffff;
 772         else
 773             val = pci_data_read(s->pci.bus, s->pci.config_reg, 4);
 774         if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800))
 775             val = bswap32(val);
 776         break;
 777
 778     case GT_PCI0_CMD:
 779     case GT_PCI0_TOR:
 780     case GT_PCI0_BS_SCS10:
 781     case GT_PCI0_BS_SCS32:
 782     case GT_PCI0_BS_CS20:
 783     case GT_PCI0_BS_CS3BT:
 784     case GT_PCI1_IACK:
 785     case GT_PCI0_BARE:
 786     case GT_PCI0_PREFMBR:
 787     case GT_PCI0_SCS10_BAR:
 788     case GT_PCI0_SCS32_BAR:
 789     case GT_PCI0_CS20_BAR:
 790     case GT_PCI0_CS3BT_BAR:
 791     case GT_PCI0_SSCS10_BAR:
 792     case GT_PCI0_SSCS32_BAR:
 793     case GT_PCI0_SCS3BT_BAR:
 794     case GT_PCI1_CMD:
 795     case GT_PCI1_TOR:
 796     case GT_PCI1_BS_SCS10:
 797     case GT_PCI1_BS_SCS32:
 798     case GT_PCI1_BS_CS20:
 799     case GT_PCI1_BS_CS3BT:
 800     case GT_PCI1_BARE:
 801     case GT_PCI1_PREFMBR:
 802     case GT_PCI1_SCS10_BAR:
 803     case GT_PCI1_SCS32_BAR:
 804     case GT_PCI1_CS20_BAR:
 805     case GT_PCI1_CS3BT_BAR:
 806     case GT_PCI1_SSCS10_BAR:
 807     case GT_PCI1_SSCS32_BAR:
 808     case GT_PCI1_SCS3BT_BAR:
 809     case GT_PCI1_CFGADDR:
 810     case GT_PCI1_CFGDATA:
 811         val = s->regs[saddr];
 812         break;
 813
 814     /* Interrupts */
 815     case GT_INTRCAUSE:
 816         val = s->regs[saddr];
 817         DPRINTF("INTRCAUSE %x\n", val);
 818         break;
 819     case GT_INTRMASK:
 820         val = s->regs[saddr];
 821         DPRINTF("INTRMASK %x\n", val);
 822         break;
 823     case GT_PCI0_ICMASK:
 824         val = s->regs[saddr];
 825         DPRINTF("ICMASK %x\n", val);
 826         break;
 827     case GT_PCI0_SERR0MASK:
 828         val = s->regs[saddr];
 829         DPRINTF("SERR0MASK %x\n", val);
 830         break;
 831
 832     /* Reserved when only PCI_0 is configured. */
 833     case GT_HINTRCAUSE:
 834     case GT_CPU_INTSEL:
 835     case GT_PCI0_INTSEL:
 836     case GT_HINTRMASK:
 837     case GT_PCI0_HICMASK:
 838     case GT_PCI1_SERR1MASK:
 839         val = s->regs[saddr];
 840         break;
 841
 842     default:
 843         val = s->regs[saddr];
 844         DPRINTF ("Bad register offset 0x%x\n", (int)addr);
 845         break;
 846     }
 847
 848     if (!(s->regs[GT_CPU] & 0x00001000))
 849         val = bswap32(val);
 850
 851     return val;
 852 }
 853
 854 static CPUWriteMemoryFunc * const gt64120_write[] = {
 855     &gt64120_writel,
 856     &gt64120_writel,
 857     &gt64120_writel,
 858 };
 859
 860 static CPUReadMemoryFunc * const gt64120_read[] = {
 861     &gt64120_readl,
 862     &gt64120_readl,
 863     &gt64120_readl,
 864 };
 865
 866 static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 867 {
 868     int slot;
 869
 870     slot = (pci_dev->devfn >> 3);
 871
 872     switch (slot) {
 873       /* PIIX4 USB */
 874       case 10:
 875         return 3;
 876       /* AMD 79C973 Ethernet */
 877       case 11:
 878         return 1;
 879       /* Crystal 4281 Sound */
 880       case 12:
 881         return 2;
 882       /* PCI slot 1 to 4 */
 883       case 18 ... 21:
 884         return ((slot - 18) + irq_num) & 0x03;
 885       /* Unknown device, don't do any translation */
 886       default:
 887         return irq_num;
 888     }
 889 }
 890
 891 static int pci_irq_levels[4];
 892
 893 static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
 894 {
 895     int i, pic_irq, pic_level;
 896     qemu_irq *pic = opaque;
 897
 898     pci_irq_levels[irq_num] = level;
 899
 900     /* now we change the pic irq level according to the piix irq mappings */
 901     /* XXX: optimize */
 902     pic_irq = piix4_dev->config[0x60 + irq_num];
 903     if (pic_irq < 16) {
 904         /* The pic level is the logical OR of all the PCI irqs mapped
 905            to it */
 906         pic_level = 0;
 907         for (i = 0; i < 4; i++) {
 908             if (pic_irq == piix4_dev->config[0x60 + i])
 909                 pic_level |= pci_irq_levels[i];
 910         }
 911         qemu_set_irq(pic[pic_irq], pic_level);
 912     }
 913 }
 914
 915
 916 static void gt64120_reset(void *opaque)
 917 {
 918     GT64120State *s = opaque;
 919
 920     /* FIXME: Malta specific hw assumptions ahead */
 921
 922     /* CPU Configuration */
 923 #ifdef TARGET_WORDS_BIGENDIAN
 924     s->regs[GT_CPU]           = 0x00000000;
 925 #else
 926     s->regs[GT_CPU]           = 0x00001000;
 927 #endif
 928     s->regs[GT_MULTI]         = 0x00000003;
 929
 930     /* CPU Address decode */
 931     s->regs[GT_SCS10LD]       = 0x00000000;
 932     s->regs[GT_SCS10HD]       = 0x00000007;
 933     s->regs[GT_SCS32LD]       = 0x00000008;
 934     s->regs[GT_SCS32HD]       = 0x0000000f;
 935     s->regs[GT_CS20LD]        = 0x000000e0;
 936     s->regs[GT_CS20HD]        = 0x00000070;
 937     s->regs[GT_CS3BOOTLD]     = 0x000000f8;
 938     s->regs[GT_CS3BOOTHD]     = 0x0000007f;
 939
 940     s->regs[GT_PCI0IOLD]      = 0x00000080;
 941     s->regs[GT_PCI0IOHD]      = 0x0000000f;
 942     s->regs[GT_PCI0M0LD]      = 0x00000090;
 943     s->regs[GT_PCI0M0HD]      = 0x0000001f;
 944     s->regs[GT_ISD]           = 0x000000a0;
 945     s->regs[GT_PCI0M1LD]      = 0x00000790;
 946     s->regs[GT_PCI0M1HD]      = 0x0000001f;
 947     s->regs[GT_PCI1IOLD]      = 0x00000100;
 948     s->regs[GT_PCI1IOHD]      = 0x0000000f;
 949     s->regs[GT_PCI1M0LD]      = 0x00000110;
 950     s->regs[GT_PCI1M0HD]      = 0x0000001f;
 951     s->regs[GT_PCI1M1LD]      = 0x00000120;
 952     s->regs[GT_PCI1M1HD]      = 0x0000002f;
 953
 954     s->regs[GT_SCS10AR]       = 0x00000000;
 955     s->regs[GT_SCS32AR]       = 0x00000008;
 956     s->regs[GT_CS20R]         = 0x000000e0;
 957     s->regs[GT_CS3BOOTR]      = 0x000000f8;
 958
 959     s->regs[GT_PCI0IOREMAP]   = 0x00000080;
 960     s->regs[GT_PCI0M0REMAP]   = 0x00000090;
 961     s->regs[GT_PCI0M1REMAP]   = 0x00000790;
 962     s->regs[GT_PCI1IOREMAP]   = 0x00000100;
 963     s->regs[GT_PCI1M0REMAP]   = 0x00000110;
 964     s->regs[GT_PCI1M1REMAP]   = 0x00000120;
 965
 966     /* CPU Error Report */
 967     s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
 968     s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
 969     s->regs[GT_CPUERR_DATALO] = 0xffffffff;
 970     s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
 971     s->regs[GT_CPUERR_PARITY] = 0x000000ff;
 972
 973     /* CPU Sync Barrier */
 974     s->regs[GT_PCI0SYNC]      = 0x00000000;
 975     s->regs[GT_PCI1SYNC]      = 0x00000000;
 976
 977     /* SDRAM and Device Address Decode */
 978     s->regs[GT_SCS0LD]        = 0x00000000;
 979     s->regs[GT_SCS0HD]        = 0x00000007;
 980     s->regs[GT_SCS1LD]        = 0x00000008;
 981     s->regs[GT_SCS1HD]        = 0x0000000f;
 982     s->regs[GT_SCS2LD]        = 0x00000010;
 983     s->regs[GT_SCS2HD]        = 0x00000017;
 984     s->regs[GT_SCS3LD]        = 0x00000018;
 985     s->regs[GT_SCS3HD]        = 0x0000001f;
 986     s->regs[GT_CS0LD]         = 0x000000c0;
 987     s->regs[GT_CS0HD]         = 0x000000c7;
 988     s->regs[GT_CS1LD]         = 0x000000c8;
 989     s->regs[GT_CS1HD]         = 0x000000cf;
 990     s->regs[GT_CS2LD]         = 0x000000d0;
 991     s->regs[GT_CS2HD]         = 0x000000df;
 992     s->regs[GT_CS3LD]         = 0x000000f0;
 993     s->regs[GT_CS3HD]         = 0x000000fb;
 994     s->regs[GT_BOOTLD]        = 0x000000fc;
 995     s->regs[GT_BOOTHD]        = 0x000000ff;
 996     s->regs[GT_ADERR]         = 0xffffffff;
 997
 998     /* SDRAM Configuration */
 999     s->regs[GT_SDRAM_CFG]     = 0x00000200;
1000     s->regs[GT_SDRAM_OPMODE]  = 0x00000000;
1001     s->regs[GT_SDRAM_BM]      = 0x00000007;
1002     s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1003
1004     /* SDRAM Parameters */
1005     s->regs[GT_SDRAM_B0]      = 0x00000005;
1006     s->regs[GT_SDRAM_B1]      = 0x00000005;
1007     s->regs[GT_SDRAM_B2]      = 0x00000005;
1008     s->regs[GT_SDRAM_B3]      = 0x00000005;
1009
1010     /* ECC */
1011     s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1012     s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1013     s->regs[GT_ECC_MEM]       = 0x00000000;
1014     s->regs[GT_ECC_CALC]      = 0x00000000;
1015     s->regs[GT_ECC_ERRADDR]   = 0x00000000;
1016
1017     /* Device Parameters */
1018     s->regs[GT_DEV_B0]        = 0x386fffff;
1019     s->regs[GT_DEV_B1]        = 0x386fffff;
1020     s->regs[GT_DEV_B2]        = 0x386fffff;
1021     s->regs[GT_DEV_B3]        = 0x386fffff;
1022     s->regs[GT_DEV_BOOT]      = 0x146fffff;
1023
1024     /* DMA registers are all zeroed at reset */
1025
1026     /* Timer/Counter */
1027     s->regs[GT_TC0]           = 0xffffffff;
1028     s->regs[GT_TC1]           = 0x00ffffff;
1029     s->regs[GT_TC2]           = 0x00ffffff;
1030     s->regs[GT_TC3]           = 0x00ffffff;
1031     s->regs[GT_TC_CONTROL]    = 0x00000000;
1032
1033     /* PCI Internal */
1034 #ifdef TARGET_WORDS_BIGENDIAN
1035     s->regs[GT_PCI0_CMD]      = 0x00000000;
1036 #else
1037     s->regs[GT_PCI0_CMD]      = 0x00010001;
1038 #endif
1039     s->regs[GT_PCI0_TOR]      = 0x0000070f;
1040     s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1041     s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1042     s->regs[GT_PCI0_BS_CS20]  = 0x01fff000;
1043     s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1044     s->regs[GT_PCI1_IACK]     = 0x00000000;
1045     s->regs[GT_PCI0_IACK]     = 0x00000000;
1046     s->regs[GT_PCI0_BARE]     = 0x0000000f;
1047     s->regs[GT_PCI0_PREFMBR]  = 0x00000040;
1048     s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1049     s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1050     s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1051     s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1052     s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1053     s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1054     s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1055 #ifdef TARGET_WORDS_BIGENDIAN
1056     s->regs[GT_PCI1_CMD]      = 0x00000000;
1057 #else
1058     s->regs[GT_PCI1_CMD]      = 0x00010001;
1059 #endif
1060     s->regs[GT_PCI1_TOR]      = 0x0000070f;
1061     s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1062     s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1063     s->regs[GT_PCI1_BS_CS20]  = 0x01fff000;
1064     s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1065     s->regs[GT_PCI1_BARE]     = 0x0000000f;
1066     s->regs[GT_PCI1_PREFMBR]  = 0x00000040;
1067     s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1068     s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1069     s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1070     s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1071     s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1072     s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1073     s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1074     s->regs[GT_PCI1_CFGADDR]  = 0x00000000;
1075     s->regs[GT_PCI1_CFGDATA]  = 0x00000000;
1076     s->regs[GT_PCI0_CFGADDR]  = 0x00000000;
1077
1078     /* Interrupt registers are all zeroed at reset */
1079
1080     gt64120_isd_mapping(s);
1081     gt64120_pci_mapping(s);
1082 }
1083
1084 PCIBus *gt64120_register(qemu_irq *pic)
1085 {
1086     SysBusDevice *s;
1087     GT64120State *d;
1088     DeviceState *dev;
1089
1090     dev = qdev_create(NULL, "gt64120");
1091     qdev_init_nofail(dev);
1092     s = sysbus_from_qdev(dev);
1093     d = FROM_SYSBUS(GT64120State, s);
1094     d->pci.bus = pci_register_bus(&d->busdev.qdev, "pci",
1095                                   gt64120_pci_set_irq, gt64120_pci_map_irq,
1096                                   pic, get_system_memory(),
1097                                   PCI_DEVFN(18, 0), 4);
1098     d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d,
1099                                            DEVICE_NATIVE_ENDIAN);
1100
1101     pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci");
1102     return d->pci.bus;
1103 }
1104
1105 static int gt64120_init(SysBusDevice *dev)
1106 {
1107     GT64120State *s;
1108
1109     s = FROM_SYSBUS(GT64120State, dev);
1110
1111     /* FIXME: This value is computed from registers during reset, but some
1112        devices (e.g. VGA card) need to know it when they are registered.
1113        This also mean that changing the register to change the mapping
1114        does not fully work. */
1115     isa_mem_base = 0x10000000;
1116     qemu_register_reset(gt64120_reset, s);
1117     return 0;
1118 }
1119
1120 static int gt64120_pci_init(PCIDevice *d)
1121 {
1122     /* FIXME: Malta specific hw assumptions ahead */
1123     pci_set_word(d->config + PCI_COMMAND, 0);
1124     pci_set_word(d->config + PCI_STATUS,
1125                  PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1126     pci_config_set_prog_interface(d->config, 0);
1127     pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1128     pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1129     pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1130     pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1131     pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1132     pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1133     pci_set_byte(d->config + 0x3d, 0x01);
1134
1135     return 0;
1136 }
1137
1138 static PCIDeviceInfo gt64120_pci_info = {
1139     .qdev.name = "gt64120_pci",
1140     .qdev.size = sizeof(PCIDevice),
1141     .init      = gt64120_pci_init,
1142     .vendor_id = PCI_VENDOR_ID_MARVELL,
1143     .device_id = PCI_DEVICE_ID_MARVELL_GT6412X,
1144     .revision  = 0x10,
1145     .class_id  = PCI_CLASS_BRIDGE_HOST,
1146 };
1147
1148 static void gt64120_pci_register_devices(void)
1149 {
1150     sysbus_register_dev("gt64120", sizeof(GT64120State),
1151                         gt64120_init);
1152     pci_qdev_register(&gt64120_pci_info);
1153 }
1154
1155 device_init(gt64120_pci_register_devices)