target/arm/kvm32.c

   1 /*
   2  * ARM implementation of KVM hooks, 32 bit specific code.
   3  *
   4  * Copyright Christoffer Dall 2009-2010
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include <sys/ioctl.h>
  13
  14 #include <linux/kvm.h>
  15
  16 #include "qemu-common.h"
  17 #include "cpu.h"
  18 #include "qemu/timer.h"
  19 #include "sysemu/sysemu.h"
  20 #include "sysemu/kvm.h"
  21 #include "kvm_arm.h"
  22 #include "internals.h"
  23 #include "hw/arm/arm.h"
  24 #include "qemu/log.h"
  25
  26 static inline void set_feature(uint64_t *features, int feature)
  27 {
  28     *features |= 1ULL << feature;
  29 }
  30
  31 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
  32 {
  33     /* Identify the feature bits corresponding to the host CPU, and
  34      * fill out the ARMHostCPUClass fields accordingly. To do this
  35      * we have to create a scratch VM, create a single CPU inside it,
  36      * and then query that CPU for the relevant ID registers.
  37      */
  38     int i, ret, fdarray[3];
  39     uint32_t midr, id_pfr0, mvfr1;
  40     uint64_t features = 0;
  41     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
  42      * we know these will only support creating one kind of guest CPU,
  43      * which is its preferred CPU type.
  44      */
  45     static const uint32_t cpus_to_try[] = {
  46         QEMU_KVM_ARM_TARGET_CORTEX_A15,
  47         QEMU_KVM_ARM_TARGET_NONE
  48     };
  49     struct kvm_vcpu_init init;
  50     struct kvm_one_reg idregs[] = {
  51         {
  52             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  53             | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0),
  54             .addr = (uintptr_t)&midr,
  55         },
  56         {
  57             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  58             | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0),
  59             .addr = (uintptr_t)&id_pfr0,
  60         },
  61         {
  62             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  63             | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
  64             .addr = (uintptr_t)&mvfr1,
  65         },
  66     };
  67
  68     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
  69         return false;
  70     }
  71
  72     ahcf->target = init.target;
  73
  74     /* This is not strictly blessed by the device tree binding docs yet,
  75      * but in practice the kernel does not care about this string so
  76      * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
  77      */
  78     ahcf->dtb_compatible = "arm,arm-v7";
  79
  80     for (i = 0; i < ARRAY_SIZE(idregs); i++) {
  81         ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
  82         if (ret) {
  83             break;
  84         }
  85     }
  86
  87     kvm_arm_destroy_scratch_host_vcpu(fdarray);
  88
  89     if (ret) {
  90         return false;
  91     }
  92
  93     /* Now we've retrieved all the register information we can
  94      * set the feature bits based on the ID register fields.
  95      * We can assume any KVM supporting CPU is at least a v7
  96      * with VFPv3, virtualization extensions, and the generic
  97      * timers; this in turn implies most of the other feature
  98      * bits, but a few must be tested.
  99      */
 100     set_feature(&features, ARM_FEATURE_V7VE);
 101     set_feature(&features, ARM_FEATURE_VFP3);
 102     set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
 103
 104     if (extract32(id_pfr0, 12, 4) == 1) {
 105         set_feature(&features, ARM_FEATURE_THUMB2EE);
 106     }
 107     if (extract32(mvfr1, 20, 4) == 1) {
 108         set_feature(&features, ARM_FEATURE_VFP_FP16);
 109     }
 110     if (extract32(mvfr1, 12, 4) == 1) {
 111         set_feature(&features, ARM_FEATURE_NEON);
 112     }
 113     if (extract32(mvfr1, 28, 4) == 1) {
 114         /* FMAC support implies VFPv4 */
 115         set_feature(&features, ARM_FEATURE_VFP4);
 116     }
 117
 118     ahcf->features = features;
 119
 120     return true;
 121 }
 122
 123 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 124 {
 125     /* Return true if the regidx is a register we should synchronize
 126      * via the cpreg_tuples array (ie is not a core reg we sync by
 127      * hand in kvm_arch_get/put_registers())
 128      */
 129     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 130     case KVM_REG_ARM_CORE:
 131     case KVM_REG_ARM_VFP:
 132         return false;
 133     default:
 134         return true;
 135     }
 136 }
 137
 138 typedef struct CPRegStateLevel {
 139     uint64_t regidx;
 140     int level;
 141 } CPRegStateLevel;
 142
 143 /* All coprocessor registers not listed in the following table are assumed to
 144  * be of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
 145  * often, you must add it to this table with a state of either
 146  * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
 147  */
 148 static const CPRegStateLevel non_runtime_cpregs[] = {
 149     { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
 150 };
 151
 152 int kvm_arm_cpreg_level(uint64_t regidx)
 153 {
 154     int i;
 155
 156     for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
 157         const CPRegStateLevel *l = &non_runtime_cpregs[i];
 158         if (l->regidx == regidx) {
 159             return l->level;
 160         }
 161     }
 162
 163     return KVM_PUT_RUNTIME_STATE;
 164 }
 165
 166 #define ARM_CPU_ID_MPIDR       0, 0, 0, 5
 167
 168 int kvm_arch_init_vcpu(CPUState *cs)
 169 {
 170     int ret;
 171     uint64_t v;
 172     uint32_t mpidr;
 173     struct kvm_one_reg r;
 174     ARMCPU *cpu = ARM_CPU(cs);
 175
 176     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
 177         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 178         return -EINVAL;
 179     }
 180
 181     /* Determine init features for this CPU */
 182     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
 183     if (cpu->start_powered_off) {
 184         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
 185     }
 186     if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
 187         cpu->psci_version = 2;
 188         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
 189     }
 190
 191     /* Do KVM_ARM_VCPU_INIT ioctl */
 192     ret = kvm_arm_vcpu_init(cs);
 193     if (ret) {
 194         return ret;
 195     }
 196
 197     /* Query the kernel to make sure it supports 32 VFP
 198      * registers: QEMU's "cortex-a15" CPU is always a
 199      * VFP-D32 core. The simplest way to do this is just
 200      * to attempt to read register d31.
 201      */
 202     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
 203     r.addr = (uintptr_t)(&v);
 204     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 205     if (ret == -ENOENT) {
 206         return -EINVAL;
 207     }
 208
 209     /*
 210      * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
 211      * Currently KVM has its own idea about MPIDR assignment, so we
 212      * override our defaults with what we get from KVM.
 213      */
 214     ret = kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr);
 215     if (ret) {
 216         return ret;
 217     }
 218     cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
 219
 220     return kvm_arm_init_cpreg_list(cpu);
 221 }
 222
 223 typedef struct Reg {
 224     uint64_t id;
 225     int offset;
 226 } Reg;
 227
 228 #define COREREG(KERNELNAME, QEMUFIELD)                       \
 229     {                                                        \
 230         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 231         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 232         offsetof(CPUARMState, QEMUFIELD)                     \
 233     }
 234
 235 #define VFPSYSREG(R)                                       \
 236     {                                                      \
 237         KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
 238         KVM_REG_ARM_VFP_##R,                               \
 239         offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R])      \
 240     }
 241
 242 /* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
 243 #define COREREG64(KERNELNAME, QEMUFIELD)                     \
 244     {                                                        \
 245         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 246         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 247         offsetoflow32(CPUARMState, QEMUFIELD)                \
 248     }
 249
 250 static const Reg regs[] = {
 251     /* R0_usr .. R14_usr */
 252     COREREG(usr_regs.uregs[0], regs[0]),
 253     COREREG(usr_regs.uregs[1], regs[1]),
 254     COREREG(usr_regs.uregs[2], regs[2]),
 255     COREREG(usr_regs.uregs[3], regs[3]),
 256     COREREG(usr_regs.uregs[4], regs[4]),
 257     COREREG(usr_regs.uregs[5], regs[5]),
 258     COREREG(usr_regs.uregs[6], regs[6]),
 259     COREREG(usr_regs.uregs[7], regs[7]),
 260     COREREG(usr_regs.uregs[8], usr_regs[0]),
 261     COREREG(usr_regs.uregs[9], usr_regs[1]),
 262     COREREG(usr_regs.uregs[10], usr_regs[2]),
 263     COREREG(usr_regs.uregs[11], usr_regs[3]),
 264     COREREG(usr_regs.uregs[12], usr_regs[4]),
 265     COREREG(usr_regs.uregs[13], banked_r13[BANK_USRSYS]),
 266     COREREG(usr_regs.uregs[14], banked_r14[BANK_USRSYS]),
 267     /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
 268     COREREG(svc_regs[0], banked_r13[BANK_SVC]),
 269     COREREG(svc_regs[1], banked_r14[BANK_SVC]),
 270     COREREG64(svc_regs[2], banked_spsr[BANK_SVC]),
 271     COREREG(abt_regs[0], banked_r13[BANK_ABT]),
 272     COREREG(abt_regs[1], banked_r14[BANK_ABT]),
 273     COREREG64(abt_regs[2], banked_spsr[BANK_ABT]),
 274     COREREG(und_regs[0], banked_r13[BANK_UND]),
 275     COREREG(und_regs[1], banked_r14[BANK_UND]),
 276     COREREG64(und_regs[2], banked_spsr[BANK_UND]),
 277     COREREG(irq_regs[0], banked_r13[BANK_IRQ]),
 278     COREREG(irq_regs[1], banked_r14[BANK_IRQ]),
 279     COREREG64(irq_regs[2], banked_spsr[BANK_IRQ]),
 280     /* R8_fiq .. R14_fiq and SPSR_fiq */
 281     COREREG(fiq_regs[0], fiq_regs[0]),
 282     COREREG(fiq_regs[1], fiq_regs[1]),
 283     COREREG(fiq_regs[2], fiq_regs[2]),
 284     COREREG(fiq_regs[3], fiq_regs[3]),
 285     COREREG(fiq_regs[4], fiq_regs[4]),
 286     COREREG(fiq_regs[5], banked_r13[BANK_FIQ]),
 287     COREREG(fiq_regs[6], banked_r14[BANK_FIQ]),
 288     COREREG64(fiq_regs[7], banked_spsr[BANK_FIQ]),
 289     /* R15 */
 290     COREREG(usr_regs.uregs[15], regs[15]),
 291     /* VFP system registers */
 292     VFPSYSREG(FPSID),
 293     VFPSYSREG(MVFR1),
 294     VFPSYSREG(MVFR0),
 295     VFPSYSREG(FPEXC),
 296     VFPSYSREG(FPINST),
 297     VFPSYSREG(FPINST2),
 298 };
 299
 300 int kvm_arch_put_registers(CPUState *cs, int level)
 301 {
 302     ARMCPU *cpu = ARM_CPU(cs);
 303     CPUARMState *env = &cpu->env;
 304     struct kvm_one_reg r;
 305     int mode, bn;
 306     int ret, i;
 307     uint32_t cpsr, fpscr;
 308
 309     /* Make sure the banked regs are properly set */
 310     mode = env->uncached_cpsr & CPSR_M;
 311     bn = bank_number(mode);
 312     if (mode == ARM_CPU_MODE_FIQ) {
 313         memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
 314     } else {
 315         memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
 316     }
 317     env->banked_r13[bn] = env->regs[13];
 318     env->banked_r14[bn] = env->regs[14];
 319     env->banked_spsr[bn] = env->spsr;
 320
 321     /* Now we can safely copy stuff down to the kernel */
 322     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 323         r.id = regs[i].id;
 324         r.addr = (uintptr_t)(env) + regs[i].offset;
 325         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 326         if (ret) {
 327             return ret;
 328         }
 329     }
 330
 331     /* Special cases which aren't a single CPUARMState field */
 332     cpsr = cpsr_read(env);
 333     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 334         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 335     r.addr = (uintptr_t)(&cpsr);
 336     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 337     if (ret) {
 338         return ret;
 339     }
 340
 341     /* VFP registers */
 342     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 343     for (i = 0; i < 32; i++) {
 344         r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 345         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 346         if (ret) {
 347             return ret;
 348         }
 349         r.id++;
 350     }
 351
 352     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 353         KVM_REG_ARM_VFP_FPSCR;
 354     fpscr = vfp_get_fpscr(env);
 355     r.addr = (uintptr_t)&fpscr;
 356     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 357     if (ret) {
 358         return ret;
 359     }
 360
 361     /* Note that we do not call write_cpustate_to_list()
 362      * here, so we are only writing the tuple list back to
 363      * KVM. This is safe because nothing can change the
 364      * CPUARMState cp15 fields (in particular gdb accesses cannot)
 365      * and so there are no changes to sync. In fact syncing would
 366      * be wrong at this point: for a constant register where TCG and
 367      * KVM disagree about its value, the preceding write_list_to_cpustate()
 368      * would not have had any effect on the CPUARMState value (since the
 369      * register is read-only), and a write_cpustate_to_list() here would
 370      * then try to write the TCG value back into KVM -- this would either
 371      * fail or incorrectly change the value the guest sees.
 372      *
 373      * If we ever want to allow the user to modify cp15 registers via
 374      * the gdb stub, we would need to be more clever here (for instance
 375      * tracking the set of registers kvm_arch_get_registers() successfully
 376      * managed to update the CPUARMState with, and only allowing those
 377      * to be written back up into the kernel).
 378      */
 379     if (!write_list_to_kvmstate(cpu, level)) {
 380         return EINVAL;
 381     }
 382
 383     kvm_arm_sync_mpstate_to_kvm(cpu);
 384
 385     return ret;
 386 }
 387
 388 int kvm_arch_get_registers(CPUState *cs)
 389 {
 390     ARMCPU *cpu = ARM_CPU(cs);
 391     CPUARMState *env = &cpu->env;
 392     struct kvm_one_reg r;
 393     int mode, bn;
 394     int ret, i;
 395     uint32_t cpsr, fpscr;
 396
 397     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 398         r.id = regs[i].id;
 399         r.addr = (uintptr_t)(env) + regs[i].offset;
 400         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 401         if (ret) {
 402             return ret;
 403         }
 404     }
 405
 406     /* Special cases which aren't a single CPUARMState field */
 407     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 408         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 409     r.addr = (uintptr_t)(&cpsr);
 410     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 411     if (ret) {
 412         return ret;
 413     }
 414     cpsr_write(env, cpsr, 0xffffffff, CPSRWriteRaw);
 415
 416     /* Make sure the current mode regs are properly set */
 417     mode = env->uncached_cpsr & CPSR_M;
 418     bn = bank_number(mode);
 419     if (mode == ARM_CPU_MODE_FIQ) {
 420         memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
 421     } else {
 422         memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
 423     }
 424     env->regs[13] = env->banked_r13[bn];
 425     env->regs[14] = env->banked_r14[bn];
 426     env->spsr = env->banked_spsr[bn];
 427
 428     /* VFP registers */
 429     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 430     for (i = 0; i < 32; i++) {
 431         r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 432         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 433         if (ret) {
 434             return ret;
 435         }
 436         r.id++;
 437     }
 438
 439     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 440         KVM_REG_ARM_VFP_FPSCR;
 441     r.addr = (uintptr_t)&fpscr;
 442     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 443     if (ret) {
 444         return ret;
 445     }
 446     vfp_set_fpscr(env, fpscr);
 447
 448     if (!write_kvmstate_to_list(cpu)) {
 449         return EINVAL;
 450     }
 451     /* Note that it's OK to have registers which aren't in CPUState,
 452      * so we can ignore a failure return here.
 453      */
 454     write_list_to_cpustate(cpu);
 455
 456     kvm_arm_sync_mpstate_to_qemu(cpu);
 457
 458     return 0;
 459 }
 460
 461 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 462 {
 463     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 464     return -EINVAL;
 465 }
 466
 467 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 468 {
 469     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 470     return -EINVAL;
 471 }
 472
 473 bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
 474 {
 475     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 476     return false;
 477 }
 478
 479 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 480                                   target_ulong len, int type)
 481 {
 482     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 483     return -EINVAL;
 484 }
 485
 486 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 487                                   target_ulong len, int type)
 488 {
 489     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 490     return -EINVAL;
 491 }
 492
 493 void kvm_arch_remove_all_hw_breakpoints(void)
 494 {
 495     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 496 }
 497
 498 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
 499 {
 500     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 501 }
 502
 503 bool kvm_arm_hw_debug_active(CPUState *cs)
 504 {
 505     return false;
 506 }
 507
 508 void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
 509 {
 510     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 511 }
 512
 513 void kvm_arm_pmu_init(CPUState *cs)
 514 {
 515     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 516 }