2 * Q35 chipset based pc system emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on pc.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "qemu/osdep.h"
32 #include "qemu/units.h"
33 #include "hw/loader.h"
34 #include "sysemu/arch_init.h"
35 #include "hw/i2c/smbus_eeprom.h"
36 #include "hw/timer/mc146818rtc.h"
37 #include "hw/xen/xen.h"
38 #include "sysemu/kvm.h"
40 #include "hw/kvm/clock.h"
41 #include "hw/pci-host/q35.h"
42 #include "hw/qdev-properties.h"
43 #include "exec/address-spaces.h"
44 #include "hw/i386/pc.h"
45 #include "hw/i386/ich9.h"
46 #include "hw/i386/amd_iommu.h"
47 #include "hw/i386/intel_iommu.h"
48 #include "hw/display/ramfb.h"
49 #include "hw/firmware/smbios.h"
50 #include "hw/ide/pci.h"
51 #include "hw/ide/ahci.h"
53 #include "qapi/error.h"
54 #include "qemu/error-report.h"
55 #include "sysemu/numa.h"
57 /* ICH9 AHCI has 6 ports */
58 #define MAX_SATA_PORTS 6
60 struct ehci_companions
{
66 static const struct ehci_companions ich9_1d
[] = {
67 { .name
= "ich9-usb-uhci1", .func
= 0, .port
= 0 },
68 { .name
= "ich9-usb-uhci2", .func
= 1, .port
= 2 },
69 { .name
= "ich9-usb-uhci3", .func
= 2, .port
= 4 },
72 static const struct ehci_companions ich9_1a
[] = {
73 { .name
= "ich9-usb-uhci4", .func
= 0, .port
= 0 },
74 { .name
= "ich9-usb-uhci5", .func
= 1, .port
= 2 },
75 { .name
= "ich9-usb-uhci6", .func
= 2, .port
= 4 },
78 static int ehci_create_ich9_with_companions(PCIBus
*bus
, int slot
)
80 const struct ehci_companions
*comp
;
81 PCIDevice
*ehci
, *uhci
;
88 name
= "ich9-usb-ehci1";
92 name
= "ich9-usb-ehci2";
99 ehci
= pci_create_multifunction(bus
, PCI_DEVFN(slot
, 7), true, name
);
100 qdev_init_nofail(&ehci
->qdev
);
101 usbbus
= QLIST_FIRST(&ehci
->qdev
.child_bus
);
103 for (i
= 0; i
< 3; i
++) {
104 uhci
= pci_create_multifunction(bus
, PCI_DEVFN(slot
, comp
[i
].func
),
106 qdev_prop_set_string(&uhci
->qdev
, "masterbus", usbbus
->name
);
107 qdev_prop_set_uint32(&uhci
->qdev
, "firstport", comp
[i
].port
);
108 qdev_init_nofail(&uhci
->qdev
);
113 /* PC hardware initialisation */
114 static void pc_q35_init(MachineState
*machine
)
116 PCMachineState
*pcms
= PC_MACHINE(machine
);
117 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
118 Q35PCIHost
*q35_host
;
122 DeviceState
*lpc_dev
;
123 BusState
*idebus
[MAX_SATA_PORTS
];
124 ISADevice
*rtc_state
;
125 MemoryRegion
*system_io
= get_system_io();
126 MemoryRegion
*pci_memory
;
127 MemoryRegion
*rom_memory
;
128 MemoryRegion
*ram_memory
;
133 ICH9LPCState
*ich9_lpc
;
136 DriveInfo
*hd
[MAX_SATA_PORTS
];
137 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
139 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
140 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
141 * also known as MMCFG).
142 * If it doesn't, we need to split it in chunks below and above 4G.
143 * In any case, try to make sure that guest addresses aligned at
144 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
146 if (machine
->ram_size
>= 0xb0000000) {
152 /* Handle the machine opt max-ram-below-4g. It is basically doing
153 * min(qemu limit, user limit).
155 if (!pcms
->max_ram_below_4g
) {
156 pcms
->max_ram_below_4g
= 1ULL << 32; /* default: 4G */;
158 if (lowmem
> pcms
->max_ram_below_4g
) {
159 lowmem
= pcms
->max_ram_below_4g
;
160 if (machine
->ram_size
- lowmem
> lowmem
&&
161 lowmem
& (1 * GiB
- 1)) {
162 warn_report("There is possibly poor performance as the ram size "
163 " (0x%" PRIx64
") is more then twice the size of"
164 " max-ram-below-4g (%"PRIu64
") and"
165 " max-ram-below-4g is not a multiple of 1G.",
166 (uint64_t)machine
->ram_size
, pcms
->max_ram_below_4g
);
170 if (machine
->ram_size
>= lowmem
) {
171 pcms
->above_4g_mem_size
= machine
->ram_size
- lowmem
;
172 pcms
->below_4g_mem_size
= lowmem
;
174 pcms
->above_4g_mem_size
= 0;
175 pcms
->below_4g_mem_size
= machine
->ram_size
;
179 xen_hvm_init(pcms
, &ram_memory
);
187 if (pcmc
->pci_enabled
) {
188 pci_memory
= g_new(MemoryRegion
, 1);
189 memory_region_init(pci_memory
, NULL
, "pci", UINT64_MAX
);
190 rom_memory
= pci_memory
;
193 rom_memory
= get_system_memory();
196 pc_guest_info_init(pcms
);
198 if (pcmc
->smbios_defaults
) {
199 /* These values are guest ABI, do not change */
200 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
201 mc
->name
, pcmc
->smbios_legacy_mode
,
202 pcmc
->smbios_uuid_encoded
,
203 SMBIOS_ENTRY_POINT_21
);
206 /* allocate ram and load rom/bios */
207 if (!xen_enabled()) {
208 pc_memory_init(pcms
, get_system_memory(),
209 rom_memory
, &ram_memory
);
213 gsi_state
= g_malloc0(sizeof(*gsi_state
));
214 if (kvm_ioapic_in_kernel()) {
215 kvm_pc_setup_irq_routing(pcmc
->pci_enabled
);
216 pcms
->gsi
= qemu_allocate_irqs(kvm_pc_gsi_handler
, gsi_state
,
219 pcms
->gsi
= qemu_allocate_irqs(gsi_handler
, gsi_state
, GSI_NUM_PINS
);
222 /* create pci host bus */
223 q35_host
= Q35_HOST_DEVICE(qdev_create(NULL
, TYPE_Q35_HOST_DEVICE
));
225 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host
), NULL
);
226 object_property_set_link(OBJECT(q35_host
), OBJECT(ram_memory
),
227 MCH_HOST_PROP_RAM_MEM
, NULL
);
228 object_property_set_link(OBJECT(q35_host
), OBJECT(pci_memory
),
229 MCH_HOST_PROP_PCI_MEM
, NULL
);
230 object_property_set_link(OBJECT(q35_host
), OBJECT(get_system_memory()),
231 MCH_HOST_PROP_SYSTEM_MEM
, NULL
);
232 object_property_set_link(OBJECT(q35_host
), OBJECT(system_io
),
233 MCH_HOST_PROP_IO_MEM
, NULL
);
234 object_property_set_int(OBJECT(q35_host
), pcms
->below_4g_mem_size
,
235 PCI_HOST_BELOW_4G_MEM_SIZE
, NULL
);
236 object_property_set_int(OBJECT(q35_host
), pcms
->above_4g_mem_size
,
237 PCI_HOST_ABOVE_4G_MEM_SIZE
, NULL
);
239 qdev_init_nofail(DEVICE(q35_host
));
240 phb
= PCI_HOST_BRIDGE(q35_host
);
243 lpc
= pci_create_simple_multifunction(host_bus
, PCI_DEVFN(ICH9_LPC_DEV
,
244 ICH9_LPC_FUNC
), true,
245 TYPE_ICH9_LPC_DEVICE
);
247 object_property_add_link(OBJECT(machine
), PC_MACHINE_ACPI_DEVICE_PROP
,
248 TYPE_HOTPLUG_HANDLER
,
249 (Object
**)&pcms
->acpi_dev
,
250 object_property_allow_set_link
,
251 OBJ_PROP_LINK_STRONG
, &error_abort
);
252 object_property_set_link(OBJECT(machine
), OBJECT(lpc
),
253 PC_MACHINE_ACPI_DEVICE_PROP
, &error_abort
);
255 ich9_lpc
= ICH9_LPC_DEVICE(lpc
);
256 lpc_dev
= DEVICE(lpc
);
257 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
258 qdev_connect_gpio_out_named(lpc_dev
, ICH9_GPIO_GSI
, i
, pcms
->gsi
[i
]);
260 pci_bus_irqs(host_bus
, ich9_lpc_set_irq
, ich9_lpc_map_irq
, ich9_lpc
,
262 pci_bus_set_route_irq_fn(host_bus
, ich9_route_intx_pin_to_irq
);
263 isa_bus
= ich9_lpc
->isa_bus
;
265 if (kvm_pic_in_kernel()) {
266 i8259
= kvm_i8259_init(isa_bus
);
267 } else if (xen_enabled()) {
268 i8259
= xen_interrupt_controller_init();
270 i8259
= i8259_init(isa_bus
, pc_allocate_cpu_irq());
273 for (i
= 0; i
< ISA_NUM_IRQS
; i
++) {
274 gsi_state
->i8259_irq
[i
] = i8259
[i
];
278 if (pcmc
->pci_enabled
) {
279 ioapic_init_gsi(gsi_state
, "q35");
282 pc_register_ferr_irq(pcms
->gsi
[13]);
284 assert(pcms
->vmport
!= ON_OFF_AUTO__MAX
);
285 if (pcms
->vmport
== ON_OFF_AUTO_AUTO
) {
286 pcms
->vmport
= xen_enabled() ? ON_OFF_AUTO_OFF
: ON_OFF_AUTO_ON
;
289 /* init basic PC hardware */
290 pc_basic_device_init(isa_bus
, pcms
->gsi
, &rtc_state
, !mc
->no_floppy
,
291 (pcms
->vmport
!= ON_OFF_AUTO_ON
), pcms
->pit_enabled
,
294 /* connect pm stuff to lpc */
295 ich9_lpc_pm_init(lpc
, pc_machine_is_smm_enabled(pcms
));
297 if (pcms
->sata_enabled
) {
298 /* ahci and SATA device, for q35 1 ahci controller is built-in */
299 ahci
= pci_create_simple_multifunction(host_bus
,
300 PCI_DEVFN(ICH9_SATA1_DEV
,
303 idebus
[0] = qdev_get_child_bus(&ahci
->qdev
, "ide.0");
304 idebus
[1] = qdev_get_child_bus(&ahci
->qdev
, "ide.1");
305 g_assert(MAX_SATA_PORTS
== ahci_get_num_ports(ahci
));
306 ide_drive_get(hd
, ahci_get_num_ports(ahci
));
307 ahci_ide_create_devs(ahci
, hd
);
309 idebus
[0] = idebus
[1] = NULL
;
312 if (machine_usb(machine
)) {
313 /* Should we create 6 UHCI according to ich9 spec? */
314 ehci_create_ich9_with_companions(host_bus
, 0x1d);
317 if (pcms
->smbus_enabled
) {
318 /* TODO: Populate SPD eeprom data. */
319 pcms
->smbus
= ich9_smb_init(host_bus
,
320 PCI_DEVFN(ICH9_SMB_DEV
, ICH9_SMB_FUNC
),
322 smbus_eeprom_init(pcms
->smbus
, 8, NULL
, 0);
325 pc_cmos_init(pcms
, idebus
[0], idebus
[1], rtc_state
);
327 /* the rest devices to which pci devfn is automatically assigned */
328 pc_vga_init(isa_bus
, host_bus
);
329 pc_nic_init(pcmc
, isa_bus
, host_bus
);
331 if (machine
->nvdimms_state
->is_enabled
) {
332 nvdimm_init_acpi_state(machine
->nvdimms_state
, system_io
,
333 pcms
->fw_cfg
, OBJECT(pcms
));
337 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
338 static void pc_init_##suffix(MachineState *machine) \
340 void (*compat)(MachineState *m) = (compatfn); \
344 pc_q35_init(machine); \
346 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
349 static void pc_q35_machine_options(MachineClass
*m
)
351 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
352 pcmc
->default_nic_model
= "e1000e";
354 m
->family
= "pc_q35";
355 m
->desc
= "Standard PC (Q35 + ICH9, 2009)";
356 m
->units_per_default_bus
= 1;
357 m
->default_machine_opts
= "firmware=bios-256k.bin";
358 m
->default_display
= "std";
359 m
->default_kernel_irqchip_split
= false;
361 machine_class_allow_dynamic_sysbus_dev(m
, TYPE_AMD_IOMMU_DEVICE
);
362 machine_class_allow_dynamic_sysbus_dev(m
, TYPE_INTEL_IOMMU_DEVICE
);
363 machine_class_allow_dynamic_sysbus_dev(m
, TYPE_RAMFB_DEVICE
);
367 static void pc_q35_4_2_machine_options(MachineClass
*m
)
369 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
370 pc_q35_machine_options(m
);
372 pcmc
->default_cpu_version
= 1;
375 DEFINE_Q35_MACHINE(v4_2
, "pc-q35-4.2", NULL
,
376 pc_q35_4_2_machine_options
);
378 static void pc_q35_4_1_machine_options(MachineClass
*m
)
380 pc_q35_4_2_machine_options(m
);
382 compat_props_add(m
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
383 compat_props_add(m
->compat_props
, pc_compat_4_1
, pc_compat_4_1_len
);
386 DEFINE_Q35_MACHINE(v4_1
, "pc-q35-4.1", NULL
,
387 pc_q35_4_1_machine_options
);
389 static void pc_q35_4_0_1_machine_options(MachineClass
*m
)
391 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
392 pc_q35_4_1_machine_options(m
);
394 pcmc
->default_cpu_version
= CPU_VERSION_LEGACY
;
396 * This is the default machine for the 4.0-stable branch. It is basically
397 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
400 compat_props_add(m
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
401 compat_props_add(m
->compat_props
, pc_compat_4_0
, pc_compat_4_0_len
);
404 DEFINE_Q35_MACHINE(v4_0_1
, "pc-q35-4.0.1", NULL
,
405 pc_q35_4_0_1_machine_options
);
407 static void pc_q35_4_0_machine_options(MachineClass
*m
)
409 pc_q35_4_0_1_machine_options(m
);
410 m
->default_kernel_irqchip_split
= true;
412 /* Compat props are applied by the 4.0.1 machine */
415 DEFINE_Q35_MACHINE(v4_0
, "pc-q35-4.0", NULL
,
416 pc_q35_4_0_machine_options
);
418 static void pc_q35_3_1_machine_options(MachineClass
*m
)
420 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
422 pc_q35_4_0_machine_options(m
);
423 m
->default_kernel_irqchip_split
= false;
424 pcmc
->do_not_add_smb_acpi
= true;
425 m
->smbus_no_migration_support
= true;
427 pcmc
->pvh_enabled
= false;
428 compat_props_add(m
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
429 compat_props_add(m
->compat_props
, pc_compat_3_1
, pc_compat_3_1_len
);
432 DEFINE_Q35_MACHINE(v3_1
, "pc-q35-3.1", NULL
,
433 pc_q35_3_1_machine_options
);
435 static void pc_q35_3_0_machine_options(MachineClass
*m
)
437 pc_q35_3_1_machine_options(m
);
438 compat_props_add(m
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
439 compat_props_add(m
->compat_props
, pc_compat_3_0
, pc_compat_3_0_len
);
442 DEFINE_Q35_MACHINE(v3_0
, "pc-q35-3.0", NULL
,
443 pc_q35_3_0_machine_options
);
445 static void pc_q35_2_12_machine_options(MachineClass
*m
)
447 pc_q35_3_0_machine_options(m
);
448 compat_props_add(m
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
449 compat_props_add(m
->compat_props
, pc_compat_2_12
, pc_compat_2_12_len
);
452 DEFINE_Q35_MACHINE(v2_12
, "pc-q35-2.12", NULL
,
453 pc_q35_2_12_machine_options
);
455 static void pc_q35_2_11_machine_options(MachineClass
*m
)
457 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
459 pc_q35_2_12_machine_options(m
);
460 pcmc
->default_nic_model
= "e1000";
461 compat_props_add(m
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
462 compat_props_add(m
->compat_props
, pc_compat_2_11
, pc_compat_2_11_len
);
465 DEFINE_Q35_MACHINE(v2_11
, "pc-q35-2.11", NULL
,
466 pc_q35_2_11_machine_options
);
468 static void pc_q35_2_10_machine_options(MachineClass
*m
)
470 pc_q35_2_11_machine_options(m
);
471 compat_props_add(m
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
472 compat_props_add(m
->compat_props
, pc_compat_2_10
, pc_compat_2_10_len
);
473 m
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
474 m
->auto_enable_numa_with_memhp
= false;
477 DEFINE_Q35_MACHINE(v2_10
, "pc-q35-2.10", NULL
,
478 pc_q35_2_10_machine_options
);
480 static void pc_q35_2_9_machine_options(MachineClass
*m
)
482 pc_q35_2_10_machine_options(m
);
483 compat_props_add(m
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
484 compat_props_add(m
->compat_props
, pc_compat_2_9
, pc_compat_2_9_len
);
487 DEFINE_Q35_MACHINE(v2_9
, "pc-q35-2.9", NULL
,
488 pc_q35_2_9_machine_options
);
490 static void pc_q35_2_8_machine_options(MachineClass
*m
)
492 pc_q35_2_9_machine_options(m
);
493 compat_props_add(m
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
494 compat_props_add(m
->compat_props
, pc_compat_2_8
, pc_compat_2_8_len
);
497 DEFINE_Q35_MACHINE(v2_8
, "pc-q35-2.8", NULL
,
498 pc_q35_2_8_machine_options
);
500 static void pc_q35_2_7_machine_options(MachineClass
*m
)
502 pc_q35_2_8_machine_options(m
);
504 compat_props_add(m
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
505 compat_props_add(m
->compat_props
, pc_compat_2_7
, pc_compat_2_7_len
);
508 DEFINE_Q35_MACHINE(v2_7
, "pc-q35-2.7", NULL
,
509 pc_q35_2_7_machine_options
);
511 static void pc_q35_2_6_machine_options(MachineClass
*m
)
513 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
515 pc_q35_2_7_machine_options(m
);
516 pcmc
->legacy_cpu_hotplug
= true;
517 pcmc
->linuxboot_dma_enabled
= false;
518 compat_props_add(m
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
519 compat_props_add(m
->compat_props
, pc_compat_2_6
, pc_compat_2_6_len
);
522 DEFINE_Q35_MACHINE(v2_6
, "pc-q35-2.6", NULL
,
523 pc_q35_2_6_machine_options
);
525 static void pc_q35_2_5_machine_options(MachineClass
*m
)
527 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
529 pc_q35_2_6_machine_options(m
);
530 pcmc
->save_tsc_khz
= false;
531 m
->legacy_fw_cfg_order
= 1;
532 compat_props_add(m
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
533 compat_props_add(m
->compat_props
, pc_compat_2_5
, pc_compat_2_5_len
);
536 DEFINE_Q35_MACHINE(v2_5
, "pc-q35-2.5", NULL
,
537 pc_q35_2_5_machine_options
);
539 static void pc_q35_2_4_machine_options(MachineClass
*m
)
541 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
543 pc_q35_2_5_machine_options(m
);
544 m
->hw_version
= "2.4.0";
545 pcmc
->broken_reserved_end
= true;
546 compat_props_add(m
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
547 compat_props_add(m
->compat_props
, pc_compat_2_4
, pc_compat_2_4_len
);
550 DEFINE_Q35_MACHINE(v2_4
, "pc-q35-2.4", NULL
,
551 pc_q35_2_4_machine_options
);