hw/char/xilinx_uartlite.c

   1 /*
   2  * QEMU model of Xilinx uartlite.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "sysemu/char.h"
  27
  28 #define DUART(x)
  29
  30 #define R_RX            0
  31 #define R_TX            1
  32 #define R_STATUS        2
  33 #define R_CTRL          3
  34 #define R_MAX           4
  35
  36 #define STATUS_RXVALID    0x01
  37 #define STATUS_RXFULL     0x02
  38 #define STATUS_TXEMPTY    0x04
  39 #define STATUS_TXFULL     0x08
  40 #define STATUS_IE         0x10
  41 #define STATUS_OVERRUN    0x20
  42 #define STATUS_FRAME      0x40
  43 #define STATUS_PARITY     0x80
  44
  45 #define CONTROL_RST_TX    0x01
  46 #define CONTROL_RST_RX    0x02
  47 #define CONTROL_IE        0x10
  48
  49 #define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
  50 #define XILINX_UARTLITE(obj) \
  51     OBJECT_CHECK(XilinxUARTLite, (obj), TYPE_XILINX_UARTLITE)
  52
  53 typedef struct XilinxUARTLite {
  54     SysBusDevice parent_obj;
  55
  56     MemoryRegion mmio;
  57     CharDriverState *chr;
  58     qemu_irq irq;
  59
  60     uint8_t rx_fifo[8];
  61     unsigned int rx_fifo_pos;
  62     unsigned int rx_fifo_len;
  63
  64     uint32_t regs[R_MAX];
  65 } XilinxUARTLite;
  66
  67 static void uart_update_irq(XilinxUARTLite *s)
  68 {
  69     unsigned int irq;
  70
  71     if (s->rx_fifo_len)
  72         s->regs[R_STATUS] |= STATUS_IE;
  73
  74     irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
  75     qemu_set_irq(s->irq, irq);
  76 }
  77
  78 static void uart_update_status(XilinxUARTLite *s)
  79 {
  80     uint32_t r;
  81
  82     r = s->regs[R_STATUS];
  83     r &= ~7;
  84     r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */
  85     r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
  86     r |= (!!s->rx_fifo_len);
  87     s->regs[R_STATUS] = r;
  88 }
  89
  90 static void xilinx_uartlite_reset(DeviceState *dev)
  91 {
  92     uart_update_status(XILINX_UARTLITE(dev));
  93 }
  94
  95 static uint64_t
  96 uart_read(void *opaque, hwaddr addr, unsigned int size)
  97 {
  98     XilinxUARTLite *s = opaque;
  99     uint32_t r = 0;
 100     addr >>= 2;
 101     switch (addr)
 102     {
 103         case R_RX:
 104             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
 105             if (s->rx_fifo_len)
 106                 s->rx_fifo_len--;
 107             uart_update_status(s);
 108             uart_update_irq(s);
 109             qemu_chr_accept_input(s->chr);
 110             break;
 111
 112         default:
 113             if (addr < ARRAY_SIZE(s->regs))
 114                 r = s->regs[addr];
 115             DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
 116             break;
 117     }
 118     return r;
 119 }
 120
 121 static void
 122 uart_write(void *opaque, hwaddr addr,
 123            uint64_t val64, unsigned int size)
 124 {
 125     XilinxUARTLite *s = opaque;
 126     uint32_t value = val64;
 127     unsigned char ch = value;
 128
 129     addr >>= 2;
 130     switch (addr)
 131     {
 132         case R_STATUS:
 133             hw_error("write to UART STATUS?\n");
 134             break;
 135
 136         case R_CTRL:
 137             if (value & CONTROL_RST_RX) {
 138                 s->rx_fifo_pos = 0;
 139                 s->rx_fifo_len = 0;
 140             }
 141             s->regs[addr] = value;
 142             break;
 143
 144         case R_TX:
 145             if (s->chr)
 146                 qemu_chr_fe_write(s->chr, &ch, 1);
 147
 148             s->regs[addr] = value;
 149
 150             /* hax.  */
 151             s->regs[R_STATUS] |= STATUS_IE;
 152             break;
 153
 154         default:
 155             DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
 156             if (addr < ARRAY_SIZE(s->regs))
 157                 s->regs[addr] = value;
 158             break;
 159     }
 160     uart_update_status(s);
 161     uart_update_irq(s);
 162 }
 163
 164 static const MemoryRegionOps uart_ops = {
 165     .read = uart_read,
 166     .write = uart_write,
 167     .endianness = DEVICE_NATIVE_ENDIAN,
 168     .valid = {
 169         .min_access_size = 1,
 170         .max_access_size = 4
 171     }
 172 };
 173
 174 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 175 {
 176     XilinxUARTLite *s = opaque;
 177
 178     /* Got a byte.  */
 179     if (s->rx_fifo_len >= 8) {
 180         printf("WARNING: UART dropped char.\n");
 181         return;
 182     }
 183     s->rx_fifo[s->rx_fifo_pos] = *buf;
 184     s->rx_fifo_pos++;
 185     s->rx_fifo_pos &= 0x7;
 186     s->rx_fifo_len++;
 187
 188     uart_update_status(s);
 189     uart_update_irq(s);
 190 }
 191
 192 static int uart_can_rx(void *opaque)
 193 {
 194     XilinxUARTLite *s = opaque;
 195
 196     return s->rx_fifo_len < sizeof(s->rx_fifo);
 197 }
 198
 199 static void uart_event(void *opaque, int event)
 200 {
 201
 202 }
 203
 204 static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
 205 {
 206     XilinxUARTLite *s = XILINX_UARTLITE(dev);
 207
 208     s->chr = qemu_char_get_next_serial();
 209     if (s->chr)
 210         qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
 211 }
 212
 213 static void xilinx_uartlite_init(Object *obj)
 214 {
 215     XilinxUARTLite *s = XILINX_UARTLITE(obj);
 216
 217     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 218
 219     memory_region_init_io(&s->mmio, obj, &uart_ops, s,
 220                           "xlnx.xps-uartlite", R_MAX * 4);
 221     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 222 }
 223
 224 static void xilinx_uartlite_class_init(ObjectClass *klass, void *data)
 225 {
 226     DeviceClass *dc = DEVICE_CLASS(klass);
 227
 228     dc->reset = xilinx_uartlite_reset;
 229     dc->realize = xilinx_uartlite_realize;
 230 }
 231
 232 static const TypeInfo xilinx_uartlite_info = {
 233     .name          = TYPE_XILINX_UARTLITE,
 234     .parent        = TYPE_SYS_BUS_DEVICE,
 235     .instance_size = sizeof(XilinxUARTLite),
 236     .instance_init = xilinx_uartlite_init,
 237     .class_init    = xilinx_uartlite_class_init,
 238 };
 239
 240 static void xilinx_uart_register_types(void)
 241 {
 242     type_register_static(&xilinx_uartlite_info);
 243 }
 244
 245 type_init(xilinx_uart_register_types)