target-cris/cpu.h

   1 /*
   2  *  CRIS virtual CPU header
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #ifndef CPU_CRIS_H
  21 #define CPU_CRIS_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define CPUState struct CPUCRISState
  26
  27 #include "cpu-defs.h"
  28
  29 #define TARGET_HAS_ICE 1
  30
  31 #define ELF_MACHINE     EM_CRIS
  32
  33 #define EXCP_NMI        1
  34 #define EXCP_GURU       2
  35 #define EXCP_BUSFAULT   3
  36 #define EXCP_IRQ        4
  37 #define EXCP_BREAK      5
  38
  39 /* Register aliases. R0 - R15 */
  40 #define R_FP  8
  41 #define R_SP  14
  42 #define R_ACR 15
  43
  44 /* Support regs, P0 - P15  */
  45 #define PR_BZ  0
  46 #define PR_VR  1
  47 #define PR_PID 2
  48 #define PR_SRS 3
  49 #define PR_WZ  4
  50 #define PR_EXS 5
  51 #define PR_EDA 6
  52 #define PR_PREFIX 6    /* On CRISv10 P6 is reserved, we use it as prefix.  */
  53 #define PR_MOF 7
  54 #define PR_DZ  8
  55 #define PR_EBP 9
  56 #define PR_ERP 10
  57 #define PR_SRP 11
  58 #define PR_NRP 12
  59 #define PR_CCS 13
  60 #define PR_USP 14
  61 #define PR_SPC 15
  62
  63 /* CPU flags.  */
  64 #define Q_FLAG 0x80000000
  65 #define M_FLAG 0x40000000
  66 #define PFIX_FLAG 0x800      /* CRISv10 Only.  */
  67 #define S_FLAG 0x200
  68 #define R_FLAG 0x100
  69 #define P_FLAG 0x80
  70 #define U_FLAG 0x40
  71 #define I_FLAG 0x20
  72 #define X_FLAG 0x10
  73 #define N_FLAG 0x08
  74 #define Z_FLAG 0x04
  75 #define V_FLAG 0x02
  76 #define C_FLAG 0x01
  77 #define ALU_FLAGS 0x1F
  78
  79 /* Condition codes.  */
  80 #define CC_CC   0
  81 #define CC_CS   1
  82 #define CC_NE   2
  83 #define CC_EQ   3
  84 #define CC_VC   4
  85 #define CC_VS   5
  86 #define CC_PL   6
  87 #define CC_MI   7
  88 #define CC_LS   8
  89 #define CC_HI   9
  90 #define CC_GE  10
  91 #define CC_LT  11
  92 #define CC_GT  12
  93 #define CC_LE  13
  94 #define CC_A   14
  95 #define CC_P   15
  96
  97 #define NB_MMU_MODES 2
  98
  99 typedef struct CPUCRISState {
 100         uint32_t regs[16];
 101         /* P0 - P15 are referred to as special registers in the docs.  */
 102         uint32_t pregs[16];
 103
 104         /* Pseudo register for the PC. Not directly accessable on CRIS.  */
 105         uint32_t pc;
 106
 107         /* Pseudo register for the kernel stack.  */
 108         uint32_t ksp;
 109
 110         /* Branch.  */
 111         int dslot;
 112         int btaken;
 113         uint32_t btarget;
 114
 115         /* Condition flag tracking.  */
 116         uint32_t cc_op;
 117         uint32_t cc_mask;
 118         uint32_t cc_dest;
 119         uint32_t cc_src;
 120         uint32_t cc_result;
 121         /* size of the operation, 1 = byte, 2 = word, 4 = dword.  */
 122         int cc_size;
 123         /* X flag at the time of cc snapshot.  */
 124         int cc_x;
 125
 126         /* CRIS has certain insns that lockout interrupts.  */
 127         int locked_irq;
 128         int interrupt_vector;
 129         int fault_vector;
 130         int trap_vector;
 131
 132         /* FIXME: add a check in the translator to avoid writing to support
 133            register sets beyond the 4th. The ISA allows up to 256! but in
 134            practice there is no core that implements more than 4.
 135
 136            Support function registers are used to control units close to the
 137            core. Accesses do not pass down the normal hierarchy.
 138         */
 139         uint32_t sregs[4][16];
 140
 141         /* Linear feedback shift reg in the mmu. Used to provide pseudo
 142            randomness for the 'hint' the mmu gives to sw for chosing valid
 143            sets on TLB refills.  */
 144         uint32_t mmu_rand_lfsr;
 145
 146         /*
 147          * We just store the stores to the tlbset here for later evaluation
 148          * when the hw needs access to them.
 149          *
 150          * One for I and another for D.
 151          */
 152         struct
 153         {
 154                 uint32_t hi;
 155                 uint32_t lo;
 156         } tlbsets[2][4][16];
 157
 158         CPU_COMMON
 159 } CPUCRISState;
 160
 161 CPUCRISState *cpu_cris_init(const char *cpu_model);
 162 int cpu_cris_exec(CPUCRISState *s);
 163 void cpu_cris_close(CPUCRISState *s);
 164 void do_interrupt(CPUCRISState *env);
 165 /* you can call this signal handler from your SIGBUS and SIGSEGV
 166    signal handlers to inform the virtual CPU of exceptions. non zero
 167    is returned if the signal was handled by the virtual CPU.  */
 168 int cpu_cris_signal_handler(int host_signum, void *pinfo,
 169                            void *puc);
 170
 171 enum {
 172     CC_OP_DYNAMIC, /* Use env->cc_op  */
 173     CC_OP_FLAGS,
 174     CC_OP_CMP,
 175     CC_OP_MOVE,
 176     CC_OP_ADD,
 177     CC_OP_ADDC,
 178     CC_OP_MCP,
 179     CC_OP_ADDU,
 180     CC_OP_SUB,
 181     CC_OP_SUBU,
 182     CC_OP_NEG,
 183     CC_OP_BTST,
 184     CC_OP_MULS,
 185     CC_OP_MULU,
 186     CC_OP_DSTEP,
 187     CC_OP_MSTEP,
 188     CC_OP_BOUND,
 189
 190     CC_OP_OR,
 191     CC_OP_AND,
 192     CC_OP_XOR,
 193     CC_OP_LSL,
 194     CC_OP_LSR,
 195     CC_OP_ASR,
 196     CC_OP_LZ
 197 };
 198
 199 /* CRIS uses 8k pages.  */
 200 #define TARGET_PAGE_BITS 13
 201 #define MMAP_SHIFT TARGET_PAGE_BITS
 202
 203 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 204 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 205
 206 #define cpu_init cpu_cris_init
 207 #define cpu_exec cpu_cris_exec
 208 #define cpu_gen_code cpu_cris_gen_code
 209 #define cpu_signal_handler cpu_cris_signal_handler
 210
 211 #define CPU_SAVE_VERSION 1
 212
 213 /* MMU modes definitions */
 214 #define MMU_MODE0_SUFFIX _kernel
 215 #define MMU_MODE1_SUFFIX _user
 216 #define MMU_USER_IDX 1
 217 static inline int cpu_mmu_index (CPUState *env)
 218 {
 219         return !!(env->pregs[PR_CCS] & U_FLAG);
 220 }
 221
 222 int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
 223                               int mmu_idx, int is_softmmu);
 224 #define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
 225
 226 #if defined(CONFIG_USER_ONLY)
 227 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 228 {
 229     if (newsp)
 230         env->regs[14] = newsp;
 231     env->regs[10] = 0;
 232 }
 233 #endif
 234
 235 static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
 236 {
 237         env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
 238 }
 239
 240 /* Support function regs.  */
 241 #define SFR_RW_GC_CFG      0][0
 242 #define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
 243 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
 244 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
 245 #define SFR_R_MM_CAUSE     env->pregs[PR_SRS]][3
 246 #define SFR_RW_MM_TLB_SEL  env->pregs[PR_SRS]][4
 247 #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 248 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 249
 250 #include "cpu-all.h"
 251 #include "exec-all.h"
 252
 253 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 254 {
 255     env->pc = tb->pc;
 256 }
 257
 258 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 259                                         target_ulong *cs_base, int *flags)
 260 {
 261     *pc = env->pc;
 262     *cs_base = 0;
 263     *flags = env->dslot |
 264             (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
 265                                      | X_FLAG | PFIX_FLAG));
 266 }
 267
 268 #define cpu_list cris_cpu_list
 269 void cris_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 270
 271 #endif