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[qemu.git] / hw / mips / cps.c
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1 /*
2 * Coherent Processing System emulation.
4 * Copyright (c) 2016 Imagination Technologies
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "hw/mips/cps.h"
23 #include "hw/mips/mips.h"
24 #include "hw/mips/cpudevs.h"
25 #include "sysemu/kvm.h"
27 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
29 MIPSCPU *cpu = MIPS_CPU(first_cpu);
30 CPUMIPSState *env = &cpu->env;
32 assert(pin_number < s->num_irq);
34 /* TODO: return GIC pins once implemented */
35 return env->irq[pin_number];
38 static void mips_cps_init(Object *obj)
40 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
41 MIPSCPSState *s = MIPS_CPS(obj);
43 /* Cover entire address space as there do not seem to be any
44 * constraints for the base address of CPC and GIC. */
45 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
46 sysbus_init_mmio(sbd, &s->container);
49 static void main_cpu_reset(void *opaque)
51 MIPSCPU *cpu = opaque;
52 CPUState *cs = CPU(cpu);
54 cpu_reset(cs);
56 /* All VPs are halted on reset. Leave powering up to CPC. */
57 cs->halted = 1;
60 static bool cpu_mips_itu_supported(CPUMIPSState *env)
62 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) ||
63 (env->CP0_Config3 & (1 << CP0C3_MT));
65 return is_mt && !kvm_enabled();
68 static void mips_cps_realize(DeviceState *dev, Error **errp)
70 MIPSCPSState *s = MIPS_CPS(dev);
71 CPUMIPSState *env;
72 MIPSCPU *cpu;
73 int i;
74 Error *err = NULL;
75 target_ulong gcr_base;
76 bool itu_present = false;
78 for (i = 0; i < s->num_vp; i++) {
79 cpu = cpu_mips_init(s->cpu_model);
80 if (cpu == NULL) {
81 error_setg(errp, "%s: CPU initialization failed\n", __func__);
82 return;
84 env = &cpu->env;
86 /* Init internal devices */
87 cpu_mips_irq_init_cpu(env);
88 cpu_mips_clock_init(env);
89 if (cpu_mips_itu_supported(env)) {
90 itu_present = true;
91 /* Attach ITC Tag to the VP */
92 env->itc_tag = mips_itu_get_tag_region(&s->itu);
94 qemu_register_reset(main_cpu_reset, cpu);
97 cpu = MIPS_CPU(first_cpu);
98 env = &cpu->env;
100 /* Inter-Thread Communication Unit */
101 if (itu_present) {
102 object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU);
103 qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default());
105 object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
106 object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
107 object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
108 if (err != NULL) {
109 error_propagate(errp, err);
110 return;
113 memory_region_add_subregion(&s->container, 0,
114 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
117 /* Cluster Power Controller */
118 object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
119 qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
121 object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err);
122 object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err);
123 object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err);
124 if (err != NULL) {
125 error_propagate(errp, err);
126 return;
129 memory_region_add_subregion(&s->container, 0,
130 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
132 /* Global Configuration Registers */
133 gcr_base = env->CP0_CMGCRBase << 4;
135 object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR);
136 qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default());
138 object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
139 object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
140 object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
141 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err);
142 object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);
143 if (err != NULL) {
144 error_propagate(errp, err);
145 return;
148 memory_region_add_subregion(&s->container, gcr_base,
149 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
152 static Property mips_cps_properties[] = {
153 DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
154 DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 8),
155 DEFINE_PROP_STRING("cpu-model", MIPSCPSState, cpu_model),
156 DEFINE_PROP_END_OF_LIST()
159 static void mips_cps_class_init(ObjectClass *klass, void *data)
161 DeviceClass *dc = DEVICE_CLASS(klass);
163 dc->realize = mips_cps_realize;
164 dc->props = mips_cps_properties;
167 static const TypeInfo mips_cps_info = {
168 .name = TYPE_MIPS_CPS,
169 .parent = TYPE_SYS_BUS_DEVICE,
170 .instance_size = sizeof(MIPSCPSState),
171 .instance_init = mips_cps_init,
172 .class_init = mips_cps_class_init,
175 static void mips_cps_register_types(void)
177 type_register_static(&mips_cps_info);
180 type_init(mips_cps_register_types)