| blob | 0574bb8bab7bb6dda264e0025781340e36211782 |
1 /*
2 * translate/vmx-impl.c
3 *
4 * Altivec/VMX translation
5 */
7 /*** Altivec vector extension ***/
8 /* Altivec registers moves */
10 static inline TCGv_ptr gen_avr_ptr(int reg)
11 {
12 TCGv_ptr r = tcg_temp_new_ptr();
13 tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
14 return r;
15 }
17 #define GEN_VR_LDX(name, opc2, opc3) \
18 static void glue(gen_, name)(DisasContext *ctx) \
19 { \
20 TCGv EA; \
21 TCGv_i64 avr; \
22 if (unlikely(!ctx->altivec_enabled)) { \
23 gen_exception(ctx, POWERPC_EXCP_VPU); \
24 return; \
25 } \
26 gen_set_access_type(ctx, ACCESS_INT); \
27 avr = tcg_temp_new_i64(); \
28 EA = tcg_temp_new(); \
29 gen_addr_reg_index(ctx, EA); \
30 tcg_gen_andi_tl(EA, EA, ~0xf); \
31 /* \
32 * We only need to swap high and low halves. gen_qemu_ld64_i64 \
33 * does necessary 64-bit byteswap already. \
34 */ \
35 if (ctx->le_mode) { \
36 gen_qemu_ld64_i64(ctx, avr, EA); \
37 set_avr64(rD(ctx->opcode), avr, false); \
38 tcg_gen_addi_tl(EA, EA, 8); \
39 gen_qemu_ld64_i64(ctx, avr, EA); \
40 set_avr64(rD(ctx->opcode), avr, true); \
41 } else { \
42 gen_qemu_ld64_i64(ctx, avr, EA); \
43 set_avr64(rD(ctx->opcode), avr, true); \
44 tcg_gen_addi_tl(EA, EA, 8); \
45 gen_qemu_ld64_i64(ctx, avr, EA); \
46 set_avr64(rD(ctx->opcode), avr, false); \
47 } \
48 tcg_temp_free(EA); \
49 tcg_temp_free_i64(avr); \
50 }
52 #define GEN_VR_STX(name, opc2, opc3) \
53 static void gen_st##name(DisasContext *ctx) \
54 { \
55 TCGv EA; \
56 TCGv_i64 avr; \
57 if (unlikely(!ctx->altivec_enabled)) { \
58 gen_exception(ctx, POWERPC_EXCP_VPU); \
59 return; \
60 } \
61 gen_set_access_type(ctx, ACCESS_INT); \
62 avr = tcg_temp_new_i64(); \
63 EA = tcg_temp_new(); \
64 gen_addr_reg_index(ctx, EA); \
65 tcg_gen_andi_tl(EA, EA, ~0xf); \
66 /* \
67 * We only need to swap high and low halves. gen_qemu_st64_i64 \
68 * does necessary 64-bit byteswap already. \
69 */ \
70 if (ctx->le_mode) { \
71 get_avr64(avr, rD(ctx->opcode), false); \
72 gen_qemu_st64_i64(ctx, avr, EA); \
73 tcg_gen_addi_tl(EA, EA, 8); \
74 get_avr64(avr, rD(ctx->opcode), true); \
75 gen_qemu_st64_i64(ctx, avr, EA); \
76 } else { \
77 get_avr64(avr, rD(ctx->opcode), true); \
78 gen_qemu_st64_i64(ctx, avr, EA); \
79 tcg_gen_addi_tl(EA, EA, 8); \
80 get_avr64(avr, rD(ctx->opcode), false); \
81 gen_qemu_st64_i64(ctx, avr, EA); \
82 } \
83 tcg_temp_free(EA); \
84 tcg_temp_free_i64(avr); \
85 }
87 #define GEN_VR_LVE(name, opc2, opc3, size) \
88 static void gen_lve##name(DisasContext *ctx) \
89 { \
90 TCGv EA; \
91 TCGv_ptr rs; \
92 if (unlikely(!ctx->altivec_enabled)) { \
93 gen_exception(ctx, POWERPC_EXCP_VPU); \
94 return; \
95 } \
96 gen_set_access_type(ctx, ACCESS_INT); \
97 EA = tcg_temp_new(); \
98 gen_addr_reg_index(ctx, EA); \
99 if (size > 1) { \
100 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
101 } \
102 rs = gen_avr_ptr(rS(ctx->opcode)); \
103 gen_helper_lve##name(cpu_env, rs, EA); \
104 tcg_temp_free(EA); \
105 tcg_temp_free_ptr(rs); \
106 }
108 #define GEN_VR_STVE(name, opc2, opc3, size) \
109 static void gen_stve##name(DisasContext *ctx) \
110 { \
111 TCGv EA; \
112 TCGv_ptr rs; \
113 if (unlikely(!ctx->altivec_enabled)) { \
114 gen_exception(ctx, POWERPC_EXCP_VPU); \
115 return; \
116 } \
117 gen_set_access_type(ctx, ACCESS_INT); \
118 EA = tcg_temp_new(); \
119 gen_addr_reg_index(ctx, EA); \
120 if (size > 1) { \
121 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
122 } \
123 rs = gen_avr_ptr(rS(ctx->opcode)); \
124 gen_helper_stve##name(cpu_env, rs, EA); \
125 tcg_temp_free(EA); \
126 tcg_temp_free_ptr(rs); \
127 }
129 GEN_VR_LDX(lvx, 0x07, 0x03);
130 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
131 GEN_VR_LDX(lvxl, 0x07, 0x0B);
133 GEN_VR_LVE(bx, 0x07, 0x00, 1);
134 GEN_VR_LVE(hx, 0x07, 0x01, 2);
135 GEN_VR_LVE(wx, 0x07, 0x02, 4);
137 GEN_VR_STX(svx, 0x07, 0x07);
138 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
139 GEN_VR_STX(svxl, 0x07, 0x0F);
141 GEN_VR_STVE(bx, 0x07, 0x04, 1);
142 GEN_VR_STVE(hx, 0x07, 0x05, 2);
143 GEN_VR_STVE(wx, 0x07, 0x06, 4);
145 static void gen_mfvscr(DisasContext *ctx)
146 {
147 TCGv_i32 t;
148 TCGv_i64 avr;
149 if (unlikely(!ctx->altivec_enabled)) {
150 gen_exception(ctx, POWERPC_EXCP_VPU);
151 return;
152 }
153 avr = tcg_temp_new_i64();
154 tcg_gen_movi_i64(avr, 0);
155 set_avr64(rD(ctx->opcode), avr, true);
156 t = tcg_temp_new_i32();
157 gen_helper_mfvscr(t, cpu_env);
158 tcg_gen_extu_i32_i64(avr, t);
159 set_avr64(rD(ctx->opcode), avr, false);
160 tcg_temp_free_i32(t);
161 tcg_temp_free_i64(avr);
162 }
164 static void gen_mtvscr(DisasContext *ctx)
165 {
166 TCGv_i32 val;
167 int bofs;
169 if (unlikely(!ctx->altivec_enabled)) {
170 gen_exception(ctx, POWERPC_EXCP_VPU);
171 return;
172 }
174 val = tcg_temp_new_i32();
175 bofs = avr_full_offset(rB(ctx->opcode));
176 #ifdef HOST_WORDS_BIGENDIAN
177 bofs += 3 * 4;
178 #endif
180 tcg_gen_ld_i32(val, cpu_env, bofs);
181 gen_helper_mtvscr(cpu_env, val);
182 tcg_temp_free_i32(val);
183 }
185 #define GEN_VX_VMUL10(name, add_cin, ret_carry) \
186 static void glue(gen_, name)(DisasContext *ctx) \
187 { \
188 TCGv_i64 t0; \
189 TCGv_i64 t1; \
190 TCGv_i64 t2; \
191 TCGv_i64 avr; \
192 TCGv_i64 ten, z; \
193 \
194 if (unlikely(!ctx->altivec_enabled)) { \
195 gen_exception(ctx, POWERPC_EXCP_VPU); \
196 return; \
197 } \
198 \
199 t0 = tcg_temp_new_i64(); \
200 t1 = tcg_temp_new_i64(); \
201 t2 = tcg_temp_new_i64(); \
202 avr = tcg_temp_new_i64(); \
203 ten = tcg_const_i64(10); \
204 z = tcg_const_i64(0); \
205 \
206 if (add_cin) { \
207 get_avr64(avr, rA(ctx->opcode), false); \
208 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
209 get_avr64(avr, rB(ctx->opcode), false); \
210 tcg_gen_andi_i64(t2, avr, 0xF); \
211 tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
212 set_avr64(rD(ctx->opcode), avr, false); \
213 } else { \
214 get_avr64(avr, rA(ctx->opcode), false); \
215 tcg_gen_mulu2_i64(avr, t2, avr, ten); \
216 set_avr64(rD(ctx->opcode), avr, false); \
217 } \
218 \
219 if (ret_carry) { \
220 get_avr64(avr, rA(ctx->opcode), true); \
221 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
222 tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
223 set_avr64(rD(ctx->opcode), avr, false); \
224 set_avr64(rD(ctx->opcode), z, true); \
225 } else { \
226 get_avr64(avr, rA(ctx->opcode), true); \
227 tcg_gen_mul_i64(t0, avr, ten); \
228 tcg_gen_add_i64(avr, t0, t2); \
229 set_avr64(rD(ctx->opcode), avr, true); \
230 } \
231 \
232 tcg_temp_free_i64(t0); \
233 tcg_temp_free_i64(t1); \
234 tcg_temp_free_i64(t2); \
235 tcg_temp_free_i64(avr); \
236 tcg_temp_free_i64(ten); \
237 tcg_temp_free_i64(z); \
238 } \
240 GEN_VX_VMUL10(vmul10uq, 0, 0);
241 GEN_VX_VMUL10(vmul10euq, 1, 0);
242 GEN_VX_VMUL10(vmul10cuq, 0, 1);
243 GEN_VX_VMUL10(vmul10ecuq, 1, 1);
245 #define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
246 static void glue(gen_, name)(DisasContext *ctx) \
247 { \
248 if (unlikely(!ctx->altivec_enabled)) { \
249 gen_exception(ctx, POWERPC_EXCP_VPU); \
250 return; \
251 } \
252 \
253 tcg_op(vece, \
254 avr_full_offset(rD(ctx->opcode)), \
255 avr_full_offset(rA(ctx->opcode)), \
256 avr_full_offset(rB(ctx->opcode)), \
257 16, 16); \
258 }
260 /* Logical operations */
261 GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
262 GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
263 GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
264 GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
265 GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
266 GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
267 GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
268 GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
270 #define GEN_VXFORM(name, opc2, opc3) \
271 static void glue(gen_, name)(DisasContext *ctx) \
272 { \
273 TCGv_ptr ra, rb, rd; \
274 if (unlikely(!ctx->altivec_enabled)) { \
275 gen_exception(ctx, POWERPC_EXCP_VPU); \
276 return; \
277 } \
278 ra = gen_avr_ptr(rA(ctx->opcode)); \
279 rb = gen_avr_ptr(rB(ctx->opcode)); \
280 rd = gen_avr_ptr(rD(ctx->opcode)); \
281 gen_helper_##name(rd, ra, rb); \
282 tcg_temp_free_ptr(ra); \
283 tcg_temp_free_ptr(rb); \
284 tcg_temp_free_ptr(rd); \
285 }
287 #define GEN_VXFORM_TRANS(name, opc2, opc3) \
288 static void glue(gen_, name)(DisasContext *ctx) \
289 { \
290 if (unlikely(!ctx->altivec_enabled)) { \
291 gen_exception(ctx, POWERPC_EXCP_VPU); \
292 return; \
293 } \
294 trans_##name(ctx); \
295 }
297 #define GEN_VXFORM_ENV(name, opc2, opc3) \
298 static void glue(gen_, name)(DisasContext *ctx) \
299 { \
300 TCGv_ptr ra, rb, rd; \
301 if (unlikely(!ctx->altivec_enabled)) { \
302 gen_exception(ctx, POWERPC_EXCP_VPU); \
303 return; \
304 } \
305 ra = gen_avr_ptr(rA(ctx->opcode)); \
306 rb = gen_avr_ptr(rB(ctx->opcode)); \
307 rd = gen_avr_ptr(rD(ctx->opcode)); \
308 gen_helper_##name(cpu_env, rd, ra, rb); \
309 tcg_temp_free_ptr(ra); \
310 tcg_temp_free_ptr(rb); \
311 tcg_temp_free_ptr(rd); \
312 }
314 #define GEN_VXFORM3(name, opc2, opc3) \
315 static void glue(gen_, name)(DisasContext *ctx) \
316 { \
317 TCGv_ptr ra, rb, rc, rd; \
318 if (unlikely(!ctx->altivec_enabled)) { \
319 gen_exception(ctx, POWERPC_EXCP_VPU); \
320 return; \
321 } \
322 ra = gen_avr_ptr(rA(ctx->opcode)); \
323 rb = gen_avr_ptr(rB(ctx->opcode)); \
324 rc = gen_avr_ptr(rC(ctx->opcode)); \
325 rd = gen_avr_ptr(rD(ctx->opcode)); \
326 gen_helper_##name(rd, ra, rb, rc); \
327 tcg_temp_free_ptr(ra); \
328 tcg_temp_free_ptr(rb); \
329 tcg_temp_free_ptr(rc); \
330 tcg_temp_free_ptr(rd); \
331 }
333 /*
334 * Support for Altivec instruction pairs that use bit 31 (Rc) as
335 * an opcode bit. In general, these pairs come from different
336 * versions of the ISA, so we must also support a pair of flags for
337 * each instruction.
338 */
339 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
340 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
341 { \
342 if ((Rc(ctx->opcode) == 0) && \
343 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
344 gen_##name0(ctx); \
345 } else if ((Rc(ctx->opcode) == 1) && \
346 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
347 gen_##name1(ctx); \
348 } else { \
349 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
350 } \
351 }
353 /*
354 * We use this macro if one instruction is realized with direct
355 * translation, and second one with helper.
356 */
357 #define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
358 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
359 { \
360 if ((Rc(ctx->opcode) == 0) && \
361 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
362 if (unlikely(!ctx->altivec_enabled)) { \
363 gen_exception(ctx, POWERPC_EXCP_VPU); \
364 return; \
365 } \
366 trans_##name0(ctx); \
367 } else if ((Rc(ctx->opcode) == 1) && \
368 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
369 gen_##name1(ctx); \
370 } else { \
371 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
372 } \
373 }
375 /* Adds support to provide invalid mask */
376 #define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
377 name1, flg1, flg2_1, inval1) \
378 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
379 { \
380 if ((Rc(ctx->opcode) == 0) && \
381 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
382 !(ctx->opcode & inval0)) { \
383 gen_##name0(ctx); \
384 } else if ((Rc(ctx->opcode) == 1) && \
385 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
386 !(ctx->opcode & inval1)) { \
387 gen_##name1(ctx); \
388 } else { \
389 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
390 } \
391 }
393 #define GEN_VXFORM_HETRO(name, opc2, opc3) \
394 static void glue(gen_, name)(DisasContext *ctx) \
395 { \
396 TCGv_ptr rb; \
397 if (unlikely(!ctx->altivec_enabled)) { \
398 gen_exception(ctx, POWERPC_EXCP_VPU); \
399 return; \
400 } \
401 rb = gen_avr_ptr(rB(ctx->opcode)); \
402 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
403 tcg_temp_free_ptr(rb); \
404 }
406 GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
407 GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
408 vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
409 GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
410 GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
411 vmul10ecuq, PPC_NONE, PPC2_ISA300)
412 GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
413 GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
414 GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
415 GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
416 GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
417 GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
418 GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
419 GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
420 GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
421 GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
422 GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
423 GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
424 GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
425 GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
426 GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
427 GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
428 GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
429 GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
430 GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
431 GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
432 GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
433 GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
434 GEN_VXFORM(vavgub, 1, 16);
435 GEN_VXFORM(vabsdub, 1, 16);
436 GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
437 vabsdub, PPC_NONE, PPC2_ISA300)
438 GEN_VXFORM(vavguh, 1, 17);
439 GEN_VXFORM(vabsduh, 1, 17);
440 GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
441 vabsduh, PPC_NONE, PPC2_ISA300)
442 GEN_VXFORM(vavguw, 1, 18);
443 GEN_VXFORM(vabsduw, 1, 18);
444 GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
445 vabsduw, PPC_NONE, PPC2_ISA300)
446 GEN_VXFORM(vavgsb, 1, 20);
447 GEN_VXFORM(vavgsh, 1, 21);
448 GEN_VXFORM(vavgsw, 1, 22);
449 GEN_VXFORM(vmrghb, 6, 0);
450 GEN_VXFORM(vmrghh, 6, 1);
451 GEN_VXFORM(vmrghw, 6, 2);
452 GEN_VXFORM(vmrglb, 6, 4);
453 GEN_VXFORM(vmrglh, 6, 5);
454 GEN_VXFORM(vmrglw, 6, 6);
456 static void trans_vmrgew(DisasContext *ctx)
457 {
458 int VT = rD(ctx->opcode);
459 int VA = rA(ctx->opcode);
460 int VB = rB(ctx->opcode);
461 TCGv_i64 tmp = tcg_temp_new_i64();
462 TCGv_i64 avr = tcg_temp_new_i64();
464 get_avr64(avr, VB, true);
465 tcg_gen_shri_i64(tmp, avr, 32);
466 get_avr64(avr, VA, true);
467 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
468 set_avr64(VT, avr, true);
470 get_avr64(avr, VB, false);
471 tcg_gen_shri_i64(tmp, avr, 32);
472 get_avr64(avr, VA, false);
473 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
474 set_avr64(VT, avr, false);
476 tcg_temp_free_i64(tmp);
477 tcg_temp_free_i64(avr);
478 }
480 static void trans_vmrgow(DisasContext *ctx)
481 {
482 int VT = rD(ctx->opcode);
483 int VA = rA(ctx->opcode);
484 int VB = rB(ctx->opcode);
485 TCGv_i64 t0 = tcg_temp_new_i64();
486 TCGv_i64 t1 = tcg_temp_new_i64();
487 TCGv_i64 avr = tcg_temp_new_i64();
489 get_avr64(t0, VB, true);
490 get_avr64(t1, VA, true);
491 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
492 set_avr64(VT, avr, true);
494 get_avr64(t0, VB, false);
495 get_avr64(t1, VA, false);
496 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
497 set_avr64(VT, avr, false);
499 tcg_temp_free_i64(t0);
500 tcg_temp_free_i64(t1);
501 tcg_temp_free_i64(avr);
502 }
504 /*
505 * lvsl VRT,RA,RB - Load Vector for Shift Left
506 *
507 * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
508 * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
509 * Bytes sh:sh+15 of X are placed into vD.
510 */
511 static void trans_lvsl(DisasContext *ctx)
512 {
513 int VT = rD(ctx->opcode);
514 TCGv_i64 result = tcg_temp_new_i64();
515 TCGv_i64 sh = tcg_temp_new_i64();
516 TCGv EA = tcg_temp_new();
518 /* Get sh(from description) by anding EA with 0xf. */
519 gen_addr_reg_index(ctx, EA);
520 tcg_gen_extu_tl_i64(sh, EA);
521 tcg_gen_andi_i64(sh, sh, 0xfULL);
523 /*
524 * Create bytes sh:sh+7 of X(from description) and place them in
525 * higher doubleword of vD.
526 */
527 tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
528 tcg_gen_addi_i64(result, sh, 0x0001020304050607ull);
529 set_avr64(VT, result, true);
530 /*
531 * Create bytes sh+8:sh+15 of X(from description) and place them in
532 * lower doubleword of vD.
533 */
534 tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL);
535 set_avr64(VT, result, false);
537 tcg_temp_free_i64(result);
538 tcg_temp_free_i64(sh);
539 tcg_temp_free(EA);
540 }
542 /*
543 * lvsr VRT,RA,RB - Load Vector for Shift Right
544 *
545 * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
546 * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
547 * Bytes (16-sh):(31-sh) of X are placed into vD.
548 */
549 static void trans_lvsr(DisasContext *ctx)
550 {
551 int VT = rD(ctx->opcode);
552 TCGv_i64 result = tcg_temp_new_i64();
553 TCGv_i64 sh = tcg_temp_new_i64();
554 TCGv EA = tcg_temp_new();
557 /* Get sh(from description) by anding EA with 0xf. */
558 gen_addr_reg_index(ctx, EA);
559 tcg_gen_extu_tl_i64(sh, EA);
560 tcg_gen_andi_i64(sh, sh, 0xfULL);
562 /*
563 * Create bytes (16-sh):(23-sh) of X(from description) and place them in
564 * higher doubleword of vD.
565 */
566 tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
567 tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh);
568 set_avr64(VT, result, true);
569 /*
570 * Create bytes (24-sh):(32-sh) of X(from description) and place them in
571 * lower doubleword of vD.
572 */
573 tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh);
574 set_avr64(VT, result, false);
576 tcg_temp_free_i64(result);
577 tcg_temp_free_i64(sh);
578 tcg_temp_free(EA);
579 }
581 /*
582 * vsl VRT,VRA,VRB - Vector Shift Left
583 *
584 * Shifting left 128 bit value of vA by value specified in bits 125-127 of vB.
585 * Lowest 3 bits in each byte element of register vB must be identical or
586 * result is undefined.
587 */
588 static void trans_vsl(DisasContext *ctx)
589 {
590 int VT = rD(ctx->opcode);
591 int VA = rA(ctx->opcode);
592 int VB = rB(ctx->opcode);
593 TCGv_i64 avr = tcg_temp_new_i64();
594 TCGv_i64 sh = tcg_temp_new_i64();
595 TCGv_i64 carry = tcg_temp_new_i64();
596 TCGv_i64 tmp = tcg_temp_new_i64();
598 /* Place bits 125-127 of vB in 'sh'. */
599 get_avr64(avr, VB, false);
600 tcg_gen_andi_i64(sh, avr, 0x07ULL);
602 /*
603 * Save highest 'sh' bits of lower doubleword element of vA in variable
604 * 'carry' and perform shift on lower doubleword.
605 */
606 get_avr64(avr, VA, false);
607 tcg_gen_subfi_i64(tmp, 32, sh);
608 tcg_gen_shri_i64(carry, avr, 32);
609 tcg_gen_shr_i64(carry, carry, tmp);
610 tcg_gen_shl_i64(avr, avr, sh);
611 set_avr64(VT, avr, false);
613 /*
614 * Perform shift on higher doubleword element of vA and replace lowest
615 * 'sh' bits with 'carry'.
616 */
617 get_avr64(avr, VA, true);
618 tcg_gen_shl_i64(avr, avr, sh);
619 tcg_gen_or_i64(avr, avr, carry);
620 set_avr64(VT, avr, true);
622 tcg_temp_free_i64(avr);
623 tcg_temp_free_i64(sh);
624 tcg_temp_free_i64(carry);
625 tcg_temp_free_i64(tmp);
626 }
628 /*
629 * vsr VRT,VRA,VRB - Vector Shift Right
630 *
631 * Shifting right 128 bit value of vA by value specified in bits 125-127 of vB.
632 * Lowest 3 bits in each byte element of register vB must be identical or
633 * result is undefined.
634 */
635 static void trans_vsr(DisasContext *ctx)
636 {
637 int VT = rD(ctx->opcode);
638 int VA = rA(ctx->opcode);
639 int VB = rB(ctx->opcode);
640 TCGv_i64 avr = tcg_temp_new_i64();
641 TCGv_i64 sh = tcg_temp_new_i64();
642 TCGv_i64 carry = tcg_temp_new_i64();
643 TCGv_i64 tmp = tcg_temp_new_i64();
645 /* Place bits 125-127 of vB in 'sh'. */
646 get_avr64(avr, VB, false);
647 tcg_gen_andi_i64(sh, avr, 0x07ULL);
649 /*
650 * Save lowest 'sh' bits of higher doubleword element of vA in variable
651 * 'carry' and perform shift on higher doubleword.
652 */
653 get_avr64(avr, VA, true);
654 tcg_gen_subfi_i64(tmp, 32, sh);
655 tcg_gen_shli_i64(carry, avr, 32);
656 tcg_gen_shl_i64(carry, carry, tmp);
657 tcg_gen_shr_i64(avr, avr, sh);
658 set_avr64(VT, avr, true);
659 /*
660 * Perform shift on lower doubleword element of vA and replace highest
661 * 'sh' bits with 'carry'.
662 */
663 get_avr64(avr, VA, false);
664 tcg_gen_shr_i64(avr, avr, sh);
665 tcg_gen_or_i64(avr, avr, carry);
666 set_avr64(VT, avr, false);
668 tcg_temp_free_i64(avr);
669 tcg_temp_free_i64(sh);
670 tcg_temp_free_i64(carry);
671 tcg_temp_free_i64(tmp);
672 }
674 /*
675 * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword
676 *
677 * All ith bits (i in range 1 to 8) of each byte of doubleword element in source
678 * register are concatenated and placed into ith byte of appropriate doubleword
679 * element in destination register.
680 *
681 * Following solution is done for both doubleword elements of source register
682 * in parallel, in order to reduce the number of instructions needed(that's why
683 * arrays are used):
684 * First, both doubleword elements of source register vB are placed in
685 * appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for
686 * loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of
687 * byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with
688 * tcg_mask. For every following iteration, both avr[i] and tcg_mask variables
689 * have to be shifted right for 7 and 8 places, respectively, in order to get
690 * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so
691 * shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask...
692 * After first 8 iteration(first loop), all the first bits are in their final
693 * places, all second bits but second bit from eight byte are in their places...
694 * only 1 eight bit from eight byte is in it's place). In second loop we do all
695 * operations symmetrically, in order to get other half of bits in their final
696 * spots. Results for first and second doubleword elements are saved in
697 * result[0] and result[1] respectively. In the end those results are saved in
698 * appropriate doubleword element of destination register vD.
699 */
700 static void trans_vgbbd(DisasContext *ctx)
701 {
702 int VT = rD(ctx->opcode);
703 int VB = rB(ctx->opcode);
704 TCGv_i64 tmp = tcg_temp_new_i64();
705 uint64_t mask = 0x8040201008040201ULL;
706 int i, j;
708 TCGv_i64 result[2];
709 result[0] = tcg_temp_new_i64();
710 result[1] = tcg_temp_new_i64();
711 TCGv_i64 avr[2];
712 avr[0] = tcg_temp_new_i64();
713 avr[1] = tcg_temp_new_i64();
714 TCGv_i64 tcg_mask = tcg_temp_new_i64();
716 tcg_gen_movi_i64(tcg_mask, mask);
717 for (j = 0; j < 2; j++) {
718 get_avr64(avr[j], VB, j);
719 tcg_gen_and_i64(result[j], avr[j], tcg_mask);
720 }
721 for (i = 1; i < 8; i++) {
722 tcg_gen_movi_i64(tcg_mask, mask >> (i * 8));
723 for (j = 0; j < 2; j++) {
724 tcg_gen_shri_i64(tmp, avr[j], i * 7);
725 tcg_gen_and_i64(tmp, tmp, tcg_mask);
726 tcg_gen_or_i64(result[j], result[j], tmp);
727 }
728 }
729 for (i = 1; i < 8; i++) {
730 tcg_gen_movi_i64(tcg_mask, mask << (i * 8));
731 for (j = 0; j < 2; j++) {
732 tcg_gen_shli_i64(tmp, avr[j], i * 7);
733 tcg_gen_and_i64(tmp, tmp, tcg_mask);
734 tcg_gen_or_i64(result[j], result[j], tmp);
735 }
736 }
737 for (j = 0; j < 2; j++) {
738 set_avr64(VT, result[j], j);
739 }
741 tcg_temp_free_i64(tmp);
742 tcg_temp_free_i64(tcg_mask);
743 tcg_temp_free_i64(result[0]);
744 tcg_temp_free_i64(result[1]);
745 tcg_temp_free_i64(avr[0]);
746 tcg_temp_free_i64(avr[1]);
747 }
749 /*
750 * vclzw VRT,VRB - Vector Count Leading Zeros Word
751 *
752 * Counting the number of leading zero bits of each word element in source
753 * register and placing result in appropriate word element of destination
754 * register.
755 */
756 static void trans_vclzw(DisasContext *ctx)
757 {
758 int VT = rD(ctx->opcode);
759 int VB = rB(ctx->opcode);
760 TCGv_i32 tmp = tcg_temp_new_i32();
761 int i;
763 /* Perform count for every word element using tcg_gen_clzi_i32. */
764 for (i = 0; i < 4; i++) {
765 tcg_gen_ld_i32(tmp, cpu_env,
766 offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
767 tcg_gen_clzi_i32(tmp, tmp, 32);
768 tcg_gen_st_i32(tmp, cpu_env,
769 offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
770 }
772 tcg_temp_free_i32(tmp);
773 }
775 /*
776 * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword
777 *
778 * Counting the number of leading zero bits of each doubleword element in source
779 * register and placing result in appropriate doubleword element of destination
780 * register.
781 */
782 static void trans_vclzd(DisasContext *ctx)
783 {
784 int VT = rD(ctx->opcode);
785 int VB = rB(ctx->opcode);
786 TCGv_i64 avr = tcg_temp_new_i64();
788 /* high doubleword */
789 get_avr64(avr, VB, true);
790 tcg_gen_clzi_i64(avr, avr, 64);
791 set_avr64(VT, avr, true);
793 /* low doubleword */
794 get_avr64(avr, VB, false);
795 tcg_gen_clzi_i64(avr, avr, 64);
796 set_avr64(VT, avr, false);
798 tcg_temp_free_i64(avr);
799 }
801 GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
802 GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
803 GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
804 GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
805 GEN_VXFORM(vrlwnm, 2, 6);
806 GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
807 vrlwnm, PPC_NONE, PPC2_ISA300)
808 GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);
809 GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8);
810 GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9);
811 GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);
812 GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);
813 GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12);
814 GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13);
815 GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);
816 GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);
817 GEN_VXFORM(vsrv, 2, 28);
818 GEN_VXFORM(vslv, 2, 29);
819 GEN_VXFORM(vslo, 6, 16);
820 GEN_VXFORM(vsro, 6, 17);
821 GEN_VXFORM(vaddcuw, 0, 6);
822 GEN_VXFORM(vsubcuw, 0, 22);
824 #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
825 static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
826 TCGv_vec sat, TCGv_vec a, \
827 TCGv_vec b) \
828 { \
829 TCGv_vec x = tcg_temp_new_vec_matching(t); \
830 glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \
831 glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \
832 tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \
833 tcg_gen_or_vec(VECE, sat, sat, x); \
834 tcg_temp_free_vec(x); \
835 } \
836 static void glue(gen_, NAME)(DisasContext *ctx) \
837 { \
838 static const TCGOpcode vecop_list[] = { \
839 glue(glue(INDEX_op_, NORM), _vec), \
840 glue(glue(INDEX_op_, SAT), _vec), \
841 INDEX_op_cmp_vec, 0 \
842 }; \
843 static const GVecGen4 g = { \
844 .fniv = glue(glue(gen_, NAME), _vec), \
845 .fno = glue(gen_helper_, NAME), \
846 .opt_opc = vecop_list, \
847 .write_aofs = true, \
848 .vece = VECE, \
849 }; \
850 if (unlikely(!ctx->altivec_enabled)) { \
851 gen_exception(ctx, POWERPC_EXCP_VPU); \
852 return; \
853 } \
854 tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \
855 offsetof(CPUPPCState, vscr_sat), \
856 avr_full_offset(rA(ctx->opcode)), \
857 avr_full_offset(rB(ctx->opcode)), \
858 16, 16, &g); \
859 }
861 GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);
862 GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
863 vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
864 GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);
865 GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
866 vmul10euq, PPC_NONE, PPC2_ISA300)
867 GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);
868 GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);
869 GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);
870 GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);
871 GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);
872 GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);
873 GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
874 GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
875 GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
876 GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
877 GEN_VXFORM(vadduqm, 0, 4);
878 GEN_VXFORM(vaddcuq, 0, 5);
879 GEN_VXFORM3(vaddeuqm, 30, 0);
880 GEN_VXFORM3(vaddecuq, 30, 0);
881 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
882 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
883 GEN_VXFORM(vsubuqm, 0, 20);
884 GEN_VXFORM(vsubcuq, 0, 21);
885 GEN_VXFORM3(vsubeuqm, 31, 0);
886 GEN_VXFORM3(vsubecuq, 31, 0);
887 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
888 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
889 GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0);
890 GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1);
891 GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2);
892 GEN_VXFORM(vrlwmi, 2, 2);
893 GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
894 vrlwmi, PPC_NONE, PPC2_ISA300)
895 GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3);
896 GEN_VXFORM(vrldmi, 2, 3);
897 GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
898 vrldmi, PPC_NONE, PPC2_ISA300)
899 GEN_VXFORM_TRANS(vsl, 2, 7);
900 GEN_VXFORM(vrldnm, 2, 7);
901 GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
902 vrldnm, PPC_NONE, PPC2_ISA300)
903 GEN_VXFORM_TRANS(vsr, 2, 11);
904 GEN_VXFORM_ENV(vpkuhum, 7, 0);
905 GEN_VXFORM_ENV(vpkuwum, 7, 1);
906 GEN_VXFORM_ENV(vpkudum, 7, 17);
907 GEN_VXFORM_ENV(vpkuhus, 7, 2);
908 GEN_VXFORM_ENV(vpkuwus, 7, 3);
909 GEN_VXFORM_ENV(vpkudus, 7, 19);
910 GEN_VXFORM_ENV(vpkshus, 7, 4);
911 GEN_VXFORM_ENV(vpkswus, 7, 5);
912 GEN_VXFORM_ENV(vpksdus, 7, 21);
913 GEN_VXFORM_ENV(vpkshss, 7, 6);
914 GEN_VXFORM_ENV(vpkswss, 7, 7);
915 GEN_VXFORM_ENV(vpksdss, 7, 23);
916 GEN_VXFORM(vpkpx, 7, 12);
917 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
918 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
919 GEN_VXFORM_ENV(vsum4shs, 4, 25);
920 GEN_VXFORM_ENV(vsum2sws, 4, 26);
921 GEN_VXFORM_ENV(vsumsws, 4, 30);
922 GEN_VXFORM_ENV(vaddfp, 5, 0);
923 GEN_VXFORM_ENV(vsubfp, 5, 1);
924 GEN_VXFORM_ENV(vmaxfp, 5, 16);
925 GEN_VXFORM_ENV(vminfp, 5, 17);
926 GEN_VXFORM_HETRO(vextublx, 6, 24)
927 GEN_VXFORM_HETRO(vextuhlx, 6, 25)
928 GEN_VXFORM_HETRO(vextuwlx, 6, 26)
929 GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
930 vextuwlx, PPC_NONE, PPC2_ISA300)
931 GEN_VXFORM_HETRO(vextubrx, 6, 28)
932 GEN_VXFORM_HETRO(vextuhrx, 6, 29)
933 GEN_VXFORM_HETRO(vextuwrx, 6, 30)
934 GEN_VXFORM_TRANS(lvsl, 6, 31)
935 GEN_VXFORM_TRANS(lvsr, 6, 32)
936 GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
937 vextuwrx, PPC_NONE, PPC2_ISA300)
939 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
940 static void glue(gen_, name)(DisasContext *ctx) \
941 { \
942 TCGv_ptr ra, rb, rd; \
943 if (unlikely(!ctx->altivec_enabled)) { \
944 gen_exception(ctx, POWERPC_EXCP_VPU); \
945 return; \
946 } \
947 ra = gen_avr_ptr(rA(ctx->opcode)); \
948 rb = gen_avr_ptr(rB(ctx->opcode)); \
949 rd = gen_avr_ptr(rD(ctx->opcode)); \
950 gen_helper_##opname(cpu_env, rd, ra, rb); \
951 tcg_temp_free_ptr(ra); \
952 tcg_temp_free_ptr(rb); \
953 tcg_temp_free_ptr(rd); \
954 }
956 #define GEN_VXRFORM(name, opc2, opc3) \
957 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
958 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
960 /*
961 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
962 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
963 * come from different versions of the ISA, so we must also support a
964 * pair of flags for each instruction.
965 */
966 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
967 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
968 { \
969 if ((Rc(ctx->opcode) == 0) && \
970 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
971 if (Rc21(ctx->opcode) == 0) { \
972 gen_##name0(ctx); \
973 } else { \
974 gen_##name0##_(ctx); \
975 } \
976 } else if ((Rc(ctx->opcode) == 1) && \
977 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
978 if (Rc21(ctx->opcode) == 0) { \
979 gen_##name1(ctx); \
980 } else { \
981 gen_##name1##_(ctx); \
982 } \
983 } else { \
984 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
985 } \
986 }
988 static void do_vcmp_rc(int vrt)
989 {
990 TCGv_i64 tmp, set, clr;
992 tmp = tcg_temp_new_i64();
993 set = tcg_temp_new_i64();
994 clr = tcg_temp_new_i64();
996 get_avr64(tmp, vrt, true);
997 tcg_gen_mov_i64(set, tmp);
998 get_avr64(tmp, vrt, false);
999 tcg_gen_or_i64(clr, set, tmp);
1000 tcg_gen_and_i64(set, set, tmp);
1002 tcg_gen_setcondi_i64(TCG_COND_EQ, clr, clr, 0);
1003 tcg_gen_shli_i64(clr, clr, 1);
1005 tcg_gen_setcondi_i64(TCG_COND_EQ, set, set, -1);
1006 tcg_gen_shli_i64(set, set, 3);
1008 tcg_gen_or_i64(tmp, set, clr);
1009 tcg_gen_extrl_i64_i32(cpu_crf[6], tmp);
1011 tcg_temp_free_i64(tmp);
1012 tcg_temp_free_i64(set);
1013 tcg_temp_free_i64(clr);
1014 }
1016 static bool do_vcmp(DisasContext *ctx, arg_VC *a, TCGCond cond, int vece)
1017 {
1018 REQUIRE_VECTOR(ctx);
1020 tcg_gen_gvec_cmp(cond, vece, avr_full_offset(a->vrt),
1021 avr_full_offset(a->vra), avr_full_offset(a->vrb), 16, 16);
1023 if (a->rc) {
1024 do_vcmp_rc(a->vrt);
1025 }
1027 return true;
1028 }
1030 TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8)
1031 TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16)
1032 TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32)
1033 TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
1035 TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8)
1036 TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16)
1037 TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32)
1038 TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
1039 TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8)
1040 TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16)
1041 TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32)
1042 TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64)
1044 TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8)
1045 TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16)
1046 TRANS_FLAGS2(ISA300, VCMPNEW, do_vcmp, TCG_COND_NE, MO_32)
1048 static void gen_vcmpnez_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1049 {
1050 TCGv_vec t0, t1, zero;
1052 t0 = tcg_temp_new_vec_matching(t);
1053 t1 = tcg_temp_new_vec_matching(t);
1054 zero = tcg_constant_vec_matching(t, vece, 0);
1056 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t0, a, zero);
1057 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t1, b, zero);
1058 tcg_gen_cmp_vec(TCG_COND_NE, vece, t, a, b);
1060 tcg_gen_or_vec(vece, t, t, t0);
1061 tcg_gen_or_vec(vece, t, t, t1);
1063 tcg_temp_free_vec(t0);
1064 tcg_temp_free_vec(t1);
1065 }
1067 static bool do_vcmpnez(DisasContext *ctx, arg_VC *a, int vece)
1068 {
1069 static const TCGOpcode vecop_list[] = {
1070 INDEX_op_cmp_vec, 0
1071 };
1072 static const GVecGen3 ops[3] = {
1073 {
1074 .fniv = gen_vcmpnez_vec,
1075 .fno = gen_helper_VCMPNEZB,
1076 .opt_opc = vecop_list,
1077 .vece = MO_8
1078 },
1079 {
1080 .fniv = gen_vcmpnez_vec,
1081 .fno = gen_helper_VCMPNEZH,
1082 .opt_opc = vecop_list,
1083 .vece = MO_16
1084 },
1085 {
1086 .fniv = gen_vcmpnez_vec,
1087 .fno = gen_helper_VCMPNEZW,
1088 .opt_opc = vecop_list,
1089 .vece = MO_32
1090 }
1091 };
1093 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1094 REQUIRE_VECTOR(ctx);
1096 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
1097 avr_full_offset(a->vrb), 16, 16, &ops[vece]);
1099 if (a->rc) {
1100 do_vcmp_rc(a->vrt);
1101 }
1103 return true;
1104 }
1106 TRANS(VCMPNEZB, do_vcmpnez, MO_8)
1107 TRANS(VCMPNEZH, do_vcmpnez, MO_16)
1108 TRANS(VCMPNEZW, do_vcmpnez, MO_32)
1110 GEN_VXRFORM(vcmpeqfp, 3, 3)
1111 GEN_VXRFORM(vcmpgefp, 3, 7)
1112 GEN_VXRFORM(vcmpgtfp, 3, 11)
1113 GEN_VXRFORM(vcmpbfp, 3, 15)
1115 static void gen_vsplti(DisasContext *ctx, int vece)
1116 {
1117 int simm;
1119 if (unlikely(!ctx->altivec_enabled)) {
1120 gen_exception(ctx, POWERPC_EXCP_VPU);
1121 return;
1122 }
1124 simm = SIMM5(ctx->opcode);
1125 tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm);
1126 }
1128 #define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \
1129 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); }
1131 GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
1132 GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
1133 GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
1135 #define GEN_VXFORM_NOA(name, opc2, opc3) \
1136 static void glue(gen_, name)(DisasContext *ctx) \
1137 { \
1138 TCGv_ptr rb, rd; \
1139 if (unlikely(!ctx->altivec_enabled)) { \
1140 gen_exception(ctx, POWERPC_EXCP_VPU); \
1141 return; \
1142 } \
1143 rb = gen_avr_ptr(rB(ctx->opcode)); \
1144 rd = gen_avr_ptr(rD(ctx->opcode)); \
1145 gen_helper_##name(rd, rb); \
1146 tcg_temp_free_ptr(rb); \
1147 tcg_temp_free_ptr(rd); \
1148 }
1150 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
1151 static void glue(gen_, name)(DisasContext *ctx) \
1152 { \
1153 TCGv_ptr rb, rd; \
1154 \
1155 if (unlikely(!ctx->altivec_enabled)) { \
1156 gen_exception(ctx, POWERPC_EXCP_VPU); \
1157 return; \
1158 } \
1159 rb = gen_avr_ptr(rB(ctx->opcode)); \
1160 rd = gen_avr_ptr(rD(ctx->opcode)); \
1161 gen_helper_##name(cpu_env, rd, rb); \
1162 tcg_temp_free_ptr(rb); \
1163 tcg_temp_free_ptr(rd); \
1164 }
1166 #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
1167 static void glue(gen_, name)(DisasContext *ctx) \
1168 { \
1169 TCGv_ptr rb, rd; \
1170 if (unlikely(!ctx->altivec_enabled)) { \
1171 gen_exception(ctx, POWERPC_EXCP_VPU); \
1172 return; \
1173 } \
1174 rb = gen_avr_ptr(rB(ctx->opcode)); \
1175 rd = gen_avr_ptr(rD(ctx->opcode)); \
1176 gen_helper_##name(rd, rb); \
1177 tcg_temp_free_ptr(rb); \
1178 tcg_temp_free_ptr(rd); \
1179 }
1181 #define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
1182 static void glue(gen_, name)(DisasContext *ctx) \
1183 { \
1184 TCGv_ptr rb; \
1185 if (unlikely(!ctx->altivec_enabled)) { \
1186 gen_exception(ctx, POWERPC_EXCP_VPU); \
1187 return; \
1188 } \
1189 rb = gen_avr_ptr(rB(ctx->opcode)); \
1190 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
1191 tcg_temp_free_ptr(rb); \
1192 }
1193 GEN_VXFORM_NOA(vupkhsb, 7, 8);
1194 GEN_VXFORM_NOA(vupkhsh, 7, 9);
1195 GEN_VXFORM_NOA(vupkhsw, 7, 25);
1196 GEN_VXFORM_NOA(vupklsb, 7, 10);
1197 GEN_VXFORM_NOA(vupklsh, 7, 11);
1198 GEN_VXFORM_NOA(vupklsw, 7, 27);
1199 GEN_VXFORM_NOA(vupkhpx, 7, 13);
1200 GEN_VXFORM_NOA(vupklpx, 7, 15);
1201 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
1202 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
1203 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
1204 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
1205 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
1206 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
1207 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
1208 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
1209 GEN_VXFORM_NOA(vprtybw, 1, 24);
1210 GEN_VXFORM_NOA(vprtybd, 1, 24);
1211 GEN_VXFORM_NOA(vprtybq, 1, 24);
1213 static void gen_vsplt(DisasContext *ctx, int vece)
1214 {
1215 int uimm, dofs, bofs;
1217 if (unlikely(!ctx->altivec_enabled)) {
1218 gen_exception(ctx, POWERPC_EXCP_VPU);
1219 return;
1220 }
1222 uimm = UIMM5(ctx->opcode);
1223 bofs = avr_full_offset(rB(ctx->opcode));
1224 dofs = avr_full_offset(rD(ctx->opcode));
1226 /* Experimental testing shows that hardware masks the immediate. */
1227 bofs += (uimm << vece) & 15;
1228 #ifndef HOST_WORDS_BIGENDIAN
1229 bofs ^= 15;
1230 bofs &= ~((1 << vece) - 1);
1231 #endif
1233 tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
1234 }
1236 #define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
1237 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
1239 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
1240 static void glue(gen_, name)(DisasContext *ctx) \
1241 { \
1242 TCGv_ptr rb, rd; \
1243 TCGv_i32 uimm; \
1244 \
1245 if (unlikely(!ctx->altivec_enabled)) { \
1246 gen_exception(ctx, POWERPC_EXCP_VPU); \
1247 return; \
1248 } \
1249 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
1250 rb = gen_avr_ptr(rB(ctx->opcode)); \
1251 rd = gen_avr_ptr(rD(ctx->opcode)); \
1252 gen_helper_##name(cpu_env, rd, rb, uimm); \
1253 tcg_temp_free_i32(uimm); \
1254 tcg_temp_free_ptr(rb); \
1255 tcg_temp_free_ptr(rd); \
1256 }
1258 #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
1259 static void glue(gen_, name)(DisasContext *ctx) \
1260 { \
1261 TCGv_ptr rb, rd; \
1262 uint8_t uimm = UIMM4(ctx->opcode); \
1263 TCGv_i32 t0; \
1264 if (unlikely(!ctx->altivec_enabled)) { \
1265 gen_exception(ctx, POWERPC_EXCP_VPU); \
1266 return; \
1267 } \
1268 if (uimm > splat_max) { \
1269 uimm = 0; \
1270 } \
1271 t0 = tcg_temp_new_i32(); \
1272 tcg_gen_movi_i32(t0, uimm); \
1273 rb = gen_avr_ptr(rB(ctx->opcode)); \
1274 rd = gen_avr_ptr(rD(ctx->opcode)); \
1275 gen_helper_##name(rd, rb, t0); \
1276 tcg_temp_free_i32(t0); \
1277 tcg_temp_free_ptr(rb); \
1278 tcg_temp_free_ptr(rd); \
1279 }
1281 GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
1282 GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
1283 GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
1284 GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
1285 GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
1286 GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
1287 GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
1288 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
1289 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
1290 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
1291 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
1292 GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE,
1293 vextractub, PPC_NONE, PPC2_ISA300);
1294 GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
1295 vextractuh, PPC_NONE, PPC2_ISA300);
1296 GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
1297 vextractuw, PPC_NONE, PPC2_ISA300);
1299 static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
1300 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv))
1301 {
1302 TCGv_ptr vrt, vra, vrb;
1303 TCGv rc;
1305 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1306 REQUIRE_VECTOR(ctx);
1308 vrt = gen_avr_ptr(a->vrt);
1309 vra = gen_avr_ptr(a->vra);
1310 vrb = gen_avr_ptr(a->vrb);
1311 rc = tcg_temp_new();
1313 tcg_gen_andi_tl(rc, cpu_gpr[a->rc], 0x1F);
1314 if (right) {
1315 tcg_gen_subfi_tl(rc, 32 - size, rc);
1316 }
1317 gen_helper(cpu_env, vrt, vra, vrb, rc);
1319 tcg_temp_free_ptr(vrt);
1320 tcg_temp_free_ptr(vra);
1321 tcg_temp_free_ptr(vrb);
1322 tcg_temp_free(rc);
1323 return true;
1324 }
1326 TRANS(VEXTDUBVLX, do_vextdx, 1, false, gen_helper_VEXTDUBVLX)
1327 TRANS(VEXTDUHVLX, do_vextdx, 2, false, gen_helper_VEXTDUHVLX)
1328 TRANS(VEXTDUWVLX, do_vextdx, 4, false, gen_helper_VEXTDUWVLX)
1329 TRANS(VEXTDDVLX, do_vextdx, 8, false, gen_helper_VEXTDDVLX)
1331 TRANS(VEXTDUBVRX, do_vextdx, 1, true, gen_helper_VEXTDUBVLX)
1332 TRANS(VEXTDUHVRX, do_vextdx, 2, true, gen_helper_VEXTDUHVLX)
1333 TRANS(VEXTDUWVRX, do_vextdx, 4, true, gen_helper_VEXTDUWVLX)
1334 TRANS(VEXTDDVRX, do_vextdx, 8, true, gen_helper_VEXTDDVLX)
1336 static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
1337 TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1338 {
1339 TCGv_ptr t;
1340 TCGv idx;
1342 t = gen_avr_ptr(vrt);
1343 idx = tcg_temp_new();
1345 tcg_gen_andi_tl(idx, ra, 0xF);
1346 if (right) {
1347 tcg_gen_subfi_tl(idx, 16 - size, idx);
1348 }
1350 gen_helper(cpu_env, t, rb, idx);
1352 tcg_temp_free_ptr(t);
1353 tcg_temp_free(idx);
1355 return true;
1356 }
1358 static bool do_vinsvx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
1359 int vrb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1360 {
1361 bool ok;
1362 TCGv_i64 val;
1364 val = tcg_temp_new_i64();
1365 get_avr64(val, vrb, true);
1366 ok = do_vinsx(ctx, vrt, size, right, ra, val, gen_helper);
1368 tcg_temp_free_i64(val);
1369 return ok;
1370 }
1372 static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
1373 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1374 {
1375 bool ok;
1376 TCGv_i64 val;
1378 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1379 REQUIRE_VECTOR(ctx);
1381 val = tcg_temp_new_i64();
1382 tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
1384 ok = do_vinsx(ctx, a->vrt, size, right, cpu_gpr[a->vra], val, gen_helper);
1386 tcg_temp_free_i64(val);
1387 return ok;
1388 }
1390 static bool do_vinsvx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
1391 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1392 {
1393 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1394 REQUIRE_VECTOR(ctx);
1396 return do_vinsvx(ctx, a->vrt, size, right, cpu_gpr[a->vra], a->vrb,
1397 gen_helper);
1398 }
1400 static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
1401 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1402 {
1403 bool ok;
1404 TCGv_i64 val;
1406 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1407 REQUIRE_VECTOR(ctx);
1409 if (a->uim > (16 - size)) {
1410 /*
1411 * PowerISA v3.1 says that the resulting value is undefined in this
1412 * case, so just log a guest error and leave VRT unchanged. The
1413 * real hardware would do a partial insert, e.g. if VRT is zeroed and
1414 * RB is 0x12345678, executing "vinsw VRT,RB,14" results in
1415 * VRT = 0x0000...00001234, but we don't bother to reproduce this
1416 * behavior as software shouldn't rely on it.
1417 */
1418 qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS* at"
1419 " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
1420 16 - size);
1421 return true;
1422 }
1424 val = tcg_temp_new_i64();
1425 tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
1427 ok = do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val,
1428 gen_helper);
1430 tcg_temp_free_i64(val);
1431 return ok;
1432 }
1434 static bool do_vinsert_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
1435 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1436 {
1437 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1438 REQUIRE_VECTOR(ctx);
1440 if (a->uim > (16 - size)) {
1441 qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINSERT* at"
1442 " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
1443 16 - size);
1444 return true;
1445 }
1447 return do_vinsvx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), a->vrb,
1448 gen_helper);
1449 }
1451 TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
1452 TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
1453 TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
1454 TRANS(VINSDLX, do_vinsx_VX, 8, false, gen_helper_VINSDLX)
1456 TRANS(VINSBRX, do_vinsx_VX, 1, true, gen_helper_VINSBLX)
1457 TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
1458 TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
1459 TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
1461 TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
1462 TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
1464 TRANS(VINSBVLX, do_vinsvx_VX, 1, false, gen_helper_VINSBLX)
1465 TRANS(VINSHVLX, do_vinsvx_VX, 2, false, gen_helper_VINSHLX)
1466 TRANS(VINSWVLX, do_vinsvx_VX, 4, false, gen_helper_VINSWLX)
1468 TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
1469 TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
1470 TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
1472 TRANS(VINSERTB, do_vinsert_VX_uim4, 1, gen_helper_VINSBLX)
1473 TRANS(VINSERTH, do_vinsert_VX_uim4, 2, gen_helper_VINSHLX)
1474 TRANS(VINSERTW, do_vinsert_VX_uim4, 4, gen_helper_VINSWLX)
1475 TRANS(VINSERTD, do_vinsert_VX_uim4, 8, gen_helper_VINSDLX)
1477 static void gen_vsldoi(DisasContext *ctx)
1478 {
1479 TCGv_ptr ra, rb, rd;
1480 TCGv_i32 sh;
1481 if (unlikely(!ctx->altivec_enabled)) {
1482 gen_exception(ctx, POWERPC_EXCP_VPU);
1483 return;
1484 }
1485 ra = gen_avr_ptr(rA(ctx->opcode));
1486 rb = gen_avr_ptr(rB(ctx->opcode));
1487 rd = gen_avr_ptr(rD(ctx->opcode));
1488 sh = tcg_const_i32(VSH(ctx->opcode));
1489 gen_helper_vsldoi(rd, ra, rb, sh);
1490 tcg_temp_free_ptr(ra);
1491 tcg_temp_free_ptr(rb);
1492 tcg_temp_free_ptr(rd);
1493 tcg_temp_free_i32(sh);
1494 }
1496 static bool trans_VSLDBI(DisasContext *ctx, arg_VN *a)
1497 {
1498 TCGv_i64 t0, t1, t2;
1500 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1501 REQUIRE_VECTOR(ctx);
1503 t0 = tcg_temp_new_i64();
1504 t1 = tcg_temp_new_i64();
1506 get_avr64(t0, a->vra, true);
1507 get_avr64(t1, a->vra, false);
1509 if (a->sh != 0) {
1510 t2 = tcg_temp_new_i64();
1512 get_avr64(t2, a->vrb, true);
1514 tcg_gen_extract2_i64(t0, t1, t0, 64 - a->sh);
1515 tcg_gen_extract2_i64(t1, t2, t1, 64 - a->sh);
1517 tcg_temp_free_i64(t2);
1518 }
1520 set_avr64(a->vrt, t0, true);
1521 set_avr64(a->vrt, t1, false);
1523 tcg_temp_free_i64(t0);
1524 tcg_temp_free_i64(t1);
1526 return true;
1527 }
1529 static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a)
1530 {
1531 TCGv_i64 t2, t1, t0;
1533 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1534 REQUIRE_VECTOR(ctx);
1536 t0 = tcg_temp_new_i64();
1537 t1 = tcg_temp_new_i64();
1539 get_avr64(t0, a->vrb, false);
1540 get_avr64(t1, a->vrb, true);
1542 if (a->sh != 0) {
1543 t2 = tcg_temp_new_i64();
1545 get_avr64(t2, a->vra, false);
1547 tcg_gen_extract2_i64(t0, t0, t1, a->sh);
1548 tcg_gen_extract2_i64(t1, t1, t2, a->sh);
1550 tcg_temp_free_i64(t2);
1551 }
1553 set_avr64(a->vrt, t0, false);
1554 set_avr64(a->vrt, t1, true);
1556 tcg_temp_free_i64(t0);
1557 tcg_temp_free_i64(t1);
1559 return true;
1560 }
1562 static bool do_vexpand(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1563 {
1564 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1565 REQUIRE_VECTOR(ctx);
1567 tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb),
1568 (8 << vece) - 1, 16, 16);
1570 return true;
1571 }
1573 TRANS(VEXPANDBM, do_vexpand, MO_8)
1574 TRANS(VEXPANDHM, do_vexpand, MO_16)
1575 TRANS(VEXPANDWM, do_vexpand, MO_32)
1576 TRANS(VEXPANDDM, do_vexpand, MO_64)
1578 static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
1579 {
1580 TCGv_i64 tmp;
1582 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1583 REQUIRE_VECTOR(ctx);
1585 tmp = tcg_temp_new_i64();
1587 get_avr64(tmp, a->vrb, true);
1588 tcg_gen_sari_i64(tmp, tmp, 63);
1589 set_avr64(a->vrt, tmp, false);
1590 set_avr64(a->vrt, tmp, true);
1592 tcg_temp_free_i64(tmp);
1593 return true;
1594 }
1596 static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1597 {
1598 const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
1599 mask = dup_const(vece, 1 << (elem_width - 1));
1600 uint64_t i, j;
1601 TCGv_i64 lo, hi, t0, t1;
1603 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1604 REQUIRE_VECTOR(ctx);
1606 hi = tcg_temp_new_i64();
1607 lo = tcg_temp_new_i64();
1608 t0 = tcg_temp_new_i64();
1609 t1 = tcg_temp_new_i64();
1611 get_avr64(lo, a->vrb, false);
1612 get_avr64(hi, a->vrb, true);
1614 tcg_gen_andi_i64(lo, lo, mask);
1615 tcg_gen_andi_i64(hi, hi, mask);
1617 /*
1618 * Gather the most significant bit of each element in the highest element
1619 * element. E.g. for bytes:
1620 * aXXXXXXXbXXXXXXXcXXXXXXXdXXXXXXXeXXXXXXXfXXXXXXXgXXXXXXXhXXXXXXX
1621 * & dup(1 << (elem_width - 1))
1622 * a0000000b0000000c0000000d0000000e0000000f0000000g0000000h0000000
1623 * << 32 - 4
1624 * 0000e0000000f0000000g0000000h00000000000000000000000000000000000
1625 * |
1626 * a000e000b000f000c000g000d000h000e0000000f0000000g0000000h0000000
1627 * << 16 - 2
1628 * 00c000g000d000h000e0000000f0000000g0000000h000000000000000000000
1629 * |
1630 * a0c0e0g0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h0000000
1631 * << 8 - 1
1632 * 0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h00000000000000
1633 * |
1634 * abcdefghbcdefgh0cdefgh00defgh000efgh0000fgh00000gh000000h0000000
1635 */
1636 for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
1637 tcg_gen_shli_i64(t0, hi, j - i);
1638 tcg_gen_shli_i64(t1, lo, j - i);
1639 tcg_gen_or_i64(hi, hi, t0);
1640 tcg_gen_or_i64(lo, lo, t1);
1641 }
1643 tcg_gen_shri_i64(hi, hi, 64 - elem_count_half);
1644 tcg_gen_extract2_i64(lo, lo, hi, 64 - elem_count_half);
1645 tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo);
1647 tcg_temp_free_i64(hi);
1648 tcg_temp_free_i64(lo);
1649 tcg_temp_free_i64(t0);
1650 tcg_temp_free_i64(t1);
1652 return true;
1653 }
1655 TRANS(VEXTRACTBM, do_vextractm, MO_8)
1656 TRANS(VEXTRACTHM, do_vextractm, MO_16)
1657 TRANS(VEXTRACTWM, do_vextractm, MO_32)
1658 TRANS(VEXTRACTDM, do_vextractm, MO_64)
1660 static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a)
1661 {
1662 TCGv_i64 tmp;
1664 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1665 REQUIRE_VECTOR(ctx);
1667 tmp = tcg_temp_new_i64();
1669 get_avr64(tmp, a->vrb, true);
1670 tcg_gen_shri_i64(tmp, tmp, 63);
1671 tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp);
1673 tcg_temp_free_i64(tmp);
1675 return true;
1676 }
1678 static bool do_mtvsrm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1679 {
1680 const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece;
1681 uint64_t c;
1682 int i, j;
1683 TCGv_i64 hi, lo, t0, t1;
1685 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1686 REQUIRE_VECTOR(ctx);
1688 hi = tcg_temp_new_i64();
1689 lo = tcg_temp_new_i64();
1690 t0 = tcg_temp_new_i64();
1691 t1 = tcg_temp_new_i64();
1693 tcg_gen_extu_tl_i64(t0, cpu_gpr[a->vrb]);
1694 tcg_gen_extract_i64(hi, t0, elem_count_half, elem_count_half);
1695 tcg_gen_extract_i64(lo, t0, 0, elem_count_half);
1697 /*
1698 * Spread the bits into their respective elements.
1699 * E.g. for bytes:
1700 * 00000000000000000000000000000000000000000000000000000000abcdefgh
1701 * << 32 - 4
1702 * 0000000000000000000000000000abcdefgh0000000000000000000000000000
1703 * |
1704 * 0000000000000000000000000000abcdefgh00000000000000000000abcdefgh
1705 * << 16 - 2
1706 * 00000000000000abcdefgh00000000000000000000abcdefgh00000000000000
1707 * |
1708 * 00000000000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh
1709 * << 8 - 1
1710 * 0000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh0000000
1711 * |
1712 * 0000000abcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgh
1713 * & dup(1)
1714 * 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h
1715 * * 0xff
1716 * aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh
1717 */
1718 for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
1719 tcg_gen_shli_i64(t0, hi, j - i);
1720 tcg_gen_shli_i64(t1, lo, j - i);
1721 tcg_gen_or_i64(hi, hi, t0);
1722 tcg_gen_or_i64(lo, lo, t1);
1723 }
1725 c = dup_const(vece, 1);
1726 tcg_gen_andi_i64(hi, hi, c);
1727 tcg_gen_andi_i64(lo, lo, c);
1729 c = MAKE_64BIT_MASK(0, elem_width);
1730 tcg_gen_muli_i64(hi, hi, c);
1731 tcg_gen_muli_i64(lo, lo, c);
1733 set_avr64(a->vrt, lo, false);
1734 set_avr64(a->vrt, hi, true);
1736 tcg_temp_free_i64(hi);
1737 tcg_temp_free_i64(lo);
1738 tcg_temp_free_i64(t0);
1739 tcg_temp_free_i64(t1);
1741 return true;
1742 }
1744 TRANS(MTVSRBM, do_mtvsrm, MO_8)
1745 TRANS(MTVSRHM, do_mtvsrm, MO_16)
1746 TRANS(MTVSRWM, do_mtvsrm, MO_32)
1747 TRANS(MTVSRDM, do_mtvsrm, MO_64)
1749 static bool trans_MTVSRQM(DisasContext *ctx, arg_VX_tb *a)
1750 {
1751 TCGv_i64 tmp;
1753 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1754 REQUIRE_VECTOR(ctx);
1756 tmp = tcg_temp_new_i64();
1758 tcg_gen_ext_tl_i64(tmp, cpu_gpr[a->vrb]);
1759 tcg_gen_sextract_i64(tmp, tmp, 0, 1);
1760 set_avr64(a->vrt, tmp, false);
1761 set_avr64(a->vrt, tmp, true);
1763 tcg_temp_free_i64(tmp);
1765 return true;
1766 }
1768 static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
1769 {
1770 const uint64_t mask = dup_const(MO_8, 1);
1771 uint64_t hi, lo;
1773 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1774 REQUIRE_VECTOR(ctx);
1776 hi = extract16(a->b, 8, 8);
1777 lo = extract16(a->b, 0, 8);
1779 for (int i = 4, j = 32; i > 0; i >>= 1, j >>= 1) {
1780 hi |= hi << (j - i);
1781 lo |= lo << (j - i);
1782 }
1784 hi = (hi & mask) * 0xFF;
1785 lo = (lo & mask) * 0xFF;
1787 set_avr64(a->vrt, tcg_constant_i64(hi), true);
1788 set_avr64(a->vrt, tcg_constant_i64(lo), false);
1790 return true;
1791 }
1793 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
1794 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
1795 { \
1796 TCGv_ptr ra, rb, rc, rd; \
1797 if (unlikely(!ctx->altivec_enabled)) { \
1798 gen_exception(ctx, POWERPC_EXCP_VPU); \
1799 return; \
1800 } \
1801 ra = gen_avr_ptr(rA(ctx->opcode)); \
1802 rb = gen_avr_ptr(rB(ctx->opcode)); \
1803 rc = gen_avr_ptr(rC(ctx->opcode)); \
1804 rd = gen_avr_ptr(rD(ctx->opcode)); \
1805 if (Rc(ctx->opcode)) { \
1806 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
1807 } else { \
1808 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
1809 } \
1810 tcg_temp_free_ptr(ra); \
1811 tcg_temp_free_ptr(rb); \
1812 tcg_temp_free_ptr(rc); \
1813 tcg_temp_free_ptr(rd); \
1814 }
1816 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
1818 static void gen_vmladduhm(DisasContext *ctx)
1819 {
1820 TCGv_ptr ra, rb, rc, rd;
1821 if (unlikely(!ctx->altivec_enabled)) {
1822 gen_exception(ctx, POWERPC_EXCP_VPU);
1823 return;
1824 }
1825 ra = gen_avr_ptr(rA(ctx->opcode));
1826 rb = gen_avr_ptr(rB(ctx->opcode));
1827 rc = gen_avr_ptr(rC(ctx->opcode));
1828 rd = gen_avr_ptr(rD(ctx->opcode));
1829 gen_helper_vmladduhm(rd, ra, rb, rc);
1830 tcg_temp_free_ptr(ra);
1831 tcg_temp_free_ptr(rb);
1832 tcg_temp_free_ptr(rc);
1833 tcg_temp_free_ptr(rd);
1834 }
1836 static void gen_vpermr(DisasContext *ctx)
1837 {
1838 TCGv_ptr ra, rb, rc, rd;
1839 if (unlikely(!ctx->altivec_enabled)) {
1840 gen_exception(ctx, POWERPC_EXCP_VPU);
1841 return;
1842 }
1843 ra = gen_avr_ptr(rA(ctx->opcode));
1844 rb = gen_avr_ptr(rB(ctx->opcode));
1845 rc = gen_avr_ptr(rC(ctx->opcode));
1846 rd = gen_avr_ptr(rD(ctx->opcode));
1847 gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
1848 tcg_temp_free_ptr(ra);
1849 tcg_temp_free_ptr(rb);
1850 tcg_temp_free_ptr(rc);
1851 tcg_temp_free_ptr(rd);
1852 }
1854 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
1855 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
1856 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
1857 GEN_VAFORM_PAIRED(vsel, vperm, 21)
1858 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
1860 GEN_VXFORM_NOA(vclzb, 1, 28)
1861 GEN_VXFORM_NOA(vclzh, 1, 29)
1862 GEN_VXFORM_TRANS(vclzw, 1, 30)
1863 GEN_VXFORM_TRANS(vclzd, 1, 31)
1864 GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
1865 GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
1867 static void gen_vexts_i64(TCGv_i64 t, TCGv_i64 b, int64_t s)
1868 {
1869 tcg_gen_sextract_i64(t, b, 0, 64 - s);
1870 }
1872 static void gen_vexts_i32(TCGv_i32 t, TCGv_i32 b, int32_t s)
1873 {
1874 tcg_gen_sextract_i32(t, b, 0, 32 - s);
1875 }
1877 static void gen_vexts_vec(unsigned vece, TCGv_vec t, TCGv_vec b, int64_t s)
1878 {
1879 tcg_gen_shli_vec(vece, t, b, s);
1880 tcg_gen_sari_vec(vece, t, t, s);
1881 }
1883 static bool do_vexts(DisasContext *ctx, arg_VX_tb *a, unsigned vece, int64_t s)
1884 {
1885 static const TCGOpcode vecop_list[] = {
1886 INDEX_op_shli_vec, INDEX_op_sari_vec, 0
1887 };
1889 static const GVecGen2i op[2] = {
1890 {
1891 .fni4 = gen_vexts_i32,
1892 .fniv = gen_vexts_vec,
1893 .opt_opc = vecop_list,
1894 .vece = MO_32
1895 },
1896 {
1897 .fni8 = gen_vexts_i64,
1898 .fniv = gen_vexts_vec,
1899 .opt_opc = vecop_list,
1900 .vece = MO_64
1901 },
1902 };
1904 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1905 REQUIRE_VECTOR(ctx);
1907 tcg_gen_gvec_2i(avr_full_offset(a->vrt), avr_full_offset(a->vrb),
1908 16, 16, s, &op[vece - MO_32]);
1910 return true;
1911 }
1913 TRANS(VEXTSB2W, do_vexts, MO_32, 24);
1914 TRANS(VEXTSH2W, do_vexts, MO_32, 16);
1915 TRANS(VEXTSB2D, do_vexts, MO_64, 56);
1916 TRANS(VEXTSH2D, do_vexts, MO_64, 48);
1917 TRANS(VEXTSW2D, do_vexts, MO_64, 32);
1919 static bool trans_VEXTSD2Q(DisasContext *ctx, arg_VX_tb *a)
1920 {
1921 TCGv_i64 tmp;
1923 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1924 REQUIRE_VECTOR(ctx);
1926 tmp = tcg_temp_new_i64();
1928 get_avr64(tmp, a->vrb, false);
1929 set_avr64(a->vrt, tmp, false);
1930 tcg_gen_sari_i64(tmp, tmp, 63);
1931 set_avr64(a->vrt, tmp, true);
1933 tcg_temp_free_i64(tmp);
1934 return true;
1935 }
1937 GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
1938 GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
1939 GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
1940 GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
1941 GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
1942 GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
1943 GEN_VXFORM_NOA(vpopcntb, 1, 28)
1944 GEN_VXFORM_NOA(vpopcnth, 1, 29)
1945 GEN_VXFORM_NOA(vpopcntw, 1, 30)
1946 GEN_VXFORM_NOA(vpopcntd, 1, 31)
1947 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
1948 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
1949 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
1950 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
1951 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
1952 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
1953 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
1954 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
1955 GEN_VXFORM(vbpermd, 6, 23);
1956 GEN_VXFORM(vbpermq, 6, 21);
1957 GEN_VXFORM_TRANS(vgbbd, 6, 20);
1958 GEN_VXFORM(vpmsumb, 4, 16)
1959 GEN_VXFORM(vpmsumh, 4, 17)
1960 GEN_VXFORM(vpmsumw, 4, 18)
1961 GEN_VXFORM(vpmsumd, 4, 19)
1963 #define GEN_BCD(op) \
1964 static void gen_##op(DisasContext *ctx) \
1965 { \
1966 TCGv_ptr ra, rb, rd; \
1967 TCGv_i32 ps; \
1968 \
1969 if (unlikely(!ctx->altivec_enabled)) { \
1970 gen_exception(ctx, POWERPC_EXCP_VPU); \
1971 return; \
1972 } \
1973 \
1974 ra = gen_avr_ptr(rA(ctx->opcode)); \
1975 rb = gen_avr_ptr(rB(ctx->opcode)); \
1976 rd = gen_avr_ptr(rD(ctx->opcode)); \
1977 \
1978 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
1979 \
1980 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
1981 \
1982 tcg_temp_free_ptr(ra); \
1983 tcg_temp_free_ptr(rb); \
1984 tcg_temp_free_ptr(rd); \
1985 tcg_temp_free_i32(ps); \
1986 }
1988 #define GEN_BCD2(op) \
1989 static void gen_##op(DisasContext *ctx) \
1990 { \
1991 TCGv_ptr rd, rb; \
1992 TCGv_i32 ps; \
1993 \
1994 if (unlikely(!ctx->altivec_enabled)) { \
1995 gen_exception(ctx, POWERPC_EXCP_VPU); \
1996 return; \
1997 } \
1998 \
1999 rb = gen_avr_ptr(rB(ctx->opcode)); \
2000 rd = gen_avr_ptr(rD(ctx->opcode)); \
2001 \
2002 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
2003 \
2004 gen_helper_##op(cpu_crf[6], rd, rb, ps); \
2005 \
2006 tcg_temp_free_ptr(rb); \
2007 tcg_temp_free_ptr(rd); \
2008 tcg_temp_free_i32(ps); \
2009 }
2011 GEN_BCD(bcdadd)
2012 GEN_BCD(bcdsub)
2013 GEN_BCD2(bcdcfn)
2014 GEN_BCD2(bcdctn)
2015 GEN_BCD2(bcdcfz)
2016 GEN_BCD2(bcdctz)
2017 GEN_BCD2(bcdcfsq)
2018 GEN_BCD2(bcdctsq)
2019 GEN_BCD2(bcdsetsgn)
2020 GEN_BCD(bcdcpsgn);
2021 GEN_BCD(bcds);
2022 GEN_BCD(bcdus);
2023 GEN_BCD(bcdsr);
2024 GEN_BCD(bcdtrunc);
2025 GEN_BCD(bcdutrunc);
2027 static void gen_xpnd04_1(DisasContext *ctx)
2028 {
2029 switch (opc4(ctx->opcode)) {
2030 case 0:
2031 gen_bcdctsq(ctx);
2032 break;
2033 case 2:
2034 gen_bcdcfsq(ctx);
2035 break;
2036 case 4:
2037 gen_bcdctz(ctx);
2038 break;
2039 case 5:
2040 gen_bcdctn(ctx);
2041 break;
2042 case 6:
2043 gen_bcdcfz(ctx);
2044 break;
2045 case 7:
2046 gen_bcdcfn(ctx);
2047 break;
2048 case 31:
2049 gen_bcdsetsgn(ctx);
2050 break;
2051 default:
2052 gen_invalid(ctx);
2053 break;
2054 }
2055 }
2057 static void gen_xpnd04_2(DisasContext *ctx)
2058 {
2059 switch (opc4(ctx->opcode)) {
2060 case 0:
2061 gen_bcdctsq(ctx);
2062 break;
2063 case 2:
2064 gen_bcdcfsq(ctx);
2065 break;
2066 case 4:
2067 gen_bcdctz(ctx);
2068 break;
2069 case 6:
2070 gen_bcdcfz(ctx);
2071 break;
2072 case 7:
2073 gen_bcdcfn(ctx);
2074 break;
2075 case 31:
2076 gen_bcdsetsgn(ctx);
2077 break;
2078 default:
2079 gen_invalid(ctx);
2080 break;
2081 }
2082 }
2085 GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
2086 xpnd04_1, PPC_NONE, PPC2_ISA300)
2087 GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
2088 xpnd04_2, PPC_NONE, PPC2_ISA300)
2090 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
2091 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
2092 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
2093 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
2094 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
2095 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
2096 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
2097 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
2098 GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
2099 bcdcpsgn, PPC_NONE, PPC2_ISA300)
2100 GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
2101 bcds, PPC_NONE, PPC2_ISA300)
2102 GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
2103 bcdus, PPC_NONE, PPC2_ISA300)
2104 GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
2105 bcdtrunc, PPC_NONE, PPC2_ISA300)
2106 GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
2107 bcdtrunc, PPC_NONE, PPC2_ISA300)
2108 GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
2109 bcdutrunc, PPC_NONE, PPC2_ISA300)
2112 static void gen_vsbox(DisasContext *ctx)
2113 {
2114 TCGv_ptr ra, rd;
2115 if (unlikely(!ctx->altivec_enabled)) {
2116 gen_exception(ctx, POWERPC_EXCP_VPU);
2117 return;
2118 }
2119 ra = gen_avr_ptr(rA(ctx->opcode));
2120 rd = gen_avr_ptr(rD(ctx->opcode));
2121 gen_helper_vsbox(rd, ra);
2122 tcg_temp_free_ptr(ra);
2123 tcg_temp_free_ptr(rd);
2124 }
2126 GEN_VXFORM(vcipher, 4, 20)
2127 GEN_VXFORM(vcipherlast, 4, 20)
2128 GEN_VXFORM(vncipher, 4, 21)
2129 GEN_VXFORM(vncipherlast, 4, 21)
2131 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
2132 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2133 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
2134 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2136 #define VSHASIGMA(op) \
2137 static void gen_##op(DisasContext *ctx) \
2138 { \
2139 TCGv_ptr ra, rd; \
2140 TCGv_i32 st_six; \
2141 if (unlikely(!ctx->altivec_enabled)) { \
2142 gen_exception(ctx, POWERPC_EXCP_VPU); \
2143 return; \
2144 } \
2145 ra = gen_avr_ptr(rA(ctx->opcode)); \
2146 rd = gen_avr_ptr(rD(ctx->opcode)); \
2147 st_six = tcg_const_i32(rB(ctx->opcode)); \
2148 gen_helper_##op(rd, ra, st_six); \
2149 tcg_temp_free_ptr(ra); \
2150 tcg_temp_free_ptr(rd); \
2151 tcg_temp_free_i32(st_six); \
2152 }
2154 VSHASIGMA(vshasigmaw)
2155 VSHASIGMA(vshasigmad)
2157 GEN_VXFORM3(vpermxor, 22, 0xFF)
2158 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
2159 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
2161 static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
2162 {
2163 static const GVecGen3 g = {
2164 .fni8 = gen_helper_CFUGED,
2165 .vece = MO_64,
2166 };
2168 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2169 REQUIRE_VECTOR(ctx);
2171 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2172 avr_full_offset(a->vrb), 16, 16, &g);
2174 return true;
2175 }
2177 static bool trans_VCLZDM(DisasContext *ctx, arg_VX *a)
2178 {
2179 static const GVecGen3i g = {
2180 .fni8 = do_cntzdm,
2181 .vece = MO_64,
2182 };
2184 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2185 REQUIRE_VECTOR(ctx);
2187 tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2188 avr_full_offset(a->vrb), 16, 16, false, &g);
2190 return true;
2191 }
2193 static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
2194 {
2195 static const GVecGen3i g = {
2196 .fni8 = do_cntzdm,
2197 .vece = MO_64,
2198 };
2200 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2201 REQUIRE_VECTOR(ctx);
2203 tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2204 avr_full_offset(a->vrb), 16, 16, true, &g);
2206 return true;
2207 }
2209 static bool trans_VPDEPD(DisasContext *ctx, arg_VX *a)
2210 {
2211 static const GVecGen3 g = {
2212 .fni8 = gen_helper_PDEPD,
2213 .vece = MO_64,
2214 };
2216 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2217 REQUIRE_VECTOR(ctx);
2219 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2220 avr_full_offset(a->vrb), 16, 16, &g);
2222 return true;
2223 }
2225 static bool trans_VPEXTD(DisasContext *ctx, arg_VX *a)
2226 {
2227 static const GVecGen3 g = {
2228 .fni8 = gen_helper_PEXTD,
2229 .vece = MO_64,
2230 };
2232 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2233 REQUIRE_VECTOR(ctx);
2235 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2236 avr_full_offset(a->vrb), 16, 16, &g);
2238 return true;
2239 }
2241 static bool trans_VMSUMUDM(DisasContext *ctx, arg_VA *a)
2242 {
2243 TCGv_i64 rl, rh, src1, src2;
2244 int dw;
2246 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
2247 REQUIRE_VECTOR(ctx);
2249 rh = tcg_temp_new_i64();
2250 rl = tcg_temp_new_i64();
2251 src1 = tcg_temp_new_i64();
2252 src2 = tcg_temp_new_i64();
2254 get_avr64(rl, a->rc, false);
2255 get_avr64(rh, a->rc, true);
2257 for (dw = 0; dw < 2; dw++) {
2258 get_avr64(src1, a->vra, dw);
2259 get_avr64(src2, a->vrb, dw);
2260 tcg_gen_mulu2_i64(src1, src2, src1, src2);
2261 tcg_gen_add2_i64(rl, rh, rl, rh, src1, src2);
2262 }
2264 set_avr64(a->vrt, rl, false);
2265 set_avr64(a->vrt, rh, true);
2267 tcg_temp_free_i64(rl);
2268 tcg_temp_free_i64(rh);
2269 tcg_temp_free_i64(src1);
2270 tcg_temp_free_i64(src2);
2272 return true;
2273 }
2275 static bool trans_VMSUMCUD(DisasContext *ctx, arg_VA *a)
2276 {
2277 TCGv_i64 tmp0, tmp1, prod1h, prod1l, prod0h, prod0l, zero;
2279 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2280 REQUIRE_VECTOR(ctx);
2282 tmp0 = tcg_temp_new_i64();
2283 tmp1 = tcg_temp_new_i64();
2284 prod1h = tcg_temp_new_i64();
2285 prod1l = tcg_temp_new_i64();
2286 prod0h = tcg_temp_new_i64();
2287 prod0l = tcg_temp_new_i64();
2288 zero = tcg_constant_i64(0);
2290 /* prod1 = vsr[vra+32].dw[1] * vsr[vrb+32].dw[1] */
2291 get_avr64(tmp0, a->vra, false);
2292 get_avr64(tmp1, a->vrb, false);
2293 tcg_gen_mulu2_i64(prod1l, prod1h, tmp0, tmp1);
2295 /* prod0 = vsr[vra+32].dw[0] * vsr[vrb+32].dw[0] */
2296 get_avr64(tmp0, a->vra, true);
2297 get_avr64(tmp1, a->vrb, true);
2298 tcg_gen_mulu2_i64(prod0l, prod0h, tmp0, tmp1);
2300 /* Sum lower 64-bits elements */
2301 get_avr64(tmp1, a->rc, false);
2302 tcg_gen_add2_i64(tmp1, tmp0, tmp1, zero, prod1l, zero);
2303 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0l, zero);
2305 /*
2306 * Discard lower 64-bits, leaving the carry into bit 64.
2307 * Then sum the higher 64-bit elements.
2308 */
2309 get_avr64(tmp1, a->rc, true);
2310 tcg_gen_add2_i64(tmp1, tmp0, tmp0, zero, tmp1, zero);
2311 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod1h, zero);
2312 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0h, zero);
2314 /* Discard 64 more bits to complete the CHOP128(temp >> 128) */
2315 set_avr64(a->vrt, tmp0, false);
2316 set_avr64(a->vrt, zero, true);
2318 tcg_temp_free_i64(tmp0);
2319 tcg_temp_free_i64(tmp1);
2320 tcg_temp_free_i64(prod1h);
2321 tcg_temp_free_i64(prod1l);
2322 tcg_temp_free_i64(prod0h);
2323 tcg_temp_free_i64(prod0l);
2325 return true;
2326 }
2328 static bool do_vx_helper(DisasContext *ctx, arg_VX *a,
2329 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
2330 {
2331 TCGv_ptr ra, rb, rd;
2332 REQUIRE_VECTOR(ctx);
2334 ra = gen_avr_ptr(a->vra);
2335 rb = gen_avr_ptr(a->vrb);
2336 rd = gen_avr_ptr(a->vrt);
2337 gen_helper(rd, ra, rb);
2338 tcg_temp_free_ptr(ra);
2339 tcg_temp_free_ptr(rb);
2340 tcg_temp_free_ptr(rd);
2342 return true;
2343 }
2345 static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
2346 void (*gen_mul)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
2347 {
2348 TCGv_i64 vra, vrb, vrt0, vrt1;
2349 REQUIRE_VECTOR(ctx);
2351 vra = tcg_temp_new_i64();
2352 vrb = tcg_temp_new_i64();
2353 vrt0 = tcg_temp_new_i64();
2354 vrt1 = tcg_temp_new_i64();
2356 get_avr64(vra, a->vra, even);
2357 get_avr64(vrb, a->vrb, even);
2358 gen_mul(vrt0, vrt1, vra, vrb);
2359 set_avr64(a->vrt, vrt0, false);
2360 set_avr64(a->vrt, vrt1, true);
2362 tcg_temp_free_i64(vra);
2363 tcg_temp_free_i64(vrb);
2364 tcg_temp_free_i64(vrt0);
2365 tcg_temp_free_i64(vrt1);
2367 return true;
2368 }
2370 static bool trans_VMULLD(DisasContext *ctx, arg_VX *a)
2371 {
2372 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2373 REQUIRE_VECTOR(ctx);
2375 tcg_gen_gvec_mul(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->vra),
2376 avr_full_offset(a->vrb), 16, 16);
2378 return true;
2379 }
2381 TRANS_FLAGS2(ALTIVEC_207, VMULESB, do_vx_helper, gen_helper_VMULESB)
2382 TRANS_FLAGS2(ALTIVEC_207, VMULOSB, do_vx_helper, gen_helper_VMULOSB)
2383 TRANS_FLAGS2(ALTIVEC_207, VMULEUB, do_vx_helper, gen_helper_VMULEUB)
2384 TRANS_FLAGS2(ALTIVEC_207, VMULOUB, do_vx_helper, gen_helper_VMULOUB)
2385 TRANS_FLAGS2(ALTIVEC_207, VMULESH, do_vx_helper, gen_helper_VMULESH)
2386 TRANS_FLAGS2(ALTIVEC_207, VMULOSH, do_vx_helper, gen_helper_VMULOSH)
2387 TRANS_FLAGS2(ALTIVEC_207, VMULEUH, do_vx_helper, gen_helper_VMULEUH)
2388 TRANS_FLAGS2(ALTIVEC_207, VMULOUH, do_vx_helper, gen_helper_VMULOUH)
2389 TRANS_FLAGS2(ALTIVEC_207, VMULESW, do_vx_helper, gen_helper_VMULESW)
2390 TRANS_FLAGS2(ALTIVEC_207, VMULOSW, do_vx_helper, gen_helper_VMULOSW)
2391 TRANS_FLAGS2(ALTIVEC_207, VMULEUW, do_vx_helper, gen_helper_VMULEUW)
2392 TRANS_FLAGS2(ALTIVEC_207, VMULOUW, do_vx_helper, gen_helper_VMULOUW)
2393 TRANS_FLAGS2(ISA310, VMULESD, do_vx_vmuleo, true , tcg_gen_muls2_i64)
2394 TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64)
2395 TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64)
2396 TRANS_FLAGS2(ISA310, VMULOUD, do_vx_vmuleo, false, tcg_gen_mulu2_i64)
2398 static void do_vx_vmulhw_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
2399 {
2400 TCGv_i64 hh, lh, temp;
2402 uint64_t c;
2403 hh = tcg_temp_new_i64();
2404 lh = tcg_temp_new_i64();
2405 temp = tcg_temp_new_i64();
2407 c = 0xFFFFFFFF;
2409 if (sign) {
2410 tcg_gen_ext32s_i64(lh, a);
2411 tcg_gen_ext32s_i64(temp, b);
2412 } else {
2413 tcg_gen_andi_i64(lh, a, c);
2414 tcg_gen_andi_i64(temp, b, c);
2415 }
2416 tcg_gen_mul_i64(lh, lh, temp);
2418 if (sign) {
2419 tcg_gen_sari_i64(hh, a, 32);
2420 tcg_gen_sari_i64(temp, b, 32);
2421 } else {
2422 tcg_gen_shri_i64(hh, a, 32);
2423 tcg_gen_shri_i64(temp, b, 32);
2424 }
2425 tcg_gen_mul_i64(hh, hh, temp);
2427 tcg_gen_shri_i64(lh, lh, 32);
2428 tcg_gen_andi_i64(hh, hh, c << 32);
2429 tcg_gen_or_i64(t, hh, lh);
2431 tcg_temp_free_i64(hh);
2432 tcg_temp_free_i64(lh);
2433 tcg_temp_free_i64(temp);
2434 }
2436 static void do_vx_vmulhd_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
2437 {
2438 TCGv_i64 tlow;
2440 tlow = tcg_temp_new_i64();
2441 if (sign) {
2442 tcg_gen_muls2_i64(tlow, t, a, b);
2443 } else {
2444 tcg_gen_mulu2_i64(tlow, t, a, b);
2445 }
2447 tcg_temp_free_i64(tlow);
2448 }
2450 static bool do_vx_mulh(DisasContext *ctx, arg_VX *a, bool sign,
2451 void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, bool))
2452 {
2453 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2454 REQUIRE_VECTOR(ctx);
2456 TCGv_i64 vra, vrb, vrt;
2457 int i;
2459 vra = tcg_temp_new_i64();
2460 vrb = tcg_temp_new_i64();
2461 vrt = tcg_temp_new_i64();
2463 for (i = 0; i < 2; i++) {
2464 get_avr64(vra, a->vra, i);
2465 get_avr64(vrb, a->vrb, i);
2466 get_avr64(vrt, a->vrt, i);
2468 func(vrt, vra, vrb, sign);
2470 set_avr64(a->vrt, vrt, i);
2471 }
2473 tcg_temp_free_i64(vra);
2474 tcg_temp_free_i64(vrb);
2475 tcg_temp_free_i64(vrt);
2477 return true;
2479 }
2481 TRANS(VMULHSW, do_vx_mulh, true , do_vx_vmulhw_i64)
2482 TRANS(VMULHSD, do_vx_mulh, true , do_vx_vmulhd_i64)
2483 TRANS(VMULHUW, do_vx_mulh, false, do_vx_vmulhw_i64)
2484 TRANS(VMULHUD, do_vx_mulh, false, do_vx_vmulhd_i64)
2486 #undef GEN_VR_LDX
2487 #undef GEN_VR_STX
2488 #undef GEN_VR_LVE
2489 #undef GEN_VR_STVE
2491 #undef GEN_VX_LOGICAL
2492 #undef GEN_VX_LOGICAL_207
2493 #undef GEN_VXFORM
2494 #undef GEN_VXFORM_207
2495 #undef GEN_VXFORM_DUAL
2496 #undef GEN_VXRFORM_DUAL
2497 #undef GEN_VXRFORM1
2498 #undef GEN_VXRFORM
2499 #undef GEN_VXFORM_VSPLTI
2500 #undef GEN_VXFORM_NOA
2501 #undef GEN_VXFORM_UIMM
2502 #undef GEN_VAFORM_PAIRED
2504 #undef GEN_BCD2