target-arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 /* internal defines */
   5 typedef struct DisasContext {
   6     target_ulong pc;
   7     uint32_t insn;
   8     int is_jmp;
   9     /* Nonzero if this instruction has been conditionally skipped.  */
  10     int condjmp;
  11     /* The label that will be jumped to when the instruction is skipped.  */
  12     int condlabel;
  13     /* Thumb-2 conditional execution bits.  */
  14     int condexec_mask;
  15     int condexec_cond;
  16     struct TranslationBlock *tb;
  17     int singlestep_enabled;
  18     int thumb;
  19     int bswap_code;
  20 #if !defined(CONFIG_USER_ONLY)
  21     int user;
  22 #endif
  23     bool ns;        /* Use non-secure CPREG bank on access */
  24     bool cpacr_fpen; /* FP enabled via CPACR.FPEN */
  25     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  26     int vec_len;
  27     int vec_stride;
  28     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  29      * so that top level loop can generate correct syndrome information.
  30      */
  31     uint32_t svc_imm;
  32     int aarch64;
  33     int current_el;
  34     GHashTable *cp_regs;
  35     uint64_t features; /* CPU features bits */
  36     /* Because unallocated encodings generate different exception syndrome
  37      * information from traps due to FP being disabled, we can't do a single
  38      * "is fp access disabled" check at a high level in the decode tree.
  39      * To help in catching bugs where the access check was forgotten in some
  40      * code path, we set this flag when the access check is done, and assert
  41      * that it is set at the point where we actually touch the FP regs.
  42      */
  43     bool fp_access_checked;
  44     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  45      * single-step support).
  46      */
  47     bool ss_active;
  48     bool pstate_ss;
  49     /* True if the insn just emitted was a load-exclusive instruction
  50      * (necessary for syndrome information for single step exceptions),
  51      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  52      */
  53     bool is_ldex;
  54     /* True if a single-step exception will be taken to the current EL */
  55     bool ss_same_el;
  56     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  57     int c15_cpar;
  58 #define TMP_A64_MAX 16
  59     int tmp_a64_count;
  60     TCGv_i64 tmp_a64[TMP_A64_MAX];
  61 } DisasContext;
  62
  63 extern TCGv_ptr cpu_env;
  64
  65 static inline int arm_dc_feature(DisasContext *dc, int feature)
  66 {
  67     return (dc->features & (1ULL << feature)) != 0;
  68 }
  69
  70 static inline int get_mem_index(DisasContext *s)
  71 {
  72     return s->current_el;
  73 }
  74
  75 /* target-specific extra values for is_jmp */
  76 /* These instructions trap after executing, so the A32/T32 decoder must
  77  * defer them until after the conditional execution state has been updated.
  78  * WFI also needs special handling when single-stepping.
  79  */
  80 #define DISAS_WFI 4
  81 #define DISAS_SWI 5
  82 /* For instructions which unconditionally cause an exception we can skip
  83  * emitting unreachable code at the end of the TB in the A64 decoder
  84  */
  85 #define DISAS_EXC 6
  86 /* WFE */
  87 #define DISAS_WFE 7
  88 #define DISAS_HVC 8
  89 #define DISAS_SMC 9
  90
  91 #ifdef TARGET_AARCH64
  92 void a64_translate_init(void);
  93 void gen_intermediate_code_internal_a64(ARMCPU *cpu,
  94                                         TranslationBlock *tb,
  95                                         bool search_pc);
  96 void gen_a64_set_pc_im(uint64_t val);
  97 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
  98                             fprintf_function cpu_fprintf, int flags);
  99 #else
 100 static inline void a64_translate_init(void)
 101 {
 102 }
 103
 104 static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
 105                                                       TranslationBlock *tb,
 106                                                       bool search_pc)
 107 {
 108 }
 109
 110 static inline void gen_a64_set_pc_im(uint64_t val)
 111 {
 112 }
 113
 114 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 115                                           fprintf_function cpu_fprintf,
 116                                           int flags)
 117 {
 118 }
 119 #endif
 120
 121 void arm_gen_test_cc(int cc, int label);
 122
 123 #endif /* TARGET_ARM_TRANSLATE_H */