hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "apb_pci.h"
  27 #include "pc.h"
  28 #include "nvram.h"
  29 #include "fdc.h"
  30 #include "net.h"
  31 #include "qemu-timer.h"
  32 #include "sysemu.h"
  33 #include "boards.h"
  34 #include "firmware_abi.h"
  35 #include "fw_cfg.h"
  36 #include "sysbus.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "elf.h"
  40
  41 //#define DEBUG_IRQ
  42 //#define DEBUG_EBUS
  43
  44 #ifdef DEBUG_IRQ
  45 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  46     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  47 #else
  48 #define CPUIRQ_DPRINTF(fmt, ...)
  49 #endif
  50
  51 #ifdef DEBUG_EBUS
  52 #define EBUS_DPRINTF(fmt, ...)                                  \
  53     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  54 #else
  55 #define EBUS_DPRINTF(fmt, ...)
  56 #endif
  57
  58 #define KERNEL_LOAD_ADDR     0x00404000
  59 #define CMDLINE_ADDR         0x003ff000
  60 #define INITRD_LOAD_ADDR     0x00300000
  61 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  62 #define PROM_VADDR           0x000ffd00000ULL
  63 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  64 #define APB_MEM_BASE         0x1ff00000000ULL
  65 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  66 #define PROM_FILENAME        "openbios-sparc64"
  67 #define NVRAM_SIZE           0x2000
  68 #define MAX_IDE_BUS          2
  69 #define BIOS_CFG_IOPORT      0x510
  70 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  71 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  72 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  73
  74 #define MAX_PILS 16
  75
  76 #define TICK_INT_DIS         0x8000000000000000ULL
  77 #define TICK_MAX             0x7fffffffffffffffULL
  78
  79 struct hwdef {
  80     const char * const default_cpu_model;
  81     uint16_t machine_id;
  82     uint64_t prom_addr;
  83     uint64_t console_serial_base;
  84 };
  85
  86 int DMA_get_channel_mode (int nchan)
  87 {
  88     return 0;
  89 }
  90 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  91 {
  92     return 0;
  93 }
  94 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  95 {
  96     return 0;
  97 }
  98 void DMA_hold_DREQ (int nchan) {}
  99 void DMA_release_DREQ (int nchan) {}
 100 void DMA_schedule(int nchan) {}
 101 void DMA_init (int high_page_enable) {}
 102 void DMA_register_channel (int nchan,
 103                            DMA_transfer_handler transfer_handler,
 104                            void *opaque)
 105 {
 106 }
 107
 108 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 109 {
 110     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 111     return 0;
 112 }
 113
 114 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 115                                    const char *arch,
 116                                    ram_addr_t RAM_size,
 117                                    const char *boot_devices,
 118                                    uint32_t kernel_image, uint32_t kernel_size,
 119                                    const char *cmdline,
 120                                    uint32_t initrd_image, uint32_t initrd_size,
 121                                    uint32_t NVRAM_image,
 122                                    int width, int height, int depth,
 123                                    const uint8_t *macaddr)
 124 {
 125     unsigned int i;
 126     uint32_t start, end;
 127     uint8_t image[0x1ff0];
 128     struct OpenBIOS_nvpart_v1 *part_header;
 129
 130     memset(image, '\0', sizeof(image));
 131
 132     start = 0;
 133
 134     // OpenBIOS nvram variables
 135     // Variable partition
 136     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 137     part_header->signature = OPENBIOS_PART_SYSTEM;
 138     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 139
 140     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 141     for (i = 0; i < nb_prom_envs; i++)
 142         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 143
 144     // End marker
 145     image[end++] = '\0';
 146
 147     end = start + ((end - start + 15) & ~15);
 148     OpenBIOS_finish_partition(part_header, end - start);
 149
 150     // free partition
 151     start = end;
 152     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 153     part_header->signature = OPENBIOS_PART_FREE;
 154     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 155
 156     end = 0x1fd0;
 157     OpenBIOS_finish_partition(part_header, end - start);
 158
 159     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 160
 161     for (i = 0; i < sizeof(image); i++)
 162         m48t59_write(nvram, i, image[i]);
 163
 164     return 0;
 165 }
 166 static unsigned long sun4u_load_kernel(const char *kernel_filename,
 167                                        const char *initrd_filename,
 168                                        ram_addr_t RAM_size, long *initrd_size)
 169 {
 170     int linux_boot;
 171     unsigned int i;
 172     long kernel_size;
 173
 174     linux_boot = (kernel_filename != NULL);
 175
 176     kernel_size = 0;
 177     if (linux_boot) {
 178         int bswap_needed;
 179
 180 #ifdef BSWAP_NEEDED
 181         bswap_needed = 1;
 182 #else
 183         bswap_needed = 0;
 184 #endif
 185         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL,
 186                                1, ELF_MACHINE, 0);
 187         if (kernel_size < 0)
 188             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 189                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 190                                     TARGET_PAGE_SIZE);
 191         if (kernel_size < 0)
 192             kernel_size = load_image_targphys(kernel_filename,
 193                                               KERNEL_LOAD_ADDR,
 194                                               RAM_size - KERNEL_LOAD_ADDR);
 195         if (kernel_size < 0) {
 196             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 197                     kernel_filename);
 198             exit(1);
 199         }
 200
 201         /* load initrd */
 202         *initrd_size = 0;
 203         if (initrd_filename) {
 204             *initrd_size = load_image_targphys(initrd_filename,
 205                                                INITRD_LOAD_ADDR,
 206                                                RAM_size - INITRD_LOAD_ADDR);
 207             if (*initrd_size < 0) {
 208                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 209                         initrd_filename);
 210                 exit(1);
 211             }
 212         }
 213         if (*initrd_size > 0) {
 214             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 215                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 216                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 217                     stl_phys(KERNEL_LOAD_ADDR + i + 20, *initrd_size);
 218                     break;
 219                 }
 220             }
 221         }
 222     }
 223     return kernel_size;
 224 }
 225
 226 void pic_info(Monitor *mon)
 227 {
 228 }
 229
 230 void irq_info(Monitor *mon)
 231 {
 232 }
 233
 234 void cpu_check_irqs(CPUState *env)
 235 {
 236     uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
 237         ((env->softint & SOFTINT_TIMER) << 14);
 238
 239     if (pil && (env->interrupt_index == 0 ||
 240                 (env->interrupt_index & ~15) == TT_EXTINT)) {
 241         unsigned int i;
 242
 243         for (i = 15; i > 0; i--) {
 244             if (pil & (1 << i)) {
 245                 int old_interrupt = env->interrupt_index;
 246
 247                 env->interrupt_index = TT_EXTINT | i;
 248                 if (old_interrupt != env->interrupt_index) {
 249                     CPUIRQ_DPRINTF("Set CPU IRQ %d\n", i);
 250                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 251                 }
 252                 break;
 253             }
 254         }
 255     } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
 256         CPUIRQ_DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
 257         env->interrupt_index = 0;
 258         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 259     }
 260 }
 261
 262 static void cpu_set_irq(void *opaque, int irq, int level)
 263 {
 264     CPUState *env = opaque;
 265
 266     if (level) {
 267         CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
 268         env->halted = 0;
 269         env->pil_in |= 1 << irq;
 270         cpu_check_irqs(env);
 271     } else {
 272         CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
 273         env->pil_in &= ~(1 << irq);
 274         cpu_check_irqs(env);
 275     }
 276 }
 277
 278 typedef struct ResetData {
 279     CPUState *env;
 280     uint64_t prom_addr;
 281 } ResetData;
 282
 283 static void main_cpu_reset(void *opaque)
 284 {
 285     ResetData *s = (ResetData *)opaque;
 286     CPUState *env = s->env;
 287     static unsigned int nr_resets;
 288
 289     cpu_reset(env);
 290     env->tick_cmpr = TICK_INT_DIS | 0;
 291     ptimer_set_limit(env->tick, TICK_MAX, 1);
 292     ptimer_run(env->tick, 1);
 293     env->stick_cmpr = TICK_INT_DIS | 0;
 294     ptimer_set_limit(env->stick, TICK_MAX, 1);
 295     ptimer_run(env->stick, 1);
 296     env->hstick_cmpr = TICK_INT_DIS | 0;
 297     ptimer_set_limit(env->hstick, TICK_MAX, 1);
 298     ptimer_run(env->hstick, 1);
 299     env->gregs[1] = 0; // Memory start
 300     env->gregs[2] = ram_size; // Memory size
 301     env->gregs[3] = 0; // Machine description XXX
 302     if (nr_resets++ == 0) {
 303         /* Power on reset */
 304         env->pc = s->prom_addr + 0x20ULL;
 305     } else {
 306         env->pc = s->prom_addr + 0x40ULL;
 307     }
 308     env->npc = env->pc + 4;
 309 }
 310
 311 static void tick_irq(void *opaque)
 312 {
 313     CPUState *env = opaque;
 314
 315     if (!(env->tick_cmpr & TICK_INT_DIS)) {
 316         env->softint |= SOFTINT_TIMER;
 317         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 318     }
 319 }
 320
 321 static void stick_irq(void *opaque)
 322 {
 323     CPUState *env = opaque;
 324
 325     if (!(env->stick_cmpr & TICK_INT_DIS)) {
 326         env->softint |= SOFTINT_STIMER;
 327         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 328     }
 329 }
 330
 331 static void hstick_irq(void *opaque)
 332 {
 333     CPUState *env = opaque;
 334
 335     if (!(env->hstick_cmpr & TICK_INT_DIS)) {
 336         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 337     }
 338 }
 339
 340 void cpu_tick_set_count(void *opaque, uint64_t count)
 341 {
 342     ptimer_set_count(opaque, -count);
 343 }
 344
 345 uint64_t cpu_tick_get_count(void *opaque)
 346 {
 347     return -ptimer_get_count(opaque);
 348 }
 349
 350 void cpu_tick_set_limit(void *opaque, uint64_t limit)
 351 {
 352     ptimer_set_limit(opaque, -limit, 0);
 353 }
 354
 355 static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
 356                               pcibus_t addr, pcibus_t size, int type)
 357 {
 358     EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n",
 359                  region_num, addr);
 360     switch (region_num) {
 361     case 0:
 362         isa_mmio_init(addr, 0x1000000);
 363         break;
 364     case 1:
 365         isa_mmio_init(addr, 0x800000);
 366         break;
 367     }
 368 }
 369
 370 static void dummy_isa_irq_handler(void *opaque, int n, int level)
 371 {
 372 }
 373
 374 /* EBUS (Eight bit bus) bridge */
 375 static void
 376 pci_ebus_init(PCIBus *bus, int devfn)
 377 {
 378     qemu_irq *isa_irq;
 379
 380     pci_create_simple(bus, devfn, "ebus");
 381     isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
 382     isa_bus_irqs(isa_irq);
 383 }
 384
 385 static int
 386 pci_ebus_init1(PCIDevice *s)
 387 {
 388     isa_bus_new(&s->qdev);
 389
 390     pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
 391     pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
 392     s->config[0x04] = 0x06; // command = bus master, pci mem
 393     s->config[0x05] = 0x00;
 394     s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 395     s->config[0x07] = 0x03; // status = medium devsel
 396     s->config[0x08] = 0x01; // revision
 397     s->config[0x09] = 0x00; // programming i/f
 398     pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
 399     s->config[0x0D] = 0x0a; // latency_timer
 400     s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 401
 402     pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY,
 403                            ebus_mmio_mapfunc);
 404     pci_register_bar(s, 1, 0x800000,  PCI_BASE_ADDRESS_SPACE_MEMORY,
 405                            ebus_mmio_mapfunc);
 406     return 0;
 407 }
 408
 409 static PCIDeviceInfo ebus_info = {
 410     .qdev.name = "ebus",
 411     .qdev.size = sizeof(PCIDevice),
 412     .init = pci_ebus_init1,
 413 };
 414
 415 static void pci_ebus_register(void)
 416 {
 417     pci_qdev_register(&ebus_info);
 418 }
 419
 420 device_init(pci_ebus_register);
 421
 422 /* Boot PROM (OpenBIOS) */
 423 static void prom_init(target_phys_addr_t addr, const char *bios_name)
 424 {
 425     DeviceState *dev;
 426     SysBusDevice *s;
 427     char *filename;
 428     int ret;
 429
 430     dev = qdev_create(NULL, "openprom");
 431     qdev_init_nofail(dev);
 432     s = sysbus_from_qdev(dev);
 433
 434     sysbus_mmio_map(s, 0, addr);
 435
 436     /* load boot prom */
 437     if (bios_name == NULL) {
 438         bios_name = PROM_FILENAME;
 439     }
 440     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 441     if (filename) {
 442         ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL,
 443                        1, ELF_MACHINE, 0);
 444         if (ret < 0 || ret > PROM_SIZE_MAX) {
 445             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 446         }
 447         qemu_free(filename);
 448     } else {
 449         ret = -1;
 450     }
 451     if (ret < 0 || ret > PROM_SIZE_MAX) {
 452         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 453         exit(1);
 454     }
 455 }
 456
 457 static int prom_init1(SysBusDevice *dev)
 458 {
 459     ram_addr_t prom_offset;
 460
 461     prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
 462     sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
 463     return 0;
 464 }
 465
 466 static SysBusDeviceInfo prom_info = {
 467     .init = prom_init1,
 468     .qdev.name  = "openprom",
 469     .qdev.size  = sizeof(SysBusDevice),
 470     .qdev.props = (Property[]) {
 471         {/* end of property list */}
 472     }
 473 };
 474
 475 static void prom_register_devices(void)
 476 {
 477     sysbus_register_withprop(&prom_info);
 478 }
 479
 480 device_init(prom_register_devices);
 481
 482
 483 typedef struct RamDevice
 484 {
 485     SysBusDevice busdev;
 486     uint64_t size;
 487 } RamDevice;
 488
 489 /* System RAM */
 490 static int ram_init1(SysBusDevice *dev)
 491 {
 492     ram_addr_t RAM_size, ram_offset;
 493     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 494
 495     RAM_size = d->size;
 496
 497     ram_offset = qemu_ram_alloc(RAM_size);
 498     sysbus_init_mmio(dev, RAM_size, ram_offset);
 499     return 0;
 500 }
 501
 502 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
 503 {
 504     DeviceState *dev;
 505     SysBusDevice *s;
 506     RamDevice *d;
 507
 508     /* allocate RAM */
 509     dev = qdev_create(NULL, "memory");
 510     s = sysbus_from_qdev(dev);
 511
 512     d = FROM_SYSBUS(RamDevice, s);
 513     d->size = RAM_size;
 514     qdev_init_nofail(dev);
 515
 516     sysbus_mmio_map(s, 0, addr);
 517 }
 518
 519 static SysBusDeviceInfo ram_info = {
 520     .init = ram_init1,
 521     .qdev.name  = "memory",
 522     .qdev.size  = sizeof(RamDevice),
 523     .qdev.props = (Property[]) {
 524         DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 525         DEFINE_PROP_END_OF_LIST(),
 526     }
 527 };
 528
 529 static void ram_register_devices(void)
 530 {
 531     sysbus_register_withprop(&ram_info);
 532 }
 533
 534 device_init(ram_register_devices);
 535
 536 static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 537 {
 538     CPUState *env;
 539     QEMUBH *bh;
 540     ResetData *reset_info;
 541
 542     if (!cpu_model)
 543         cpu_model = hwdef->default_cpu_model;
 544     env = cpu_init(cpu_model);
 545     if (!env) {
 546         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 547         exit(1);
 548     }
 549     bh = qemu_bh_new(tick_irq, env);
 550     env->tick = ptimer_init(bh);
 551     ptimer_set_period(env->tick, 1ULL);
 552
 553     bh = qemu_bh_new(stick_irq, env);
 554     env->stick = ptimer_init(bh);
 555     ptimer_set_period(env->stick, 1ULL);
 556
 557     bh = qemu_bh_new(hstick_irq, env);
 558     env->hstick = ptimer_init(bh);
 559     ptimer_set_period(env->hstick, 1ULL);
 560
 561     reset_info = qemu_mallocz(sizeof(ResetData));
 562     reset_info->env = env;
 563     reset_info->prom_addr = hwdef->prom_addr;
 564     qemu_register_reset(main_cpu_reset, reset_info);
 565
 566     return env;
 567 }
 568
 569 static void sun4uv_init(ram_addr_t RAM_size,
 570                         const char *boot_devices,
 571                         const char *kernel_filename, const char *kernel_cmdline,
 572                         const char *initrd_filename, const char *cpu_model,
 573                         const struct hwdef *hwdef)
 574 {
 575     CPUState *env;
 576     m48t59_t *nvram;
 577     unsigned int i;
 578     long initrd_size, kernel_size;
 579     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 580     qemu_irq *irq;
 581     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 582     DriveInfo *fd[MAX_FD];
 583     void *fw_cfg;
 584
 585     /* init CPUs */
 586     env = cpu_devinit(cpu_model, hwdef);
 587
 588     /* set up devices */
 589     ram_init(0, RAM_size);
 590
 591     prom_init(hwdef->prom_addr, bios_name);
 592
 593
 594     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 595     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
 596                            &pci_bus3);
 597     isa_mem_base = VGA_BASE;
 598     pci_vga_init(pci_bus, 0, 0);
 599
 600     // XXX Should be pci_bus3
 601     pci_ebus_init(pci_bus, -1);
 602
 603     i = 0;
 604     if (hwdef->console_serial_base) {
 605         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 606                        serial_hds[i], 1);
 607         i++;
 608     }
 609     for(; i < MAX_SERIAL_PORTS; i++) {
 610         if (serial_hds[i]) {
 611             serial_isa_init(i, serial_hds[i]);
 612         }
 613     }
 614
 615     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 616         if (parallel_hds[i]) {
 617             parallel_init(i, parallel_hds[i]);
 618         }
 619     }
 620
 621     for(i = 0; i < nb_nics; i++)
 622         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 623
 624     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 625         fprintf(stderr, "qemu: too many IDE bus\n");
 626         exit(1);
 627     }
 628     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 629         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS,
 630                           i % MAX_IDE_DEVS);
 631     }
 632
 633     pci_cmd646_ide_init(pci_bus, hd, 1);
 634
 635     isa_create_simple("i8042");
 636     for(i = 0; i < MAX_FD; i++) {
 637         fd[i] = drive_get(IF_FLOPPY, 0, i);
 638     }
 639     fdctrl_init_isa(fd);
 640     nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59);
 641
 642     initrd_size = 0;
 643     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 644                                     ram_size, &initrd_size);
 645
 646     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 647                            KERNEL_LOAD_ADDR, kernel_size,
 648                            kernel_cmdline,
 649                            INITRD_LOAD_ADDR, initrd_size,
 650                            /* XXX: need an option to load a NVRAM image */
 651                            0,
 652                            graphic_width, graphic_height, graphic_depth,
 653                            (uint8_t *)&nd_table[0].macaddr);
 654
 655     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 656     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 657     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 658     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 659     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
 660     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 661     if (kernel_cmdline) {
 662         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 663         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 664         fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 665                          (uint8_t*)strdup(kernel_cmdline),
 666                          strlen(kernel_cmdline) + 1);
 667     } else {
 668         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 669     }
 670     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
 671     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 672     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 673
 674     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 675     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 676     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 677
 678     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 679 }
 680
 681 enum {
 682     sun4u_id = 0,
 683     sun4v_id = 64,
 684     niagara_id,
 685 };
 686
 687 static const struct hwdef hwdefs[] = {
 688     /* Sun4u generic PC-like machine */
 689     {
 690         .default_cpu_model = "TI UltraSparc II",
 691         .machine_id = sun4u_id,
 692         .prom_addr = 0x1fff0000000ULL,
 693         .console_serial_base = 0,
 694     },
 695     /* Sun4v generic PC-like machine */
 696     {
 697         .default_cpu_model = "Sun UltraSparc T1",
 698         .machine_id = sun4v_id,
 699         .prom_addr = 0x1fff0000000ULL,
 700         .console_serial_base = 0,
 701     },
 702     /* Sun4v generic Niagara machine */
 703     {
 704         .default_cpu_model = "Sun UltraSparc T1",
 705         .machine_id = niagara_id,
 706         .prom_addr = 0xfff0000000ULL,
 707         .console_serial_base = 0xfff0c2c000ULL,
 708     },
 709 };
 710
 711 /* Sun4u hardware initialisation */
 712 static void sun4u_init(ram_addr_t RAM_size,
 713                        const char *boot_devices,
 714                        const char *kernel_filename, const char *kernel_cmdline,
 715                        const char *initrd_filename, const char *cpu_model)
 716 {
 717     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 718                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 719 }
 720
 721 /* Sun4v hardware initialisation */
 722 static void sun4v_init(ram_addr_t RAM_size,
 723                        const char *boot_devices,
 724                        const char *kernel_filename, const char *kernel_cmdline,
 725                        const char *initrd_filename, const char *cpu_model)
 726 {
 727     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 728                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 729 }
 730
 731 /* Niagara hardware initialisation */
 732 static void niagara_init(ram_addr_t RAM_size,
 733                          const char *boot_devices,
 734                          const char *kernel_filename, const char *kernel_cmdline,
 735                          const char *initrd_filename, const char *cpu_model)
 736 {
 737     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 738                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 739 }
 740
 741 static QEMUMachine sun4u_machine = {
 742     .name = "sun4u",
 743     .desc = "Sun4u platform",
 744     .init = sun4u_init,
 745     .max_cpus = 1, // XXX for now
 746     .is_default = 1,
 747 };
 748
 749 static QEMUMachine sun4v_machine = {
 750     .name = "sun4v",
 751     .desc = "Sun4v platform",
 752     .init = sun4v_init,
 753     .max_cpus = 1, // XXX for now
 754 };
 755
 756 static QEMUMachine niagara_machine = {
 757     .name = "Niagara",
 758     .desc = "Sun4v platform, Niagara",
 759     .init = niagara_init,
 760     .max_cpus = 1, // XXX for now
 761 };
 762
 763 static void sun4u_machine_init(void)
 764 {
 765     qemu_register_machine(&sun4u_machine);
 766     qemu_register_machine(&sun4v_machine);
 767     qemu_register_machine(&niagara_machine);
 768 }
 769
 770 machine_init(sun4u_machine_init);