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cadence_gem: initial version of device model
[qemu.git] / hw / vga.c
blob5994f43b757afccbddd6695d9208dc0f81e334ae
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "vga.h"
26 #include "console.h"
27 #include "pc.h"
28 #include "pci.h"
29 #include "vga_int.h"
30 #include "pixel_ops.h"
31 #include "qemu-timer.h"
32 #include "xen.h"
33
34 //#define DEBUG_VGA
35 //#define DEBUG_VGA_MEM
36 //#define DEBUG_VGA_REG
37
38 //#define DEBUG_BOCHS_VBE
39
40 /*
41 * Video Graphics Array (VGA)
42 *
43 * Chipset docs for original IBM VGA:
44 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
45 *
46 * FreeVGA site:
47 * http://www.osdever.net/FreeVGA/home.htm
48 *
49 * Standard VGA features and Bochs VBE extensions are implemented.
50 */
51
52 /* force some bits to zero */
53 const uint8_t sr_mask[8] = {
54 0x03,
55 0x3d,
56 0x0f,
57 0x3f,
58 0x0e,
59 0x00,
60 0x00,
61 0xff,
62 };
63
64 const uint8_t gr_mask[16] = {
65 0x0f, /* 0x00 */
66 0x0f, /* 0x01 */
67 0x0f, /* 0x02 */
68 0x1f, /* 0x03 */
69 0x03, /* 0x04 */
70 0x7b, /* 0x05 */
71 0x0f, /* 0x06 */
72 0x0f, /* 0x07 */
73 0xff, /* 0x08 */
74 0x00, /* 0x09 */
75 0x00, /* 0x0a */
76 0x00, /* 0x0b */
77 0x00, /* 0x0c */
78 0x00, /* 0x0d */
79 0x00, /* 0x0e */
80 0x00, /* 0x0f */
81 };
82
83 #define cbswap_32(__x) \
84 ((uint32_t)( \
85 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
86 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
87 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
88 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
89
90 #ifdef HOST_WORDS_BIGENDIAN
91 #define PAT(x) cbswap_32(x)
92 #else
93 #define PAT(x) (x)
94 #endif
95
96 #ifdef HOST_WORDS_BIGENDIAN
97 #define BIG 1
98 #else
99 #define BIG 0
100 #endif
101
102 #ifdef HOST_WORDS_BIGENDIAN
103 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
104 #else
105 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
106 #endif
107
108 static const uint32_t mask16[16] = {
109 PAT(0x00000000),
110 PAT(0x000000ff),
111 PAT(0x0000ff00),
112 PAT(0x0000ffff),
113 PAT(0x00ff0000),
114 PAT(0x00ff00ff),
115 PAT(0x00ffff00),
116 PAT(0x00ffffff),
117 PAT(0xff000000),
118 PAT(0xff0000ff),
119 PAT(0xff00ff00),
120 PAT(0xff00ffff),
121 PAT(0xffff0000),
122 PAT(0xffff00ff),
123 PAT(0xffffff00),
124 PAT(0xffffffff),
125 };
126
127 #undef PAT
128
129 #ifdef HOST_WORDS_BIGENDIAN
130 #define PAT(x) (x)
131 #else
132 #define PAT(x) cbswap_32(x)
133 #endif
134
135 static const uint32_t dmask16[16] = {
136 PAT(0x00000000),
137 PAT(0x000000ff),
138 PAT(0x0000ff00),
139 PAT(0x0000ffff),
140 PAT(0x00ff0000),
141 PAT(0x00ff00ff),
142 PAT(0x00ffff00),
143 PAT(0x00ffffff),
144 PAT(0xff000000),
145 PAT(0xff0000ff),
146 PAT(0xff00ff00),
147 PAT(0xff00ffff),
148 PAT(0xffff0000),
149 PAT(0xffff00ff),
150 PAT(0xffffff00),
151 PAT(0xffffffff),
152 };
153
154 static const uint32_t dmask4[4] = {
155 PAT(0x00000000),
156 PAT(0x0000ffff),
157 PAT(0xffff0000),
158 PAT(0xffffffff),
159 };
160
161 static uint32_t expand4[256];
162 static uint16_t expand2[256];
163 static uint8_t expand4to8[16];
164
165 static void vga_screen_dump(void *opaque, const char *filename, bool cswitch);
166
167 static void vga_update_memory_access(VGACommonState *s)
168 {
169 MemoryRegion *region, *old_region = s->chain4_alias;
170 target_phys_addr_t base, offset, size;
171
172 s->chain4_alias = NULL;
173
174 if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
175 VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
176 offset = 0;
177 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
178 case 0:
179 base = 0xa0000;
180 size = 0x20000;
181 break;
182 case 1:
183 base = 0xa0000;
184 size = 0x10000;
185 offset = s->bank_offset;
186 break;
187 case 2:
188 base = 0xb0000;
189 size = 0x8000;
190 break;
191 case 3:
192 default:
193 base = 0xb8000;
194 size = 0x8000;
195 break;
196 }
197 base += isa_mem_base;
198 region = g_malloc(sizeof(*region));
199 memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);
200 memory_region_add_subregion_overlap(s->legacy_address_space, base,
201 region, 2);
202 s->chain4_alias = region;
203 }
204 if (old_region) {
205 memory_region_del_subregion(s->legacy_address_space, old_region);
206 memory_region_destroy(old_region);
207 g_free(old_region);
208 s->plane_updated = 0xf;
209 }
210 }
211
212 static void vga_dumb_update_retrace_info(VGACommonState *s)
213 {
214 (void) s;
215 }
216
217 static void vga_precise_update_retrace_info(VGACommonState *s)
218 {
219 int htotal_chars;
220 int hretr_start_char;
221 int hretr_skew_chars;
222 int hretr_end_char;
223
224 int vtotal_lines;
225 int vretr_start_line;
226 int vretr_end_line;
227
228 int dots;
229 #if 0
230 int div2, sldiv2;
231 #endif
232 int clocking_mode;
233 int clock_sel;
234 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
235 int64_t chars_per_sec;
236 struct vga_precise_retrace *r = &s->retrace_info.precise;
237
238 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
239 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
240 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
241 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
242
243 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
244 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
245 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
246 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
247 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
248 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
249 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
250
251 clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;
252 clock_sel = (s->msr >> 2) & 3;
253 dots = (s->msr & 1) ? 8 : 9;
254
255 chars_per_sec = clk_hz[clock_sel] / dots;
256
257 htotal_chars <<= clocking_mode;
258
259 r->total_chars = vtotal_lines * htotal_chars;
260 if (r->freq) {
261 r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
262 } else {
263 r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
264 }
265
266 r->vstart = vretr_start_line;
267 r->vend = r->vstart + vretr_end_line + 1;
268
269 r->hstart = hretr_start_char + hretr_skew_chars;
270 r->hend = r->hstart + hretr_end_char + 1;
271 r->htotal = htotal_chars;
272
273 #if 0
274 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
275 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
276 printf (
277 "hz=%f\n"
278 "htotal = %d\n"
279 "hretr_start = %d\n"
280 "hretr_skew = %d\n"
281 "hretr_end = %d\n"
282 "vtotal = %d\n"
283 "vretr_start = %d\n"
284 "vretr_end = %d\n"
285 "div2 = %d sldiv2 = %d\n"
286 "clocking_mode = %d\n"
287 "clock_sel = %d %d\n"
288 "dots = %d\n"
289 "ticks/char = %" PRId64 "\n"
290 "\n",
291 (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
292 htotal_chars,
293 hretr_start_char,
294 hretr_skew_chars,
295 hretr_end_char,
296 vtotal_lines,
297 vretr_start_line,
298 vretr_end_line,
299 div2, sldiv2,
300 clocking_mode,
301 clock_sel,
302 clk_hz[clock_sel],
303 dots,
304 r->ticks_per_char
305 );
306 #endif
307 }
308
309 static uint8_t vga_precise_retrace(VGACommonState *s)
310 {
311 struct vga_precise_retrace *r = &s->retrace_info.precise;
312 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
313
314 if (r->total_chars) {
315 int cur_line, cur_line_char, cur_char;
316 int64_t cur_tick;
317
318 cur_tick = qemu_get_clock_ns(vm_clock);
319
320 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
321 cur_line = cur_char / r->htotal;
322
323 if (cur_line >= r->vstart && cur_line <= r->vend) {
324 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
325 } else {
326 cur_line_char = cur_char % r->htotal;
327 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
328 val |= ST01_DISP_ENABLE;
329 }
330 }
331
332 return val;
333 } else {
334 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
335 }
336 }
337
338 static uint8_t vga_dumb_retrace(VGACommonState *s)
339 {
340 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
341 }
342
343 int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
344 {
345 if (s->msr & VGA_MIS_COLOR) {
346 /* Color */
347 return (addr >= 0x3b0 && addr <= 0x3bf);
348 } else {
349 /* Monochrome */
350 return (addr >= 0x3d0 && addr <= 0x3df);
351 }
352 }
353
354 uint32_t vga_ioport_read(void *opaque, uint32_t addr)
355 {
356 VGACommonState *s = opaque;
357 int val, index;
358
359 if (vga_ioport_invalid(s, addr)) {
360 val = 0xff;
361 } else {
362 switch(addr) {
363 case VGA_ATT_W:
364 if (s->ar_flip_flop == 0) {
365 val = s->ar_index;
366 } else {
367 val = 0;
368 }
369 break;
370 case VGA_ATT_R:
371 index = s->ar_index & 0x1f;
372 if (index < VGA_ATT_C) {
373 val = s->ar[index];
374 } else {
375 val = 0;
376 }
377 break;
378 case VGA_MIS_W:
379 val = s->st00;
380 break;
381 case VGA_SEQ_I:
382 val = s->sr_index;
383 break;
384 case VGA_SEQ_D:
385 val = s->sr[s->sr_index];
386 #ifdef DEBUG_VGA_REG
387 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
388 #endif
389 break;
390 case VGA_PEL_IR:
391 val = s->dac_state;
392 break;
393 case VGA_PEL_IW:
394 val = s->dac_write_index;
395 break;
396 case VGA_PEL_D:
397 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
398 if (++s->dac_sub_index == 3) {
399 s->dac_sub_index = 0;
400 s->dac_read_index++;
401 }
402 break;
403 case VGA_FTC_R:
404 val = s->fcr;
405 break;
406 case VGA_MIS_R:
407 val = s->msr;
408 break;
409 case VGA_GFX_I:
410 val = s->gr_index;
411 break;
412 case VGA_GFX_D:
413 val = s->gr[s->gr_index];
414 #ifdef DEBUG_VGA_REG
415 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
416 #endif
417 break;
418 case VGA_CRT_IM:
419 case VGA_CRT_IC:
420 val = s->cr_index;
421 break;
422 case VGA_CRT_DM:
423 case VGA_CRT_DC:
424 val = s->cr[s->cr_index];
425 #ifdef DEBUG_VGA_REG
426 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
427 #endif
428 break;
429 case VGA_IS1_RM:
430 case VGA_IS1_RC:
431 /* just toggle to fool polling */
432 val = s->st01 = s->retrace(s);
433 s->ar_flip_flop = 0;
434 break;
435 default:
436 val = 0x00;
437 break;
438 }
439 }
440 #if defined(DEBUG_VGA)
441 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
442 #endif
443 return val;
444 }
445
446 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
447 {
448 VGACommonState *s = opaque;
449 int index;
450
451 /* check port range access depending on color/monochrome mode */
452 if (vga_ioport_invalid(s, addr)) {
453 return;
454 }
455 #ifdef DEBUG_VGA
456 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
457 #endif
458
459 switch(addr) {
460 case VGA_ATT_W:
461 if (s->ar_flip_flop == 0) {
462 val &= 0x3f;
463 s->ar_index = val;
464 } else {
465 index = s->ar_index & 0x1f;
466 switch(index) {
467 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
468 s->ar[index] = val & 0x3f;
469 break;
470 case VGA_ATC_MODE:
471 s->ar[index] = val & ~0x10;
472 break;
473 case VGA_ATC_OVERSCAN:
474 s->ar[index] = val;
475 break;
476 case VGA_ATC_PLANE_ENABLE:
477 s->ar[index] = val & ~0xc0;
478 break;
479 case VGA_ATC_PEL:
480 s->ar[index] = val & ~0xf0;
481 break;
482 case VGA_ATC_COLOR_PAGE:
483 s->ar[index] = val & ~0xf0;
484 break;
485 default:
486 break;
487 }
488 }
489 s->ar_flip_flop ^= 1;
490 break;
491 case VGA_MIS_W:
492 s->msr = val & ~0x10;
493 s->update_retrace_info(s);
494 break;
495 case VGA_SEQ_I:
496 s->sr_index = val & 7;
497 break;
498 case VGA_SEQ_D:
499 #ifdef DEBUG_VGA_REG
500 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
501 #endif
502 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
503 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
504 s->update_retrace_info(s);
505 }
506 vga_update_memory_access(s);
507 break;
508 case VGA_PEL_IR:
509 s->dac_read_index = val;
510 s->dac_sub_index = 0;
511 s->dac_state = 3;
512 break;
513 case VGA_PEL_IW:
514 s->dac_write_index = val;
515 s->dac_sub_index = 0;
516 s->dac_state = 0;
517 break;
518 case VGA_PEL_D:
519 s->dac_cache[s->dac_sub_index] = val;
520 if (++s->dac_sub_index == 3) {
521 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
522 s->dac_sub_index = 0;
523 s->dac_write_index++;
524 }
525 break;
526 case VGA_GFX_I:
527 s->gr_index = val & 0x0f;
528 break;
529 case VGA_GFX_D:
530 #ifdef DEBUG_VGA_REG
531 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
532 #endif
533 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
534 vga_update_memory_access(s);
535 break;
536 case VGA_CRT_IM:
537 case VGA_CRT_IC:
538 s->cr_index = val;
539 break;
540 case VGA_CRT_DM:
541 case VGA_CRT_DC:
542 #ifdef DEBUG_VGA_REG
543 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
544 #endif
545 /* handle CR0-7 protection */
546 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
547 s->cr_index <= VGA_CRTC_OVERFLOW) {
548 /* can always write bit 4 of CR7 */
549 if (s->cr_index == VGA_CRTC_OVERFLOW) {
550 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
551 (val & 0x10);
552 }
553 return;
554 }
555 s->cr[s->cr_index] = val;
556
557 switch(s->cr_index) {
558 case VGA_CRTC_H_TOTAL:
559 case VGA_CRTC_H_SYNC_START:
560 case VGA_CRTC_H_SYNC_END:
561 case VGA_CRTC_V_TOTAL:
562 case VGA_CRTC_OVERFLOW:
563 case VGA_CRTC_V_SYNC_END:
564 case VGA_CRTC_MODE:
565 s->update_retrace_info(s);
566 break;
567 }
568 break;
569 case VGA_IS1_RM:
570 case VGA_IS1_RC:
571 s->fcr = val & 0x10;
572 break;
573 }
574 }
575
576 #ifdef CONFIG_BOCHS_VBE
577 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
578 {
579 VGACommonState *s = opaque;
580 uint32_t val;
581 val = s->vbe_index;
582 return val;
583 }
584
585 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
586 {
587 VGACommonState *s = opaque;
588 uint32_t val;
589
590 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
591 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
592 switch(s->vbe_index) {
593 /* XXX: do not hardcode ? */
594 case VBE_DISPI_INDEX_XRES:
595 val = VBE_DISPI_MAX_XRES;
596 break;
597 case VBE_DISPI_INDEX_YRES:
598 val = VBE_DISPI_MAX_YRES;
599 break;
600 case VBE_DISPI_INDEX_BPP:
601 val = VBE_DISPI_MAX_BPP;
602 break;
603 default:
604 val = s->vbe_regs[s->vbe_index];
605 break;
606 }
607 } else {
608 val = s->vbe_regs[s->vbe_index];
609 }
610 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
611 val = s->vram_size / (64 * 1024);
612 } else {
613 val = 0;
614 }
615 #ifdef DEBUG_BOCHS_VBE
616 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
617 #endif
618 return val;
619 }
620
621 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
622 {
623 VGACommonState *s = opaque;
624 s->vbe_index = val;
625 }
626
627 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
628 {
629 VGACommonState *s = opaque;
630
631 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
632 #ifdef DEBUG_BOCHS_VBE
633 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
634 #endif
635 switch(s->vbe_index) {
636 case VBE_DISPI_INDEX_ID:
637 if (val == VBE_DISPI_ID0 ||
638 val == VBE_DISPI_ID1 ||
639 val == VBE_DISPI_ID2 ||
640 val == VBE_DISPI_ID3 ||
641 val == VBE_DISPI_ID4) {
642 s->vbe_regs[s->vbe_index] = val;
643 }
644 break;
645 case VBE_DISPI_INDEX_XRES:
646 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
647 s->vbe_regs[s->vbe_index] = val;
648 }
649 break;
650 case VBE_DISPI_INDEX_YRES:
651 if (val <= VBE_DISPI_MAX_YRES) {
652 s->vbe_regs[s->vbe_index] = val;
653 }
654 break;
655 case VBE_DISPI_INDEX_BPP:
656 if (val == 0)
657 val = 8;
658 if (val == 4 || val == 8 || val == 15 ||
659 val == 16 || val == 24 || val == 32) {
660 s->vbe_regs[s->vbe_index] = val;
661 }
662 break;
663 case VBE_DISPI_INDEX_BANK:
664 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
665 val &= (s->vbe_bank_mask >> 2);
666 } else {
667 val &= s->vbe_bank_mask;
668 }
669 s->vbe_regs[s->vbe_index] = val;
670 s->bank_offset = (val << 16);
671 vga_update_memory_access(s);
672 break;
673 case VBE_DISPI_INDEX_ENABLE:
674 if ((val & VBE_DISPI_ENABLED) &&
675 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
676 int h, shift_control;
677
678 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
679 s->vbe_regs[VBE_DISPI_INDEX_XRES];
680 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
681 s->vbe_regs[VBE_DISPI_INDEX_YRES];
682 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
683 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
684
685 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
686 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
687 else
688 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
689 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
690 s->vbe_start_addr = 0;
691
692 /* clear the screen (should be done in BIOS) */
693 if (!(val & VBE_DISPI_NOCLEARMEM)) {
694 memset(s->vram_ptr, 0,
695 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
696 }
697
698 /* we initialize the VGA graphic mode (should be done
699 in BIOS) */
700 /* graphic mode + memory map 1 */
701 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
702 VGA_GR06_GRAPHICS_MODE;
703 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
704 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
705 /* width */
706 s->cr[VGA_CRTC_H_DISP] =
707 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
708 /* height (only meaningful if < 1024) */
709 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
710 s->cr[VGA_CRTC_V_DISP_END] = h;
711 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
712 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
713 /* line compare to 1023 */
714 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
715 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
716 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
717
718 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
719 shift_control = 0;
720 s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
721 } else {
722 shift_control = 2;
723 /* set chain 4 mode */
724 s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
725 /* activate all planes */
726 s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
727 }
728 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
729 (shift_control << 5);
730 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
731 } else {
732 /* XXX: the bios should do that */
733 s->bank_offset = 0;
734 }
735 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
736 s->vbe_regs[s->vbe_index] = val;
737 vga_update_memory_access(s);
738 break;
739 case VBE_DISPI_INDEX_VIRT_WIDTH:
740 {
741 int w, h, line_offset;
742
743 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
744 return;
745 w = val;
746 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
747 line_offset = w >> 1;
748 else
749 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
750 h = s->vram_size / line_offset;
751 /* XXX: support weird bochs semantics ? */
752 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
753 return;
754 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
755 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
756 s->vbe_line_offset = line_offset;
757 }
758 break;
759 case VBE_DISPI_INDEX_X_OFFSET:
760 case VBE_DISPI_INDEX_Y_OFFSET:
761 {
762 int x;
763 s->vbe_regs[s->vbe_index] = val;
764 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
765 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
766 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
767 s->vbe_start_addr += x >> 1;
768 else
769 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
770 s->vbe_start_addr >>= 2;
771 }
772 break;
773 default:
774 break;
775 }
776 }
777 }
778 #endif
779
780 /* called for accesses between 0xa0000 and 0xc0000 */
781 uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr)
782 {
783 int memory_map_mode, plane;
784 uint32_t ret;
785
786 /* convert to VGA memory offset */
787 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
788 addr &= 0x1ffff;
789 switch(memory_map_mode) {
790 case 0:
791 break;
792 case 1:
793 if (addr >= 0x10000)
794 return 0xff;
795 addr += s->bank_offset;
796 break;
797 case 2:
798 addr -= 0x10000;
799 if (addr >= 0x8000)
800 return 0xff;
801 break;
802 default:
803 case 3:
804 addr -= 0x18000;
805 if (addr >= 0x8000)
806 return 0xff;
807 break;
808 }
809
810 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
811 /* chain 4 mode : simplest access */
812 ret = s->vram_ptr[addr];
813 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
814 /* odd/even mode (aka text mode mapping) */
815 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
816 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
817 } else {
818 /* standard VGA latched access */
819 s->latch = ((uint32_t *)s->vram_ptr)[addr];
820
821 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
822 /* read mode 0 */
823 plane = s->gr[VGA_GFX_PLANE_READ];
824 ret = GET_PLANE(s->latch, plane);
825 } else {
826 /* read mode 1 */
827 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
828 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
829 ret |= ret >> 16;
830 ret |= ret >> 8;
831 ret = (~ret) & 0xff;
832 }
833 }
834 return ret;
835 }
836
837 /* called for accesses between 0xa0000 and 0xc0000 */
838 void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val)
839 {
840 int memory_map_mode, plane, write_mode, b, func_select, mask;
841 uint32_t write_mask, bit_mask, set_mask;
842
843 #ifdef DEBUG_VGA_MEM
844 printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
845 #endif
846 /* convert to VGA memory offset */
847 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
848 addr &= 0x1ffff;
849 switch(memory_map_mode) {
850 case 0:
851 break;
852 case 1:
853 if (addr >= 0x10000)
854 return;
855 addr += s->bank_offset;
856 break;
857 case 2:
858 addr -= 0x10000;
859 if (addr >= 0x8000)
860 return;
861 break;
862 default:
863 case 3:
864 addr -= 0x18000;
865 if (addr >= 0x8000)
866 return;
867 break;
868 }
869
870 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
871 /* chain 4 mode : simplest access */
872 plane = addr & 3;
873 mask = (1 << plane);
874 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
875 s->vram_ptr[addr] = val;
876 #ifdef DEBUG_VGA_MEM
877 printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
878 #endif
879 s->plane_updated |= mask; /* only used to detect font change */
880 memory_region_set_dirty(&s->vram, addr, 1);
881 }
882 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
883 /* odd/even mode (aka text mode mapping) */
884 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
885 mask = (1 << plane);
886 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
887 addr = ((addr & ~1) << 1) | plane;
888 s->vram_ptr[addr] = val;
889 #ifdef DEBUG_VGA_MEM
890 printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
891 #endif
892 s->plane_updated |= mask; /* only used to detect font change */
893 memory_region_set_dirty(&s->vram, addr, 1);
894 }
895 } else {
896 /* standard VGA latched access */
897 write_mode = s->gr[VGA_GFX_MODE] & 3;
898 switch(write_mode) {
899 default:
900 case 0:
901 /* rotate */
902 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
903 val = ((val >> b) | (val << (8 - b))) & 0xff;
904 val |= val << 8;
905 val |= val << 16;
906
907 /* apply set/reset mask */
908 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
909 val = (val & ~set_mask) |
910 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
911 bit_mask = s->gr[VGA_GFX_BIT_MASK];
912 break;
913 case 1:
914 val = s->latch;
915 goto do_write;
916 case 2:
917 val = mask16[val & 0x0f];
918 bit_mask = s->gr[VGA_GFX_BIT_MASK];
919 break;
920 case 3:
921 /* rotate */
922 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
923 val = (val >> b) | (val << (8 - b));
924
925 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
926 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
927 break;
928 }
929
930 /* apply logical operation */
931 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
932 switch(func_select) {
933 case 0:
934 default:
935 /* nothing to do */
936 break;
937 case 1:
938 /* and */
939 val &= s->latch;
940 break;
941 case 2:
942 /* or */
943 val |= s->latch;
944 break;
945 case 3:
946 /* xor */
947 val ^= s->latch;
948 break;
949 }
950
951 /* apply bit mask */
952 bit_mask |= bit_mask << 8;
953 bit_mask |= bit_mask << 16;
954 val = (val & bit_mask) | (s->latch & ~bit_mask);
955
956 do_write:
957 /* mask data according to sr[2] */
958 mask = s->sr[VGA_SEQ_PLANE_WRITE];
959 s->plane_updated |= mask; /* only used to detect font change */
960 write_mask = mask16[mask];
961 ((uint32_t *)s->vram_ptr)[addr] =
962 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
963 (val & write_mask);
964 #ifdef DEBUG_VGA_MEM
965 printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
966 addr * 4, write_mask, val);
967 #endif
968 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
969 }
970 }
971
972 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
973 const uint8_t *font_ptr, int h,
974 uint32_t fgcol, uint32_t bgcol);
975 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
976 const uint8_t *font_ptr, int h,
977 uint32_t fgcol, uint32_t bgcol, int dup9);
978 typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
979 const uint8_t *s, int width);
980
981 #define DEPTH 8
982 #include "vga_template.h"
983
984 #define DEPTH 15
985 #include "vga_template.h"
986
987 #define BGR_FORMAT
988 #define DEPTH 15
989 #include "vga_template.h"
990
991 #define DEPTH 16
992 #include "vga_template.h"
993
994 #define BGR_FORMAT
995 #define DEPTH 16
996 #include "vga_template.h"
997
998 #define DEPTH 32
999 #include "vga_template.h"
1000
1001 #define BGR_FORMAT
1002 #define DEPTH 32
1003 #include "vga_template.h"
1004
1005 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1006 {
1007 unsigned int col;
1008 col = rgb_to_pixel8(r, g, b);
1009 col |= col << 8;
1010 col |= col << 16;
1011 return col;
1012 }
1013
1014 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1015 {
1016 unsigned int col;
1017 col = rgb_to_pixel15(r, g, b);
1018 col |= col << 16;
1019 return col;
1020 }
1021
1022 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1023 unsigned int b)
1024 {
1025 unsigned int col;
1026 col = rgb_to_pixel15bgr(r, g, b);
1027 col |= col << 16;
1028 return col;
1029 }
1030
1031 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1032 {
1033 unsigned int col;
1034 col = rgb_to_pixel16(r, g, b);
1035 col |= col << 16;
1036 return col;
1037 }
1038
1039 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1040 unsigned int b)
1041 {
1042 unsigned int col;
1043 col = rgb_to_pixel16bgr(r, g, b);
1044 col |= col << 16;
1045 return col;
1046 }
1047
1048 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1049 {
1050 unsigned int col;
1051 col = rgb_to_pixel32(r, g, b);
1052 return col;
1053 }
1054
1055 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1056 {
1057 unsigned int col;
1058 col = rgb_to_pixel32bgr(r, g, b);
1059 return col;
1060 }
1061
1062 /* return true if the palette was modified */
1063 static int update_palette16(VGACommonState *s)
1064 {
1065 int full_update, i;
1066 uint32_t v, col, *palette;
1067
1068 full_update = 0;
1069 palette = s->last_palette;
1070 for(i = 0; i < 16; i++) {
1071 v = s->ar[i];
1072 if (s->ar[VGA_ATC_MODE] & 0x80) {
1073 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1074 } else {
1075 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1076 }
1077 v = v * 3;
1078 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1079 c6_to_8(s->palette[v + 1]),
1080 c6_to_8(s->palette[v + 2]));
1081 if (col != palette[i]) {
1082 full_update = 1;
1083 palette[i] = col;
1084 }
1085 }
1086 return full_update;
1087 }
1088
1089 /* return true if the palette was modified */
1090 static int update_palette256(VGACommonState *s)
1091 {
1092 int full_update, i;
1093 uint32_t v, col, *palette;
1094
1095 full_update = 0;
1096 palette = s->last_palette;
1097 v = 0;
1098 for(i = 0; i < 256; i++) {
1099 if (s->dac_8bit) {
1100 col = s->rgb_to_pixel(s->palette[v],
1101 s->palette[v + 1],
1102 s->palette[v + 2]);
1103 } else {
1104 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1105 c6_to_8(s->palette[v + 1]),
1106 c6_to_8(s->palette[v + 2]));
1107 }
1108 if (col != palette[i]) {
1109 full_update = 1;
1110 palette[i] = col;
1111 }
1112 v += 3;
1113 }
1114 return full_update;
1115 }
1116
1117 static void vga_get_offsets(VGACommonState *s,
1118 uint32_t *pline_offset,
1119 uint32_t *pstart_addr,
1120 uint32_t *pline_compare)
1121 {
1122 uint32_t start_addr, line_offset, line_compare;
1123 #ifdef CONFIG_BOCHS_VBE
1124 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1125 line_offset = s->vbe_line_offset;
1126 start_addr = s->vbe_start_addr;
1127 line_compare = 65535;
1128 } else
1129 #endif
1130 {
1131 /* compute line_offset in bytes */
1132 line_offset = s->cr[VGA_CRTC_OFFSET];
1133 line_offset <<= 3;
1134
1135 /* starting address */
1136 start_addr = s->cr[VGA_CRTC_START_LO] |
1137 (s->cr[VGA_CRTC_START_HI] << 8);
1138
1139 /* line compare */
1140 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1141 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1142 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
1143 }
1144 *pline_offset = line_offset;
1145 *pstart_addr = start_addr;
1146 *pline_compare = line_compare;
1147 }
1148
1149 /* update start_addr and line_offset. Return TRUE if modified */
1150 static int update_basic_params(VGACommonState *s)
1151 {
1152 int full_update;
1153 uint32_t start_addr, line_offset, line_compare;
1154
1155 full_update = 0;
1156
1157 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1158
1159 if (line_offset != s->line_offset ||
1160 start_addr != s->start_addr ||
1161 line_compare != s->line_compare) {
1162 s->line_offset = line_offset;
1163 s->start_addr = start_addr;
1164 s->line_compare = line_compare;
1165 full_update = 1;
1166 }
1167 return full_update;
1168 }
1169
1170 #define NB_DEPTHS 7
1171
1172 static inline int get_depth_index(DisplayState *s)
1173 {
1174 switch(ds_get_bits_per_pixel(s)) {
1175 default:
1176 case 8:
1177 return 0;
1178 case 15:
1179 return 1;
1180 case 16:
1181 return 2;
1182 case 32:
1183 if (is_surface_bgr(s->surface))
1184 return 4;
1185 else
1186 return 3;
1187 }
1188 }
1189
1190 static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = {
1191 vga_draw_glyph8_8,
1192 vga_draw_glyph8_16,
1193 vga_draw_glyph8_16,
1194 vga_draw_glyph8_32,
1195 vga_draw_glyph8_32,
1196 vga_draw_glyph8_16,
1197 vga_draw_glyph8_16,
1198 };
1199
1200 static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = {
1201 vga_draw_glyph16_8,
1202 vga_draw_glyph16_16,
1203 vga_draw_glyph16_16,
1204 vga_draw_glyph16_32,
1205 vga_draw_glyph16_32,
1206 vga_draw_glyph16_16,
1207 vga_draw_glyph16_16,
1208 };
1209
1210 static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = {
1211 vga_draw_glyph9_8,
1212 vga_draw_glyph9_16,
1213 vga_draw_glyph9_16,
1214 vga_draw_glyph9_32,
1215 vga_draw_glyph9_32,
1216 vga_draw_glyph9_16,
1217 vga_draw_glyph9_16,
1218 };
1219
1220 static const uint8_t cursor_glyph[32 * 4] = {
1221 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1222 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1223 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1224 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1225 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1226 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1227 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1228 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1229 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1230 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1231 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1232 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1233 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1234 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1235 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1236 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1237 };
1238
1239 static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
1240 int *pcwidth, int *pcheight)
1241 {
1242 int width, cwidth, height, cheight;
1243
1244 /* total width & height */
1245 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1246 cwidth = 8;
1247 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
1248 cwidth = 9;
1249 }
1250 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
1251 cwidth = 16; /* NOTE: no 18 pixel wide */
1252 }
1253 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1254 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1255 /* ugly hack for CGA 160x100x16 - explain me the logic */
1256 height = 100;
1257 } else {
1258 height = s->cr[VGA_CRTC_V_DISP_END] |
1259 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1260 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1261 height = (height + 1) / cheight;
1262 }
1263
1264 *pwidth = width;
1265 *pheight = height;
1266 *pcwidth = cwidth;
1267 *pcheight = cheight;
1268 }
1269
1270 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1271
1272 static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = {
1273 rgb_to_pixel8_dup,
1274 rgb_to_pixel15_dup,
1275 rgb_to_pixel16_dup,
1276 rgb_to_pixel32_dup,
1277 rgb_to_pixel32bgr_dup,
1278 rgb_to_pixel15bgr_dup,
1279 rgb_to_pixel16bgr_dup,
1280 };
1281
1282 /*
1283 * Text mode update
1284 * Missing:
1285 * - double scan
1286 * - double width
1287 * - underline
1288 * - flashing
1289 */
1290 static void vga_draw_text(VGACommonState *s, int full_update)
1291 {
1292 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1293 int cx_min, cx_max, linesize, x_incr, line, line1;
1294 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1295 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
1296 const uint8_t *font_ptr, *font_base[2];
1297 int dup9, line_offset, depth_index;
1298 uint32_t *palette;
1299 uint32_t *ch_attr_ptr;
1300 vga_draw_glyph8_func *vga_draw_glyph8;
1301 vga_draw_glyph9_func *vga_draw_glyph9;
1302
1303 /* compute font data address (in plane 2) */
1304 v = s->sr[VGA_SEQ_CHARACTER_MAP];
1305 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1306 if (offset != s->font_offsets[0]) {
1307 s->font_offsets[0] = offset;
1308 full_update = 1;
1309 }
1310 font_base[0] = s->vram_ptr + offset;
1311
1312 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1313 font_base[1] = s->vram_ptr + offset;
1314 if (offset != s->font_offsets[1]) {
1315 s->font_offsets[1] = offset;
1316 full_update = 1;
1317 }
1318 if (s->plane_updated & (1 << 2) || s->chain4_alias) {
1319 /* if the plane 2 was modified since the last display, it
1320 indicates the font may have been modified */
1321 s->plane_updated = 0;
1322 full_update = 1;
1323 }
1324 full_update |= update_basic_params(s);
1325
1326 line_offset = s->line_offset;
1327
1328 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1329 if ((height * width) > CH_ATTR_SIZE) {
1330 /* better than nothing: exit if transient size is too big */
1331 return;
1332 }
1333
1334 if (width != s->last_width || height != s->last_height ||
1335 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1336 s->last_scr_width = width * cw;
1337 s->last_scr_height = height * cheight;
1338 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
1339 s->last_depth = 0;
1340 s->last_width = width;
1341 s->last_height = height;
1342 s->last_ch = cheight;
1343 s->last_cw = cw;
1344 full_update = 1;
1345 }
1346 s->rgb_to_pixel =
1347 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1348 full_update |= update_palette16(s);
1349 palette = s->last_palette;
1350 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1351
1352 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1353 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1354 if (cursor_offset != s->cursor_offset ||
1355 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1356 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
1357 /* if the cursor position changed, we update the old and new
1358 chars */
1359 if (s->cursor_offset < CH_ATTR_SIZE)
1360 s->last_ch_attr[s->cursor_offset] = -1;
1361 if (cursor_offset < CH_ATTR_SIZE)
1362 s->last_ch_attr[cursor_offset] = -1;
1363 s->cursor_offset = cursor_offset;
1364 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1365 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1366 }
1367 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1368
1369 depth_index = get_depth_index(s->ds);
1370 if (cw == 16)
1371 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1372 else
1373 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1374 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1375
1376 dest = ds_get_data(s->ds);
1377 linesize = ds_get_linesize(s->ds);
1378 ch_attr_ptr = s->last_ch_attr;
1379 line = 0;
1380 offset = s->start_addr * 4;
1381 for(cy = 0; cy < height; cy++) {
1382 d1 = dest;
1383 src = s->vram_ptr + offset;
1384 cx_min = width;
1385 cx_max = -1;
1386 for(cx = 0; cx < width; cx++) {
1387 ch_attr = *(uint16_t *)src;
1388 if (full_update || ch_attr != *ch_attr_ptr) {
1389 if (cx < cx_min)
1390 cx_min = cx;
1391 if (cx > cx_max)
1392 cx_max = cx;
1393 *ch_attr_ptr = ch_attr;
1394 #ifdef HOST_WORDS_BIGENDIAN
1395 ch = ch_attr >> 8;
1396 cattr = ch_attr & 0xff;
1397 #else
1398 ch = ch_attr & 0xff;
1399 cattr = ch_attr >> 8;
1400 #endif
1401 font_ptr = font_base[(cattr >> 3) & 1];
1402 font_ptr += 32 * 4 * ch;
1403 bgcol = palette[cattr >> 4];
1404 fgcol = palette[cattr & 0x0f];
1405 if (cw != 9) {
1406 vga_draw_glyph8(d1, linesize,
1407 font_ptr, cheight, fgcol, bgcol);
1408 } else {
1409 dup9 = 0;
1410 if (ch >= 0xb0 && ch <= 0xdf &&
1411 (s->ar[VGA_ATC_MODE] & 0x04)) {
1412 dup9 = 1;
1413 }
1414 vga_draw_glyph9(d1, linesize,
1415 font_ptr, cheight, fgcol, bgcol, dup9);
1416 }
1417 if (src == cursor_ptr &&
1418 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20)) {
1419 int line_start, line_last, h;
1420 /* draw the cursor */
1421 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1422 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
1423 /* XXX: check that */
1424 if (line_last > cheight - 1)
1425 line_last = cheight - 1;
1426 if (line_last >= line_start && line_start < cheight) {
1427 h = line_last - line_start + 1;
1428 d = d1 + linesize * line_start;
1429 if (cw != 9) {
1430 vga_draw_glyph8(d, linesize,
1431 cursor_glyph, h, fgcol, bgcol);
1432 } else {
1433 vga_draw_glyph9(d, linesize,
1434 cursor_glyph, h, fgcol, bgcol, 1);
1435 }
1436 }
1437 }
1438 }
1439 d1 += x_incr;
1440 src += 4;
1441 ch_attr_ptr++;
1442 }
1443 if (cx_max != -1) {
1444 dpy_update(s->ds, cx_min * cw, cy * cheight,
1445 (cx_max - cx_min + 1) * cw, cheight);
1446 }
1447 dest += linesize * cheight;
1448 line1 = line + cheight;
1449 offset += line_offset;
1450 if (line < s->line_compare && line1 >= s->line_compare) {
1451 offset = 0;
1452 }
1453 line = line1;
1454 }
1455 }
1456
1457 enum {
1458 VGA_DRAW_LINE2,
1459 VGA_DRAW_LINE2D2,
1460 VGA_DRAW_LINE4,
1461 VGA_DRAW_LINE4D2,
1462 VGA_DRAW_LINE8D2,
1463 VGA_DRAW_LINE8,
1464 VGA_DRAW_LINE15,
1465 VGA_DRAW_LINE16,
1466 VGA_DRAW_LINE24,
1467 VGA_DRAW_LINE32,
1468 VGA_DRAW_LINE_NB,
1469 };
1470
1471 static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1472 vga_draw_line2_8,
1473 vga_draw_line2_16,
1474 vga_draw_line2_16,
1475 vga_draw_line2_32,
1476 vga_draw_line2_32,
1477 vga_draw_line2_16,
1478 vga_draw_line2_16,
1479
1480 vga_draw_line2d2_8,
1481 vga_draw_line2d2_16,
1482 vga_draw_line2d2_16,
1483 vga_draw_line2d2_32,
1484 vga_draw_line2d2_32,
1485 vga_draw_line2d2_16,
1486 vga_draw_line2d2_16,
1487
1488 vga_draw_line4_8,
1489 vga_draw_line4_16,
1490 vga_draw_line4_16,
1491 vga_draw_line4_32,
1492 vga_draw_line4_32,
1493 vga_draw_line4_16,
1494 vga_draw_line4_16,
1495
1496 vga_draw_line4d2_8,
1497 vga_draw_line4d2_16,
1498 vga_draw_line4d2_16,
1499 vga_draw_line4d2_32,
1500 vga_draw_line4d2_32,
1501 vga_draw_line4d2_16,
1502 vga_draw_line4d2_16,
1503
1504 vga_draw_line8d2_8,
1505 vga_draw_line8d2_16,
1506 vga_draw_line8d2_16,
1507 vga_draw_line8d2_32,
1508 vga_draw_line8d2_32,
1509 vga_draw_line8d2_16,
1510 vga_draw_line8d2_16,
1511
1512 vga_draw_line8_8,
1513 vga_draw_line8_16,
1514 vga_draw_line8_16,
1515 vga_draw_line8_32,
1516 vga_draw_line8_32,
1517 vga_draw_line8_16,
1518 vga_draw_line8_16,
1519
1520 vga_draw_line15_8,
1521 vga_draw_line15_15,
1522 vga_draw_line15_16,
1523 vga_draw_line15_32,
1524 vga_draw_line15_32bgr,
1525 vga_draw_line15_15bgr,
1526 vga_draw_line15_16bgr,
1527
1528 vga_draw_line16_8,
1529 vga_draw_line16_15,
1530 vga_draw_line16_16,
1531 vga_draw_line16_32,
1532 vga_draw_line16_32bgr,
1533 vga_draw_line16_15bgr,
1534 vga_draw_line16_16bgr,
1535
1536 vga_draw_line24_8,
1537 vga_draw_line24_15,
1538 vga_draw_line24_16,
1539 vga_draw_line24_32,
1540 vga_draw_line24_32bgr,
1541 vga_draw_line24_15bgr,
1542 vga_draw_line24_16bgr,
1543
1544 vga_draw_line32_8,
1545 vga_draw_line32_15,
1546 vga_draw_line32_16,
1547 vga_draw_line32_32,
1548 vga_draw_line32_32bgr,
1549 vga_draw_line32_15bgr,
1550 vga_draw_line32_16bgr,
1551 };
1552
1553 static int vga_get_bpp(VGACommonState *s)
1554 {
1555 int ret;
1556 #ifdef CONFIG_BOCHS_VBE
1557 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1558 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1559 } else
1560 #endif
1561 {
1562 ret = 0;
1563 }
1564 return ret;
1565 }
1566
1567 static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1568 {
1569 int width, height;
1570
1571 #ifdef CONFIG_BOCHS_VBE
1572 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1573 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1574 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1575 } else
1576 #endif
1577 {
1578 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1579 height = s->cr[VGA_CRTC_V_DISP_END] |
1580 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1581 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1582 height = (height + 1);
1583 }
1584 *pwidth = width;
1585 *pheight = height;
1586 }
1587
1588 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
1589 {
1590 int y;
1591 if (y1 >= VGA_MAX_HEIGHT)
1592 return;
1593 if (y2 >= VGA_MAX_HEIGHT)
1594 y2 = VGA_MAX_HEIGHT;
1595 for(y = y1; y < y2; y++) {
1596 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1597 }
1598 }
1599
1600 static void vga_sync_dirty_bitmap(VGACommonState *s)
1601 {
1602 memory_region_sync_dirty_bitmap(&s->vram);
1603 }
1604
1605 void vga_dirty_log_start(VGACommonState *s)
1606 {
1607 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
1608 }
1609
1610 void vga_dirty_log_stop(VGACommonState *s)
1611 {
1612 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
1613 }
1614
1615 /*
1616 * graphic modes
1617 */
1618 static void vga_draw_graphic(VGACommonState *s, int full_update)
1619 {
1620 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1621 int width, height, shift_control, line_offset, bwidth, bits;
1622 ram_addr_t page0, page1, page_min, page_max;
1623 int disp_width, multi_scan, multi_run;
1624 uint8_t *d;
1625 uint32_t v, addr1, addr;
1626 vga_draw_line_func *vga_draw_line;
1627
1628 full_update |= update_basic_params(s);
1629
1630 if (!full_update)
1631 vga_sync_dirty_bitmap(s);
1632
1633 s->get_resolution(s, &width, &height);
1634 disp_width = width;
1635
1636 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1637 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
1638 if (shift_control != 1) {
1639 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1640 - 1;
1641 } else {
1642 /* in CGA modes, multi_scan is ignored */
1643 /* XXX: is it correct ? */
1644 multi_scan = double_scan;
1645 }
1646 multi_run = multi_scan;
1647 if (shift_control != s->shift_control ||
1648 double_scan != s->double_scan) {
1649 full_update = 1;
1650 s->shift_control = shift_control;
1651 s->double_scan = double_scan;
1652 }
1653
1654 if (shift_control == 0) {
1655 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1656 disp_width <<= 1;
1657 }
1658 } else if (shift_control == 1) {
1659 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1660 disp_width <<= 1;
1661 }
1662 }
1663
1664 depth = s->get_bpp(s);
1665 if (s->line_offset != s->last_line_offset ||
1666 disp_width != s->last_width ||
1667 height != s->last_height ||
1668 s->last_depth != depth) {
1669 #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1670 if (depth == 16 || depth == 32) {
1671 #else
1672 if (depth == 32) {
1673 #endif
1674 qemu_free_displaysurface(s->ds);
1675 s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1676 s->line_offset,
1677 s->vram_ptr + (s->start_addr * 4));
1678 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
1679 s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
1680 #endif
1681 dpy_resize(s->ds);
1682 } else {
1683 qemu_console_resize(s->ds, disp_width, height);
1684 }
1685 s->last_scr_width = disp_width;
1686 s->last_scr_height = height;
1687 s->last_width = disp_width;
1688 s->last_height = height;
1689 s->last_line_offset = s->line_offset;
1690 s->last_depth = depth;
1691 full_update = 1;
1692 } else if (is_buffer_shared(s->ds->surface) &&
1693 (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1694 s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
1695 dpy_setdata(s->ds);
1696 }
1697
1698 s->rgb_to_pixel =
1699 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1700
1701 if (shift_control == 0) {
1702 full_update |= update_palette16(s);
1703 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1704 v = VGA_DRAW_LINE4D2;
1705 } else {
1706 v = VGA_DRAW_LINE4;
1707 }
1708 bits = 4;
1709 } else if (shift_control == 1) {
1710 full_update |= update_palette16(s);
1711 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1712 v = VGA_DRAW_LINE2D2;
1713 } else {
1714 v = VGA_DRAW_LINE2;
1715 }
1716 bits = 4;
1717 } else {
1718 switch(s->get_bpp(s)) {
1719 default:
1720 case 0:
1721 full_update |= update_palette256(s);
1722 v = VGA_DRAW_LINE8D2;
1723 bits = 4;
1724 break;
1725 case 8:
1726 full_update |= update_palette256(s);
1727 v = VGA_DRAW_LINE8;
1728 bits = 8;
1729 break;
1730 case 15:
1731 v = VGA_DRAW_LINE15;
1732 bits = 16;
1733 break;
1734 case 16:
1735 v = VGA_DRAW_LINE16;
1736 bits = 16;
1737 break;
1738 case 24:
1739 v = VGA_DRAW_LINE24;
1740 bits = 24;
1741 break;
1742 case 32:
1743 v = VGA_DRAW_LINE32;
1744 bits = 32;
1745 break;
1746 }
1747 }
1748 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1749
1750 if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
1751 s->cursor_invalidate(s);
1752
1753 line_offset = s->line_offset;
1754 #if 0
1755 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1756 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1757 s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]);
1758 #endif
1759 addr1 = (s->start_addr * 4);
1760 bwidth = (width * bits + 7) / 8;
1761 y_start = -1;
1762 page_min = -1;
1763 page_max = 0;
1764 d = ds_get_data(s->ds);
1765 linesize = ds_get_linesize(s->ds);
1766 y1 = 0;
1767 for(y = 0; y < height; y++) {
1768 addr = addr1;
1769 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
1770 int shift;
1771 /* CGA compatibility handling */
1772 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
1773 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1774 }
1775 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
1776 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1777 }
1778 update = full_update;
1779 page0 = addr;
1780 page1 = addr + bwidth - 1;
1781 update |= memory_region_get_dirty(&s->vram, page0, page1 - page0,
1782 DIRTY_MEMORY_VGA);
1783 /* explicit invalidation for the hardware cursor */
1784 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1785 if (update) {
1786 if (y_start < 0)
1787 y_start = y;
1788 if (page0 < page_min)
1789 page_min = page0;
1790 if (page1 > page_max)
1791 page_max = page1;
1792 if (!(is_buffer_shared(s->ds->surface))) {
1793 vga_draw_line(s, d, s->vram_ptr + addr, width);
1794 if (s->cursor_draw_line)
1795 s->cursor_draw_line(s, d, y);
1796 }
1797 } else {
1798 if (y_start >= 0) {
1799 /* flush to display */
1800 dpy_update(s->ds, 0, y_start,
1801 disp_width, y - y_start);
1802 y_start = -1;
1803 }
1804 }
1805 if (!multi_run) {
1806 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
1807 if ((y1 & mask) == mask)
1808 addr1 += line_offset;
1809 y1++;
1810 multi_run = multi_scan;
1811 } else {
1812 multi_run--;
1813 }
1814 /* line compare acts on the displayed lines */
1815 if (y == s->line_compare)
1816 addr1 = 0;
1817 d += linesize;
1818 }
1819 if (y_start >= 0) {
1820 /* flush to display */
1821 dpy_update(s->ds, 0, y_start,
1822 disp_width, y - y_start);
1823 }
1824 /* reset modified pages */
1825 if (page_max >= page_min) {
1826 memory_region_reset_dirty(&s->vram,
1827 page_min,
1828 page_max - page_min,
1829 DIRTY_MEMORY_VGA);
1830 }
1831 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1832 }
1833
1834 static void vga_draw_blank(VGACommonState *s, int full_update)
1835 {
1836 int i, w, val;
1837 uint8_t *d;
1838
1839 if (!full_update)
1840 return;
1841 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1842 return;
1843
1844 s->rgb_to_pixel =
1845 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1846 if (ds_get_bits_per_pixel(s->ds) == 8)
1847 val = s->rgb_to_pixel(0, 0, 0);
1848 else
1849 val = 0;
1850 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1851 d = ds_get_data(s->ds);
1852 for(i = 0; i < s->last_scr_height; i++) {
1853 memset(d, val, w);
1854 d += ds_get_linesize(s->ds);
1855 }
1856 dpy_update(s->ds, 0, 0,
1857 s->last_scr_width, s->last_scr_height);
1858 }
1859
1860 #define GMODE_TEXT 0
1861 #define GMODE_GRAPH 1
1862 #define GMODE_BLANK 2
1863
1864 static void vga_update_display(void *opaque)
1865 {
1866 VGACommonState *s = opaque;
1867 int full_update, graphic_mode;
1868
1869 qemu_flush_coalesced_mmio_buffer();
1870
1871 if (ds_get_bits_per_pixel(s->ds) == 0) {
1872 /* nothing to do */
1873 } else {
1874 full_update = 0;
1875 if (!(s->ar_index & 0x20)) {
1876 graphic_mode = GMODE_BLANK;
1877 } else {
1878 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1879 }
1880 if (graphic_mode != s->graphic_mode) {
1881 s->graphic_mode = graphic_mode;
1882 full_update = 1;
1883 }
1884 switch(graphic_mode) {
1885 case GMODE_TEXT:
1886 vga_draw_text(s, full_update);
1887 break;
1888 case GMODE_GRAPH:
1889 vga_draw_graphic(s, full_update);
1890 break;
1891 case GMODE_BLANK:
1892 default:
1893 vga_draw_blank(s, full_update);
1894 break;
1895 }
1896 }
1897 }
1898
1899 /* force a full display refresh */
1900 static void vga_invalidate_display(void *opaque)
1901 {
1902 VGACommonState *s = opaque;
1903
1904 s->last_width = -1;
1905 s->last_height = -1;
1906 }
1907
1908 void vga_common_reset(VGACommonState *s)
1909 {
1910 s->sr_index = 0;
1911 memset(s->sr, '\0', sizeof(s->sr));
1912 s->gr_index = 0;
1913 memset(s->gr, '\0', sizeof(s->gr));
1914 s->ar_index = 0;
1915 memset(s->ar, '\0', sizeof(s->ar));
1916 s->ar_flip_flop = 0;
1917 s->cr_index = 0;
1918 memset(s->cr, '\0', sizeof(s->cr));
1919 s->msr = 0;
1920 s->fcr = 0;
1921 s->st00 = 0;
1922 s->st01 = 0;
1923 s->dac_state = 0;
1924 s->dac_sub_index = 0;
1925 s->dac_read_index = 0;
1926 s->dac_write_index = 0;
1927 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1928 s->dac_8bit = 0;
1929 memset(s->palette, '\0', sizeof(s->palette));
1930 s->bank_offset = 0;
1931 #ifdef CONFIG_BOCHS_VBE
1932 s->vbe_index = 0;
1933 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1934 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
1935 s->vbe_start_addr = 0;
1936 s->vbe_line_offset = 0;
1937 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1938 #endif
1939 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1940 s->graphic_mode = -1; /* force full update */
1941 s->shift_control = 0;
1942 s->double_scan = 0;
1943 s->line_offset = 0;
1944 s->line_compare = 0;
1945 s->start_addr = 0;
1946 s->plane_updated = 0;
1947 s->last_cw = 0;
1948 s->last_ch = 0;
1949 s->last_width = 0;
1950 s->last_height = 0;
1951 s->last_scr_width = 0;
1952 s->last_scr_height = 0;
1953 s->cursor_start = 0;
1954 s->cursor_end = 0;
1955 s->cursor_offset = 0;
1956 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1957 memset(s->last_palette, '\0', sizeof(s->last_palette));
1958 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1959 switch (vga_retrace_method) {
1960 case VGA_RETRACE_DUMB:
1961 break;
1962 case VGA_RETRACE_PRECISE:
1963 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1964 break;
1965 }
1966 vga_update_memory_access(s);
1967 }
1968
1969 static void vga_reset(void *opaque)
1970 {
1971 VGACommonState *s = opaque;
1972 vga_common_reset(s);
1973 }
1974
1975 #define TEXTMODE_X(x) ((x) % width)
1976 #define TEXTMODE_Y(x) ((x) / width)
1977 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1978 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1979 /* relay text rendering to the display driver
1980 * instead of doing a full vga_update_display() */
1981 static void vga_update_text(void *opaque, console_ch_t *chardata)
1982 {
1983 VGACommonState *s = opaque;
1984 int graphic_mode, i, cursor_offset, cursor_visible;
1985 int cw, cheight, width, height, size, c_min, c_max;
1986 uint32_t *src;
1987 console_ch_t *dst, val;
1988 char msg_buffer[80];
1989 int full_update = 0;
1990
1991 qemu_flush_coalesced_mmio_buffer();
1992
1993 if (!(s->ar_index & 0x20)) {
1994 graphic_mode = GMODE_BLANK;
1995 } else {
1996 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1997 }
1998 if (graphic_mode != s->graphic_mode) {
1999 s->graphic_mode = graphic_mode;
2000 full_update = 1;
2001 }
2002 if (s->last_width == -1) {
2003 s->last_width = 0;
2004 full_update = 1;
2005 }
2006
2007 switch (graphic_mode) {
2008 case GMODE_TEXT:
2009 /* TODO: update palette */
2010 full_update |= update_basic_params(s);
2011
2012 /* total width & height */
2013 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
2014 cw = 8;
2015 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
2016 cw = 9;
2017 }
2018 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
2019 cw = 16; /* NOTE: no 18 pixel wide */
2020 }
2021 width = (s->cr[VGA_CRTC_H_DISP] + 1);
2022 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
2023 /* ugly hack for CGA 160x100x16 - explain me the logic */
2024 height = 100;
2025 } else {
2026 height = s->cr[VGA_CRTC_V_DISP_END] |
2027 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
2028 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
2029 height = (height + 1) / cheight;
2030 }
2031
2032 size = (height * width);
2033 if (size > CH_ATTR_SIZE) {
2034 if (!full_update)
2035 return;
2036
2037 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2038 width, height);
2039 break;
2040 }
2041
2042 if (width != s->last_width || height != s->last_height ||
2043 cw != s->last_cw || cheight != s->last_ch) {
2044 s->last_scr_width = width * cw;
2045 s->last_scr_height = height * cheight;
2046 s->ds->surface->width = width;
2047 s->ds->surface->height = height;
2048 dpy_resize(s->ds);
2049 s->last_width = width;
2050 s->last_height = height;
2051 s->last_ch = cheight;
2052 s->last_cw = cw;
2053 full_update = 1;
2054 }
2055
2056 /* Update "hardware" cursor */
2057 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
2058 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
2059 if (cursor_offset != s->cursor_offset ||
2060 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
2061 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
2062 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
2063 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
2064 dpy_cursor(s->ds,
2065 TEXTMODE_X(cursor_offset),
2066 TEXTMODE_Y(cursor_offset));
2067 else
2068 dpy_cursor(s->ds, -1, -1);
2069 s->cursor_offset = cursor_offset;
2070 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
2071 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
2072 }
2073
2074 src = (uint32_t *) s->vram_ptr + s->start_addr;
2075 dst = chardata;
2076
2077 if (full_update) {
2078 for (i = 0; i < size; src ++, dst ++, i ++)
2079 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
2080
2081 dpy_update(s->ds, 0, 0, width, height);
2082 } else {
2083 c_max = 0;
2084
2085 for (i = 0; i < size; src ++, dst ++, i ++) {
2086 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
2087 if (*dst != val) {
2088 *dst = val;
2089 c_max = i;
2090 break;
2091 }
2092 }
2093 c_min = i;
2094 for (; i < size; src ++, dst ++, i ++) {
2095 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
2096 if (*dst != val) {
2097 *dst = val;
2098 c_max = i;
2099 }
2100 }
2101
2102 if (c_min <= c_max) {
2103 i = TEXTMODE_Y(c_min);
2104 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2105 }
2106 }
2107
2108 return;
2109 case GMODE_GRAPH:
2110 if (!full_update)
2111 return;
2112
2113 s->get_resolution(s, &width, &height);
2114 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2115 width, height);
2116 break;
2117 case GMODE_BLANK:
2118 default:
2119 if (!full_update)
2120 return;
2121
2122 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2123 break;
2124 }
2125
2126 /* Display a message */
2127 s->last_width = 60;
2128 s->last_height = height = 3;
2129 dpy_cursor(s->ds, -1, -1);
2130 s->ds->surface->width = s->last_width;
2131 s->ds->surface->height = height;
2132 dpy_resize(s->ds);
2133
2134 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2135 console_write_ch(dst ++, ' ');
2136
2137 size = strlen(msg_buffer);
2138 width = (s->last_width - size) / 2;
2139 dst = chardata + s->last_width + width;
2140 for (i = 0; i < size; i ++)
2141 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2142
2143 dpy_update(s->ds, 0, 0, s->last_width, height);
2144 }
2145
2146 static uint64_t vga_mem_read(void *opaque, target_phys_addr_t addr,
2147 unsigned size)
2148 {
2149 VGACommonState *s = opaque;
2150
2151 return vga_mem_readb(s, addr);
2152 }
2153
2154 static void vga_mem_write(void *opaque, target_phys_addr_t addr,
2155 uint64_t data, unsigned size)
2156 {
2157 VGACommonState *s = opaque;
2158
2159 return vga_mem_writeb(s, addr, data);
2160 }
2161
2162 const MemoryRegionOps vga_mem_ops = {
2163 .read = vga_mem_read,
2164 .write = vga_mem_write,
2165 .endianness = DEVICE_LITTLE_ENDIAN,
2166 .impl = {
2167 .min_access_size = 1,
2168 .max_access_size = 1,
2169 },
2170 };
2171
2172 static int vga_common_post_load(void *opaque, int version_id)
2173 {
2174 VGACommonState *s = opaque;
2175
2176 /* force refresh */
2177 s->graphic_mode = -1;
2178 return 0;
2179 }
2180
2181 const VMStateDescription vmstate_vga_common = {
2182 .name = "vga",
2183 .version_id = 2,
2184 .minimum_version_id = 2,
2185 .minimum_version_id_old = 2,
2186 .post_load = vga_common_post_load,
2187 .fields = (VMStateField []) {
2188 VMSTATE_UINT32(latch, VGACommonState),
2189 VMSTATE_UINT8(sr_index, VGACommonState),
2190 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2191 VMSTATE_UINT8(gr_index, VGACommonState),
2192 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2193 VMSTATE_UINT8(ar_index, VGACommonState),
2194 VMSTATE_BUFFER(ar, VGACommonState),
2195 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2196 VMSTATE_UINT8(cr_index, VGACommonState),
2197 VMSTATE_BUFFER(cr, VGACommonState),
2198 VMSTATE_UINT8(msr, VGACommonState),
2199 VMSTATE_UINT8(fcr, VGACommonState),
2200 VMSTATE_UINT8(st00, VGACommonState),
2201 VMSTATE_UINT8(st01, VGACommonState),
2202
2203 VMSTATE_UINT8(dac_state, VGACommonState),
2204 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2205 VMSTATE_UINT8(dac_read_index, VGACommonState),
2206 VMSTATE_UINT8(dac_write_index, VGACommonState),
2207 VMSTATE_BUFFER(dac_cache, VGACommonState),
2208 VMSTATE_BUFFER(palette, VGACommonState),
2209
2210 VMSTATE_INT32(bank_offset, VGACommonState),
2211 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
2212 #ifdef CONFIG_BOCHS_VBE
2213 VMSTATE_UINT16(vbe_index, VGACommonState),
2214 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2215 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2216 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2217 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
2218 #endif
2219 VMSTATE_END_OF_LIST()
2220 }
2221 };
2222
2223 void vga_common_init(VGACommonState *s, int vga_ram_size)
2224 {
2225 int i, j, v, b;
2226
2227 for(i = 0;i < 256; i++) {
2228 v = 0;
2229 for(j = 0; j < 8; j++) {
2230 v |= ((i >> j) & 1) << (j * 4);
2231 }
2232 expand4[i] = v;
2233
2234 v = 0;
2235 for(j = 0; j < 4; j++) {
2236 v |= ((i >> (2 * j)) & 3) << (j * 4);
2237 }
2238 expand2[i] = v;
2239 }
2240 for(i = 0; i < 16; i++) {
2241 v = 0;
2242 for(j = 0; j < 4; j++) {
2243 b = ((i >> j) & 1);
2244 v |= b << (2 * j);
2245 v |= b << (2 * j + 1);
2246 }
2247 expand4to8[i] = v;
2248 }
2249
2250 #ifdef CONFIG_BOCHS_VBE
2251 s->is_vbe_vmstate = 1;
2252 #else
2253 s->is_vbe_vmstate = 0;
2254 #endif
2255 memory_region_init_ram(&s->vram, "vga.vram", vga_ram_size);
2256 vmstate_register_ram_global(&s->vram);
2257 xen_register_framebuffer(&s->vram);
2258 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
2259 s->vram_size = vga_ram_size;
2260 s->get_bpp = vga_get_bpp;
2261 s->get_offsets = vga_get_offsets;
2262 s->get_resolution = vga_get_resolution;
2263 s->update = vga_update_display;
2264 s->invalidate = vga_invalidate_display;
2265 s->screen_dump = vga_screen_dump;
2266 s->text_update = vga_update_text;
2267 switch (vga_retrace_method) {
2268 case VGA_RETRACE_DUMB:
2269 s->retrace = vga_dumb_retrace;
2270 s->update_retrace_info = vga_dumb_update_retrace_info;
2271 break;
2272
2273 case VGA_RETRACE_PRECISE:
2274 s->retrace = vga_precise_retrace;
2275 s->update_retrace_info = vga_precise_update_retrace_info;
2276 break;
2277 }
2278 vga_dirty_log_start(s);
2279 }
2280
2281 static const MemoryRegionPortio vga_portio_list[] = {
2282 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2283 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2284 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2285 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2286 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2287 PORTIO_END_OF_LIST(),
2288 };
2289
2290 #ifdef CONFIG_BOCHS_VBE
2291 static const MemoryRegionPortio vbe_portio_list[] = {
2292 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2293 # ifdef TARGET_I386
2294 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2295 # else
2296 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2297 # endif
2298 PORTIO_END_OF_LIST(),
2299 };
2300 #endif /* CONFIG_BOCHS_VBE */
2301
2302 /* Used by both ISA and PCI */
2303 MemoryRegion *vga_init_io(VGACommonState *s,
2304 const MemoryRegionPortio **vga_ports,
2305 const MemoryRegionPortio **vbe_ports)
2306 {
2307 MemoryRegion *vga_mem;
2308
2309 *vga_ports = vga_portio_list;
2310 *vbe_ports = NULL;
2311 #ifdef CONFIG_BOCHS_VBE
2312 *vbe_ports = vbe_portio_list;
2313 #endif
2314
2315 vga_mem = g_malloc(sizeof(*vga_mem));
2316 memory_region_init_io(vga_mem, &vga_mem_ops, s,
2317 "vga-lowmem", 0x20000);
2318
2319 return vga_mem;
2320 }
2321
2322 void vga_init(VGACommonState *s, MemoryRegion *address_space,
2323 MemoryRegion *address_space_io, bool init_vga_ports)
2324 {
2325 MemoryRegion *vga_io_memory;
2326 const MemoryRegionPortio *vga_ports, *vbe_ports;
2327 PortioList *vga_port_list = g_new(PortioList, 1);
2328 PortioList *vbe_port_list = g_new(PortioList, 1);
2329
2330 qemu_register_reset(vga_reset, s);
2331
2332 s->bank_offset = 0;
2333
2334 s->legacy_address_space = address_space;
2335
2336 vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports);
2337 memory_region_add_subregion_overlap(address_space,
2338 isa_mem_base + 0x000a0000,
2339 vga_io_memory,
2340 1);
2341 memory_region_set_coalescing(vga_io_memory);
2342 if (init_vga_ports) {
2343 portio_list_init(vga_port_list, vga_ports, s, "vga");
2344 portio_list_add(vga_port_list, address_space_io, 0x3b0);
2345 }
2346 if (vbe_ports) {
2347 portio_list_init(vbe_port_list, vbe_ports, s, "vbe");
2348 portio_list_add(vbe_port_list, address_space_io, 0x1ce);
2349 }
2350 }
2351
2352 void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
2353 {
2354 #ifdef CONFIG_BOCHS_VBE
2355 /* XXX: use optimized standard vga accesses */
2356 memory_region_add_subregion(system_memory,
2357 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2358 &s->vram);
2359 s->vbe_mapped = 1;
2360 #endif
2361 }
2362 /********************************************************/
2363 /* vga screen dump */
2364
2365 int ppm_save(const char *filename, struct DisplaySurface *ds)
2366 {
2367 FILE *f;
2368 uint8_t *d, *d1;
2369 uint32_t v;
2370 int y, x;
2371 uint8_t r, g, b;
2372 int ret;
2373 char *linebuf, *pbuf;
2374
2375 f = fopen(filename, "wb");
2376 if (!f)
2377 return -1;
2378 fprintf(f, "P6\n%d %d\n%d\n",
2379 ds->width, ds->height, 255);
2380 linebuf = g_malloc(ds->width * 3);
2381 d1 = ds->data;
2382 for(y = 0; y < ds->height; y++) {
2383 d = d1;
2384 pbuf = linebuf;
2385 for(x = 0; x < ds->width; x++) {
2386 if (ds->pf.bits_per_pixel == 32)
2387 v = *(uint32_t *)d;
2388 else
2389 v = (uint32_t) (*(uint16_t *)d);
2390 /* Limited to 8 or fewer bits per channel: */
2391 r = ((v >> ds->pf.rshift) & ds->pf.rmax) << (8 - ds->pf.rbits);
2392 g = ((v >> ds->pf.gshift) & ds->pf.gmax) << (8 - ds->pf.gbits);
2393 b = ((v >> ds->pf.bshift) & ds->pf.bmax) << (8 - ds->pf.bbits);
2394 *pbuf++ = r;
2395 *pbuf++ = g;
2396 *pbuf++ = b;
2397 d += ds->pf.bytes_per_pixel;
2398 }
2399 d1 += ds->linesize;
2400 ret = fwrite(linebuf, 1, pbuf - linebuf, f);
2401 (void)ret;
2402 }
2403 g_free(linebuf);
2404 fclose(f);
2405 return 0;
2406 }
2407
2408 /* save the vga display in a PPM image even if no display is
2409 available */
2410 static void vga_screen_dump(void *opaque, const char *filename, bool cswitch)
2411 {
2412 VGACommonState *s = opaque;
2413
2414 if (cswitch) {
2415 vga_invalidate_display(s);
2416 vga_hw_update();
2417 }
2418 ppm_save(filename, s->ds->surface);
2419 }
QEmu