hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-timer.h"
  26 #include "sysemu.h"
  27 #include "pc.h"
  28 #include "isa.h"
  29 #include "mc146818rtc.h"
  30
  31 #ifdef TARGET_I386
  32 #include "apic.h"
  33 #endif
  34
  35 //#define DEBUG_CMOS
  36 //#define DEBUG_COALESCED
  37
  38 #ifdef DEBUG_CMOS
  39 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  40 #else
  41 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  42 #endif
  43
  44 #ifdef DEBUG_COALESCED
  45 # define DPRINTF_C(format, ...)      printf(format, ## __VA_ARGS__)
  46 #else
  47 # define DPRINTF_C(format, ...)      do { } while (0)
  48 #endif
  49
  50 #define RTC_REINJECT_ON_ACK_COUNT 20
  51
  52 #define RTC_SECONDS             0
  53 #define RTC_SECONDS_ALARM       1
  54 #define RTC_MINUTES             2
  55 #define RTC_MINUTES_ALARM       3
  56 #define RTC_HOURS               4
  57 #define RTC_HOURS_ALARM         5
  58 #define RTC_ALARM_DONT_CARE    0xC0
  59
  60 #define RTC_DAY_OF_WEEK         6
  61 #define RTC_DAY_OF_MONTH        7
  62 #define RTC_MONTH               8
  63 #define RTC_YEAR                9
  64
  65 #define RTC_REG_A               10
  66 #define RTC_REG_B               11
  67 #define RTC_REG_C               12
  68 #define RTC_REG_D               13
  69
  70 #define REG_A_UIP 0x80
  71
  72 #define REG_B_SET  0x80
  73 #define REG_B_PIE  0x40
  74 #define REG_B_AIE  0x20
  75 #define REG_B_UIE  0x10
  76 #define REG_B_SQWE 0x08
  77 #define REG_B_DM   0x04
  78 #define REG_B_24H  0x02
  79
  80 #define REG_C_UF   0x10
  81 #define REG_C_IRQF 0x80
  82 #define REG_C_PF   0x40
  83 #define REG_C_AF   0x20
  84
  85 typedef struct RTCState {
  86     ISADevice dev;
  87     MemoryRegion io;
  88     uint8_t cmos_data[128];
  89     uint8_t cmos_index;
  90     struct tm current_tm;
  91     int32_t base_year;
  92     qemu_irq irq;
  93     qemu_irq sqw_irq;
  94     int it_shift;
  95     /* periodic timer */
  96     QEMUTimer *periodic_timer;
  97     int64_t next_periodic_time;
  98     /* second update */
  99     int64_t next_second_time;
 100     uint16_t irq_reinject_on_ack_count;
 101     uint32_t irq_coalesced;
 102     uint32_t period;
 103     QEMUTimer *coalesced_timer;
 104     QEMUTimer *second_timer;
 105     QEMUTimer *second_timer2;
 106     Notifier clock_reset_notifier;
 107     LostTickPolicy lost_tick_policy;
 108     Notifier suspend_notifier;
 109 } RTCState;
 110
 111 static void rtc_set_time(RTCState *s);
 112 static void rtc_copy_date(RTCState *s);
 113
 114 #ifdef TARGET_I386
 115 static void rtc_coalesced_timer_update(RTCState *s)
 116 {
 117     if (s->irq_coalesced == 0) {
 118         qemu_del_timer(s->coalesced_timer);
 119     } else {
 120         /* divide each RTC interval to 2 - 8 smaller intervals */
 121         int c = MIN(s->irq_coalesced, 7) + 1;
 122         int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
 123             muldiv64(s->period / c, get_ticks_per_sec(), 32768);
 124         qemu_mod_timer(s->coalesced_timer, next_clock);
 125     }
 126 }
 127
 128 static void rtc_coalesced_timer(void *opaque)
 129 {
 130     RTCState *s = opaque;
 131
 132     if (s->irq_coalesced != 0) {
 133         apic_reset_irq_delivered();
 134         s->cmos_data[RTC_REG_C] |= 0xc0;
 135         DPRINTF_C("cmos: injecting from timer\n");
 136         qemu_irq_raise(s->irq);
 137         if (apic_get_irq_delivered()) {
 138             s->irq_coalesced--;
 139             DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 140                       s->irq_coalesced);
 141         }
 142     }
 143
 144     rtc_coalesced_timer_update(s);
 145 }
 146 #endif
 147
 148 static void rtc_timer_update(RTCState *s, int64_t current_time)
 149 {
 150     int period_code, period;
 151     int64_t cur_clock, next_irq_clock;
 152
 153     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 154     if (period_code != 0
 155         && ((s->cmos_data[RTC_REG_B] & REG_B_PIE)
 156             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 157         if (period_code <= 2)
 158             period_code += 7;
 159         /* period in 32 Khz cycles */
 160         period = 1 << (period_code - 1);
 161 #ifdef TARGET_I386
 162         if (period != s->period) {
 163             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 164             DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
 165         }
 166         s->period = period;
 167 #endif
 168         /* compute 32 khz clock */
 169         cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
 170         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 171         s->next_periodic_time =
 172             muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
 173         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 174     } else {
 175 #ifdef TARGET_I386
 176         s->irq_coalesced = 0;
 177 #endif
 178         qemu_del_timer(s->periodic_timer);
 179     }
 180 }
 181
 182 static void rtc_periodic_timer(void *opaque)
 183 {
 184     RTCState *s = opaque;
 185
 186     rtc_timer_update(s, s->next_periodic_time);
 187     s->cmos_data[RTC_REG_C] |= REG_C_PF;
 188     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 189         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 190 #ifdef TARGET_I386
 191         if (s->lost_tick_policy == LOST_TICK_SLEW) {
 192             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 193                 s->irq_reinject_on_ack_count = 0;
 194             apic_reset_irq_delivered();
 195             qemu_irq_raise(s->irq);
 196             if (!apic_get_irq_delivered()) {
 197                 s->irq_coalesced++;
 198                 rtc_coalesced_timer_update(s);
 199                 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
 200                           s->irq_coalesced);
 201             }
 202         } else
 203 #endif
 204         qemu_irq_raise(s->irq);
 205     }
 206     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 207         /* Not square wave at all but we don't want 2048Hz interrupts!
 208            Must be seen as a pulse.  */
 209         qemu_irq_raise(s->sqw_irq);
 210     }
 211 }
 212
 213 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 214 {
 215     RTCState *s = opaque;
 216
 217     if ((addr & 1) == 0) {
 218         s->cmos_index = data & 0x7f;
 219     } else {
 220         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
 221                      s->cmos_index, data);
 222         switch(s->cmos_index) {
 223         case RTC_SECONDS_ALARM:
 224         case RTC_MINUTES_ALARM:
 225         case RTC_HOURS_ALARM:
 226             s->cmos_data[s->cmos_index] = data;
 227             break;
 228         case RTC_SECONDS:
 229         case RTC_MINUTES:
 230         case RTC_HOURS:
 231         case RTC_DAY_OF_WEEK:
 232         case RTC_DAY_OF_MONTH:
 233         case RTC_MONTH:
 234         case RTC_YEAR:
 235             s->cmos_data[s->cmos_index] = data;
 236             /* if in set mode, do not update the time */
 237             if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 238                 rtc_set_time(s);
 239             }
 240             break;
 241         case RTC_REG_A:
 242             /* UIP bit is read only */
 243             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 244                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 245             rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
 246             break;
 247         case RTC_REG_B:
 248             if (data & REG_B_SET) {
 249                 /* set mode: reset UIP mode */
 250                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 251                 data &= ~REG_B_UIE;
 252             } else {
 253                 /* if disabling set mode, update the time */
 254                 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
 255                     rtc_set_time(s);
 256                 }
 257             }
 258             if (((s->cmos_data[RTC_REG_B] ^ data) & (REG_B_DM | REG_B_24H)) &&
 259                 !(data & REG_B_SET)) {
 260                 /* If the time format has changed and not in set mode,
 261                    update the registers immediately. */
 262                 s->cmos_data[RTC_REG_B] = data;
 263                 rtc_copy_date(s);
 264             } else {
 265                 s->cmos_data[RTC_REG_B] = data;
 266             }
 267             rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
 268             break;
 269         case RTC_REG_C:
 270         case RTC_REG_D:
 271             /* cannot write to them */
 272             break;
 273         default:
 274             s->cmos_data[s->cmos_index] = data;
 275             break;
 276         }
 277     }
 278 }
 279
 280 static inline int rtc_to_bcd(RTCState *s, int a)
 281 {
 282     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 283         return a;
 284     } else {
 285         return ((a / 10) << 4) | (a % 10);
 286     }
 287 }
 288
 289 static inline int rtc_from_bcd(RTCState *s, int a)
 290 {
 291     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 292         return a;
 293     } else {
 294         return ((a >> 4) * 10) + (a & 0x0f);
 295     }
 296 }
 297
 298 static void rtc_set_time(RTCState *s)
 299 {
 300     struct tm *tm = &s->current_tm;
 301
 302     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 303     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 304     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 305     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 306         tm->tm_hour %= 12;
 307         if (s->cmos_data[RTC_HOURS] & 0x80) {
 308             tm->tm_hour += 12;
 309         }
 310     }
 311     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 312     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 313     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 314     tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
 315
 316     rtc_change_mon_event(tm);
 317 }
 318
 319 static void rtc_copy_date(RTCState *s)
 320 {
 321     const struct tm *tm = &s->current_tm;
 322     int year;
 323
 324     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 325     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 326     if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
 327         /* 24 hour format */
 328         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 329     } else {
 330         /* 12 hour format */
 331         int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
 332         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
 333         if (tm->tm_hour >= 12)
 334             s->cmos_data[RTC_HOURS] |= 0x80;
 335     }
 336     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 337     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 338     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 339     year = (tm->tm_year - s->base_year) % 100;
 340     if (year < 0)
 341         year += 100;
 342     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year);
 343 }
 344
 345 /* month is between 0 and 11. */
 346 static int get_days_in_month(int month, int year)
 347 {
 348     static const int days_tab[12] = {
 349         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 350     };
 351     int d;
 352     if ((unsigned )month >= 12)
 353         return 31;
 354     d = days_tab[month];
 355     if (month == 1) {
 356         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
 357             d++;
 358     }
 359     return d;
 360 }
 361
 362 /* update 'tm' to the next second */
 363 static void rtc_next_second(struct tm *tm)
 364 {
 365     int days_in_month;
 366
 367     tm->tm_sec++;
 368     if ((unsigned)tm->tm_sec >= 60) {
 369         tm->tm_sec = 0;
 370         tm->tm_min++;
 371         if ((unsigned)tm->tm_min >= 60) {
 372             tm->tm_min = 0;
 373             tm->tm_hour++;
 374             if ((unsigned)tm->tm_hour >= 24) {
 375                 tm->tm_hour = 0;
 376                 /* next day */
 377                 tm->tm_wday++;
 378                 if ((unsigned)tm->tm_wday >= 7)
 379                     tm->tm_wday = 0;
 380                 days_in_month = get_days_in_month(tm->tm_mon,
 381                                                   tm->tm_year + 1900);
 382                 tm->tm_mday++;
 383                 if (tm->tm_mday < 1) {
 384                     tm->tm_mday = 1;
 385                 } else if (tm->tm_mday > days_in_month) {
 386                     tm->tm_mday = 1;
 387                     tm->tm_mon++;
 388                     if (tm->tm_mon >= 12) {
 389                         tm->tm_mon = 0;
 390                         tm->tm_year++;
 391                     }
 392                 }
 393             }
 394         }
 395     }
 396 }
 397
 398
 399 static void rtc_update_second(void *opaque)
 400 {
 401     RTCState *s = opaque;
 402     int64_t delay;
 403
 404     /* if the oscillator is not in normal operation, we do not update */
 405     if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
 406         s->next_second_time += get_ticks_per_sec();
 407         qemu_mod_timer(s->second_timer, s->next_second_time);
 408     } else {
 409         rtc_next_second(&s->current_tm);
 410
 411         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 412             /* update in progress bit */
 413             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 414         }
 415         /* should be 244 us = 8 / 32768 seconds, but currently the
 416            timers do not have the necessary resolution. */
 417         delay = (get_ticks_per_sec() * 1) / 100;
 418         if (delay < 1)
 419             delay = 1;
 420         qemu_mod_timer(s->second_timer2,
 421                        s->next_second_time + delay);
 422     }
 423 }
 424
 425 static void rtc_update_second2(void *opaque)
 426 {
 427     RTCState *s = opaque;
 428
 429     if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 430         rtc_copy_date(s);
 431     }
 432
 433     /* check alarm */
 434     if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
 435          rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) &&
 436         ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
 437          rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) &&
 438         ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
 439          rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) {
 440
 441         s->cmos_data[RTC_REG_C] |= REG_C_AF;
 442         if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 443             qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
 444             qemu_irq_raise(s->irq);
 445             s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 446         }
 447     }
 448
 449     /* update ended interrupt */
 450     s->cmos_data[RTC_REG_C] |= REG_C_UF;
 451     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
 452         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 453         qemu_irq_raise(s->irq);
 454     }
 455
 456     /* clear update in progress bit */
 457     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 458
 459     s->next_second_time += get_ticks_per_sec();
 460     qemu_mod_timer(s->second_timer, s->next_second_time);
 461 }
 462
 463 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 464 {
 465     RTCState *s = opaque;
 466     int ret;
 467     if ((addr & 1) == 0) {
 468         return 0xff;
 469     } else {
 470         switch(s->cmos_index) {
 471         case RTC_SECONDS:
 472         case RTC_MINUTES:
 473         case RTC_HOURS:
 474         case RTC_DAY_OF_WEEK:
 475         case RTC_DAY_OF_MONTH:
 476         case RTC_MONTH:
 477         case RTC_YEAR:
 478             ret = s->cmos_data[s->cmos_index];
 479             break;
 480         case RTC_REG_A:
 481             ret = s->cmos_data[s->cmos_index];
 482             break;
 483         case RTC_REG_C:
 484             ret = s->cmos_data[s->cmos_index];
 485             qemu_irq_lower(s->irq);
 486             s->cmos_data[RTC_REG_C] = 0x00;
 487 #ifdef TARGET_I386
 488             if(s->irq_coalesced &&
 489                     (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
 490                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 491                 s->irq_reinject_on_ack_count++;
 492                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
 493                 apic_reset_irq_delivered();
 494                 DPRINTF_C("cmos: injecting on ack\n");
 495                 qemu_irq_raise(s->irq);
 496                 if (apic_get_irq_delivered()) {
 497                     s->irq_coalesced--;
 498                     DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 499                               s->irq_coalesced);
 500                 }
 501             }
 502 #endif
 503             break;
 504         default:
 505             ret = s->cmos_data[s->cmos_index];
 506             break;
 507         }
 508         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 509                      s->cmos_index, ret);
 510         return ret;
 511     }
 512 }
 513
 514 void rtc_set_memory(ISADevice *dev, int addr, int val)
 515 {
 516     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 517     if (addr >= 0 && addr <= 127)
 518         s->cmos_data[addr] = val;
 519 }
 520
 521 void rtc_set_date(ISADevice *dev, const struct tm *tm)
 522 {
 523     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 524     s->current_tm = *tm;
 525     rtc_copy_date(s);
 526 }
 527
 528 /* PC cmos mappings */
 529 #define REG_IBM_CENTURY_BYTE        0x32
 530 #define REG_IBM_PS2_CENTURY_BYTE    0x37
 531
 532 static void rtc_set_date_from_host(ISADevice *dev)
 533 {
 534     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 535     struct tm tm;
 536     int val;
 537
 538     /* set the CMOS date */
 539     qemu_get_timedate(&tm, 0);
 540     rtc_set_date(dev, &tm);
 541
 542     val = rtc_to_bcd(s, (tm.tm_year / 100) + 19);
 543     rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val);
 544     rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val);
 545 }
 546
 547 static int rtc_post_load(void *opaque, int version_id)
 548 {
 549 #ifdef TARGET_I386
 550     RTCState *s = opaque;
 551
 552     if (version_id >= 2) {
 553         if (s->lost_tick_policy == LOST_TICK_SLEW) {
 554             rtc_coalesced_timer_update(s);
 555         }
 556     }
 557 #endif
 558     return 0;
 559 }
 560
 561 static const VMStateDescription vmstate_rtc = {
 562     .name = "mc146818rtc",
 563     .version_id = 2,
 564     .minimum_version_id = 1,
 565     .minimum_version_id_old = 1,
 566     .post_load = rtc_post_load,
 567     .fields      = (VMStateField []) {
 568         VMSTATE_BUFFER(cmos_data, RTCState),
 569         VMSTATE_UINT8(cmos_index, RTCState),
 570         VMSTATE_INT32(current_tm.tm_sec, RTCState),
 571         VMSTATE_INT32(current_tm.tm_min, RTCState),
 572         VMSTATE_INT32(current_tm.tm_hour, RTCState),
 573         VMSTATE_INT32(current_tm.tm_wday, RTCState),
 574         VMSTATE_INT32(current_tm.tm_mday, RTCState),
 575         VMSTATE_INT32(current_tm.tm_mon, RTCState),
 576         VMSTATE_INT32(current_tm.tm_year, RTCState),
 577         VMSTATE_TIMER(periodic_timer, RTCState),
 578         VMSTATE_INT64(next_periodic_time, RTCState),
 579         VMSTATE_INT64(next_second_time, RTCState),
 580         VMSTATE_TIMER(second_timer, RTCState),
 581         VMSTATE_TIMER(second_timer2, RTCState),
 582         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 583         VMSTATE_UINT32_V(period, RTCState, 2),
 584         VMSTATE_END_OF_LIST()
 585     }
 586 };
 587
 588 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
 589 {
 590     RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
 591     int64_t now = *(int64_t *)data;
 592
 593     rtc_set_date_from_host(&s->dev);
 594     s->next_second_time = now + (get_ticks_per_sec() * 99) / 100;
 595     qemu_mod_timer(s->second_timer2, s->next_second_time);
 596     rtc_timer_update(s, now);
 597 #ifdef TARGET_I386
 598     if (s->lost_tick_policy == LOST_TICK_SLEW) {
 599         rtc_coalesced_timer_update(s);
 600     }
 601 #endif
 602 }
 603
 604 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 605    BIOS will read it and start S3 resume at POST Entry */
 606 static void rtc_notify_suspend(Notifier *notifier, void *data)
 607 {
 608     RTCState *s = container_of(notifier, RTCState, suspend_notifier);
 609     rtc_set_memory(&s->dev, 0xF, 0xFE);
 610 }
 611
 612 static void rtc_reset(void *opaque)
 613 {
 614     RTCState *s = opaque;
 615
 616     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 617     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 618
 619     qemu_irq_lower(s->irq);
 620
 621 #ifdef TARGET_I386
 622     if (s->lost_tick_policy == LOST_TICK_SLEW) {
 623         s->irq_coalesced = 0;
 624     }
 625 #endif
 626 }
 627
 628 static const MemoryRegionPortio cmos_portio[] = {
 629     {0, 2, 1, .read = cmos_ioport_read, .write = cmos_ioport_write },
 630     PORTIO_END_OF_LIST(),
 631 };
 632
 633 static const MemoryRegionOps cmos_ops = {
 634     .old_portio = cmos_portio
 635 };
 636
 637 // FIXME add int32 visitor
 638 static void visit_type_int32(Visitor *v, int *value, const char *name, Error **errp)
 639 {
 640     int64_t val = *value;
 641     visit_type_int(v, &val, name, errp);
 642 }
 643
 644 static void rtc_get_date(Object *obj, Visitor *v, void *opaque,
 645                          const char *name, Error **errp)
 646 {
 647     ISADevice *isa = ISA_DEVICE(obj);
 648     RTCState *s = DO_UPCAST(RTCState, dev, isa);
 649
 650     visit_start_struct(v, NULL, "struct tm", name, 0, errp);
 651     visit_type_int32(v, &s->current_tm.tm_year, "tm_year", errp);
 652     visit_type_int32(v, &s->current_tm.tm_mon, "tm_mon", errp);
 653     visit_type_int32(v, &s->current_tm.tm_mday, "tm_mday", errp);
 654     visit_type_int32(v, &s->current_tm.tm_hour, "tm_hour", errp);
 655     visit_type_int32(v, &s->current_tm.tm_min, "tm_min", errp);
 656     visit_type_int32(v, &s->current_tm.tm_sec, "tm_sec", errp);
 657     visit_end_struct(v, errp);
 658 }
 659
 660 static int rtc_initfn(ISADevice *dev)
 661 {
 662     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 663     int base = 0x70;
 664
 665     s->cmos_data[RTC_REG_A] = 0x26;
 666     s->cmos_data[RTC_REG_B] = 0x02;
 667     s->cmos_data[RTC_REG_C] = 0x00;
 668     s->cmos_data[RTC_REG_D] = 0x80;
 669
 670     rtc_set_date_from_host(dev);
 671
 672 #ifdef TARGET_I386
 673     switch (s->lost_tick_policy) {
 674     case LOST_TICK_SLEW:
 675         s->coalesced_timer =
 676             qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
 677         break;
 678     case LOST_TICK_DISCARD:
 679         break;
 680     default:
 681         return -EINVAL;
 682     }
 683 #endif
 684
 685     s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
 686     s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s);
 687     s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s);
 688
 689     s->clock_reset_notifier.notify = rtc_notify_clock_reset;
 690     qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
 691
 692     s->suspend_notifier.notify = rtc_notify_suspend;
 693     qemu_register_suspend_notifier(&s->suspend_notifier);
 694
 695     s->next_second_time =
 696         qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
 697     qemu_mod_timer(s->second_timer2, s->next_second_time);
 698
 699     memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2);
 700     isa_register_ioport(dev, &s->io, base);
 701
 702     qdev_set_legacy_instance_id(&dev->qdev, base, 2);
 703     qemu_register_reset(rtc_reset, s);
 704
 705     object_property_add(OBJECT(s), "date", "struct tm",
 706                         rtc_get_date, NULL, NULL, s, NULL);
 707
 708     return 0;
 709 }
 710
 711 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
 712 {
 713     ISADevice *dev;
 714     RTCState *s;
 715
 716     dev = isa_create(bus, "mc146818rtc");
 717     s = DO_UPCAST(RTCState, dev, dev);
 718     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 719     qdev_init_nofail(&dev->qdev);
 720     if (intercept_irq) {
 721         s->irq = intercept_irq;
 722     } else {
 723         isa_init_irq(dev, &s->irq, RTC_ISA_IRQ);
 724     }
 725     return dev;
 726 }
 727
 728 static Property mc146818rtc_properties[] = {
 729     DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 730     DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
 731                                lost_tick_policy, LOST_TICK_DISCARD),
 732     DEFINE_PROP_END_OF_LIST(),
 733 };
 734
 735 static void rtc_class_initfn(ObjectClass *klass, void *data)
 736 {
 737     DeviceClass *dc = DEVICE_CLASS(klass);
 738     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 739     ic->init = rtc_initfn;
 740     dc->no_user = 1;
 741     dc->vmsd = &vmstate_rtc;
 742     dc->props = mc146818rtc_properties;
 743 }
 744
 745 static TypeInfo mc146818rtc_info = {
 746     .name          = "mc146818rtc",
 747     .parent        = TYPE_ISA_DEVICE,
 748     .instance_size = sizeof(RTCState),
 749     .class_init    = rtc_class_initfn,
 750 };
 751
 752 static void mc146818rtc_register_types(void)
 753 {
 754     type_register_static(&mc146818rtc_info);
 755 }
 756
 757 type_init(mc146818rtc_register_types)