hw/exynos4210.c

   1 /*
   2  *  Samsung exynos4210 SoC emulation
   3  *
   4  *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
   5  *    Maksim Kozlov <m.kozlov@samsung.com>
   6  *    Evgeny Voevodin <e.voevodin@samsung.com>
   7  *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License as published by the
  11  *  Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This program is distributed in the hope that it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  */
  23
  24 #include "boards.h"
  25 #include "sysemu.h"
  26 #include "sysbus.h"
  27 #include "arm-misc.h"
  28 #include "exynos4210.h"
  29
  30 #define EXYNOS4210_CHIPID_ADDR         0x10000000
  31
  32 /* PWM */
  33 #define EXYNOS4210_PWM_BASE_ADDR       0x139D0000
  34
  35 /* MCT */
  36 #define EXYNOS4210_MCT_BASE_ADDR       0x10050000
  37
  38 /* UART's definitions */
  39 #define EXYNOS4210_UART0_BASE_ADDR     0x13800000
  40 #define EXYNOS4210_UART1_BASE_ADDR     0x13810000
  41 #define EXYNOS4210_UART2_BASE_ADDR     0x13820000
  42 #define EXYNOS4210_UART3_BASE_ADDR     0x13830000
  43 #define EXYNOS4210_UART0_FIFO_SIZE     256
  44 #define EXYNOS4210_UART1_FIFO_SIZE     64
  45 #define EXYNOS4210_UART2_FIFO_SIZE     16
  46 #define EXYNOS4210_UART3_FIFO_SIZE     16
  47 /* Interrupt Group of External Interrupt Combiner for UART */
  48 #define EXYNOS4210_UART_INT_GRP        26
  49
  50 /* External GIC */
  51 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
  52 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000
  53
  54 /* Combiner */
  55 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
  56 #define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000
  57
  58 /* PMU SFR base address */
  59 #define EXYNOS4210_PMU_BASE_ADDR            0x10020000
  60
  61 /* Display controllers (FIMD) */
  62 #define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
  63
  64 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
  65                                     0x09, 0x00, 0x00, 0x00 };
  66
  67 Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
  68         unsigned long ram_size)
  69 {
  70     qemu_irq cpu_irq[4];
  71     int n;
  72     Exynos4210State *s = g_new(Exynos4210State, 1);
  73     qemu_irq *irqp;
  74     qemu_irq gate_irq[EXYNOS4210_IRQ_GATE_NINPUTS];
  75     unsigned long mem_size;
  76     DeviceState *dev;
  77     SysBusDevice *busdev;
  78
  79     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
  80         s->env[n] = cpu_init("cortex-a9");
  81         if (!s->env[n]) {
  82             fprintf(stderr, "Unable to find CPU %d definition\n", n);
  83             exit(1);
  84         }
  85         /* Create PIC controller for each processor instance */
  86         irqp = arm_pic_init_cpu(s->env[n]);
  87
  88         /*
  89          * Get GICs gpio_in cpu_irq to connect a combiner to them later.
  90          * Use only IRQ for a while.
  91          */
  92         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
  93     }
  94
  95     /*** IRQs ***/
  96
  97     s->irq_table = exynos4210_init_irq(&s->irqs);
  98
  99     /* IRQ Gate */
 100     dev = qdev_create(NULL, "exynos4210.irq_gate");
 101     qdev_init_nofail(dev);
 102     /* Get IRQ Gate input in gate_irq */
 103     for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
 104         gate_irq[n] = qdev_get_gpio_in(dev, n);
 105     }
 106     busdev = sysbus_from_qdev(dev);
 107     /* Connect IRQ Gate output to cpu_irq */
 108     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 109         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 110     }
 111
 112     /* Private memory region and Internal GIC */
 113     dev = qdev_create(NULL, "a9mpcore_priv");
 114     qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 115     qdev_init_nofail(dev);
 116     busdev = sysbus_from_qdev(dev);
 117     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
 118     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 119         sysbus_connect_irq(busdev, n, gate_irq[n * 2]);
 120     }
 121     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
 122         s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
 123     }
 124
 125     /* Cache controller */
 126     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
 127
 128     /* External GIC */
 129     dev = qdev_create(NULL, "exynos4210.gic");
 130     qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 131     qdev_init_nofail(dev);
 132     busdev = sysbus_from_qdev(dev);
 133     /* Map CPU interface */
 134     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
 135     /* Map Distributer interface */
 136     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
 137     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 138         sysbus_connect_irq(busdev, n, gate_irq[n * 2 + 1]);
 139     }
 140     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
 141         s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
 142     }
 143
 144     /* Internal Interrupt Combiner */
 145     dev = qdev_create(NULL, "exynos4210.combiner");
 146     qdev_init_nofail(dev);
 147     busdev = sysbus_from_qdev(dev);
 148     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 149         sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
 150     }
 151     exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
 152     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 153
 154     /* External Interrupt Combiner */
 155     dev = qdev_create(NULL, "exynos4210.combiner");
 156     qdev_prop_set_uint32(dev, "external", 1);
 157     qdev_init_nofail(dev);
 158     busdev = sysbus_from_qdev(dev);
 159     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 160         sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
 161     }
 162     exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
 163     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 164
 165     /* Initialize board IRQs. */
 166     exynos4210_init_board_irqs(&s->irqs);
 167
 168     /*** Memory ***/
 169
 170     /* Chip-ID and OMR */
 171     memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
 172             sizeof(chipid_and_omr), chipid_and_omr);
 173     memory_region_set_readonly(&s->chipid_mem, true);
 174     memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
 175                                 &s->chipid_mem);
 176
 177     /* Internal ROM */
 178     memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
 179                            EXYNOS4210_IROM_SIZE);
 180     memory_region_set_readonly(&s->irom_mem, true);
 181     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
 182                                 &s->irom_mem);
 183     /* mirror of iROM */
 184     memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
 185                              &s->irom_mem,
 186                              EXYNOS4210_IROM_BASE_ADDR,
 187                              EXYNOS4210_IROM_SIZE);
 188     memory_region_set_readonly(&s->irom_alias_mem, true);
 189     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
 190                                 &s->irom_alias_mem);
 191
 192     /* Internal RAM */
 193     memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
 194                            EXYNOS4210_IRAM_SIZE);
 195     vmstate_register_ram_global(&s->iram_mem);
 196     memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
 197                                 &s->iram_mem);
 198
 199     /* DRAM */
 200     mem_size = ram_size;
 201     if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
 202         memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
 203                 mem_size - EXYNOS4210_DRAM_MAX_SIZE);
 204         vmstate_register_ram_global(&s->dram1_mem);
 205         memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
 206                 &s->dram1_mem);
 207         mem_size = EXYNOS4210_DRAM_MAX_SIZE;
 208     }
 209     memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
 210     vmstate_register_ram_global(&s->dram0_mem);
 211     memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
 212             &s->dram0_mem);
 213
 214    /* PMU.
 215     * The only reason of existence at the moment is that secondary CPU boot
 216     * loader uses PMU INFORM5 register as a holding pen.
 217     */
 218     sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
 219
 220     /* PWM */
 221     sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
 222                           s->irq_table[exynos4210_get_irq(22, 0)],
 223                           s->irq_table[exynos4210_get_irq(22, 1)],
 224                           s->irq_table[exynos4210_get_irq(22, 2)],
 225                           s->irq_table[exynos4210_get_irq(22, 3)],
 226                           s->irq_table[exynos4210_get_irq(22, 4)],
 227                           NULL);
 228
 229     /* Multi Core Timer */
 230     dev = qdev_create(NULL, "exynos4210.mct");
 231     qdev_init_nofail(dev);
 232     busdev = sysbus_from_qdev(dev);
 233     for (n = 0; n < 4; n++) {
 234         /* Connect global timer interrupts to Combiner gpio_in */
 235         sysbus_connect_irq(busdev, n,
 236                 s->irq_table[exynos4210_get_irq(1, 4 + n)]);
 237     }
 238     /* Connect local timer interrupts to Combiner gpio_in */
 239     sysbus_connect_irq(busdev, 4,
 240             s->irq_table[exynos4210_get_irq(51, 0)]);
 241     sysbus_connect_irq(busdev, 5,
 242             s->irq_table[exynos4210_get_irq(35, 3)]);
 243     sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
 244
 245     /*** UARTs ***/
 246     exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
 247                            EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
 248                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
 249
 250     exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
 251                            EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
 252                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
 253
 254     exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
 255                            EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
 256                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
 257
 258     exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
 259                            EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
 260                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
 261
 262     /*** Display controller (FIMD) ***/
 263     sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
 264             s->irq_table[exynos4210_get_irq(11, 0)],
 265             s->irq_table[exynos4210_get_irq(11, 1)],
 266             s->irq_table[exynos4210_get_irq(11, 2)],
 267             NULL);
 268
 269     return s;
 270 }