hw/lm32_boards.c

   1 /*
   2  *  QEMU models for LatticeMico32 uclinux and evr32 boards.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "sysbus.h"
  21 #include "hw.h"
  22 #include "net.h"
  23 #include "flash.h"
  24 #include "sysemu.h"
  25 #include "devices.h"
  26 #include "boards.h"
  27 #include "loader.h"
  28 #include "blockdev.h"
  29 #include "elf.h"
  30 #include "lm32_hwsetup.h"
  31 #include "lm32.h"
  32
  33 typedef struct {
  34     CPUState *env;
  35     target_phys_addr_t bootstrap_pc;
  36     target_phys_addr_t flash_base;
  37     target_phys_addr_t hwsetup_base;
  38     target_phys_addr_t initrd_base;
  39     size_t initrd_size;
  40     target_phys_addr_t cmdline_base;
  41 } ResetInfo;
  42
  43 static void cpu_irq_handler(void *opaque, int irq, int level)
  44 {
  45     CPUState *env = opaque;
  46
  47     if (level) {
  48         cpu_interrupt(env, CPU_INTERRUPT_HARD);
  49     } else {
  50         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  51     }
  52 }
  53
  54 static void main_cpu_reset(void *opaque)
  55 {
  56     ResetInfo *reset_info = opaque;
  57     CPUState *env = reset_info->env;
  58
  59     cpu_reset(env);
  60
  61     /* init defaults */
  62     env->pc = (uint32_t)reset_info->bootstrap_pc;
  63     env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
  64     env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
  65     env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
  66     env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
  67         reset_info->initrd_size);
  68     env->eba = reset_info->flash_base;
  69     env->deba = reset_info->flash_base;
  70 }
  71
  72 static void lm32_evr_init(ram_addr_t ram_size_not_used,
  73                           const char *boot_device,
  74                           const char *kernel_filename,
  75                           const char *kernel_cmdline,
  76                           const char *initrd_filename, const char *cpu_model)
  77 {
  78     CPUState *env;
  79     DriveInfo *dinfo;
  80     ram_addr_t phys_ram;
  81     ram_addr_t phys_flash;
  82     qemu_irq *cpu_irq, irq[32];
  83     ResetInfo *reset_info;
  84     int i;
  85
  86     /* memory map */
  87     target_phys_addr_t flash_base  = 0x04000000;
  88     size_t flash_sector_size       = 256 * 1024;
  89     size_t flash_size              = 32 * 1024 * 1024;
  90     target_phys_addr_t ram_base    = 0x08000000;
  91     size_t ram_size                = 64 * 1024 * 1024;
  92     target_phys_addr_t timer0_base = 0x80002000;
  93     target_phys_addr_t uart0_base  = 0x80006000;
  94     target_phys_addr_t timer1_base = 0x8000a000;
  95     int uart0_irq                  = 0;
  96     int timer0_irq                 = 1;
  97     int timer1_irq                 = 3;
  98
  99     reset_info = qemu_mallocz(sizeof(ResetInfo));
 100
 101     if (cpu_model == NULL) {
 102         cpu_model = "lm32-full";
 103     }
 104     env = cpu_init(cpu_model);
 105     reset_info->env = env;
 106
 107     reset_info->flash_base = flash_base;
 108
 109     phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size);
 110     cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
 111
 112     phys_flash = qemu_ram_alloc(NULL, "lm32_evr.flash", flash_size);
 113     dinfo = drive_get(IF_PFLASH, 0, 0);
 114     /* Spansion S29NS128P */
 115     pflash_cfi02_register(flash_base, phys_flash,
 116                           dinfo ? dinfo->bdrv : NULL, flash_sector_size,
 117                           flash_size / flash_sector_size, 1, 2,
 118                           0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 119
 120     /* create irq lines */
 121     cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
 122     env->pic_state = lm32_pic_init(*cpu_irq);
 123     for (i = 0; i < 32; i++) {
 124         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 125     }
 126
 127     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 128     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 129     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 130
 131     /* make sure juart isn't the first chardev */
 132     env->juart_state = lm32_juart_init();
 133
 134     reset_info->bootstrap_pc = flash_base;
 135
 136     if (kernel_filename) {
 137         uint64_t entry;
 138         int kernel_size;
 139
 140         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 141                                1, ELF_MACHINE, 0);
 142         reset_info->bootstrap_pc = entry;
 143
 144         if (kernel_size < 0) {
 145             kernel_size = load_image_targphys(kernel_filename, ram_base,
 146                                               ram_size);
 147             reset_info->bootstrap_pc = ram_base;
 148         }
 149
 150         if (kernel_size < 0) {
 151             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 152                     kernel_filename);
 153             exit(1);
 154         }
 155     }
 156
 157     qemu_register_reset(main_cpu_reset, reset_info);
 158 }
 159
 160 static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
 161                           const char *boot_device,
 162                           const char *kernel_filename,
 163                           const char *kernel_cmdline,
 164                           const char *initrd_filename, const char *cpu_model)
 165 {
 166     CPUState *env;
 167     DriveInfo *dinfo;
 168     ram_addr_t phys_ram;
 169     ram_addr_t phys_flash;
 170     qemu_irq *cpu_irq, irq[32];
 171     HWSetup *hw;
 172     ResetInfo *reset_info;
 173     int i;
 174
 175     /* memory map */
 176     target_phys_addr_t flash_base   = 0x04000000;
 177     size_t flash_sector_size        = 256 * 1024;
 178     size_t flash_size               = 32 * 1024 * 1024;
 179     target_phys_addr_t ram_base     = 0x08000000;
 180     size_t ram_size                 = 64 * 1024 * 1024;
 181     target_phys_addr_t uart0_base   = 0x80000000;
 182     target_phys_addr_t timer0_base  = 0x80002000;
 183     target_phys_addr_t timer1_base  = 0x80010000;
 184     target_phys_addr_t timer2_base  = 0x80012000;
 185     int uart0_irq                   = 0;
 186     int timer0_irq                  = 1;
 187     int timer1_irq                  = 20;
 188     int timer2_irq                  = 21;
 189     target_phys_addr_t hwsetup_base = 0x0bffe000;
 190     target_phys_addr_t cmdline_base = 0x0bfff000;
 191     target_phys_addr_t initrd_base  = 0x08400000;
 192     size_t initrd_max               = 0x01000000;
 193
 194     reset_info = qemu_mallocz(sizeof(ResetInfo));
 195
 196     if (cpu_model == NULL) {
 197         cpu_model = "lm32-full";
 198     }
 199     env = cpu_init(cpu_model);
 200     reset_info->env = env;
 201
 202     reset_info->flash_base = flash_base;
 203
 204     phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size);
 205     cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
 206
 207     phys_flash = qemu_ram_alloc(NULL, "lm32_uclinux.flash", flash_size);
 208     dinfo = drive_get(IF_PFLASH, 0, 0);
 209     /* Spansion S29NS128P */
 210     pflash_cfi02_register(flash_base, phys_flash,
 211                           dinfo ? dinfo->bdrv : NULL, flash_sector_size,
 212                           flash_size / flash_sector_size, 1, 2,
 213                           0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 214
 215     /* create irq lines */
 216     cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
 217     env->pic_state = lm32_pic_init(*cpu_irq);
 218     for (i = 0; i < 32; i++) {
 219         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 220     }
 221
 222     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 223     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 224     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 225     sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
 226
 227     /* make sure juart isn't the first chardev */
 228     env->juart_state = lm32_juart_init();
 229
 230     reset_info->bootstrap_pc = flash_base;
 231
 232     if (kernel_filename) {
 233         uint64_t entry;
 234         int kernel_size;
 235
 236         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 237                                1, ELF_MACHINE, 0);
 238         reset_info->bootstrap_pc = entry;
 239
 240         if (kernel_size < 0) {
 241             kernel_size = load_image_targphys(kernel_filename, ram_base,
 242                                               ram_size);
 243             reset_info->bootstrap_pc = ram_base;
 244         }
 245
 246         if (kernel_size < 0) {
 247             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 248                     kernel_filename);
 249             exit(1);
 250         }
 251     }
 252
 253     /* generate a rom with the hardware description */
 254     hw = hwsetup_init();
 255     hwsetup_add_cpu(hw, "LM32", 75000000);
 256     hwsetup_add_flash(hw, "flash", flash_base, flash_size);
 257     hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
 258     hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
 259     hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
 260     hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
 261     hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
 262     hwsetup_add_trailer(hw);
 263     hwsetup_create_rom(hw, hwsetup_base);
 264     hwsetup_free(hw);
 265
 266     reset_info->hwsetup_base = hwsetup_base;
 267
 268     if (kernel_cmdline && strlen(kernel_cmdline)) {
 269         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
 270                 kernel_cmdline);
 271         reset_info->cmdline_base = cmdline_base;
 272     }
 273
 274     if (initrd_filename) {
 275         size_t initrd_size;
 276         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 277                 initrd_max);
 278         reset_info->initrd_base = initrd_base;
 279         reset_info->initrd_size = initrd_size;
 280     }
 281
 282     qemu_register_reset(main_cpu_reset, reset_info);
 283 }
 284
 285 static QEMUMachine lm32_evr_machine = {
 286     .name = "lm32-evr",
 287     .desc = "LatticeMico32 EVR32 eval system",
 288     .init = lm32_evr_init,
 289     .is_default = 1
 290 };
 291
 292 static QEMUMachine lm32_uclinux_machine = {
 293     .name = "lm32-uclinux",
 294     .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
 295     .init = lm32_uclinux_init,
 296     .is_default = 0
 297 };
 298
 299 static void lm32_machine_init(void)
 300 {
 301     qemu_register_machine(&lm32_uclinux_machine);
 302     qemu_register_machine(&lm32_evr_machine);
 303 }
 304
 305 machine_init(lm32_machine_init);