2 * IMX31 Clock Control Module
4 * Copyright (C) 2012 NICTA
5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
10 * To get the timer frequencies right, we need to emulate at least part of
14 #include "hw/misc/imx31_ccm.h"
16 #define CKIH_FREQ 26000000 /* 26MHz crystal input */
18 #ifndef DEBUG_IMX31_CCM
19 #define DEBUG_IMX31_CCM 0
22 #define DPRINTF(fmt, args...) \
24 if (DEBUG_IMX31_CCM) { \
25 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
30 static char const *imx31_ccm_reg_name(uint32_t reg
)
32 static char unknown
[20];
35 case IMX31_CCM_CCMR_REG
:
37 case IMX31_CCM_PDR0_REG
:
39 case IMX31_CCM_PDR1_REG
:
41 case IMX31_CCM_RCSR_REG
:
43 case IMX31_CCM_MPCTL_REG
:
45 case IMX31_CCM_UPCTL_REG
:
47 case IMX31_CCM_SPCTL_REG
:
49 case IMX31_CCM_COSR_REG
:
51 case IMX31_CCM_CGR0_REG
:
53 case IMX31_CCM_CGR1_REG
:
55 case IMX31_CCM_CGR2_REG
:
57 case IMX31_CCM_WIMR_REG
:
59 case IMX31_CCM_LDC_REG
:
61 case IMX31_CCM_DCVR0_REG
:
63 case IMX31_CCM_DCVR1_REG
:
65 case IMX31_CCM_DCVR2_REG
:
67 case IMX31_CCM_DCVR3_REG
:
69 case IMX31_CCM_LTR0_REG
:
71 case IMX31_CCM_LTR1_REG
:
73 case IMX31_CCM_LTR2_REG
:
75 case IMX31_CCM_LTR3_REG
:
77 case IMX31_CCM_LTBR0_REG
:
79 case IMX31_CCM_LTBR1_REG
:
81 case IMX31_CCM_PMCR0_REG
:
83 case IMX31_CCM_PMCR1_REG
:
85 case IMX31_CCM_PDR2_REG
:
88 sprintf(unknown
, "[%d ?]", reg
);
93 static const VMStateDescription vmstate_imx31_ccm
= {
94 .name
= TYPE_IMX31_CCM
,
96 .minimum_version_id
= 2,
97 .fields
= (VMStateField
[]) {
98 VMSTATE_UINT32_ARRAY(reg
, IMX31CCMState
, IMX31_CCM_MAX_REG
),
103 static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState
*dev
)
106 IMX31CCMState
*s
= IMX31_CCM(dev
);
108 if ((s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_PRCS
) == 2) {
109 if (s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_FPME
) {
111 if (s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_FPMF
) {
119 DPRINTF("freq = %d\n", freq
);
124 static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState
*dev
)
127 IMX31CCMState
*s
= IMX31_CCM(dev
);
129 freq
= imx_ccm_calc_pll(s
->reg
[IMX31_CCM_MPCTL_REG
],
130 imx31_ccm_get_pll_ref_clk(dev
));
132 DPRINTF("freq = %d\n", freq
);
137 static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState
*dev
)
140 IMX31CCMState
*s
= IMX31_CCM(dev
);
142 if ((s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_MDS
) ||
143 !(s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_MPE
)) {
144 freq
= imx31_ccm_get_pll_ref_clk(dev
);
146 freq
= imx31_ccm_get_mpll_clk(dev
);
149 DPRINTF("freq = %d\n", freq
);
154 static uint32_t imx31_ccm_get_mcu_clk(IMXCCMState
*dev
)
157 IMX31CCMState
*s
= IMX31_CCM(dev
);
159 freq
= imx31_ccm_get_mcu_main_clk(dev
)
160 / (1 + EXTRACT(s
->reg
[IMX31_CCM_PDR0_REG
], MCU
));
162 DPRINTF("freq = %d\n", freq
);
167 static uint32_t imx31_ccm_get_hsp_clk(IMXCCMState
*dev
)
170 IMX31CCMState
*s
= IMX31_CCM(dev
);
172 freq
= imx31_ccm_get_mcu_main_clk(dev
)
173 / (1 + EXTRACT(s
->reg
[IMX31_CCM_PDR0_REG
], HSP
));
175 DPRINTF("freq = %d\n", freq
);
180 static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState
*dev
)
183 IMX31CCMState
*s
= IMX31_CCM(dev
);
185 freq
= imx31_ccm_get_mcu_main_clk(dev
)
186 / (1 + EXTRACT(s
->reg
[IMX31_CCM_PDR0_REG
], MAX
));
188 DPRINTF("freq = %d\n", freq
);
193 static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState
*dev
)
196 IMX31CCMState
*s
= IMX31_CCM(dev
);
198 freq
= imx31_ccm_get_hclk_clk(dev
)
199 / (1 + EXTRACT(s
->reg
[IMX31_CCM_PDR0_REG
], IPG
));
201 DPRINTF("freq = %d\n", freq
);
206 static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState
*dev
, IMXClk clock
)
214 freq
= imx31_ccm_get_mcu_clk(dev
);
217 freq
= imx31_ccm_get_hsp_clk(dev
);
220 freq
= imx31_ccm_get_ipg_clk(dev
);
226 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: unsupported clock %d\n",
227 TYPE_IMX31_CCM
, __func__
, clock
);
231 DPRINTF("Clock = %d) = %d\n", clock
, freq
);
236 static void imx31_ccm_reset(DeviceState
*dev
)
238 IMX31CCMState
*s
= IMX31_CCM(dev
);
242 memset(s
->reg
, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG
);
244 s
->reg
[IMX31_CCM_CCMR_REG
] = 0x074b0b7d;
245 s
->reg
[IMX31_CCM_PDR0_REG
] = 0xff870b48;
246 s
->reg
[IMX31_CCM_PDR1_REG
] = 0x49fcfe7f;
247 s
->reg
[IMX31_CCM_RCSR_REG
] = 0x007f0000;
248 s
->reg
[IMX31_CCM_MPCTL_REG
] = 0x04001800;
249 s
->reg
[IMX31_CCM_UPCTL_REG
] = 0x04051c03;
250 s
->reg
[IMX31_CCM_SPCTL_REG
] = 0x04043001;
251 s
->reg
[IMX31_CCM_COSR_REG
] = 0x00000280;
252 s
->reg
[IMX31_CCM_CGR0_REG
] = 0xffffffff;
253 s
->reg
[IMX31_CCM_CGR1_REG
] = 0xffffffff;
254 s
->reg
[IMX31_CCM_CGR2_REG
] = 0xffffffff;
255 s
->reg
[IMX31_CCM_WIMR_REG
] = 0xffffffff;
256 s
->reg
[IMX31_CCM_LTR1_REG
] = 0x00004040;
257 s
->reg
[IMX31_CCM_PMCR0_REG
] = 0x80209828;
258 s
->reg
[IMX31_CCM_PMCR1_REG
] = 0x00aa0000;
259 s
->reg
[IMX31_CCM_PDR2_REG
] = 0x00000285;
262 static uint64_t imx31_ccm_read(void *opaque
, hwaddr offset
, unsigned size
)
265 IMX31CCMState
*s
= (IMX31CCMState
*)opaque
;
267 if ((offset
>> 2) < IMX31_CCM_MAX_REG
) {
268 value
= s
->reg
[offset
>> 2];
270 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
271 HWADDR_PRIx
"\n", TYPE_IMX31_CCM
, __func__
, offset
);
274 DPRINTF("reg[%s] => 0x%" PRIx32
"\n", imx31_ccm_reg_name(offset
>> 2),
277 return (uint64_t)value
;
280 static void imx31_ccm_write(void *opaque
, hwaddr offset
, uint64_t value
,
283 IMX31CCMState
*s
= (IMX31CCMState
*)opaque
;
285 DPRINTF("reg[%s] <= 0x%" PRIx32
"\n", imx31_ccm_reg_name(offset
>> 2),
288 switch (offset
>> 2) {
289 case IMX31_CCM_CCMR_REG
:
290 s
->reg
[IMX31_CCM_CCMR_REG
] = CCMR_FPMF
| (value
& 0x3b6fdfff);
292 case IMX31_CCM_PDR0_REG
:
293 s
->reg
[IMX31_CCM_PDR0_REG
] = value
& 0xff9f3fff;
295 case IMX31_CCM_PDR1_REG
:
296 s
->reg
[IMX31_CCM_PDR1_REG
] = value
;
298 case IMX31_CCM_MPCTL_REG
:
299 s
->reg
[IMX31_CCM_MPCTL_REG
] = value
& 0xbfff3fff;
301 case IMX31_CCM_SPCTL_REG
:
302 s
->reg
[IMX31_CCM_SPCTL_REG
] = value
& 0xbfff3fff;
304 case IMX31_CCM_CGR0_REG
:
305 s
->reg
[IMX31_CCM_CGR0_REG
] = value
;
307 case IMX31_CCM_CGR1_REG
:
308 s
->reg
[IMX31_CCM_CGR1_REG
] = value
;
310 case IMX31_CCM_CGR2_REG
:
311 s
->reg
[IMX31_CCM_CGR2_REG
] = value
;
314 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
315 HWADDR_PRIx
"\n", TYPE_IMX31_CCM
, __func__
, offset
);
320 static const struct MemoryRegionOps imx31_ccm_ops
= {
321 .read
= imx31_ccm_read
,
322 .write
= imx31_ccm_write
,
323 .endianness
= DEVICE_NATIVE_ENDIAN
,
326 * Our device would not work correctly if the guest was doing
327 * unaligned access. This might not be a limitation on the real
328 * device but in practice there is no reason for a guest to access
329 * this device unaligned.
331 .min_access_size
= 4,
332 .max_access_size
= 4,
338 static void imx31_ccm_init(Object
*obj
)
340 DeviceState
*dev
= DEVICE(obj
);
341 SysBusDevice
*sd
= SYS_BUS_DEVICE(obj
);
342 IMX31CCMState
*s
= IMX31_CCM(obj
);
344 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &imx31_ccm_ops
, s
,
345 TYPE_IMX31_CCM
, 0x1000);
346 sysbus_init_mmio(sd
, &s
->iomem
);
349 static void imx31_ccm_class_init(ObjectClass
*klass
, void *data
)
351 DeviceClass
*dc
= DEVICE_CLASS(klass
);
352 IMXCCMClass
*ccm
= IMX_CCM_CLASS(klass
);
354 dc
->reset
= imx31_ccm_reset
;
355 dc
->vmsd
= &vmstate_imx31_ccm
;
356 dc
->desc
= "i.MX31 Clock Control Module";
358 ccm
->get_clock_frequency
= imx31_ccm_get_clock_frequency
;
361 static const TypeInfo imx31_ccm_info
= {
362 .name
= TYPE_IMX31_CCM
,
363 .parent
= TYPE_IMX_CCM
,
364 .instance_size
= sizeof(IMX31CCMState
),
365 .instance_init
= imx31_ccm_init
,
366 .class_init
= imx31_ccm_class_init
,
369 static void imx31_ccm_register_types(void)
371 type_register_static(&imx31_ccm_info
);
374 type_init(imx31_ccm_register_types
)