hw/misc/imx31_ccm.c

   1 /*
   2  * IMX31 Clock Control Module
   3  *
   4  * Copyright (C) 2012 NICTA
   5  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   8  * See the COPYING file in the top-level directory.
   9  *
  10  * To get the timer frequencies right, we need to emulate at least part of
  11  * the i.MX31 CCM.
  12  */
  13
  14 #include "hw/misc/imx31_ccm.h"
  15
  16 #define CKIH_FREQ 26000000 /* 26MHz crystal input */
  17
  18 #ifndef DEBUG_IMX31_CCM
  19 #define DEBUG_IMX31_CCM 0
  20 #endif
  21
  22 #define DPRINTF(fmt, args...) \
  23     do { \
  24         if (DEBUG_IMX31_CCM) { \
  25             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
  26                                              __func__, ##args); \
  27         } \
  28     } while (0)
  29
  30 static char const *imx31_ccm_reg_name(uint32_t reg)
  31 {
  32     static char unknown[20];
  33
  34     switch (reg) {
  35     case IMX31_CCM_CCMR_REG:
  36         return "CCMR";
  37     case IMX31_CCM_PDR0_REG:
  38         return "PDR0";
  39     case IMX31_CCM_PDR1_REG:
  40         return "PDR1";
  41     case IMX31_CCM_RCSR_REG:
  42         return "RCSR";
  43     case IMX31_CCM_MPCTL_REG:
  44         return "MPCTL";
  45     case IMX31_CCM_UPCTL_REG:
  46         return "UPCTL";
  47     case IMX31_CCM_SPCTL_REG:
  48         return "SPCTL";
  49     case IMX31_CCM_COSR_REG:
  50         return "COSR";
  51     case IMX31_CCM_CGR0_REG:
  52         return "CGR0";
  53     case IMX31_CCM_CGR1_REG:
  54         return "CGR1";
  55     case IMX31_CCM_CGR2_REG:
  56         return "CGR2";
  57     case IMX31_CCM_WIMR_REG:
  58         return "WIMR";
  59     case IMX31_CCM_LDC_REG:
  60         return "LDC";
  61     case IMX31_CCM_DCVR0_REG:
  62         return "DCVR0";
  63     case IMX31_CCM_DCVR1_REG:
  64         return "DCVR1";
  65     case IMX31_CCM_DCVR2_REG:
  66         return "DCVR2";
  67     case IMX31_CCM_DCVR3_REG:
  68         return "DCVR3";
  69     case IMX31_CCM_LTR0_REG:
  70         return "LTR0";
  71     case IMX31_CCM_LTR1_REG:
  72         return "LTR1";
  73     case IMX31_CCM_LTR2_REG:
  74         return "LTR2";
  75     case IMX31_CCM_LTR3_REG:
  76         return "LTR3";
  77     case IMX31_CCM_LTBR0_REG:
  78         return "LTBR0";
  79     case IMX31_CCM_LTBR1_REG:
  80         return "LTBR1";
  81     case IMX31_CCM_PMCR0_REG:
  82         return "PMCR0";
  83     case IMX31_CCM_PMCR1_REG:
  84         return "PMCR1";
  85     case IMX31_CCM_PDR2_REG:
  86         return "PDR2";
  87     default:
  88         sprintf(unknown, "[%d ?]", reg);
  89         return unknown;
  90     }
  91 }
  92
  93 static const VMStateDescription vmstate_imx31_ccm = {
  94     .name = TYPE_IMX31_CCM,
  95     .version_id = 2,
  96     .minimum_version_id = 2,
  97     .fields = (VMStateField[]) {
  98         VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
  99         VMSTATE_END_OF_LIST()
 100     },
 101 };
 102
 103 static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
 104 {
 105     uint32_t freq = 0;
 106     IMX31CCMState *s = IMX31_CCM(dev);
 107
 108     if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
 109         if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
 110             freq = CKIL_FREQ;
 111             if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
 112                 freq *= 1024;
 113             }
 114         }
 115     } else {
 116         freq = CKIH_FREQ;
 117     }
 118
 119     DPRINTF("freq = %d\n", freq);
 120
 121     return freq;
 122 }
 123
 124 static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
 125 {
 126     uint32_t freq;
 127     IMX31CCMState *s = IMX31_CCM(dev);
 128
 129     freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
 130                             imx31_ccm_get_pll_ref_clk(dev));
 131
 132     DPRINTF("freq = %d\n", freq);
 133
 134     return freq;
 135 }
 136
 137 static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
 138 {
 139     uint32_t freq;
 140     IMX31CCMState *s = IMX31_CCM(dev);
 141
 142     if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) ||
 143         !(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
 144         freq = imx31_ccm_get_pll_ref_clk(dev);
 145     } else {
 146         freq = imx31_ccm_get_mpll_clk(dev);
 147     }
 148
 149     DPRINTF("freq = %d\n", freq);
 150
 151     return freq;
 152 }
 153
 154 static uint32_t imx31_ccm_get_mcu_clk(IMXCCMState *dev)
 155 {
 156     uint32_t freq;
 157     IMX31CCMState *s = IMX31_CCM(dev);
 158
 159     freq = imx31_ccm_get_mcu_main_clk(dev)
 160            / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MCU));
 161
 162     DPRINTF("freq = %d\n", freq);
 163
 164     return freq;
 165 }
 166
 167 static uint32_t imx31_ccm_get_hsp_clk(IMXCCMState *dev)
 168 {
 169     uint32_t freq;
 170     IMX31CCMState *s = IMX31_CCM(dev);
 171
 172     freq = imx31_ccm_get_mcu_main_clk(dev)
 173            / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], HSP));
 174
 175     DPRINTF("freq = %d\n", freq);
 176
 177     return freq;
 178 }
 179
 180 static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
 181 {
 182     uint32_t freq;
 183     IMX31CCMState *s = IMX31_CCM(dev);
 184
 185     freq = imx31_ccm_get_mcu_main_clk(dev)
 186            / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
 187
 188     DPRINTF("freq = %d\n", freq);
 189
 190     return freq;
 191 }
 192
 193 static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
 194 {
 195     uint32_t freq;
 196     IMX31CCMState *s = IMX31_CCM(dev);
 197
 198     freq = imx31_ccm_get_hclk_clk(dev)
 199            / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
 200
 201     DPRINTF("freq = %d\n", freq);
 202
 203     return freq;
 204 }
 205
 206 static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
 207 {
 208     uint32_t freq = 0;
 209
 210     switch (clock) {
 211     case NOCLK:
 212         break;
 213     case CLK_MCU:
 214         freq = imx31_ccm_get_mcu_clk(dev);
 215         break;
 216     case CLK_HSP:
 217         freq = imx31_ccm_get_hsp_clk(dev);
 218         break;
 219     case CLK_IPG:
 220         freq = imx31_ccm_get_ipg_clk(dev);
 221         break;
 222     case CLK_32k:
 223         freq = CKIL_FREQ;
 224         break;
 225     default:
 226         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
 227                       TYPE_IMX31_CCM, __func__, clock);
 228         break;
 229     }
 230
 231     DPRINTF("Clock = %d) = %d\n", clock, freq);
 232
 233     return freq;
 234 }
 235
 236 static void imx31_ccm_reset(DeviceState *dev)
 237 {
 238     IMX31CCMState *s = IMX31_CCM(dev);
 239
 240     DPRINTF("()\n");
 241
 242     memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);
 243
 244     s->reg[IMX31_CCM_CCMR_REG]   = 0x074b0b7d;
 245     s->reg[IMX31_CCM_PDR0_REG]   = 0xff870b48;
 246     s->reg[IMX31_CCM_PDR1_REG]   = 0x49fcfe7f;
 247     s->reg[IMX31_CCM_RCSR_REG]   = 0x007f0000;
 248     s->reg[IMX31_CCM_MPCTL_REG]  = 0x04001800;
 249     s->reg[IMX31_CCM_UPCTL_REG]  = 0x04051c03;
 250     s->reg[IMX31_CCM_SPCTL_REG]  = 0x04043001;
 251     s->reg[IMX31_CCM_COSR_REG]   = 0x00000280;
 252     s->reg[IMX31_CCM_CGR0_REG]   = 0xffffffff;
 253     s->reg[IMX31_CCM_CGR1_REG]   = 0xffffffff;
 254     s->reg[IMX31_CCM_CGR2_REG]   = 0xffffffff;
 255     s->reg[IMX31_CCM_WIMR_REG]   = 0xffffffff;
 256     s->reg[IMX31_CCM_LTR1_REG]   = 0x00004040;
 257     s->reg[IMX31_CCM_PMCR0_REG]  = 0x80209828;
 258     s->reg[IMX31_CCM_PMCR1_REG]  = 0x00aa0000;
 259     s->reg[IMX31_CCM_PDR2_REG]   = 0x00000285;
 260 }
 261
 262 static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
 263 {
 264     uint32 value = 0;
 265     IMX31CCMState *s = (IMX31CCMState *)opaque;
 266
 267     if ((offset >> 2) < IMX31_CCM_MAX_REG) {
 268         value = s->reg[offset >> 2];
 269     } else {
 270         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 271                       HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
 272     }
 273
 274     DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
 275             value);
 276
 277     return (uint64_t)value;
 278 }
 279
 280 static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
 281                             unsigned size)
 282 {
 283     IMX31CCMState *s = (IMX31CCMState *)opaque;
 284
 285     DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
 286             (uint32_t)value);
 287
 288     switch (offset >> 2) {
 289     case IMX31_CCM_CCMR_REG:
 290         s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF | (value & 0x3b6fdfff);
 291         break;
 292     case IMX31_CCM_PDR0_REG:
 293         s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
 294         break;
 295     case IMX31_CCM_PDR1_REG:
 296         s->reg[IMX31_CCM_PDR1_REG] = value;
 297         break;
 298     case IMX31_CCM_MPCTL_REG:
 299         s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
 300         break;
 301     case IMX31_CCM_SPCTL_REG:
 302         s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
 303         break;
 304     case IMX31_CCM_CGR0_REG:
 305         s->reg[IMX31_CCM_CGR0_REG] = value;
 306         break;
 307     case IMX31_CCM_CGR1_REG:
 308         s->reg[IMX31_CCM_CGR1_REG] = value;
 309         break;
 310     case IMX31_CCM_CGR2_REG:
 311         s->reg[IMX31_CCM_CGR2_REG] = value;
 312         break;
 313     default:
 314         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 315                       HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
 316         break;
 317     }
 318 }
 319
 320 static const struct MemoryRegionOps imx31_ccm_ops = {
 321     .read = imx31_ccm_read,
 322     .write = imx31_ccm_write,
 323     .endianness = DEVICE_NATIVE_ENDIAN,
 324     .valid = {
 325         /*
 326          * Our device would not work correctly if the guest was doing
 327          * unaligned access. This might not be a limitation on the real
 328          * device but in practice there is no reason for a guest to access
 329          * this device unaligned.
 330          */
 331         .min_access_size = 4,
 332         .max_access_size = 4,
 333         .unaligned = false,
 334     },
 335
 336 };
 337
 338 static void imx31_ccm_init(Object *obj)
 339 {
 340     DeviceState *dev = DEVICE(obj);
 341     SysBusDevice *sd = SYS_BUS_DEVICE(obj);
 342     IMX31CCMState *s = IMX31_CCM(obj);
 343
 344     memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
 345                           TYPE_IMX31_CCM, 0x1000);
 346     sysbus_init_mmio(sd, &s->iomem);
 347 }
 348
 349 static void imx31_ccm_class_init(ObjectClass *klass, void *data)
 350 {
 351     DeviceClass *dc  = DEVICE_CLASS(klass);
 352     IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
 353
 354     dc->reset = imx31_ccm_reset;
 355     dc->vmsd  = &vmstate_imx31_ccm;
 356     dc->desc  = "i.MX31 Clock Control Module";
 357
 358     ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
 359 }
 360
 361 static const TypeInfo imx31_ccm_info = {
 362     .name          = TYPE_IMX31_CCM,
 363     .parent        = TYPE_IMX_CCM,
 364     .instance_size = sizeof(IMX31CCMState),
 365     .instance_init = imx31_ccm_init,
 366     .class_init    = imx31_ccm_class_init,
 367 };
 368
 369 static void imx31_ccm_register_types(void)
 370 {
 371     type_register_static(&imx31_ccm_info);
 372 }
 373
 374 type_init(imx31_ccm_register_types)