2 * ARM GICv3 support - common bits of emulated and KVM kernel model
4 * Copyright (c) 2012 Linaro Limited
5 * Copyright (c) 2015 Huawei.
6 * Written by Peter Maydell
7 * Extended to 64 cores by Shlomo Pongratz
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "hw/intc/arm_gicv3_common.h"
26 static void gicv3_pre_save(void *opaque
)
28 GICv3State
*s
= (GICv3State
*)opaque
;
29 ARMGICv3CommonClass
*c
= ARM_GICV3_COMMON_GET_CLASS(s
);
36 static int gicv3_post_load(void *opaque
, int version_id
)
38 GICv3State
*s
= (GICv3State
*)opaque
;
39 ARMGICv3CommonClass
*c
= ARM_GICV3_COMMON_GET_CLASS(s
);
47 static const VMStateDescription vmstate_gicv3
= {
50 .pre_save
= gicv3_pre_save
,
51 .post_load
= gicv3_post_load
,
54 void gicv3_init_irqs_and_mmio(GICv3State
*s
, qemu_irq_handler handler
,
55 const MemoryRegionOps
*ops
)
57 SysBusDevice
*sbd
= SYS_BUS_DEVICE(s
);
60 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
61 * GPIO array layout is thus:
63 * [N..N+31] PPIs for CPU 0
64 * [N+32..N+63] PPIs for CPU 1
67 i
= s
->num_irq
- GIC_INTERNAL
+ GIC_INTERNAL
* s
->num_cpu
;
68 qdev_init_gpio_in(DEVICE(s
), handler
, i
);
70 s
->parent_irq
= g_malloc(s
->num_cpu
* sizeof(qemu_irq
));
71 s
->parent_fiq
= g_malloc(s
->num_cpu
* sizeof(qemu_irq
));
73 for (i
= 0; i
< s
->num_cpu
; i
++) {
74 sysbus_init_irq(sbd
, &s
->parent_irq
[i
]);
76 for (i
= 0; i
< s
->num_cpu
; i
++) {
77 sysbus_init_irq(sbd
, &s
->parent_fiq
[i
]);
80 memory_region_init_io(&s
->iomem_dist
, OBJECT(s
), ops
, s
,
81 "gicv3_dist", 0x10000);
82 memory_region_init_io(&s
->iomem_redist
, OBJECT(s
), ops
? &ops
[1] : NULL
, s
,
83 "gicv3_redist", 0x20000 * s
->num_cpu
);
85 sysbus_init_mmio(sbd
, &s
->iomem_dist
);
86 sysbus_init_mmio(sbd
, &s
->iomem_redist
);
89 static void arm_gicv3_common_realize(DeviceState
*dev
, Error
**errp
)
91 GICv3State
*s
= ARM_GICV3_COMMON(dev
);
93 /* revision property is actually reserved and currently used only in order
94 * to keep the interface compatible with GICv2 code, avoiding extra
95 * conditions. However, in future it could be used, for example, if we
98 if (s
->revision
!= 3) {
99 error_setg(errp
, "unsupported GIC revision %d", s
->revision
);
104 static void arm_gicv3_common_reset(DeviceState
*dev
)
109 static Property arm_gicv3_common_properties
[] = {
110 DEFINE_PROP_UINT32("num-cpu", GICv3State
, num_cpu
, 1),
111 DEFINE_PROP_UINT32("num-irq", GICv3State
, num_irq
, 32),
112 DEFINE_PROP_UINT32("revision", GICv3State
, revision
, 3),
113 DEFINE_PROP_BOOL("has-security-extensions", GICv3State
, security_extn
, 0),
114 DEFINE_PROP_END_OF_LIST(),
117 static void arm_gicv3_common_class_init(ObjectClass
*klass
, void *data
)
119 DeviceClass
*dc
= DEVICE_CLASS(klass
);
121 dc
->reset
= arm_gicv3_common_reset
;
122 dc
->realize
= arm_gicv3_common_realize
;
123 dc
->props
= arm_gicv3_common_properties
;
124 dc
->vmsd
= &vmstate_gicv3
;
127 static const TypeInfo arm_gicv3_common_type
= {
128 .name
= TYPE_ARM_GICV3_COMMON
,
129 .parent
= TYPE_SYS_BUS_DEVICE
,
130 .instance_size
= sizeof(GICv3State
),
131 .class_size
= sizeof(ARMGICv3CommonClass
),
132 .class_init
= arm_gicv3_common_class_init
,
136 static void register_types(void)
138 type_register_static(&arm_gicv3_common_type
);
141 type_init(register_types
)