hw/dma/i8257.c

   1 /*
   2  * QEMU DMA emulation
   3  *
   4  * Copyright (c) 2003-2004 Vassili Karpov (malc)
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "hw/isa/isa.h"
  27 #include "qemu/main-loop.h"
  28 #include "trace.h"
  29
  30 /* #define DEBUG_DMA */
  31
  32 #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
  33 #ifdef DEBUG_DMA
  34 #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
  35 #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
  36 #else
  37 #define linfo(...)
  38 #define ldebug(...)
  39 #endif
  40
  41 struct dma_regs {
  42     int now[2];
  43     uint16_t base[2];
  44     uint8_t mode;
  45     uint8_t page;
  46     uint8_t pageh;
  47     uint8_t dack;
  48     uint8_t eop;
  49     DMA_transfer_handler transfer_handler;
  50     void *opaque;
  51 };
  52
  53 #define ADDR 0
  54 #define COUNT 1
  55
  56 static struct dma_cont {
  57     uint8_t status;
  58     uint8_t command;
  59     uint8_t mask;
  60     uint8_t flip_flop;
  61     int dshift;
  62     struct dma_regs regs[4];
  63     MemoryRegion channel_io;
  64     MemoryRegion cont_io;
  65 } dma_controllers[2];
  66
  67 enum {
  68     CMD_MEMORY_TO_MEMORY = 0x01,
  69     CMD_FIXED_ADDRESS    = 0x02,
  70     CMD_BLOCK_CONTROLLER = 0x04,
  71     CMD_COMPRESSED_TIME  = 0x08,
  72     CMD_CYCLIC_PRIORITY  = 0x10,
  73     CMD_EXTENDED_WRITE   = 0x20,
  74     CMD_LOW_DREQ         = 0x40,
  75     CMD_LOW_DACK         = 0x80,
  76     CMD_NOT_SUPPORTED    = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
  77     | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
  78     | CMD_LOW_DREQ | CMD_LOW_DACK
  79
  80 };
  81
  82 static void DMA_run (void);
  83
  84 static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
  85
  86 static void write_page (void *opaque, uint32_t nport, uint32_t data)
  87 {
  88     struct dma_cont *d = opaque;
  89     int ichan;
  90
  91     ichan = channels[nport & 7];
  92     if (-1 == ichan) {
  93         dolog ("invalid channel %#x %#x\n", nport, data);
  94         return;
  95     }
  96     d->regs[ichan].page = data;
  97 }
  98
  99 static void write_pageh (void *opaque, uint32_t nport, uint32_t data)
 100 {
 101     struct dma_cont *d = opaque;
 102     int ichan;
 103
 104     ichan = channels[nport & 7];
 105     if (-1 == ichan) {
 106         dolog ("invalid channel %#x %#x\n", nport, data);
 107         return;
 108     }
 109     d->regs[ichan].pageh = data;
 110 }
 111
 112 static uint32_t read_page (void *opaque, uint32_t nport)
 113 {
 114     struct dma_cont *d = opaque;
 115     int ichan;
 116
 117     ichan = channels[nport & 7];
 118     if (-1 == ichan) {
 119         dolog ("invalid channel read %#x\n", nport);
 120         return 0;
 121     }
 122     return d->regs[ichan].page;
 123 }
 124
 125 static uint32_t read_pageh (void *opaque, uint32_t nport)
 126 {
 127     struct dma_cont *d = opaque;
 128     int ichan;
 129
 130     ichan = channels[nport & 7];
 131     if (-1 == ichan) {
 132         dolog ("invalid channel read %#x\n", nport);
 133         return 0;
 134     }
 135     return d->regs[ichan].pageh;
 136 }
 137
 138 static inline void init_chan (struct dma_cont *d, int ichan)
 139 {
 140     struct dma_regs *r;
 141
 142     r = d->regs + ichan;
 143     r->now[ADDR] = r->base[ADDR] << d->dshift;
 144     r->now[COUNT] = 0;
 145 }
 146
 147 static inline int getff (struct dma_cont *d)
 148 {
 149     int ff;
 150
 151     ff = d->flip_flop;
 152     d->flip_flop = !ff;
 153     return ff;
 154 }
 155
 156 static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size)
 157 {
 158     struct dma_cont *d = opaque;
 159     int ichan, nreg, iport, ff, val, dir;
 160     struct dma_regs *r;
 161
 162     iport = (nport >> d->dshift) & 0x0f;
 163     ichan = iport >> 1;
 164     nreg = iport & 1;
 165     r = d->regs + ichan;
 166
 167     dir = ((r->mode >> 5) & 1) ? -1 : 1;
 168     ff = getff (d);
 169     if (nreg)
 170         val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
 171     else
 172         val = r->now[ADDR] + r->now[COUNT] * dir;
 173
 174     ldebug ("read_chan %#x -> %d\n", iport, val);
 175     return (val >> (d->dshift + (ff << 3))) & 0xff;
 176 }
 177
 178 static void write_chan(void *opaque, hwaddr nport, uint64_t data,
 179                        unsigned size)
 180 {
 181     struct dma_cont *d = opaque;
 182     int iport, ichan, nreg;
 183     struct dma_regs *r;
 184
 185     iport = (nport >> d->dshift) & 0x0f;
 186     ichan = iport >> 1;
 187     nreg = iport & 1;
 188     r = d->regs + ichan;
 189     if (getff (d)) {
 190         r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
 191         init_chan (d, ichan);
 192     } else {
 193         r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
 194     }
 195 }
 196
 197 static void write_cont(void *opaque, hwaddr nport, uint64_t data,
 198                        unsigned size)
 199 {
 200     struct dma_cont *d = opaque;
 201     int iport, ichan = 0;
 202
 203     iport = (nport >> d->dshift) & 0x0f;
 204     switch (iport) {
 205     case 0x00:                  /* command */
 206         if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
 207             dolog("command %"PRIx64" not supported\n", data);
 208             return;
 209         }
 210         d->command = data;
 211         break;
 212
 213     case 0x01:
 214         ichan = data & 3;
 215         if (data & 4) {
 216             d->status |= 1 << (ichan + 4);
 217         }
 218         else {
 219             d->status &= ~(1 << (ichan + 4));
 220         }
 221         d->status &= ~(1 << ichan);
 222         DMA_run();
 223         break;
 224
 225     case 0x02:                  /* single mask */
 226         if (data & 4)
 227             d->mask |= 1 << (data & 3);
 228         else
 229             d->mask &= ~(1 << (data & 3));
 230         DMA_run();
 231         break;
 232
 233     case 0x03:                  /* mode */
 234         {
 235             ichan = data & 3;
 236 #ifdef DEBUG_DMA
 237             {
 238                 int op, ai, dir, opmode;
 239                 op = (data >> 2) & 3;
 240                 ai = (data >> 4) & 1;
 241                 dir = (data >> 5) & 1;
 242                 opmode = (data >> 6) & 3;
 243
 244                 linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
 245                        ichan, op, ai, dir, opmode);
 246             }
 247 #endif
 248             d->regs[ichan].mode = data;
 249             break;
 250         }
 251
 252     case 0x04:                  /* clear flip flop */
 253         d->flip_flop = 0;
 254         break;
 255
 256     case 0x05:                  /* reset */
 257         d->flip_flop = 0;
 258         d->mask = ~0;
 259         d->status = 0;
 260         d->command = 0;
 261         break;
 262
 263     case 0x06:                  /* clear mask for all channels */
 264         d->mask = 0;
 265         DMA_run();
 266         break;
 267
 268     case 0x07:                  /* write mask for all channels */
 269         d->mask = data;
 270         DMA_run();
 271         break;
 272
 273     default:
 274         dolog ("unknown iport %#x\n", iport);
 275         break;
 276     }
 277
 278 #ifdef DEBUG_DMA
 279     if (0xc != iport) {
 280         linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
 281                nport, ichan, data);
 282     }
 283 #endif
 284 }
 285
 286 static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size)
 287 {
 288     struct dma_cont *d = opaque;
 289     int iport, val;
 290
 291     iport = (nport >> d->dshift) & 0x0f;
 292     switch (iport) {
 293     case 0x00:                  /* status */
 294         val = d->status;
 295         d->status &= 0xf0;
 296         break;
 297     case 0x01:                  /* mask */
 298         val = d->mask;
 299         break;
 300     default:
 301         val = 0;
 302         break;
 303     }
 304
 305     ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
 306     return val;
 307 }
 308
 309 int DMA_get_channel_mode (int nchan)
 310 {
 311     return dma_controllers[nchan > 3].regs[nchan & 3].mode;
 312 }
 313
 314 void DMA_hold_DREQ (int nchan)
 315 {
 316     int ncont, ichan;
 317
 318     ncont = nchan > 3;
 319     ichan = nchan & 3;
 320     linfo ("held cont=%d chan=%d\n", ncont, ichan);
 321     dma_controllers[ncont].status |= 1 << (ichan + 4);
 322     DMA_run();
 323 }
 324
 325 void DMA_release_DREQ (int nchan)
 326 {
 327     int ncont, ichan;
 328
 329     ncont = nchan > 3;
 330     ichan = nchan & 3;
 331     linfo ("released cont=%d chan=%d\n", ncont, ichan);
 332     dma_controllers[ncont].status &= ~(1 << (ichan + 4));
 333     DMA_run();
 334 }
 335
 336 static void channel_run (int ncont, int ichan)
 337 {
 338     int n;
 339     struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
 340 #ifdef DEBUG_DMA
 341     int dir, opmode;
 342
 343     dir = (r->mode >> 5) & 1;
 344     opmode = (r->mode >> 6) & 3;
 345
 346     if (dir) {
 347         dolog ("DMA in address decrement mode\n");
 348     }
 349     if (opmode != 1) {
 350         dolog ("DMA not in single mode select %#x\n", opmode);
 351     }
 352 #endif
 353
 354     n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
 355                              r->now[COUNT], (r->base[COUNT] + 1) << ncont);
 356     r->now[COUNT] = n;
 357     ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
 358 }
 359
 360 static QEMUBH *dma_bh;
 361 static bool dma_bh_scheduled;
 362
 363 static void DMA_run (void)
 364 {
 365     struct dma_cont *d;
 366     int icont, ichan;
 367     int rearm = 0;
 368     static int running = 0;
 369
 370     if (running) {
 371         rearm = 1;
 372         goto out;
 373     } else {
 374         running = 1;
 375     }
 376
 377     d = dma_controllers;
 378
 379     for (icont = 0; icont < 2; icont++, d++) {
 380         for (ichan = 0; ichan < 4; ichan++) {
 381             int mask;
 382
 383             mask = 1 << ichan;
 384
 385             if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {
 386                 channel_run (icont, ichan);
 387                 rearm = 1;
 388             }
 389         }
 390     }
 391
 392     running = 0;
 393 out:
 394     if (rearm) {
 395         qemu_bh_schedule_idle(dma_bh);
 396         dma_bh_scheduled = true;
 397     }
 398 }
 399
 400 static void DMA_run_bh(void *unused)
 401 {
 402     dma_bh_scheduled = false;
 403     DMA_run();
 404 }
 405
 406 void DMA_register_channel (int nchan,
 407                            DMA_transfer_handler transfer_handler,
 408                            void *opaque)
 409 {
 410     struct dma_regs *r;
 411     int ichan, ncont;
 412
 413     ncont = nchan > 3;
 414     ichan = nchan & 3;
 415
 416     r = dma_controllers[ncont].regs + ichan;
 417     r->transfer_handler = transfer_handler;
 418     r->opaque = opaque;
 419 }
 420
 421 int DMA_read_memory (int nchan, void *buf, int pos, int len)
 422 {
 423     struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
 424     hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
 425
 426     if (r->mode & 0x20) {
 427         int i;
 428         uint8_t *p = buf;
 429
 430         cpu_physical_memory_read (addr - pos - len, buf, len);
 431         /* What about 16bit transfers? */
 432         for (i = 0; i < len >> 1; i++) {
 433             uint8_t b = p[len - i - 1];
 434             p[i] = b;
 435         }
 436     }
 437     else
 438         cpu_physical_memory_read (addr + pos, buf, len);
 439
 440     return len;
 441 }
 442
 443 int DMA_write_memory (int nchan, void *buf, int pos, int len)
 444 {
 445     struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
 446     hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
 447
 448     if (r->mode & 0x20) {
 449         int i;
 450         uint8_t *p = buf;
 451
 452         cpu_physical_memory_write (addr - pos - len, buf, len);
 453         /* What about 16bit transfers? */
 454         for (i = 0; i < len; i++) {
 455             uint8_t b = p[len - i - 1];
 456             p[i] = b;
 457         }
 458     }
 459     else
 460         cpu_physical_memory_write (addr + pos, buf, len);
 461
 462     return len;
 463 }
 464
 465 /* request the emulator to transfer a new DMA memory block ASAP (even
 466  * if the idle bottom half would not have exited the iothread yet).
 467  */
 468 void DMA_schedule(void)
 469 {
 470     if (dma_bh_scheduled) {
 471         qemu_notify_event();
 472     }
 473 }
 474
 475 static void dma_reset(void *opaque)
 476 {
 477     struct dma_cont *d = opaque;
 478     write_cont(d, (0x05 << d->dshift), 0, 1);
 479 }
 480
 481 static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)
 482 {
 483     trace_i8257_unregistered_dma(nchan, dma_pos, dma_len);
 484     return dma_pos;
 485 }
 486
 487
 488 static const MemoryRegionOps channel_io_ops = {
 489     .read = read_chan,
 490     .write = write_chan,
 491     .endianness = DEVICE_NATIVE_ENDIAN,
 492     .impl = {
 493         .min_access_size = 1,
 494         .max_access_size = 1,
 495     },
 496 };
 497
 498 /* IOport from page_base */
 499 static const MemoryRegionPortio page_portio_list[] = {
 500     { 0x01, 3, 1, .write = write_page, .read = read_page, },
 501     { 0x07, 1, 1, .write = write_page, .read = read_page, },
 502     PORTIO_END_OF_LIST(),
 503 };
 504
 505 /* IOport from pageh_base */
 506 static const MemoryRegionPortio pageh_portio_list[] = {
 507     { 0x01, 3, 1, .write = write_pageh, .read = read_pageh, },
 508     { 0x07, 3, 1, .write = write_pageh, .read = read_pageh, },
 509     PORTIO_END_OF_LIST(),
 510 };
 511
 512 static const MemoryRegionOps cont_io_ops = {
 513     .read = read_cont,
 514     .write = write_cont,
 515     .endianness = DEVICE_NATIVE_ENDIAN,
 516     .impl = {
 517         .min_access_size = 1,
 518         .max_access_size = 1,
 519     },
 520 };
 521
 522 /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
 523 static void dma_init2(struct dma_cont *d, int base, int dshift,
 524                       int page_base, int pageh_base)
 525 {
 526     int i;
 527
 528     d->dshift = dshift;
 529
 530     memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d,
 531                           "dma-chan", 8 << d->dshift);
 532     memory_region_add_subregion(isa_address_space_io(NULL),
 533                                 base, &d->channel_io);
 534
 535     isa_register_portio_list(NULL, page_base, page_portio_list, d,
 536                              "dma-page");
 537     if (pageh_base >= 0) {
 538         isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d,
 539                                  "dma-pageh");
 540     }
 541
 542     memory_region_init_io(&d->cont_io, NULL, &cont_io_ops, d, "dma-cont",
 543                           8 << d->dshift);
 544     memory_region_add_subregion(isa_address_space_io(NULL),
 545                                 base + (8 << d->dshift), &d->cont_io);
 546
 547     qemu_register_reset(dma_reset, d);
 548     dma_reset(d);
 549     for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
 550         d->regs[i].transfer_handler = dma_phony_handler;
 551     }
 552 }
 553
 554 static const VMStateDescription vmstate_dma_regs = {
 555     .name = "dma_regs",
 556     .version_id = 1,
 557     .minimum_version_id = 1,
 558     .fields = (VMStateField[]) {
 559         VMSTATE_INT32_ARRAY(now, struct dma_regs, 2),
 560         VMSTATE_UINT16_ARRAY(base, struct dma_regs, 2),
 561         VMSTATE_UINT8(mode, struct dma_regs),
 562         VMSTATE_UINT8(page, struct dma_regs),
 563         VMSTATE_UINT8(pageh, struct dma_regs),
 564         VMSTATE_UINT8(dack, struct dma_regs),
 565         VMSTATE_UINT8(eop, struct dma_regs),
 566         VMSTATE_END_OF_LIST()
 567     }
 568 };
 569
 570 static int dma_post_load(void *opaque, int version_id)
 571 {
 572     DMA_run();
 573
 574     return 0;
 575 }
 576
 577 static const VMStateDescription vmstate_dma = {
 578     .name = "dma",
 579     .version_id = 1,
 580     .minimum_version_id = 1,
 581     .post_load = dma_post_load,
 582     .fields = (VMStateField[]) {
 583         VMSTATE_UINT8(command, struct dma_cont),
 584         VMSTATE_UINT8(mask, struct dma_cont),
 585         VMSTATE_UINT8(flip_flop, struct dma_cont),
 586         VMSTATE_INT32(dshift, struct dma_cont),
 587         VMSTATE_STRUCT_ARRAY(regs, struct dma_cont, 4, 1, vmstate_dma_regs, struct dma_regs),
 588         VMSTATE_END_OF_LIST()
 589     }
 590 };
 591
 592 void DMA_init(int high_page_enable)
 593 {
 594     dma_init2(&dma_controllers[0], 0x00, 0, 0x80, high_page_enable ? 0x480 : -1);
 595     dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, high_page_enable ? 0x488 : -1);
 596     vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]);
 597     vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]);
 598
 599     dma_bh = qemu_bh_new(DMA_run_bh, NULL);
 600 }