target/nios2/cpu.h

   1 /*
   2  * Altera Nios II virtual CPU header
   3  *
   4  * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #ifndef NIOS2_CPU_H
  22 #define NIOS2_CPU_H
  23
  24 #include "exec/cpu-defs.h"
  25 #include "hw/core/cpu.h"
  26 #include "hw/registerfields.h"
  27 #include "qom/object.h"
  28
  29 typedef struct CPUArchState CPUNios2State;
  30 #if !defined(CONFIG_USER_ONLY)
  31 #include "mmu.h"
  32 #endif
  33
  34 #define TYPE_NIOS2_CPU "nios2-cpu"
  35
  36 OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
  37
  38 /**
  39  * Nios2CPUClass:
  40  * @parent_reset: The parent class' reset handler.
  41  *
  42  * A Nios2 CPU model.
  43  */
  44 struct Nios2CPUClass {
  45     /*< private >*/
  46     CPUClass parent_class;
  47     /*< public >*/
  48
  49     DeviceRealize parent_realize;
  50     DeviceReset parent_reset;
  51 };
  52
  53 #define TARGET_HAS_ICE 1
  54
  55 /* Configuration options for Nios II */
  56 #define RESET_ADDRESS         0x00000000
  57 #define EXCEPTION_ADDRESS     0x00000004
  58 #define FAST_TLB_MISS_ADDRESS 0x00000008
  59
  60 #define NUM_GP_REGS 32
  61 #define NUM_CR_REGS 32
  62
  63 /* General purpose register aliases */
  64 enum {
  65     R_ZERO   = 0,
  66     R_AT     = 1,
  67     R_RET0   = 2,
  68     R_RET1   = 3,
  69     R_ARG0   = 4,
  70     R_ARG1   = 5,
  71     R_ARG2   = 6,
  72     R_ARG3   = 7,
  73     R_ET     = 24,
  74     R_BT     = 25,
  75     R_GP     = 26,
  76     R_SP     = 27,
  77     R_FP     = 28,
  78     R_EA     = 29,
  79     R_BA     = 30,
  80     R_RA     = 31,
  81 };
  82
  83 /* Control register aliases */
  84 enum {
  85     CR_STATUS        = 0,
  86     CR_ESTATUS       = 1,
  87     CR_BSTATUS       = 2,
  88     CR_IENABLE       = 3,
  89     CR_IPENDING      = 4,
  90     CR_CPUID         = 5,
  91     CR_EXCEPTION     = 7,
  92     CR_PTEADDR       = 8,
  93     CR_TLBACC        = 9,
  94     CR_TLBMISC       = 10,
  95     CR_ENCINJ        = 11,
  96     CR_BADADDR       = 12,
  97     CR_CONFIG        = 13,
  98     CR_MPUBASE       = 14,
  99     CR_MPUACC        = 15,
 100 };
 101
 102 FIELD(CR_STATUS, PIE, 0, 1)
 103 FIELD(CR_STATUS, U, 1, 1)
 104 FIELD(CR_STATUS, EH, 2, 1)
 105 FIELD(CR_STATUS, IH, 3, 1)
 106 FIELD(CR_STATUS, IL, 4, 6)
 107 FIELD(CR_STATUS, CRS, 10, 6)
 108 FIELD(CR_STATUS, PRS, 16, 6)
 109 FIELD(CR_STATUS, NMI, 22, 1)
 110 FIELD(CR_STATUS, RSIE, 23, 1)
 111
 112 #define CR_STATUS_PIE    R_CR_STATUS_PIE_MASK
 113 #define CR_STATUS_U      R_CR_STATUS_U_MASK
 114 #define CR_STATUS_EH     R_CR_STATUS_EH_MASK
 115 #define CR_STATUS_IH     R_CR_STATUS_IH_MASK
 116 #define CR_STATUS_NMI    R_CR_STATUS_NMI_MASK
 117 #define CR_STATUS_RSIE   R_CR_STATUS_RSIE_MASK
 118
 119 FIELD(CR_EXCEPTION, CAUSE, 2, 5)
 120 FIELD(CR_EXCEPTION, ECCFTL, 31, 1)
 121
 122 FIELD(CR_PTEADDR, VPN, 2, 20)
 123 FIELD(CR_PTEADDR, PTBASE, 22, 10)
 124
 125 FIELD(CR_TLBACC, PFN, 0, 20)
 126 FIELD(CR_TLBACC, G, 20, 1)
 127 FIELD(CR_TLBACC, X, 21, 1)
 128 FIELD(CR_TLBACC, W, 22, 1)
 129 FIELD(CR_TLBACC, R, 23, 1)
 130 FIELD(CR_TLBACC, C, 24, 1)
 131 FIELD(CR_TLBACC, IG, 25, 7)
 132
 133 #define CR_TLBACC_C      R_CR_TLBACC_C_MASK
 134 #define CR_TLBACC_R      R_CR_TLBACC_R_MASK
 135 #define CR_TLBACC_W      R_CR_TLBACC_W_MASK
 136 #define CR_TLBACC_X      R_CR_TLBACC_X_MASK
 137 #define CR_TLBACC_G      R_CR_TLBACC_G_MASK
 138
 139 FIELD(CR_TLBMISC, D, 0, 1)
 140 FIELD(CR_TLBMISC, PERM, 1, 1)
 141 FIELD(CR_TLBMISC, BAD, 2, 1)
 142 FIELD(CR_TLBMISC, DBL, 3, 1)
 143 FIELD(CR_TLBMISC, PID, 4, 14)
 144 FIELD(CR_TLBMISC, WE, 18, 1)
 145 FIELD(CR_TLBMISC, RD, 19, 1)
 146 FIELD(CR_TLBMISC, WAY, 20, 4)
 147 FIELD(CR_TLBMISC, EE, 24, 1)
 148
 149 #define CR_TLBMISC_EE    R_CR_TLBMISC_EE_MASK
 150 #define CR_TLBMISC_RD    R_CR_TLBMISC_RD_MASK
 151 #define CR_TLBMISC_WE    R_CR_TLBMISC_WE_MASK
 152 #define CR_TLBMISC_DBL   R_CR_TLBMISC_DBL_MASK
 153 #define CR_TLBMISC_BAD   R_CR_TLBMISC_BAD_MASK
 154 #define CR_TLBMISC_PERM  R_CR_TLBMISC_PERM_MASK
 155 #define CR_TLBMISC_D     R_CR_TLBMISC_D_MASK
 156
 157 /* Exceptions */
 158 #define EXCP_BREAK    0x1000
 159 #define EXCP_SEMIHOST 0x1001
 160 #define EXCP_RESET    0
 161 #define EXCP_PRESET   1
 162 #define EXCP_IRQ      2
 163 #define EXCP_TRAP     3
 164 #define EXCP_UNIMPL   4
 165 #define EXCP_ILLEGAL  5
 166 #define EXCP_UNALIGN  6
 167 #define EXCP_UNALIGND 7
 168 #define EXCP_DIV      8
 169 #define EXCP_SUPERA_X 9
 170 #define EXCP_SUPERI   10
 171 #define EXCP_SUPERA_D 11
 172 #define EXCP_TLB_X    12
 173 #define EXCP_TLB_D    (0x1000 | EXCP_TLB_X)
 174 #define EXCP_PERM_X   13
 175 #define EXCP_PERM_R   14
 176 #define EXCP_PERM_W   15
 177 #define EXCP_MPUI     16
 178 #define EXCP_MPUD     17
 179
 180 struct CPUArchState {
 181     uint32_t regs[NUM_GP_REGS];
 182     uint32_t ctrl[NUM_CR_REGS];
 183     uint32_t pc;
 184
 185 #if !defined(CONFIG_USER_ONLY)
 186     Nios2MMU mmu;
 187 #endif
 188     int error_code;
 189 };
 190
 191 typedef struct {
 192     uint32_t writable;
 193     uint32_t readonly;
 194 } ControlRegState;
 195
 196 /**
 197  * Nios2CPU:
 198  * @env: #CPUNios2State
 199  *
 200  * A Nios2 CPU.
 201  */
 202 struct ArchCPU {
 203     /*< private >*/
 204     CPUState parent_obj;
 205     /*< public >*/
 206
 207     CPUNegativeOffsetState neg;
 208     CPUNios2State env;
 209
 210     bool mmu_present;
 211     uint32_t pid_num_bits;
 212     uint32_t tlb_num_ways;
 213     uint32_t tlb_num_entries;
 214
 215     /* Addresses that are hard-coded in the FPGA build settings */
 216     uint32_t reset_addr;
 217     uint32_t exception_addr;
 218     uint32_t fast_tlb_miss_addr;
 219
 220     /* Bits within each control register which are reserved or readonly. */
 221     ControlRegState cr_state[NUM_CR_REGS];
 222 };
 223
 224
 225 static inline bool nios2_cr_reserved(const ControlRegState *s)
 226 {
 227     return (s->writable | s->readonly) == 0;
 228 }
 229
 230 void nios2_tcg_init(void);
 231 void nios2_cpu_do_interrupt(CPUState *cs);
 232 void dump_mmu(CPUNios2State *env);
 233 void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 234 hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 235 G_NORETURN void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 236                                               MMUAccessType access_type, int mmu_idx,
 237                                               uintptr_t retaddr);
 238
 239 void do_nios2_semihosting(CPUNios2State *env);
 240
 241 #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU
 242
 243 #define cpu_gen_code cpu_nios2_gen_code
 244
 245 #define CPU_SAVE_VERSION 1
 246
 247 /* MMU modes definitions */
 248 #define MMU_SUPERVISOR_IDX  0
 249 #define MMU_USER_IDX        1
 250
 251 static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
 252 {
 253     return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
 254                                                   MMU_SUPERVISOR_IDX;
 255 }
 256
 257 #ifndef CONFIG_USER_ONLY
 258 bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 259                         MMUAccessType access_type, int mmu_idx,
 260                         bool probe, uintptr_t retaddr);
 261 #endif
 262
 263 typedef CPUNios2State CPUArchState;
 264 typedef Nios2CPU ArchCPU;
 265
 266 #include "exec/cpu-all.h"
 267
 268 static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
 269                                         target_ulong *cs_base, uint32_t *flags)
 270 {
 271     *pc = env->pc;
 272     *cs_base = 0;
 273     *flags = env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U);
 274 }
 275
 276 #endif /* NIOS2_CPU_H */