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ppc/pegasos2: Fix use of && instead of &
[qemu.git] / hw / ppc / pegasos2.c
blobcf1dc53c83f73eeec1119a3b7dcf3750c69bb1dc
1 /*
2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator
3 *
4 * Copyright (c) 2018-2021 BALATON Zoltan
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 *
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu-common.h"
12 #include "qemu/units.h"
13 #include "qapi/error.h"
14 #include "hw/hw.h"
15 #include "hw/ppc/ppc.h"
16 #include "hw/sysbus.h"
17 #include "hw/pci/pci_host.h"
18 #include "hw/irq.h"
19 #include "hw/pci-host/mv64361.h"
20 #include "hw/isa/vt82c686.h"
21 #include "hw/ide/pci.h"
22 #include "hw/i2c/smbus_eeprom.h"
23 #include "hw/qdev-properties.h"
24 #include "sysemu/reset.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/fw-path-provider.h"
28 #include "elf.h"
29 #include "qemu/log.h"
30 #include "qemu/error-report.h"
31 #include "sysemu/kvm.h"
32 #include "kvm_ppc.h"
33 #include "exec/address-spaces.h"
34 #include "trace.h"
35 #include "qemu/datadir.h"
36 #include "sysemu/device_tree.h"
37 #include "hw/ppc/vof.h"
38
39 #include <libfdt.h>
40
41 #define PROM_FILENAME "vof.bin"
42 #define PROM_ADDR 0xfff00000
43 #define PROM_SIZE 0x80000
44
45 #define KVMPPC_HCALL_BASE 0xf000
46 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
47
48 #define H_SUCCESS 0
49 #define H_PRIVILEGE -3 /* Caller not privileged */
50 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
51
52 #define BUS_FREQ_HZ 133333333
53
54 #define PCI0_MEM_BASE 0xc0000000
55 #define PCI0_MEM_SIZE 0x20000000
56 #define PCI0_IO_BASE 0xf8000000
57 #define PCI0_IO_SIZE 0x10000
58
59 #define PCI1_MEM_BASE 0x80000000
60 #define PCI1_MEM_SIZE 0x40000000
61 #define PCI1_IO_BASE 0xfe000000
62 #define PCI1_IO_SIZE 0x10000
63
64 #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2")
65 OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE)
66
67 struct Pegasos2MachineState {
68 MachineState parent_obj;
69 PowerPCCPU *cpu;
70 DeviceState *mv;
71 Vof *vof;
72 void *fdt_blob;
73 uint64_t kernel_addr;
74 uint64_t kernel_entry;
75 uint64_t kernel_size;
76 };
77
78 static void *build_fdt(MachineState *machine, int *fdt_size);
79
80 static void pegasos2_cpu_reset(void *opaque)
81 {
82 PowerPCCPU *cpu = opaque;
83 Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine);
84
85 cpu_reset(CPU(cpu));
86 cpu->env.spr[SPR_HID1] = 7ULL << 28;
87 if (pm->vof) {
88 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20;
89 cpu->env.nip = 0x100;
90 }
91 }
92
93 static void pegasos2_init(MachineState *machine)
94 {
95 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
96 CPUPPCState *env;
97 MemoryRegion *rom = g_new(MemoryRegion, 1);
98 PCIBus *pci_bus;
99 PCIDevice *dev;
100 I2CBus *i2c_bus;
101 const char *fwname = machine->firmware ?: PROM_FILENAME;
102 char *filename;
103 int sz;
104 uint8_t *spd_data;
105
106 /* init CPU */
107 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
108 env = &pm->cpu->env;
109 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
110 error_report("Incompatible CPU, only 6xx bus supported");
111 exit(1);
112 }
113
114 /* Set time-base frequency */
115 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4);
116 qemu_register_reset(pegasos2_cpu_reset, pm->cpu);
117
118 /* RAM */
119 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
120
121 /* allocate and load firmware */
122 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname);
123 if (!filename) {
124 error_report("Could not find firmware '%s'", fwname);
125 exit(1);
126 }
127 if (!machine->firmware && !pm->vof) {
128 pm->vof = g_malloc0(sizeof(*pm->vof));
129 }
130 memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal);
131 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom);
132 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1,
133 PPC_ELF_MACHINE, 0, 0);
134 if (sz <= 0) {
135 sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE);
136 }
137 if (sz <= 0 || sz > PROM_SIZE) {
138 error_report("Could not load firmware '%s'", filename);
139 exit(1);
140 }
141 g_free(filename);
142 if (pm->vof) {
143 pm->vof->fw_size = sz;
144 }
145
146 /* Marvell Discovery II system controller */
147 pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
148 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]));
149 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
150
151 /* VIA VT8231 South Bridge (multifunction PCI device) */
152 /* VT8231 function 0: PCI-to-ISA Bridge */
153 dev = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true,
154 TYPE_VT8231_ISA);
155 qdev_connect_gpio_out(DEVICE(dev), 0,
156 qdev_get_gpio_in_named(pm->mv, "gpp", 31));
157
158 /* VT8231 function 1: IDE Controller */
159 dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 1), "via-ide");
160 pci_ide_create_devs(dev);
161
162 /* VT8231 function 2-3: USB Ports */
163 pci_create_simple(pci_bus, PCI_DEVFN(12, 2), "vt82c686b-usb-uhci");
164 pci_create_simple(pci_bus, PCI_DEVFN(12, 3), "vt82c686b-usb-uhci");
165
166 /* VT8231 function 4: Power Management Controller */
167 dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 4), TYPE_VT8231_PM);
168 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
169 spd_data = spd_data_generate(DDR, machine->ram_size);
170 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data);
171
172 /* VT8231 function 5-6: AC97 Audio & Modem */
173 pci_create_simple(pci_bus, PCI_DEVFN(12, 5), TYPE_VIA_AC97);
174 pci_create_simple(pci_bus, PCI_DEVFN(12, 6), TYPE_VIA_MC97);
175
176 /* other PC hardware */
177 pci_vga_init(pci_bus);
178
179 if (machine->kernel_filename) {
180 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL,
181 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1,
182 PPC_ELF_MACHINE, 0, 0);
183 if (sz <= 0) {
184 error_report("Could not load kernel '%s'",
185 machine->kernel_filename);
186 exit(1);
187 }
188 pm->kernel_size = sz;
189 if (!pm->vof) {
190 warn_report("Option -kernel may be ineffective with -bios.");
191 }
192 }
193 if (machine->kernel_cmdline && !pm->vof) {
194 warn_report("Option -append may be ineffective with -bios.");
195 }
196 }
197
198 static void pegasos2_pci_config_write(AddressSpace *as, int bus, uint32_t addr,
199 uint32_t len, uint32_t val)
200 {
201 hwaddr pcicfg = (bus ? 0xf1000c78 : 0xf1000cf8);
202
203 stl_le_phys(as, pcicfg, addr | BIT(31));
204 switch (len) {
205 case 4:
206 stl_le_phys(as, pcicfg + 4, val);
207 break;
208 case 2:
209 stw_le_phys(as, pcicfg + 4, val);
210 break;
211 case 1:
212 stb_phys(as, pcicfg + 4, val);
213 break;
214 default:
215 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid length\n", __func__);
216 break;
217 }
218 }
219
220 static void pegasos2_machine_reset(MachineState *machine)
221 {
222 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
223 AddressSpace *as = CPU(pm->cpu)->as;
224 void *fdt;
225 uint64_t d[2];
226 int sz;
227
228 qemu_devices_reset();
229 if (!pm->vof) {
230 return; /* Firmware should set up machine so nothing to do */
231 }
232
233 /* Otherwise, set up devices that board firmware would normally do */
234 stl_le_phys(as, 0xf1000000, 0x28020ff);
235 stl_le_phys(as, 0xf1000278, 0xa31fc);
236 stl_le_phys(as, 0xf100f300, 0x11ff0400);
237 stl_le_phys(as, 0xf100f10c, 0x80000000);
238 stl_le_phys(as, 0xf100001c, 0x8000000);
239 pegasos2_pci_config_write(as, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
240 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
241 pegasos2_pci_config_write(as, 1, PCI_COMMAND, 2, PCI_COMMAND_IO |
242 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
243
244 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 0) << 8) |
245 PCI_INTERRUPT_LINE, 2, 0x9);
246 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 0) << 8) |
247 0x50, 1, 0x2);
248
249 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 1) << 8) |
250 PCI_INTERRUPT_LINE, 2, 0x109);
251 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 1) << 8) |
252 PCI_CLASS_PROG, 1, 0xf);
253 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 1) << 8) |
254 0x40, 1, 0xb);
255 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 1) << 8) |
256 0x50, 4, 0x17171717);
257 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 1) << 8) |
258 PCI_COMMAND, 2, 0x87);
259
260 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 2) << 8) |
261 PCI_INTERRUPT_LINE, 2, 0x409);
262
263 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 3) << 8) |
264 PCI_INTERRUPT_LINE, 2, 0x409);
265
266 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 4) << 8) |
267 PCI_INTERRUPT_LINE, 2, 0x9);
268 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 4) << 8) |
269 0x48, 4, 0xf00);
270 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 4) << 8) |
271 0x40, 4, 0x558020);
272 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 4) << 8) |
273 0x90, 4, 0xd00);
274
275 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 5) << 8) |
276 PCI_INTERRUPT_LINE, 2, 0x309);
277
278 pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 6) << 8) |
279 PCI_INTERRUPT_LINE, 2, 0x309);
280
281 /* Device tree and VOF set up */
282 vof_init(pm->vof, machine->ram_size, &error_fatal);
283 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) {
284 error_report("Memory allocation for stack failed");
285 exit(1);
286 }
287 if (pm->kernel_size &&
288 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) {
289 error_report("Memory for kernel is in use");
290 exit(1);
291 }
292 fdt = build_fdt(machine, &sz);
293 /* FIXME: VOF assumes entry is same as load address */
294 d[0] = cpu_to_be64(pm->kernel_entry);
295 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr));
296 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d));
297
298 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
299 g_free(pm->fdt_blob);
300 pm->fdt_blob = fdt;
301
302 vof_build_dt(fdt, pm->vof);
303 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe");
304 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine);
305 }
306
307 static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
308 {
309 Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp);
310 CPUPPCState *env = &cpu->env;
311
312 /* The TCG path should also be holding the BQL at this point */
313 g_assert(qemu_mutex_iothread_locked());
314
315 if (msr_pr) {
316 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n");
317 env->gpr[3] = H_PRIVILEGE;
318 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) {
319 int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob,
320 env->gpr[4]);
321 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS);
322 } else {
323 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx
324 "\n", env->gpr[3]);
325 env->gpr[3] = -1;
326 }
327 }
328
329 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
330 {
331 }
332
333 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
334 {
335 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1];
336 }
337
338 static void pegasos2_machine_class_init(ObjectClass *oc, void *data)
339 {
340 MachineClass *mc = MACHINE_CLASS(oc);
341 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
342
343 mc->desc = "Genesi/bPlan Pegasos II";
344 mc->init = pegasos2_init;
345 mc->reset = pegasos2_machine_reset;
346 mc->block_default_type = IF_IDE;
347 mc->default_boot_order = "cd";
348 mc->default_display = "std";
349 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9");
350 mc->default_ram_id = "pegasos2.ram";
351 mc->default_ram_size = 512 * MiB;
352
353 vhc->hypercall = pegasos2_hypercall;
354 vhc->cpu_exec_enter = vhyp_nop;
355 vhc->cpu_exec_exit = vhyp_nop;
356 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr;
357 }
358
359 static const TypeInfo pegasos2_machine_info = {
360 .name = TYPE_PEGASOS2_MACHINE,
361 .parent = TYPE_MACHINE,
362 .class_init = pegasos2_machine_class_init,
363 .instance_size = sizeof(Pegasos2MachineState),
364 .interfaces = (InterfaceInfo[]) {
365 { TYPE_PPC_VIRTUAL_HYPERVISOR },
366 { }
367 },
368 };
369
370 static void pegasos2_machine_register_types(void)
371 {
372 type_register_static(&pegasos2_machine_info);
373 }
374
375 type_init(pegasos2_machine_register_types)
376
377 /* FDT creation for passing to firmware */
378
379 typedef struct {
380 void *fdt;
381 const char *path;
382 } FDTInfo;
383
384 /* We do everything in reverse order so it comes out right in the tree */
385
386 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
387 {
388 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi");
389 }
390
391 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
392 {
393 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0);
394 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1);
395 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb");
396 }
397
398 static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
399 {
400 GString *name = g_string_sized_new(64);
401 uint32_t cells[3];
402
403 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1);
404 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2);
405 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa");
406 qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa");
407
408 /* addional devices */
409 g_string_printf(name, "%s/lpt@i3bc", fi->path);
410 qemu_fdt_add_subnode(fi->fdt, name->str);
411 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
412 cells[0] = cpu_to_be32(7);
413 cells[1] = 0;
414 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
415 cells, 2 * sizeof(cells[0]));
416 cells[0] = cpu_to_be32(1);
417 cells[1] = cpu_to_be32(0x3bc);
418 cells[2] = cpu_to_be32(8);
419 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
420 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt");
421 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt");
422
423 g_string_printf(name, "%s/fdc@i3f0", fi->path);
424 qemu_fdt_add_subnode(fi->fdt, name->str);
425 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
426 cells[0] = cpu_to_be32(6);
427 cells[1] = 0;
428 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
429 cells, 2 * sizeof(cells[0]));
430 cells[0] = cpu_to_be32(1);
431 cells[1] = cpu_to_be32(0x3f0);
432 cells[2] = cpu_to_be32(8);
433 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
434 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc");
435 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc");
436
437 g_string_printf(name, "%s/timer@i40", fi->path);
438 qemu_fdt_add_subnode(fi->fdt, name->str);
439 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
440 cells[0] = cpu_to_be32(1);
441 cells[1] = cpu_to_be32(0x40);
442 cells[2] = cpu_to_be32(8);
443 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
444 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer");
445 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer");
446
447 g_string_printf(name, "%s/rtc@i70", fi->path);
448 qemu_fdt_add_subnode(fi->fdt, name->str);
449 qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc");
450 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
451 cells[0] = cpu_to_be32(8);
452 cells[1] = 0;
453 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
454 cells, 2 * sizeof(cells[0]));
455 cells[0] = cpu_to_be32(1);
456 cells[1] = cpu_to_be32(0x70);
457 cells[2] = cpu_to_be32(2);
458 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
459 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc");
460 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc");
461
462 g_string_printf(name, "%s/keyboard@i60", fi->path);
463 qemu_fdt_add_subnode(fi->fdt, name->str);
464 cells[0] = cpu_to_be32(1);
465 cells[1] = 0;
466 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
467 cells, 2 * sizeof(cells[0]));
468 cells[0] = cpu_to_be32(1);
469 cells[1] = cpu_to_be32(0x60);
470 cells[2] = cpu_to_be32(5);
471 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
472 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard");
473 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard");
474
475 g_string_printf(name, "%s/8042@i60", fi->path);
476 qemu_fdt_add_subnode(fi->fdt, name->str);
477 qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2);
478 qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0);
479 qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1);
480 qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", "");
481 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
482 cells[0] = cpu_to_be32(1);
483 cells[1] = cpu_to_be32(0x60);
484 cells[2] = cpu_to_be32(5);
485 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
486 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "");
487 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042");
488
489 g_string_printf(name, "%s/serial@i2f8", fi->path);
490 qemu_fdt_add_subnode(fi->fdt, name->str);
491 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
492 cells[0] = cpu_to_be32(3);
493 cells[1] = 0;
494 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
495 cells, 2 * sizeof(cells[0]));
496 cells[0] = cpu_to_be32(1);
497 cells[1] = cpu_to_be32(0x2f8);
498 cells[2] = cpu_to_be32(8);
499 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
500 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial");
501 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial");
502
503 g_string_free(name, TRUE);
504 }
505
506 static struct {
507 const char *id;
508 const char *name;
509 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi);
510 } device_map[] = {
511 { "pci11ab,6460", "host", NULL },
512 { "pci1106,8231", "isa", dt_isa },
513 { "pci1106,571", "ide", dt_ide },
514 { "pci1106,3044", "firewire", NULL },
515 { "pci1106,3038", "usb", dt_usb },
516 { "pci1106,8235", "other", NULL },
517 { "pci1106,3058", "sound", NULL },
518 { NULL, NULL }
519 };
520
521 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
522 {
523 FDTInfo *fi = opaque;
524 GString *node = g_string_new(NULL);
525 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5];
526 int i, j;
527 const char *name = NULL;
528 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x",
529 pci_get_word(&d->config[PCI_VENDOR_ID]),
530 pci_get_word(&d->config[PCI_DEVICE_ID]));
531
532 for (i = 0; device_map[i].id; i++) {
533 if (!strcmp(pn, device_map[i].id)) {
534 name = device_map[i].name;
535 break;
536 }
537 }
538 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn),
539 PCI_SLOT(d->devfn));
540 if (PCI_FUNC(d->devfn)) {
541 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn));
542 }
543
544 qemu_fdt_add_subnode(fi->fdt, node->str);
545 if (device_map[i].dtf) {
546 FDTInfo cfi = { fi->fdt, node->str };
547 device_map[i].dtf(bus, d, &cfi);
548 }
549 cells[0] = cpu_to_be32(d->devfn << 8);
550 cells[1] = 0;
551 cells[2] = 0;
552 cells[3] = 0;
553 cells[4] = 0;
554 j = 5;
555 for (i = 0; i < PCI_NUM_REGIONS; i++) {
556 if (!d->io_regions[i].size) {
557 continue;
558 }
559 cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4));
560 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
561 cells[j] |= cpu_to_be32(1 << 24);
562 } else {
563 cells[j] |= cpu_to_be32(2 << 24);
564 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
565 cells[j] |= cpu_to_be32(4 << 28);
566 }
567 }
568 cells[j + 1] = 0;
569 cells[j + 2] = 0;
570 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32);
571 cells[j + 4] = cpu_to_be32(d->io_regions[i].size);
572 j += 5;
573 }
574 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0]));
575 qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn);
576 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) {
577 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts",
578 pci_get_byte(&d->config[PCI_INTERRUPT_PIN]));
579 }
580 /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */
581 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id",
582 pci_get_word(&d->config[PCI_SUBSYSTEM_ID]));
583 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id",
584 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID]));
585 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]);
586 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8);
587 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff);
588 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id",
589 pci_get_word(&d->config[PCI_DEVICE_ID]));
590 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id",
591 pci_get_word(&d->config[PCI_VENDOR_ID]));
592
593 g_string_free(node, TRUE);
594 }
595
596 static void *build_fdt(MachineState *machine, int *fdt_size)
597 {
598 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
599 PowerPCCPU *cpu = pm->cpu;
600 PCIBus *pci_bus;
601 FDTInfo fi;
602 uint32_t cells[16];
603 void *fdt = create_device_tree(fdt_size);
604
605 fi.fdt = fdt;
606
607 /* root node */
608 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description",
609 "Pegasos CHRP PowerPC System");
610 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2");
611 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH");
612 qemu_fdt_setprop_string(fdt, "/", "revision", "2B");
613 qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2");
614 qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp");
615 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1);
616 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2");
617
618 /* pci@c0000000 */
619 qemu_fdt_add_subnode(fdt, "/pci@c0000000");
620 cells[0] = 0;
621 cells[1] = 0;
622 qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range",
623 cells, 2 * sizeof(cells[0]));
624 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1);
625 cells[0] = cpu_to_be32(PCI0_MEM_BASE);
626 cells[1] = cpu_to_be32(PCI0_MEM_SIZE);
627 qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0]));
628 cells[0] = cpu_to_be32(0x01000000);
629 cells[1] = 0;
630 cells[2] = 0;
631 cells[3] = cpu_to_be32(PCI0_IO_BASE);
632 cells[4] = 0;
633 cells[5] = cpu_to_be32(PCI0_IO_SIZE);
634 cells[6] = cpu_to_be32(0x02000000);
635 cells[7] = 0;
636 cells[8] = cpu_to_be32(PCI0_MEM_BASE);
637 cells[9] = cpu_to_be32(PCI0_MEM_BASE);
638 cells[10] = 0;
639 cells[11] = cpu_to_be32(PCI0_MEM_SIZE);
640 qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges",
641 cells, 12 * sizeof(cells[0]));
642 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2);
643 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3);
644 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci");
645 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci");
646
647 fi.path = "/pci@c0000000";
648 pci_bus = mv64361_get_pci_bus(pm->mv, 0);
649 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
650
651 /* pci@80000000 */
652 qemu_fdt_add_subnode(fdt, "/pci@80000000");
653 cells[0] = 0;
654 cells[1] = 0;
655 qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range",
656 cells, 2 * sizeof(cells[0]));
657 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0);
658 cells[0] = cpu_to_be32(PCI1_MEM_BASE);
659 cells[1] = cpu_to_be32(PCI1_MEM_SIZE);
660 qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0]));
661 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge",
662 0xf1000cb4);
663 cells[0] = cpu_to_be32(0x01000000);
664 cells[1] = 0;
665 cells[2] = 0;
666 cells[3] = cpu_to_be32(PCI1_IO_BASE);
667 cells[4] = 0;
668 cells[5] = cpu_to_be32(PCI1_IO_SIZE);
669 cells[6] = cpu_to_be32(0x02000000);
670 cells[7] = 0;
671 cells[8] = cpu_to_be32(PCI1_MEM_BASE);
672 cells[9] = cpu_to_be32(PCI1_MEM_BASE);
673 cells[10] = 0;
674 cells[11] = cpu_to_be32(PCI1_MEM_SIZE);
675 qemu_fdt_setprop(fdt, "/pci@80000000", "ranges",
676 cells, 12 * sizeof(cells[0]));
677 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2);
678 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3);
679 qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci");
680 qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci");
681
682 fi.path = "/pci@80000000";
683 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
684 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
685
686 qemu_fdt_add_subnode(fdt, "/failsafe");
687 qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial");
688 qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe");
689
690 /* cpus */
691 qemu_fdt_add_subnode(fdt, "/cpus");
692 qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1);
693 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
694 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
695 qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus");
696
697 /* FIXME Get CPU name from CPU object */
698 const char *cp = "/cpus/PowerPC,G4";
699 qemu_fdt_add_subnode(fdt, cp);
700 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0);
701 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000);
702 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size",
703 cpu->env.dcache_line_size);
704 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size",
705 cpu->env.dcache_line_size);
706 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000);
707 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size",
708 cpu->env.icache_line_size);
709 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
710 cpu->env.icache_line_size);
711 if (cpu->env.id_tlbs) {
712 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
713 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
714 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
715 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way);
716 qemu_fdt_setprop_string(fdt, cp, "tlb-split", "");
717 }
718 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways);
719 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb);
720 qemu_fdt_setprop_string(fdt, cp, "state", "running");
721 if (cpu->env.insns_flags & PPC_ALTIVEC) {
722 qemu_fdt_setprop_string(fdt, cp, "altivec", "");
723 qemu_fdt_setprop_string(fdt, cp, "data-streams", "");
724 }
725 /*
726 * FIXME What flags do data-streams, external-control and
727 * performance-monitor depend on?
728 */
729 qemu_fdt_setprop_string(fdt, cp, "external-control", "");
730 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) {
731 qemu_fdt_setprop_string(fdt, cp, "general-purpose", "");
732 }
733 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", "");
734 if (cpu->env.insns_flags & PPC_FLOAT_FRES) {
735 qemu_fdt_setprop_string(fdt, cp, "graphics", "");
736 }
737 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4);
738 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency",
739 cpu->env.tb_env->tb_freq);
740 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ);
741 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5);
742 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]);
743 cells[0] = 0;
744 cells[1] = 0;
745 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0]));
746 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu");
747 qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1);
748
749 /* memory */
750 qemu_fdt_add_subnode(fdt, "/memory@0");
751 cells[0] = 0;
752 cells[1] = cpu_to_be32(machine->ram_size);
753 qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0]));
754 qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory");
755 qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory");
756
757 qemu_fdt_add_subnode(fdt, "/chosen");
758 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
759 machine->kernel_cmdline ?: "");
760 qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen");
761
762 qemu_fdt_add_subnode(fdt, "/openprom");
763 qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1");
764
765 return fdt;
766 }
QEmu