target-arm/op_helper.c

   1 /*
   2  *  ARM helper routines
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery, LLC
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "exec/helper-proto.h"
  21 #include "internals.h"
  22 #include "exec/cpu_ldst.h"
  23
  24 #define SIGNBIT (uint32_t)0x80000000
  25 #define SIGNBIT64 ((uint64_t)1 << 63)
  26
  27 static void raise_exception(CPUARMState *env, int tt)
  28 {
  29     ARMCPU *cpu = arm_env_get_cpu(env);
  30     CPUState *cs = CPU(cpu);
  31
  32     cs->exception_index = tt;
  33     cpu_loop_exit(cs);
  34 }
  35
  36 uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
  37                           uint32_t rn, uint32_t maxindex)
  38 {
  39     uint32_t val;
  40     uint32_t tmp;
  41     int index;
  42     int shift;
  43     uint64_t *table;
  44     table = (uint64_t *)&env->vfp.regs[rn];
  45     val = 0;
  46     for (shift = 0; shift < 32; shift += 8) {
  47         index = (ireg >> shift) & 0xff;
  48         if (index < maxindex) {
  49             tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
  50             val |= tmp << shift;
  51         } else {
  52             val |= def & (0xff << shift);
  53         }
  54     }
  55     return val;
  56 }
  57
  58 #if !defined(CONFIG_USER_ONLY)
  59
  60 /* try to fill the TLB and return an exception if error. If retaddr is
  61  * NULL, it means that the function was called in C code (i.e. not
  62  * from generated code or from helper.c)
  63  */
  64 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  65               uintptr_t retaddr)
  66 {
  67     int ret;
  68
  69     ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
  70     if (unlikely(ret)) {
  71         ARMCPU *cpu = ARM_CPU(cs);
  72         CPUARMState *env = &cpu->env;
  73
  74         if (retaddr) {
  75             /* now we have a real cpu fault */
  76             cpu_restore_state(cs, retaddr);
  77         }
  78         raise_exception(env, cs->exception_index);
  79     }
  80 }
  81 #endif
  82
  83 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
  84 {
  85     uint32_t res = a + b;
  86     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
  87         env->QF = 1;
  88     return res;
  89 }
  90
  91 uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
  92 {
  93     uint32_t res = a + b;
  94     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
  95         env->QF = 1;
  96         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
  97     }
  98     return res;
  99 }
 100
 101 uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 102 {
 103     uint32_t res = a - b;
 104     if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
 105         env->QF = 1;
 106         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 107     }
 108     return res;
 109 }
 110
 111 uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
 112 {
 113     uint32_t res;
 114     if (val >= 0x40000000) {
 115         res = ~SIGNBIT;
 116         env->QF = 1;
 117     } else if (val <= (int32_t)0xc0000000) {
 118         res = SIGNBIT;
 119         env->QF = 1;
 120     } else {
 121         res = val << 1;
 122     }
 123     return res;
 124 }
 125
 126 uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 127 {
 128     uint32_t res = a + b;
 129     if (res < a) {
 130         env->QF = 1;
 131         res = ~0;
 132     }
 133     return res;
 134 }
 135
 136 uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 137 {
 138     uint32_t res = a - b;
 139     if (res > a) {
 140         env->QF = 1;
 141         res = 0;
 142     }
 143     return res;
 144 }
 145
 146 /* Signed saturation.  */
 147 static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
 148 {
 149     int32_t top;
 150     uint32_t mask;
 151
 152     top = val >> shift;
 153     mask = (1u << shift) - 1;
 154     if (top > 0) {
 155         env->QF = 1;
 156         return mask;
 157     } else if (top < -1) {
 158         env->QF = 1;
 159         return ~mask;
 160     }
 161     return val;
 162 }
 163
 164 /* Unsigned saturation.  */
 165 static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
 166 {
 167     uint32_t max;
 168
 169     max = (1u << shift) - 1;
 170     if (val < 0) {
 171         env->QF = 1;
 172         return 0;
 173     } else if (val > max) {
 174         env->QF = 1;
 175         return max;
 176     }
 177     return val;
 178 }
 179
 180 /* Signed saturate.  */
 181 uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
 182 {
 183     return do_ssat(env, x, shift);
 184 }
 185
 186 /* Dual halfword signed saturate.  */
 187 uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 188 {
 189     uint32_t res;
 190
 191     res = (uint16_t)do_ssat(env, (int16_t)x, shift);
 192     res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
 193     return res;
 194 }
 195
 196 /* Unsigned saturate.  */
 197 uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
 198 {
 199     return do_usat(env, x, shift);
 200 }
 201
 202 /* Dual halfword unsigned saturate.  */
 203 uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 204 {
 205     uint32_t res;
 206
 207     res = (uint16_t)do_usat(env, (int16_t)x, shift);
 208     res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
 209     return res;
 210 }
 211
 212 void HELPER(wfi)(CPUARMState *env)
 213 {
 214     CPUState *cs = CPU(arm_env_get_cpu(env));
 215
 216     cs->exception_index = EXCP_HLT;
 217     cs->halted = 1;
 218     cpu_loop_exit(cs);
 219 }
 220
 221 void HELPER(wfe)(CPUARMState *env)
 222 {
 223     CPUState *cs = CPU(arm_env_get_cpu(env));
 224
 225     /* Don't actually halt the CPU, just yield back to top
 226      * level loop
 227      */
 228     cs->exception_index = EXCP_YIELD;
 229     cpu_loop_exit(cs);
 230 }
 231
 232 /* Raise an internal-to-QEMU exception. This is limited to only
 233  * those EXCP values which are special cases for QEMU to interrupt
 234  * execution and not to be used for exceptions which are passed to
 235  * the guest (those must all have syndrome information and thus should
 236  * use exception_with_syndrome).
 237  */
 238 void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
 239 {
 240     CPUState *cs = CPU(arm_env_get_cpu(env));
 241
 242     assert(excp_is_internal(excp));
 243     cs->exception_index = excp;
 244     cpu_loop_exit(cs);
 245 }
 246
 247 /* Raise an exception with the specified syndrome register value */
 248 void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
 249                                      uint32_t syndrome)
 250 {
 251     CPUState *cs = CPU(arm_env_get_cpu(env));
 252
 253     assert(!excp_is_internal(excp));
 254     cs->exception_index = excp;
 255     env->exception.syndrome = syndrome;
 256     cpu_loop_exit(cs);
 257 }
 258
 259 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 260 {
 261     return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED);
 262 }
 263
 264 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
 265 {
 266     cpsr_write(env, val, mask);
 267 }
 268
 269 /* Access to user mode registers from privileged modes.  */
 270 uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
 271 {
 272     uint32_t val;
 273
 274     if (regno == 13) {
 275         val = env->banked_r13[0];
 276     } else if (regno == 14) {
 277         val = env->banked_r14[0];
 278     } else if (regno >= 8
 279                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 280         val = env->usr_regs[regno - 8];
 281     } else {
 282         val = env->regs[regno];
 283     }
 284     return val;
 285 }
 286
 287 void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
 288 {
 289     if (regno == 13) {
 290         env->banked_r13[0] = val;
 291     } else if (regno == 14) {
 292         env->banked_r14[0] = val;
 293     } else if (regno >= 8
 294                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 295         env->usr_regs[regno - 8] = val;
 296     } else {
 297         env->regs[regno] = val;
 298     }
 299 }
 300
 301 void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome)
 302 {
 303     const ARMCPRegInfo *ri = rip;
 304
 305     if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
 306         && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
 307         env->exception.syndrome = syndrome;
 308         raise_exception(env, EXCP_UDEF);
 309     }
 310
 311     if (!ri->accessfn) {
 312         return;
 313     }
 314
 315     switch (ri->accessfn(env, ri)) {
 316     case CP_ACCESS_OK:
 317         return;
 318     case CP_ACCESS_TRAP:
 319         env->exception.syndrome = syndrome;
 320         break;
 321     case CP_ACCESS_TRAP_UNCATEGORIZED:
 322         env->exception.syndrome = syn_uncategorized();
 323         break;
 324     default:
 325         g_assert_not_reached();
 326     }
 327     raise_exception(env, EXCP_UDEF);
 328 }
 329
 330 void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
 331 {
 332     const ARMCPRegInfo *ri = rip;
 333
 334     ri->writefn(env, ri, value);
 335 }
 336
 337 uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
 338 {
 339     const ARMCPRegInfo *ri = rip;
 340
 341     return ri->readfn(env, ri);
 342 }
 343
 344 void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
 345 {
 346     const ARMCPRegInfo *ri = rip;
 347
 348     ri->writefn(env, ri, value);
 349 }
 350
 351 uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
 352 {
 353     const ARMCPRegInfo *ri = rip;
 354
 355     return ri->readfn(env, ri);
 356 }
 357
 358 void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
 359 {
 360     /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
 361      * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
 362      * to catch that case at translate time.
 363      */
 364     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
 365         raise_exception(env, EXCP_UDEF);
 366     }
 367
 368     switch (op) {
 369     case 0x05: /* SPSel */
 370         update_spsel(env, imm);
 371         break;
 372     case 0x1e: /* DAIFSet */
 373         env->daif |= (imm << 6) & PSTATE_DAIF;
 374         break;
 375     case 0x1f: /* DAIFClear */
 376         env->daif &= ~((imm << 6) & PSTATE_DAIF);
 377         break;
 378     default:
 379         g_assert_not_reached();
 380     }
 381 }
 382
 383 void HELPER(clear_pstate_ss)(CPUARMState *env)
 384 {
 385     env->pstate &= ~PSTATE_SS;
 386 }
 387
 388 void HELPER(pre_hvc)(CPUARMState *env)
 389 {
 390     int cur_el = arm_current_pl(env);
 391     /* FIXME: Use actual secure state.  */
 392     bool secure = false;
 393     bool undef;
 394
 395     /* We've already checked that EL2 exists at translation time.
 396      * EL3.HCE has priority over EL2.HCD.
 397      */
 398     if (arm_feature(env, ARM_FEATURE_EL3)) {
 399         undef = !(env->cp15.scr_el3 & SCR_HCE);
 400     } else {
 401         undef = env->cp15.hcr_el2 & HCR_HCD;
 402     }
 403
 404     /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
 405      * For ARMv8/AArch64, HVC is allowed in EL3.
 406      * Note that we've already trapped HVC from EL0 at translation
 407      * time.
 408      */
 409     if (secure && (!is_a64(env) || cur_el == 1)) {
 410         undef = true;
 411     }
 412
 413     if (undef) {
 414         env->exception.syndrome = syn_uncategorized();
 415         raise_exception(env, EXCP_UDEF);
 416     }
 417 }
 418
 419 void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
 420 {
 421     int cur_el = arm_current_pl(env);
 422     /* FIXME: Use real secure state.  */
 423     bool secure = false;
 424     bool smd = env->cp15.scr_el3 & SCR_SMD;
 425     /* On ARMv8 AArch32, SMD only applies to NS state.
 426      * On ARMv7 SMD only applies to NS state and only if EL2 is available.
 427      * For ARMv7 non EL2, we force SMD to zero so we don't need to re-check
 428      * the EL2 condition here.
 429      */
 430     bool undef = is_a64(env) ? smd : (!secure && smd);
 431
 432     /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.  */
 433     if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
 434         env->exception.syndrome = syndrome;
 435         raise_exception(env, EXCP_HYP_TRAP);
 436     }
 437
 438     /* We've already checked that EL3 exists at translation time.  */
 439     if (undef) {
 440         env->exception.syndrome = syn_uncategorized();
 441         raise_exception(env, EXCP_UDEF);
 442     }
 443 }
 444
 445 void HELPER(exception_return)(CPUARMState *env)
 446 {
 447     int cur_el = arm_current_pl(env);
 448     unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
 449     uint32_t spsr = env->banked_spsr[spsr_idx];
 450     int new_el, i;
 451
 452     aarch64_save_sp(env, cur_el);
 453
 454     env->exclusive_addr = -1;
 455
 456     /* We must squash the PSTATE.SS bit to zero unless both of the
 457      * following hold:
 458      *  1. debug exceptions are currently disabled
 459      *  2. singlestep will be active in the EL we return to
 460      * We check 1 here and 2 after we've done the pstate/cpsr write() to
 461      * transition to the EL we're going to.
 462      */
 463     if (arm_generate_debug_exceptions(env)) {
 464         spsr &= ~PSTATE_SS;
 465     }
 466
 467     if (spsr & PSTATE_nRW) {
 468         /* TODO: We currently assume EL1/2/3 are running in AArch64.  */
 469         env->aarch64 = 0;
 470         new_el = 0;
 471         env->uncached_cpsr = 0x10;
 472         cpsr_write(env, spsr, ~0);
 473         if (!arm_singlestep_active(env)) {
 474             env->uncached_cpsr &= ~PSTATE_SS;
 475         }
 476         for (i = 0; i < 15; i++) {
 477             env->regs[i] = env->xregs[i];
 478         }
 479
 480         env->regs[15] = env->elr_el[1] & ~0x1;
 481     } else {
 482         new_el = extract32(spsr, 2, 2);
 483         if (new_el > cur_el
 484             || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) {
 485             /* Disallow return to an EL which is unimplemented or higher
 486              * than the current one.
 487              */
 488             goto illegal_return;
 489         }
 490         if (extract32(spsr, 1, 1)) {
 491             /* Return with reserved M[1] bit set */
 492             goto illegal_return;
 493         }
 494         if (new_el == 0 && (spsr & PSTATE_SP)) {
 495             /* Return to EL0 with M[0] bit set */
 496             goto illegal_return;
 497         }
 498         env->aarch64 = 1;
 499         pstate_write(env, spsr);
 500         if (!arm_singlestep_active(env)) {
 501             env->pstate &= ~PSTATE_SS;
 502         }
 503         aarch64_restore_sp(env, new_el);
 504         env->pc = env->elr_el[cur_el];
 505     }
 506
 507     return;
 508
 509 illegal_return:
 510     /* Illegal return events of various kinds have architecturally
 511      * mandated behaviour:
 512      * restore NZCV and DAIF from SPSR_ELx
 513      * set PSTATE.IL
 514      * restore PC from ELR_ELx
 515      * no change to exception level, execution state or stack pointer
 516      */
 517     env->pstate |= PSTATE_IL;
 518     env->pc = env->elr_el[cur_el];
 519     spsr &= PSTATE_NZCV | PSTATE_DAIF;
 520     spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
 521     pstate_write(env, spsr);
 522     if (!arm_singlestep_active(env)) {
 523         env->pstate &= ~PSTATE_SS;
 524     }
 525 }
 526
 527 /* Return true if the linked breakpoint entry lbn passes its checks */
 528 static bool linked_bp_matches(ARMCPU *cpu, int lbn)
 529 {
 530     CPUARMState *env = &cpu->env;
 531     uint64_t bcr = env->cp15.dbgbcr[lbn];
 532     int brps = extract32(cpu->dbgdidr, 24, 4);
 533     int ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
 534     int bt;
 535     uint32_t contextidr;
 536
 537     /* Links to unimplemented or non-context aware breakpoints are
 538      * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
 539      * as if linked to an UNKNOWN context-aware breakpoint (in which
 540      * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
 541      * We choose the former.
 542      */
 543     if (lbn > brps || lbn < (brps - ctx_cmps)) {
 544         return false;
 545     }
 546
 547     bcr = env->cp15.dbgbcr[lbn];
 548
 549     if (extract64(bcr, 0, 1) == 0) {
 550         /* Linked breakpoint disabled : generate no events */
 551         return false;
 552     }
 553
 554     bt = extract64(bcr, 20, 4);
 555
 556     /* We match the whole register even if this is AArch32 using the
 557      * short descriptor format (in which case it holds both PROCID and ASID),
 558      * since we don't implement the optional v7 context ID masking.
 559      */
 560     contextidr = extract64(env->cp15.contextidr_el1, 0, 32);
 561
 562     switch (bt) {
 563     case 3: /* linked context ID match */
 564         if (arm_current_pl(env) > 1) {
 565             /* Context matches never fire in EL2 or (AArch64) EL3 */
 566             return false;
 567         }
 568         return (contextidr == extract64(env->cp15.dbgbvr[lbn], 0, 32));
 569     case 5: /* linked address mismatch (reserved in AArch64) */
 570     case 9: /* linked VMID match (reserved if no EL2) */
 571     case 11: /* linked context ID and VMID match (reserved if no EL2) */
 572     default:
 573         /* Links to Unlinked context breakpoints must generate no
 574          * events; we choose to do the same for reserved values too.
 575          */
 576         return false;
 577     }
 578
 579     return false;
 580 }
 581
 582 static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
 583 {
 584     CPUARMState *env = &cpu->env;
 585     uint64_t cr;
 586     int pac, hmc, ssc, wt, lbn;
 587     /* TODO: check against CPU security state when we implement TrustZone */
 588     bool is_secure = false;
 589
 590     if (is_wp) {
 591         if (!env->cpu_watchpoint[n]
 592             || !(env->cpu_watchpoint[n]->flags & BP_WATCHPOINT_HIT)) {
 593             return false;
 594         }
 595         cr = env->cp15.dbgwcr[n];
 596     } else {
 597         uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
 598
 599         if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc != pc) {
 600             return false;
 601         }
 602         cr = env->cp15.dbgbcr[n];
 603     }
 604     /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
 605      * enabled and that the address and access type match; for breakpoints
 606      * we know the address matched; check the remaining fields, including
 607      * linked breakpoints. We rely on WCR and BCR having the same layout
 608      * for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
 609      * Note that some combinations of {PAC, HMC, SSC} are reserved and
 610      * must act either like some valid combination or as if the watchpoint
 611      * were disabled. We choose the former, and use this together with
 612      * the fact that EL3 must always be Secure and EL2 must always be
 613      * Non-Secure to simplify the code slightly compared to the full
 614      * table in the ARM ARM.
 615      */
 616     pac = extract64(cr, 1, 2);
 617     hmc = extract64(cr, 13, 1);
 618     ssc = extract64(cr, 14, 2);
 619
 620     switch (ssc) {
 621     case 0:
 622         break;
 623     case 1:
 624     case 3:
 625         if (is_secure) {
 626             return false;
 627         }
 628         break;
 629     case 2:
 630         if (!is_secure) {
 631             return false;
 632         }
 633         break;
 634     }
 635
 636     /* TODO: this is not strictly correct because the LDRT/STRT/LDT/STT
 637      * "unprivileged access" instructions should match watchpoints as if
 638      * they were accesses done at EL0, even if the CPU is at EL1 or higher.
 639      * Implementing this would require reworking the core watchpoint code
 640      * to plumb the mmu_idx through to this point. Luckily Linux does not
 641      * rely on this behaviour currently.
 642      * For breakpoints we do want to use the current CPU state.
 643      */
 644     switch (arm_current_pl(env)) {
 645     case 3:
 646     case 2:
 647         if (!hmc) {
 648             return false;
 649         }
 650         break;
 651     case 1:
 652         if (extract32(pac, 0, 1) == 0) {
 653             return false;
 654         }
 655         break;
 656     case 0:
 657         if (extract32(pac, 1, 1) == 0) {
 658             return false;
 659         }
 660         break;
 661     default:
 662         g_assert_not_reached();
 663     }
 664
 665     wt = extract64(cr, 20, 1);
 666     lbn = extract64(cr, 16, 4);
 667
 668     if (wt && !linked_bp_matches(cpu, lbn)) {
 669         return false;
 670     }
 671
 672     return true;
 673 }
 674
 675 static bool check_watchpoints(ARMCPU *cpu)
 676 {
 677     CPUARMState *env = &cpu->env;
 678     int n;
 679
 680     /* If watchpoints are disabled globally or we can't take debug
 681      * exceptions here then watchpoint firings are ignored.
 682      */
 683     if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
 684         || !arm_generate_debug_exceptions(env)) {
 685         return false;
 686     }
 687
 688     for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) {
 689         if (bp_wp_matches(cpu, n, true)) {
 690             return true;
 691         }
 692     }
 693     return false;
 694 }
 695
 696 static bool check_breakpoints(ARMCPU *cpu)
 697 {
 698     CPUARMState *env = &cpu->env;
 699     int n;
 700
 701     /* If breakpoints are disabled globally or we can't take debug
 702      * exceptions here then breakpoint firings are ignored.
 703      */
 704     if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
 705         || !arm_generate_debug_exceptions(env)) {
 706         return false;
 707     }
 708
 709     for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
 710         if (bp_wp_matches(cpu, n, false)) {
 711             return true;
 712         }
 713     }
 714     return false;
 715 }
 716
 717 void arm_debug_excp_handler(CPUState *cs)
 718 {
 719     /* Called by core code when a watchpoint or breakpoint fires;
 720      * need to check which one and raise the appropriate exception.
 721      */
 722     ARMCPU *cpu = ARM_CPU(cs);
 723     CPUARMState *env = &cpu->env;
 724     CPUWatchpoint *wp_hit = cs->watchpoint_hit;
 725
 726     if (wp_hit) {
 727         if (wp_hit->flags & BP_CPU) {
 728             cs->watchpoint_hit = NULL;
 729             if (check_watchpoints(cpu)) {
 730                 bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
 731                 bool same_el = arm_debug_target_el(env) == arm_current_pl(env);
 732
 733                 env->exception.syndrome = syn_watchpoint(same_el, 0, wnr);
 734                 if (extended_addresses_enabled(env)) {
 735                     env->exception.fsr = (1 << 9) | 0x22;
 736                 } else {
 737                     env->exception.fsr = 0x2;
 738                 }
 739                 env->exception.vaddress = wp_hit->hitaddr;
 740                 raise_exception(env, EXCP_DATA_ABORT);
 741             } else {
 742                 cpu_resume_from_signal(cs, NULL);
 743             }
 744         }
 745     } else {
 746         if (check_breakpoints(cpu)) {
 747             bool same_el = (arm_debug_target_el(env) == arm_current_pl(env));
 748             env->exception.syndrome = syn_breakpoint(same_el);
 749             if (extended_addresses_enabled(env)) {
 750                 env->exception.fsr = (1 << 9) | 0x22;
 751             } else {
 752                 env->exception.fsr = 0x2;
 753             }
 754             /* FAR is UNKNOWN, so doesn't need setting */
 755             raise_exception(env, EXCP_PREFETCH_ABORT);
 756         }
 757     }
 758 }
 759
 760 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
 761    The only way to do that in TCG is a conditional branch, which clobbers
 762    all our temporaries.  For now implement these as helper functions.  */
 763
 764 /* Similarly for variable shift instructions.  */
 765
 766 uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 767 {
 768     int shift = i & 0xff;
 769     if (shift >= 32) {
 770         if (shift == 32)
 771             env->CF = x & 1;
 772         else
 773             env->CF = 0;
 774         return 0;
 775     } else if (shift != 0) {
 776         env->CF = (x >> (32 - shift)) & 1;
 777         return x << shift;
 778     }
 779     return x;
 780 }
 781
 782 uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 783 {
 784     int shift = i & 0xff;
 785     if (shift >= 32) {
 786         if (shift == 32)
 787             env->CF = (x >> 31) & 1;
 788         else
 789             env->CF = 0;
 790         return 0;
 791     } else if (shift != 0) {
 792         env->CF = (x >> (shift - 1)) & 1;
 793         return x >> shift;
 794     }
 795     return x;
 796 }
 797
 798 uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 799 {
 800     int shift = i & 0xff;
 801     if (shift >= 32) {
 802         env->CF = (x >> 31) & 1;
 803         return (int32_t)x >> 31;
 804     } else if (shift != 0) {
 805         env->CF = (x >> (shift - 1)) & 1;
 806         return (int32_t)x >> shift;
 807     }
 808     return x;
 809 }
 810
 811 uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 812 {
 813     int shift1, shift;
 814     shift1 = i & 0xff;
 815     shift = shift1 & 0x1f;
 816     if (shift == 0) {
 817         if (shift1 != 0)
 818             env->CF = (x >> 31) & 1;
 819         return x;
 820     } else {
 821         env->CF = (x >> (shift - 1)) & 1;
 822         return ((uint32_t)x >> shift) | (x << (32 - shift));
 823     }
 824 }