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target-sparc: address_mask(), asi_address_mask() are TARGET_SPARC64 only
[qemu.git] / target-sparc / ldst_helper.c
blobcdc21d3325dcfdd3ef112a0096f1604e9f38021a
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22 #include "exec/cpu_ldst.h"
23
24 //#define DEBUG_MMU
25 //#define DEBUG_MXCC
26 //#define DEBUG_UNALIGNED
27 //#define DEBUG_UNASSIGNED
28 //#define DEBUG_ASI
29 //#define DEBUG_CACHE_CONTROL
30
31 #ifdef DEBUG_MMU
32 #define DPRINTF_MMU(fmt, ...) \
33 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
34 #else
35 #define DPRINTF_MMU(fmt, ...) do {} while (0)
36 #endif
37
38 #ifdef DEBUG_MXCC
39 #define DPRINTF_MXCC(fmt, ...) \
40 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
41 #else
42 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
43 #endif
44
45 #ifdef DEBUG_ASI
46 #define DPRINTF_ASI(fmt, ...) \
47 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
48 #endif
49
50 #ifdef DEBUG_CACHE_CONTROL
51 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
52 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
53 #else
54 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
55 #endif
56
57 #ifdef TARGET_SPARC64
58 #ifndef TARGET_ABI32
59 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
60 #else
61 #define AM_CHECK(env1) (1)
62 #endif
63 #endif
64
65 #define QT0 (env->qt0)
66 #define QT1 (env->qt1)
67
68 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
69 /* Calculates TSB pointer value for fault page size 8k or 64k */
70 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
71 uint64_t tag_access_register,
72 int page_size)
73 {
74 uint64_t tsb_base = tsb_register & ~0x1fffULL;
75 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
76 int tsb_size = tsb_register & 0xf;
77
78 /* discard lower 13 bits which hold tag access context */
79 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
80
81 /* now reorder bits */
82 uint64_t tsb_base_mask = ~0x1fffULL;
83 uint64_t va = tag_access_va;
84
85 /* move va bits to correct position */
86 if (page_size == 8*1024) {
87 va >>= 9;
88 } else if (page_size == 64*1024) {
89 va >>= 12;
90 }
91
92 if (tsb_size) {
93 tsb_base_mask <<= tsb_size;
94 }
95
96 /* calculate tsb_base mask and adjust va if split is in use */
97 if (tsb_split) {
98 if (page_size == 8*1024) {
99 va &= ~(1ULL << (13 + tsb_size));
100 } else if (page_size == 64*1024) {
101 va |= (1ULL << (13 + tsb_size));
102 }
103 tsb_base_mask <<= 1;
104 }
105
106 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
107 }
108
109 /* Calculates tag target register value by reordering bits
110 in tag access register */
111 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
112 {
113 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
114 }
115
116 static void replace_tlb_entry(SparcTLBEntry *tlb,
117 uint64_t tlb_tag, uint64_t tlb_tte,
118 CPUSPARCState *env1)
119 {
120 target_ulong mask, size, va, offset;
121
122 /* flush page range if translation is valid */
123 if (TTE_IS_VALID(tlb->tte)) {
124 CPUState *cs = CPU(sparc_env_get_cpu(env1));
125
126 mask = 0xffffffffffffe000ULL;
127 mask <<= 3 * ((tlb->tte >> 61) & 3);
128 size = ~mask + 1;
129
130 va = tlb->tag & mask;
131
132 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
133 tlb_flush_page(cs, va + offset);
134 }
135 }
136
137 tlb->tag = tlb_tag;
138 tlb->tte = tlb_tte;
139 }
140
141 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
142 const char *strmmu, CPUSPARCState *env1)
143 {
144 unsigned int i;
145 target_ulong mask;
146 uint64_t context;
147
148 int is_demap_context = (demap_addr >> 6) & 1;
149
150 /* demap context */
151 switch ((demap_addr >> 4) & 3) {
152 case 0: /* primary */
153 context = env1->dmmu.mmu_primary_context;
154 break;
155 case 1: /* secondary */
156 context = env1->dmmu.mmu_secondary_context;
157 break;
158 case 2: /* nucleus */
159 context = 0;
160 break;
161 case 3: /* reserved */
162 default:
163 return;
164 }
165
166 for (i = 0; i < 64; i++) {
167 if (TTE_IS_VALID(tlb[i].tte)) {
168
169 if (is_demap_context) {
170 /* will remove non-global entries matching context value */
171 if (TTE_IS_GLOBAL(tlb[i].tte) ||
172 !tlb_compare_context(&tlb[i], context)) {
173 continue;
174 }
175 } else {
176 /* demap page
177 will remove any entry matching VA */
178 mask = 0xffffffffffffe000ULL;
179 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
180
181 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
182 continue;
183 }
184
185 /* entry should be global or matching context value */
186 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
187 !tlb_compare_context(&tlb[i], context)) {
188 continue;
189 }
190 }
191
192 replace_tlb_entry(&tlb[i], 0, 0, env1);
193 #ifdef DEBUG_MMU
194 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
195 dump_mmu(stdout, fprintf, env1);
196 #endif
197 }
198 }
199 }
200
201 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
202 uint64_t tlb_tag, uint64_t tlb_tte,
203 const char *strmmu, CPUSPARCState *env1)
204 {
205 unsigned int i, replace_used;
206
207 /* Try replacing invalid entry */
208 for (i = 0; i < 64; i++) {
209 if (!TTE_IS_VALID(tlb[i].tte)) {
210 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
211 #ifdef DEBUG_MMU
212 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
213 dump_mmu(stdout, fprintf, env1);
214 #endif
215 return;
216 }
217 }
218
219 /* All entries are valid, try replacing unlocked entry */
220
221 for (replace_used = 0; replace_used < 2; ++replace_used) {
222
223 /* Used entries are not replaced on first pass */
224
225 for (i = 0; i < 64; i++) {
226 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
227
228 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
229 #ifdef DEBUG_MMU
230 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
231 strmmu, (replace_used ? "used" : "unused"), i);
232 dump_mmu(stdout, fprintf, env1);
233 #endif
234 return;
235 }
236 }
237
238 /* Now reset used bit and search for unused entries again */
239
240 for (i = 0; i < 64; i++) {
241 TTE_SET_UNUSED(tlb[i].tte);
242 }
243 }
244
245 #ifdef DEBUG_MMU
246 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
247 #endif
248 /* error state? */
249 }
250
251 #endif
252
253 #if defined(TARGET_SPARC64) || defined(CONFIG_USER_ONLY)
254 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
255 {
256 #ifdef TARGET_SPARC64
257 if (AM_CHECK(env1)) {
258 addr &= 0xffffffffULL;
259 }
260 #endif
261 return addr;
262 }
263 #endif
264
265 /* returns true if access using this ASI is to have address translated by MMU
266 otherwise access is to raw physical address */
267 static inline int is_translating_asi(int asi)
268 {
269 #ifdef TARGET_SPARC64
270 /* Ultrasparc IIi translating asi
271 - note this list is defined by cpu implementation
272 */
273 switch (asi) {
274 case 0x04 ... 0x11:
275 case 0x16 ... 0x19:
276 case 0x1E ... 0x1F:
277 case 0x24 ... 0x2C:
278 case 0x70 ... 0x73:
279 case 0x78 ... 0x79:
280 case 0x80 ... 0xFF:
281 return 1;
282
283 default:
284 return 0;
285 }
286 #else
287 /* TODO: check sparc32 bits */
288 return 0;
289 #endif
290 }
291
292 #ifdef TARGET_SPARC64
293 static inline target_ulong asi_address_mask(CPUSPARCState *env,
294 int asi, target_ulong addr)
295 {
296 if (is_translating_asi(asi)) {
297 return address_mask(env, addr);
298 } else {
299 return addr;
300 }
301 }
302 #endif
303
304 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
305 {
306 if (addr & align) {
307 #ifdef DEBUG_UNALIGNED
308 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
309 "\n", addr, env->pc);
310 #endif
311 helper_raise_exception(env, TT_UNALIGNED);
312 }
313 }
314
315 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
316 defined(DEBUG_MXCC)
317 static void dump_mxcc(CPUSPARCState *env)
318 {
319 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
320 "\n",
321 env->mxccdata[0], env->mxccdata[1],
322 env->mxccdata[2], env->mxccdata[3]);
323 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
324 "\n"
325 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
326 "\n",
327 env->mxccregs[0], env->mxccregs[1],
328 env->mxccregs[2], env->mxccregs[3],
329 env->mxccregs[4], env->mxccregs[5],
330 env->mxccregs[6], env->mxccregs[7]);
331 }
332 #endif
333
334 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
335 && defined(DEBUG_ASI)
336 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
337 uint64_t r1)
338 {
339 switch (size) {
340 case 1:
341 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
342 addr, asi, r1 & 0xff);
343 break;
344 case 2:
345 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
346 addr, asi, r1 & 0xffff);
347 break;
348 case 4:
349 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
350 addr, asi, r1 & 0xffffffff);
351 break;
352 case 8:
353 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
354 addr, asi, r1);
355 break;
356 }
357 }
358 #endif
359
360 #ifndef TARGET_SPARC64
361 #ifndef CONFIG_USER_ONLY
362
363
364 /* Leon3 cache control */
365
366 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
367 uint64_t val, int size)
368 {
369 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
370 addr, val, size);
371
372 if (size != 4) {
373 DPRINTF_CACHE_CONTROL("32bits only\n");
374 return;
375 }
376
377 switch (addr) {
378 case 0x00: /* Cache control */
379
380 /* These values must always be read as zeros */
381 val &= ~CACHE_CTRL_FD;
382 val &= ~CACHE_CTRL_FI;
383 val &= ~CACHE_CTRL_IB;
384 val &= ~CACHE_CTRL_IP;
385 val &= ~CACHE_CTRL_DP;
386
387 env->cache_control = val;
388 break;
389 case 0x04: /* Instruction cache configuration */
390 case 0x08: /* Data cache configuration */
391 /* Read Only */
392 break;
393 default:
394 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
395 break;
396 };
397 }
398
399 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
400 int size)
401 {
402 uint64_t ret = 0;
403
404 if (size != 4) {
405 DPRINTF_CACHE_CONTROL("32bits only\n");
406 return 0;
407 }
408
409 switch (addr) {
410 case 0x00: /* Cache control */
411 ret = env->cache_control;
412 break;
413
414 /* Configuration registers are read and only always keep those
415 predefined values */
416
417 case 0x04: /* Instruction cache configuration */
418 ret = 0x10220000;
419 break;
420 case 0x08: /* Data cache configuration */
421 ret = 0x18220000;
422 break;
423 default:
424 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
425 break;
426 };
427 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
428 addr, ret, size);
429 return ret;
430 }
431
432 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
433 int sign)
434 {
435 CPUState *cs = CPU(sparc_env_get_cpu(env));
436 uint64_t ret = 0;
437 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
438 uint32_t last_addr = addr;
439 #endif
440
441 helper_check_align(env, addr, size - 1);
442 switch (asi) {
443 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
444 switch (addr) {
445 case 0x00: /* Leon3 Cache Control */
446 case 0x08: /* Leon3 Instruction Cache config */
447 case 0x0C: /* Leon3 Date Cache config */
448 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
449 ret = leon3_cache_control_ld(env, addr, size);
450 }
451 break;
452 case 0x01c00a00: /* MXCC control register */
453 if (size == 8) {
454 ret = env->mxccregs[3];
455 } else {
456 qemu_log_mask(LOG_UNIMP,
457 "%08x: unimplemented access size: %d\n", addr,
458 size);
459 }
460 break;
461 case 0x01c00a04: /* MXCC control register */
462 if (size == 4) {
463 ret = env->mxccregs[3];
464 } else {
465 qemu_log_mask(LOG_UNIMP,
466 "%08x: unimplemented access size: %d\n", addr,
467 size);
468 }
469 break;
470 case 0x01c00c00: /* Module reset register */
471 if (size == 8) {
472 ret = env->mxccregs[5];
473 /* should we do something here? */
474 } else {
475 qemu_log_mask(LOG_UNIMP,
476 "%08x: unimplemented access size: %d\n", addr,
477 size);
478 }
479 break;
480 case 0x01c00f00: /* MBus port address register */
481 if (size == 8) {
482 ret = env->mxccregs[7];
483 } else {
484 qemu_log_mask(LOG_UNIMP,
485 "%08x: unimplemented access size: %d\n", addr,
486 size);
487 }
488 break;
489 default:
490 qemu_log_mask(LOG_UNIMP,
491 "%08x: unimplemented address, size: %d\n", addr,
492 size);
493 break;
494 }
495 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
496 "addr = %08x -> ret = %" PRIx64 ","
497 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
498 #ifdef DEBUG_MXCC
499 dump_mxcc(env);
500 #endif
501 break;
502 case 3: /* MMU probe */
503 case 0x18: /* LEON3 MMU probe */
504 {
505 int mmulev;
506
507 mmulev = (addr >> 8) & 15;
508 if (mmulev > 4) {
509 ret = 0;
510 } else {
511 ret = mmu_probe(env, addr, mmulev);
512 }
513 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
514 addr, mmulev, ret);
515 }
516 break;
517 case 4: /* read MMU regs */
518 case 0x19: /* LEON3 read MMU regs */
519 {
520 int reg = (addr >> 8) & 0x1f;
521
522 ret = env->mmuregs[reg];
523 if (reg == 3) { /* Fault status cleared on read */
524 env->mmuregs[3] = 0;
525 } else if (reg == 0x13) { /* Fault status read */
526 ret = env->mmuregs[3];
527 } else if (reg == 0x14) { /* Fault address read */
528 ret = env->mmuregs[4];
529 }
530 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
531 }
532 break;
533 case 5: /* Turbosparc ITLB Diagnostic */
534 case 6: /* Turbosparc DTLB Diagnostic */
535 case 7: /* Turbosparc IOTLB Diagnostic */
536 break;
537 case 9: /* Supervisor code access */
538 switch (size) {
539 case 1:
540 ret = cpu_ldub_code(env, addr);
541 break;
542 case 2:
543 ret = cpu_lduw_code(env, addr);
544 break;
545 default:
546 case 4:
547 ret = cpu_ldl_code(env, addr);
548 break;
549 case 8:
550 ret = cpu_ldq_code(env, addr);
551 break;
552 }
553 break;
554 case 0xa: /* User data access */
555 switch (size) {
556 case 1:
557 ret = cpu_ldub_user(env, addr);
558 break;
559 case 2:
560 ret = cpu_lduw_user(env, addr);
561 break;
562 default:
563 case 4:
564 ret = cpu_ldl_user(env, addr);
565 break;
566 case 8:
567 ret = cpu_ldq_user(env, addr);
568 break;
569 }
570 break;
571 case 0xb: /* Supervisor data access */
572 case 0x80:
573 switch (size) {
574 case 1:
575 ret = cpu_ldub_kernel(env, addr);
576 break;
577 case 2:
578 ret = cpu_lduw_kernel(env, addr);
579 break;
580 default:
581 case 4:
582 ret = cpu_ldl_kernel(env, addr);
583 break;
584 case 8:
585 ret = cpu_ldq_kernel(env, addr);
586 break;
587 }
588 break;
589 case 0xc: /* I-cache tag */
590 case 0xd: /* I-cache data */
591 case 0xe: /* D-cache tag */
592 case 0xf: /* D-cache data */
593 break;
594 case 0x20: /* MMU passthrough */
595 case 0x1c: /* LEON MMU passthrough */
596 switch (size) {
597 case 1:
598 ret = ldub_phys(cs->as, addr);
599 break;
600 case 2:
601 ret = lduw_phys(cs->as, addr);
602 break;
603 default:
604 case 4:
605 ret = ldl_phys(cs->as, addr);
606 break;
607 case 8:
608 ret = ldq_phys(cs->as, addr);
609 break;
610 }
611 break;
612 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
613 switch (size) {
614 case 1:
615 ret = ldub_phys(cs->as, (hwaddr)addr
616 | ((hwaddr)(asi & 0xf) << 32));
617 break;
618 case 2:
619 ret = lduw_phys(cs->as, (hwaddr)addr
620 | ((hwaddr)(asi & 0xf) << 32));
621 break;
622 default:
623 case 4:
624 ret = ldl_phys(cs->as, (hwaddr)addr
625 | ((hwaddr)(asi & 0xf) << 32));
626 break;
627 case 8:
628 ret = ldq_phys(cs->as, (hwaddr)addr
629 | ((hwaddr)(asi & 0xf) << 32));
630 break;
631 }
632 break;
633 case 0x30: /* Turbosparc secondary cache diagnostic */
634 case 0x31: /* Turbosparc RAM snoop */
635 case 0x32: /* Turbosparc page table descriptor diagnostic */
636 case 0x39: /* data cache diagnostic register */
637 ret = 0;
638 break;
639 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
640 {
641 int reg = (addr >> 8) & 3;
642
643 switch (reg) {
644 case 0: /* Breakpoint Value (Addr) */
645 ret = env->mmubpregs[reg];
646 break;
647 case 1: /* Breakpoint Mask */
648 ret = env->mmubpregs[reg];
649 break;
650 case 2: /* Breakpoint Control */
651 ret = env->mmubpregs[reg];
652 break;
653 case 3: /* Breakpoint Status */
654 ret = env->mmubpregs[reg];
655 env->mmubpregs[reg] = 0ULL;
656 break;
657 }
658 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
659 ret);
660 }
661 break;
662 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
663 ret = env->mmubpctrv;
664 break;
665 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
666 ret = env->mmubpctrc;
667 break;
668 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
669 ret = env->mmubpctrs;
670 break;
671 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
672 ret = env->mmubpaction;
673 break;
674 case 8: /* User code access, XXX */
675 default:
676 cpu_unassigned_access(cs, addr, false, false, asi, size);
677 ret = 0;
678 break;
679 }
680 if (sign) {
681 switch (size) {
682 case 1:
683 ret = (int8_t) ret;
684 break;
685 case 2:
686 ret = (int16_t) ret;
687 break;
688 case 4:
689 ret = (int32_t) ret;
690 break;
691 default:
692 break;
693 }
694 }
695 #ifdef DEBUG_ASI
696 dump_asi("read ", last_addr, asi, size, ret);
697 #endif
698 return ret;
699 }
700
701 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
702 int size)
703 {
704 SPARCCPU *cpu = sparc_env_get_cpu(env);
705 CPUState *cs = CPU(cpu);
706
707 helper_check_align(env, addr, size - 1);
708 switch (asi) {
709 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
710 switch (addr) {
711 case 0x00: /* Leon3 Cache Control */
712 case 0x08: /* Leon3 Instruction Cache config */
713 case 0x0C: /* Leon3 Date Cache config */
714 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
715 leon3_cache_control_st(env, addr, val, size);
716 }
717 break;
718
719 case 0x01c00000: /* MXCC stream data register 0 */
720 if (size == 8) {
721 env->mxccdata[0] = val;
722 } else {
723 qemu_log_mask(LOG_UNIMP,
724 "%08x: unimplemented access size: %d\n", addr,
725 size);
726 }
727 break;
728 case 0x01c00008: /* MXCC stream data register 1 */
729 if (size == 8) {
730 env->mxccdata[1] = val;
731 } else {
732 qemu_log_mask(LOG_UNIMP,
733 "%08x: unimplemented access size: %d\n", addr,
734 size);
735 }
736 break;
737 case 0x01c00010: /* MXCC stream data register 2 */
738 if (size == 8) {
739 env->mxccdata[2] = val;
740 } else {
741 qemu_log_mask(LOG_UNIMP,
742 "%08x: unimplemented access size: %d\n", addr,
743 size);
744 }
745 break;
746 case 0x01c00018: /* MXCC stream data register 3 */
747 if (size == 8) {
748 env->mxccdata[3] = val;
749 } else {
750 qemu_log_mask(LOG_UNIMP,
751 "%08x: unimplemented access size: %d\n", addr,
752 size);
753 }
754 break;
755 case 0x01c00100: /* MXCC stream source */
756 if (size == 8) {
757 env->mxccregs[0] = val;
758 } else {
759 qemu_log_mask(LOG_UNIMP,
760 "%08x: unimplemented access size: %d\n", addr,
761 size);
762 }
763 env->mxccdata[0] = ldq_phys(cs->as,
764 (env->mxccregs[0] & 0xffffffffULL) +
765 0);
766 env->mxccdata[1] = ldq_phys(cs->as,
767 (env->mxccregs[0] & 0xffffffffULL) +
768 8);
769 env->mxccdata[2] = ldq_phys(cs->as,
770 (env->mxccregs[0] & 0xffffffffULL) +
771 16);
772 env->mxccdata[3] = ldq_phys(cs->as,
773 (env->mxccregs[0] & 0xffffffffULL) +
774 24);
775 break;
776 case 0x01c00200: /* MXCC stream destination */
777 if (size == 8) {
778 env->mxccregs[1] = val;
779 } else {
780 qemu_log_mask(LOG_UNIMP,
781 "%08x: unimplemented access size: %d\n", addr,
782 size);
783 }
784 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
785 env->mxccdata[0]);
786 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
787 env->mxccdata[1]);
788 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
789 env->mxccdata[2]);
790 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
791 env->mxccdata[3]);
792 break;
793 case 0x01c00a00: /* MXCC control register */
794 if (size == 8) {
795 env->mxccregs[3] = val;
796 } else {
797 qemu_log_mask(LOG_UNIMP,
798 "%08x: unimplemented access size: %d\n", addr,
799 size);
800 }
801 break;
802 case 0x01c00a04: /* MXCC control register */
803 if (size == 4) {
804 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
805 | val;
806 } else {
807 qemu_log_mask(LOG_UNIMP,
808 "%08x: unimplemented access size: %d\n", addr,
809 size);
810 }
811 break;
812 case 0x01c00e00: /* MXCC error register */
813 /* writing a 1 bit clears the error */
814 if (size == 8) {
815 env->mxccregs[6] &= ~val;
816 } else {
817 qemu_log_mask(LOG_UNIMP,
818 "%08x: unimplemented access size: %d\n", addr,
819 size);
820 }
821 break;
822 case 0x01c00f00: /* MBus port address register */
823 if (size == 8) {
824 env->mxccregs[7] = val;
825 } else {
826 qemu_log_mask(LOG_UNIMP,
827 "%08x: unimplemented access size: %d\n", addr,
828 size);
829 }
830 break;
831 default:
832 qemu_log_mask(LOG_UNIMP,
833 "%08x: unimplemented address, size: %d\n", addr,
834 size);
835 break;
836 }
837 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
838 asi, size, addr, val);
839 #ifdef DEBUG_MXCC
840 dump_mxcc(env);
841 #endif
842 break;
843 case 3: /* MMU flush */
844 case 0x18: /* LEON3 MMU flush */
845 {
846 int mmulev;
847
848 mmulev = (addr >> 8) & 15;
849 DPRINTF_MMU("mmu flush level %d\n", mmulev);
850 switch (mmulev) {
851 case 0: /* flush page */
852 tlb_flush_page(CPU(cpu), addr & 0xfffff000);
853 break;
854 case 1: /* flush segment (256k) */
855 case 2: /* flush region (16M) */
856 case 3: /* flush context (4G) */
857 case 4: /* flush entire */
858 tlb_flush(CPU(cpu), 1);
859 break;
860 default:
861 break;
862 }
863 #ifdef DEBUG_MMU
864 dump_mmu(stdout, fprintf, env);
865 #endif
866 }
867 break;
868 case 4: /* write MMU regs */
869 case 0x19: /* LEON3 write MMU regs */
870 {
871 int reg = (addr >> 8) & 0x1f;
872 uint32_t oldreg;
873
874 oldreg = env->mmuregs[reg];
875 switch (reg) {
876 case 0: /* Control Register */
877 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
878 (val & 0x00ffffff);
879 /* Mappings generated during no-fault mode or MMU
880 disabled mode are invalid in normal mode */
881 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
882 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
883 tlb_flush(CPU(cpu), 1);
884 }
885 break;
886 case 1: /* Context Table Pointer Register */
887 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
888 break;
889 case 2: /* Context Register */
890 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
891 if (oldreg != env->mmuregs[reg]) {
892 /* we flush when the MMU context changes because
893 QEMU has no MMU context support */
894 tlb_flush(CPU(cpu), 1);
895 }
896 break;
897 case 3: /* Synchronous Fault Status Register with Clear */
898 case 4: /* Synchronous Fault Address Register */
899 break;
900 case 0x10: /* TLB Replacement Control Register */
901 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
902 break;
903 case 0x13: /* Synchronous Fault Status Register with Read
904 and Clear */
905 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
906 break;
907 case 0x14: /* Synchronous Fault Address Register */
908 env->mmuregs[4] = val;
909 break;
910 default:
911 env->mmuregs[reg] = val;
912 break;
913 }
914 if (oldreg != env->mmuregs[reg]) {
915 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
916 reg, oldreg, env->mmuregs[reg]);
917 }
918 #ifdef DEBUG_MMU
919 dump_mmu(stdout, fprintf, env);
920 #endif
921 }
922 break;
923 case 5: /* Turbosparc ITLB Diagnostic */
924 case 6: /* Turbosparc DTLB Diagnostic */
925 case 7: /* Turbosparc IOTLB Diagnostic */
926 break;
927 case 0xa: /* User data access */
928 switch (size) {
929 case 1:
930 cpu_stb_user(env, addr, val);
931 break;
932 case 2:
933 cpu_stw_user(env, addr, val);
934 break;
935 default:
936 case 4:
937 cpu_stl_user(env, addr, val);
938 break;
939 case 8:
940 cpu_stq_user(env, addr, val);
941 break;
942 }
943 break;
944 case 0xb: /* Supervisor data access */
945 case 0x80:
946 switch (size) {
947 case 1:
948 cpu_stb_kernel(env, addr, val);
949 break;
950 case 2:
951 cpu_stw_kernel(env, addr, val);
952 break;
953 default:
954 case 4:
955 cpu_stl_kernel(env, addr, val);
956 break;
957 case 8:
958 cpu_stq_kernel(env, addr, val);
959 break;
960 }
961 break;
962 case 0xc: /* I-cache tag */
963 case 0xd: /* I-cache data */
964 case 0xe: /* D-cache tag */
965 case 0xf: /* D-cache data */
966 case 0x10: /* I/D-cache flush page */
967 case 0x11: /* I/D-cache flush segment */
968 case 0x12: /* I/D-cache flush region */
969 case 0x13: /* I/D-cache flush context */
970 case 0x14: /* I/D-cache flush user */
971 break;
972 case 0x17: /* Block copy, sta access */
973 {
974 /* val = src
975 addr = dst
976 copy 32 bytes */
977 unsigned int i;
978 uint32_t src = val & ~3, dst = addr & ~3, temp;
979
980 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
981 temp = cpu_ldl_kernel(env, src);
982 cpu_stl_kernel(env, dst, temp);
983 }
984 }
985 break;
986 case 0x1f: /* Block fill, stda access */
987 {
988 /* addr = dst
989 fill 32 bytes with val */
990 unsigned int i;
991 uint32_t dst = addr & 7;
992
993 for (i = 0; i < 32; i += 8, dst += 8) {
994 cpu_stq_kernel(env, dst, val);
995 }
996 }
997 break;
998 case 0x20: /* MMU passthrough */
999 case 0x1c: /* LEON MMU passthrough */
1000 {
1001 switch (size) {
1002 case 1:
1003 stb_phys(cs->as, addr, val);
1004 break;
1005 case 2:
1006 stw_phys(cs->as, addr, val);
1007 break;
1008 case 4:
1009 default:
1010 stl_phys(cs->as, addr, val);
1011 break;
1012 case 8:
1013 stq_phys(cs->as, addr, val);
1014 break;
1015 }
1016 }
1017 break;
1018 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1019 {
1020 switch (size) {
1021 case 1:
1022 stb_phys(cs->as, (hwaddr)addr
1023 | ((hwaddr)(asi & 0xf) << 32), val);
1024 break;
1025 case 2:
1026 stw_phys(cs->as, (hwaddr)addr
1027 | ((hwaddr)(asi & 0xf) << 32), val);
1028 break;
1029 case 4:
1030 default:
1031 stl_phys(cs->as, (hwaddr)addr
1032 | ((hwaddr)(asi & 0xf) << 32), val);
1033 break;
1034 case 8:
1035 stq_phys(cs->as, (hwaddr)addr
1036 | ((hwaddr)(asi & 0xf) << 32), val);
1037 break;
1038 }
1039 }
1040 break;
1041 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1042 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1043 Turbosparc snoop RAM */
1044 case 0x32: /* store buffer control or Turbosparc page table
1045 descriptor diagnostic */
1046 case 0x36: /* I-cache flash clear */
1047 case 0x37: /* D-cache flash clear */
1048 break;
1049 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1050 {
1051 int reg = (addr >> 8) & 3;
1052
1053 switch (reg) {
1054 case 0: /* Breakpoint Value (Addr) */
1055 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1056 break;
1057 case 1: /* Breakpoint Mask */
1058 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1059 break;
1060 case 2: /* Breakpoint Control */
1061 env->mmubpregs[reg] = (val & 0x7fULL);
1062 break;
1063 case 3: /* Breakpoint Status */
1064 env->mmubpregs[reg] = (val & 0xfULL);
1065 break;
1066 }
1067 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1068 env->mmuregs[reg]);
1069 }
1070 break;
1071 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1072 env->mmubpctrv = val & 0xffffffff;
1073 break;
1074 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1075 env->mmubpctrc = val & 0x3;
1076 break;
1077 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1078 env->mmubpctrs = val & 0x3;
1079 break;
1080 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1081 env->mmubpaction = val & 0x1fff;
1082 break;
1083 case 8: /* User code access, XXX */
1084 case 9: /* Supervisor code access, XXX */
1085 default:
1086 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
1087 addr, true, false, asi, size);
1088 break;
1089 }
1090 #ifdef DEBUG_ASI
1091 dump_asi("write", addr, asi, size, val);
1092 #endif
1093 }
1094
1095 #endif /* CONFIG_USER_ONLY */
1096 #else /* TARGET_SPARC64 */
1097
1098 #ifdef CONFIG_USER_ONLY
1099 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1100 int sign)
1101 {
1102 uint64_t ret = 0;
1103 #if defined(DEBUG_ASI)
1104 target_ulong last_addr = addr;
1105 #endif
1106
1107 if (asi < 0x80) {
1108 helper_raise_exception(env, TT_PRIV_ACT);
1109 }
1110
1111 helper_check_align(env, addr, size - 1);
1112 addr = asi_address_mask(env, asi, addr);
1113
1114 switch (asi) {
1115 case 0x82: /* Primary no-fault */
1116 case 0x8a: /* Primary no-fault LE */
1117 if (page_check_range(addr, size, PAGE_READ) == -1) {
1118 #ifdef DEBUG_ASI
1119 dump_asi("read ", last_addr, asi, size, ret);
1120 #endif
1121 return 0;
1122 }
1123 /* Fall through */
1124 case 0x80: /* Primary */
1125 case 0x88: /* Primary LE */
1126 {
1127 switch (size) {
1128 case 1:
1129 ret = cpu_ldub_data(env, addr);
1130 break;
1131 case 2:
1132 ret = cpu_lduw_data(env, addr);
1133 break;
1134 case 4:
1135 ret = cpu_ldl_data(env, addr);
1136 break;
1137 default:
1138 case 8:
1139 ret = cpu_ldq_data(env, addr);
1140 break;
1141 }
1142 }
1143 break;
1144 case 0x83: /* Secondary no-fault */
1145 case 0x8b: /* Secondary no-fault LE */
1146 if (page_check_range(addr, size, PAGE_READ) == -1) {
1147 #ifdef DEBUG_ASI
1148 dump_asi("read ", last_addr, asi, size, ret);
1149 #endif
1150 return 0;
1151 }
1152 /* Fall through */
1153 case 0x81: /* Secondary */
1154 case 0x89: /* Secondary LE */
1155 /* XXX */
1156 break;
1157 default:
1158 break;
1159 }
1160
1161 /* Convert from little endian */
1162 switch (asi) {
1163 case 0x88: /* Primary LE */
1164 case 0x89: /* Secondary LE */
1165 case 0x8a: /* Primary no-fault LE */
1166 case 0x8b: /* Secondary no-fault LE */
1167 switch (size) {
1168 case 2:
1169 ret = bswap16(ret);
1170 break;
1171 case 4:
1172 ret = bswap32(ret);
1173 break;
1174 case 8:
1175 ret = bswap64(ret);
1176 break;
1177 default:
1178 break;
1179 }
1180 default:
1181 break;
1182 }
1183
1184 /* Convert to signed number */
1185 if (sign) {
1186 switch (size) {
1187 case 1:
1188 ret = (int8_t) ret;
1189 break;
1190 case 2:
1191 ret = (int16_t) ret;
1192 break;
1193 case 4:
1194 ret = (int32_t) ret;
1195 break;
1196 default:
1197 break;
1198 }
1199 }
1200 #ifdef DEBUG_ASI
1201 dump_asi("read ", last_addr, asi, size, ret);
1202 #endif
1203 return ret;
1204 }
1205
1206 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1207 int asi, int size)
1208 {
1209 #ifdef DEBUG_ASI
1210 dump_asi("write", addr, asi, size, val);
1211 #endif
1212 if (asi < 0x80) {
1213 helper_raise_exception(env, TT_PRIV_ACT);
1214 }
1215
1216 helper_check_align(env, addr, size - 1);
1217 addr = asi_address_mask(env, asi, addr);
1218
1219 /* Convert to little endian */
1220 switch (asi) {
1221 case 0x88: /* Primary LE */
1222 case 0x89: /* Secondary LE */
1223 switch (size) {
1224 case 2:
1225 val = bswap16(val);
1226 break;
1227 case 4:
1228 val = bswap32(val);
1229 break;
1230 case 8:
1231 val = bswap64(val);
1232 break;
1233 default:
1234 break;
1235 }
1236 default:
1237 break;
1238 }
1239
1240 switch (asi) {
1241 case 0x80: /* Primary */
1242 case 0x88: /* Primary LE */
1243 {
1244 switch (size) {
1245 case 1:
1246 cpu_stb_data(env, addr, val);
1247 break;
1248 case 2:
1249 cpu_stw_data(env, addr, val);
1250 break;
1251 case 4:
1252 cpu_stl_data(env, addr, val);
1253 break;
1254 case 8:
1255 default:
1256 cpu_stq_data(env, addr, val);
1257 break;
1258 }
1259 }
1260 break;
1261 case 0x81: /* Secondary */
1262 case 0x89: /* Secondary LE */
1263 /* XXX */
1264 return;
1265
1266 case 0x82: /* Primary no-fault, RO */
1267 case 0x83: /* Secondary no-fault, RO */
1268 case 0x8a: /* Primary no-fault LE, RO */
1269 case 0x8b: /* Secondary no-fault LE, RO */
1270 default:
1271 helper_raise_exception(env, TT_DATA_ACCESS);
1272 return;
1273 }
1274 }
1275
1276 #else /* CONFIG_USER_ONLY */
1277
1278 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1279 int sign)
1280 {
1281 CPUState *cs = CPU(sparc_env_get_cpu(env));
1282 uint64_t ret = 0;
1283 #if defined(DEBUG_ASI)
1284 target_ulong last_addr = addr;
1285 #endif
1286
1287 asi &= 0xff;
1288
1289 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1290 || (cpu_has_hypervisor(env)
1291 && asi >= 0x30 && asi < 0x80
1292 && !(env->hpstate & HS_PRIV))) {
1293 helper_raise_exception(env, TT_PRIV_ACT);
1294 }
1295
1296 helper_check_align(env, addr, size - 1);
1297 addr = asi_address_mask(env, asi, addr);
1298
1299 /* process nonfaulting loads first */
1300 if ((asi & 0xf6) == 0x82) {
1301 int mmu_idx;
1302
1303 /* secondary space access has lowest asi bit equal to 1 */
1304 if (env->pstate & PS_PRIV) {
1305 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1306 } else {
1307 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1308 }
1309
1310 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1311 #ifdef DEBUG_ASI
1312 dump_asi("read ", last_addr, asi, size, ret);
1313 #endif
1314 /* env->exception_index is set in get_physical_address_data(). */
1315 helper_raise_exception(env, cs->exception_index);
1316 }
1317
1318 /* convert nonfaulting load ASIs to normal load ASIs */
1319 asi &= ~0x02;
1320 }
1321
1322 switch (asi) {
1323 case 0x10: /* As if user primary */
1324 case 0x11: /* As if user secondary */
1325 case 0x18: /* As if user primary LE */
1326 case 0x19: /* As if user secondary LE */
1327 case 0x80: /* Primary */
1328 case 0x81: /* Secondary */
1329 case 0x88: /* Primary LE */
1330 case 0x89: /* Secondary LE */
1331 case 0xe2: /* UA2007 Primary block init */
1332 case 0xe3: /* UA2007 Secondary block init */
1333 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1334 if (cpu_hypervisor_mode(env)) {
1335 switch (size) {
1336 case 1:
1337 ret = cpu_ldub_hypv(env, addr);
1338 break;
1339 case 2:
1340 ret = cpu_lduw_hypv(env, addr);
1341 break;
1342 case 4:
1343 ret = cpu_ldl_hypv(env, addr);
1344 break;
1345 default:
1346 case 8:
1347 ret = cpu_ldq_hypv(env, addr);
1348 break;
1349 }
1350 } else {
1351 /* secondary space access has lowest asi bit equal to 1 */
1352 if (asi & 1) {
1353 switch (size) {
1354 case 1:
1355 ret = cpu_ldub_kernel_secondary(env, addr);
1356 break;
1357 case 2:
1358 ret = cpu_lduw_kernel_secondary(env, addr);
1359 break;
1360 case 4:
1361 ret = cpu_ldl_kernel_secondary(env, addr);
1362 break;
1363 default:
1364 case 8:
1365 ret = cpu_ldq_kernel_secondary(env, addr);
1366 break;
1367 }
1368 } else {
1369 switch (size) {
1370 case 1:
1371 ret = cpu_ldub_kernel(env, addr);
1372 break;
1373 case 2:
1374 ret = cpu_lduw_kernel(env, addr);
1375 break;
1376 case 4:
1377 ret = cpu_ldl_kernel(env, addr);
1378 break;
1379 default:
1380 case 8:
1381 ret = cpu_ldq_kernel(env, addr);
1382 break;
1383 }
1384 }
1385 }
1386 } else {
1387 /* secondary space access has lowest asi bit equal to 1 */
1388 if (asi & 1) {
1389 switch (size) {
1390 case 1:
1391 ret = cpu_ldub_user_secondary(env, addr);
1392 break;
1393 case 2:
1394 ret = cpu_lduw_user_secondary(env, addr);
1395 break;
1396 case 4:
1397 ret = cpu_ldl_user_secondary(env, addr);
1398 break;
1399 default:
1400 case 8:
1401 ret = cpu_ldq_user_secondary(env, addr);
1402 break;
1403 }
1404 } else {
1405 switch (size) {
1406 case 1:
1407 ret = cpu_ldub_user(env, addr);
1408 break;
1409 case 2:
1410 ret = cpu_lduw_user(env, addr);
1411 break;
1412 case 4:
1413 ret = cpu_ldl_user(env, addr);
1414 break;
1415 default:
1416 case 8:
1417 ret = cpu_ldq_user(env, addr);
1418 break;
1419 }
1420 }
1421 }
1422 break;
1423 case 0x14: /* Bypass */
1424 case 0x15: /* Bypass, non-cacheable */
1425 case 0x1c: /* Bypass LE */
1426 case 0x1d: /* Bypass, non-cacheable LE */
1427 {
1428 switch (size) {
1429 case 1:
1430 ret = ldub_phys(cs->as, addr);
1431 break;
1432 case 2:
1433 ret = lduw_phys(cs->as, addr);
1434 break;
1435 case 4:
1436 ret = ldl_phys(cs->as, addr);
1437 break;
1438 default:
1439 case 8:
1440 ret = ldq_phys(cs->as, addr);
1441 break;
1442 }
1443 break;
1444 }
1445 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1446 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1447 Only ldda allowed */
1448 helper_raise_exception(env, TT_ILL_INSN);
1449 return 0;
1450 case 0x04: /* Nucleus */
1451 case 0x0c: /* Nucleus Little Endian (LE) */
1452 {
1453 switch (size) {
1454 case 1:
1455 ret = cpu_ldub_nucleus(env, addr);
1456 break;
1457 case 2:
1458 ret = cpu_lduw_nucleus(env, addr);
1459 break;
1460 case 4:
1461 ret = cpu_ldl_nucleus(env, addr);
1462 break;
1463 default:
1464 case 8:
1465 ret = cpu_ldq_nucleus(env, addr);
1466 break;
1467 }
1468 break;
1469 }
1470 case 0x4a: /* UPA config */
1471 /* XXX */
1472 break;
1473 case 0x45: /* LSU */
1474 ret = env->lsu;
1475 break;
1476 case 0x50: /* I-MMU regs */
1477 {
1478 int reg = (addr >> 3) & 0xf;
1479
1480 if (reg == 0) {
1481 /* I-TSB Tag Target register */
1482 ret = ultrasparc_tag_target(env->immu.tag_access);
1483 } else {
1484 ret = env->immuregs[reg];
1485 }
1486
1487 break;
1488 }
1489 case 0x51: /* I-MMU 8k TSB pointer */
1490 {
1491 /* env->immuregs[5] holds I-MMU TSB register value
1492 env->immuregs[6] holds I-MMU Tag Access register value */
1493 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1494 8*1024);
1495 break;
1496 }
1497 case 0x52: /* I-MMU 64k TSB pointer */
1498 {
1499 /* env->immuregs[5] holds I-MMU TSB register value
1500 env->immuregs[6] holds I-MMU Tag Access register value */
1501 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1502 64*1024);
1503 break;
1504 }
1505 case 0x55: /* I-MMU data access */
1506 {
1507 int reg = (addr >> 3) & 0x3f;
1508
1509 ret = env->itlb[reg].tte;
1510 break;
1511 }
1512 case 0x56: /* I-MMU tag read */
1513 {
1514 int reg = (addr >> 3) & 0x3f;
1515
1516 ret = env->itlb[reg].tag;
1517 break;
1518 }
1519 case 0x58: /* D-MMU regs */
1520 {
1521 int reg = (addr >> 3) & 0xf;
1522
1523 if (reg == 0) {
1524 /* D-TSB Tag Target register */
1525 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1526 } else {
1527 ret = env->dmmuregs[reg];
1528 }
1529 break;
1530 }
1531 case 0x59: /* D-MMU 8k TSB pointer */
1532 {
1533 /* env->dmmuregs[5] holds D-MMU TSB register value
1534 env->dmmuregs[6] holds D-MMU Tag Access register value */
1535 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1536 8*1024);
1537 break;
1538 }
1539 case 0x5a: /* D-MMU 64k TSB pointer */
1540 {
1541 /* env->dmmuregs[5] holds D-MMU TSB register value
1542 env->dmmuregs[6] holds D-MMU Tag Access register value */
1543 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1544 64*1024);
1545 break;
1546 }
1547 case 0x5d: /* D-MMU data access */
1548 {
1549 int reg = (addr >> 3) & 0x3f;
1550
1551 ret = env->dtlb[reg].tte;
1552 break;
1553 }
1554 case 0x5e: /* D-MMU tag read */
1555 {
1556 int reg = (addr >> 3) & 0x3f;
1557
1558 ret = env->dtlb[reg].tag;
1559 break;
1560 }
1561 case 0x48: /* Interrupt dispatch, RO */
1562 break;
1563 case 0x49: /* Interrupt data receive */
1564 ret = env->ivec_status;
1565 break;
1566 case 0x7f: /* Incoming interrupt vector, RO */
1567 {
1568 int reg = (addr >> 4) & 0x3;
1569 if (reg < 3) {
1570 ret = env->ivec_data[reg];
1571 }
1572 break;
1573 }
1574 case 0x46: /* D-cache data */
1575 case 0x47: /* D-cache tag access */
1576 case 0x4b: /* E-cache error enable */
1577 case 0x4c: /* E-cache asynchronous fault status */
1578 case 0x4d: /* E-cache asynchronous fault address */
1579 case 0x4e: /* E-cache tag data */
1580 case 0x66: /* I-cache instruction access */
1581 case 0x67: /* I-cache tag access */
1582 case 0x6e: /* I-cache predecode */
1583 case 0x6f: /* I-cache LRU etc. */
1584 case 0x76: /* E-cache tag */
1585 case 0x7e: /* E-cache tag */
1586 break;
1587 case 0x5b: /* D-MMU data pointer */
1588 case 0x54: /* I-MMU data in, WO */
1589 case 0x57: /* I-MMU demap, WO */
1590 case 0x5c: /* D-MMU data in, WO */
1591 case 0x5f: /* D-MMU demap, WO */
1592 case 0x77: /* Interrupt vector, WO */
1593 default:
1594 cpu_unassigned_access(cs, addr, false, false, 1, size);
1595 ret = 0;
1596 break;
1597 }
1598
1599 /* Convert from little endian */
1600 switch (asi) {
1601 case 0x0c: /* Nucleus Little Endian (LE) */
1602 case 0x18: /* As if user primary LE */
1603 case 0x19: /* As if user secondary LE */
1604 case 0x1c: /* Bypass LE */
1605 case 0x1d: /* Bypass, non-cacheable LE */
1606 case 0x88: /* Primary LE */
1607 case 0x89: /* Secondary LE */
1608 switch(size) {
1609 case 2:
1610 ret = bswap16(ret);
1611 break;
1612 case 4:
1613 ret = bswap32(ret);
1614 break;
1615 case 8:
1616 ret = bswap64(ret);
1617 break;
1618 default:
1619 break;
1620 }
1621 default:
1622 break;
1623 }
1624
1625 /* Convert to signed number */
1626 if (sign) {
1627 switch (size) {
1628 case 1:
1629 ret = (int8_t) ret;
1630 break;
1631 case 2:
1632 ret = (int16_t) ret;
1633 break;
1634 case 4:
1635 ret = (int32_t) ret;
1636 break;
1637 default:
1638 break;
1639 }
1640 }
1641 #ifdef DEBUG_ASI
1642 dump_asi("read ", last_addr, asi, size, ret);
1643 #endif
1644 return ret;
1645 }
1646
1647 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1648 int asi, int size)
1649 {
1650 SPARCCPU *cpu = sparc_env_get_cpu(env);
1651 CPUState *cs = CPU(cpu);
1652
1653 #ifdef DEBUG_ASI
1654 dump_asi("write", addr, asi, size, val);
1655 #endif
1656
1657 asi &= 0xff;
1658
1659 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1660 || (cpu_has_hypervisor(env)
1661 && asi >= 0x30 && asi < 0x80
1662 && !(env->hpstate & HS_PRIV))) {
1663 helper_raise_exception(env, TT_PRIV_ACT);
1664 }
1665
1666 helper_check_align(env, addr, size - 1);
1667 addr = asi_address_mask(env, asi, addr);
1668
1669 /* Convert to little endian */
1670 switch (asi) {
1671 case 0x0c: /* Nucleus Little Endian (LE) */
1672 case 0x18: /* As if user primary LE */
1673 case 0x19: /* As if user secondary LE */
1674 case 0x1c: /* Bypass LE */
1675 case 0x1d: /* Bypass, non-cacheable LE */
1676 case 0x88: /* Primary LE */
1677 case 0x89: /* Secondary LE */
1678 switch (size) {
1679 case 2:
1680 val = bswap16(val);
1681 break;
1682 case 4:
1683 val = bswap32(val);
1684 break;
1685 case 8:
1686 val = bswap64(val);
1687 break;
1688 default:
1689 break;
1690 }
1691 default:
1692 break;
1693 }
1694
1695 switch (asi) {
1696 case 0x10: /* As if user primary */
1697 case 0x11: /* As if user secondary */
1698 case 0x18: /* As if user primary LE */
1699 case 0x19: /* As if user secondary LE */
1700 case 0x80: /* Primary */
1701 case 0x81: /* Secondary */
1702 case 0x88: /* Primary LE */
1703 case 0x89: /* Secondary LE */
1704 case 0xe2: /* UA2007 Primary block init */
1705 case 0xe3: /* UA2007 Secondary block init */
1706 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1707 if (cpu_hypervisor_mode(env)) {
1708 switch (size) {
1709 case 1:
1710 cpu_stb_hypv(env, addr, val);
1711 break;
1712 case 2:
1713 cpu_stw_hypv(env, addr, val);
1714 break;
1715 case 4:
1716 cpu_stl_hypv(env, addr, val);
1717 break;
1718 case 8:
1719 default:
1720 cpu_stq_hypv(env, addr, val);
1721 break;
1722 }
1723 } else {
1724 /* secondary space access has lowest asi bit equal to 1 */
1725 if (asi & 1) {
1726 switch (size) {
1727 case 1:
1728 cpu_stb_kernel_secondary(env, addr, val);
1729 break;
1730 case 2:
1731 cpu_stw_kernel_secondary(env, addr, val);
1732 break;
1733 case 4:
1734 cpu_stl_kernel_secondary(env, addr, val);
1735 break;
1736 case 8:
1737 default:
1738 cpu_stq_kernel_secondary(env, addr, val);
1739 break;
1740 }
1741 } else {
1742 switch (size) {
1743 case 1:
1744 cpu_stb_kernel(env, addr, val);
1745 break;
1746 case 2:
1747 cpu_stw_kernel(env, addr, val);
1748 break;
1749 case 4:
1750 cpu_stl_kernel(env, addr, val);
1751 break;
1752 case 8:
1753 default:
1754 cpu_stq_kernel(env, addr, val);
1755 break;
1756 }
1757 }
1758 }
1759 } else {
1760 /* secondary space access has lowest asi bit equal to 1 */
1761 if (asi & 1) {
1762 switch (size) {
1763 case 1:
1764 cpu_stb_user_secondary(env, addr, val);
1765 break;
1766 case 2:
1767 cpu_stw_user_secondary(env, addr, val);
1768 break;
1769 case 4:
1770 cpu_stl_user_secondary(env, addr, val);
1771 break;
1772 case 8:
1773 default:
1774 cpu_stq_user_secondary(env, addr, val);
1775 break;
1776 }
1777 } else {
1778 switch (size) {
1779 case 1:
1780 cpu_stb_user(env, addr, val);
1781 break;
1782 case 2:
1783 cpu_stw_user(env, addr, val);
1784 break;
1785 case 4:
1786 cpu_stl_user(env, addr, val);
1787 break;
1788 case 8:
1789 default:
1790 cpu_stq_user(env, addr, val);
1791 break;
1792 }
1793 }
1794 }
1795 break;
1796 case 0x14: /* Bypass */
1797 case 0x15: /* Bypass, non-cacheable */
1798 case 0x1c: /* Bypass LE */
1799 case 0x1d: /* Bypass, non-cacheable LE */
1800 {
1801 switch (size) {
1802 case 1:
1803 stb_phys(cs->as, addr, val);
1804 break;
1805 case 2:
1806 stw_phys(cs->as, addr, val);
1807 break;
1808 case 4:
1809 stl_phys(cs->as, addr, val);
1810 break;
1811 case 8:
1812 default:
1813 stq_phys(cs->as, addr, val);
1814 break;
1815 }
1816 }
1817 return;
1818 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1819 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1820 Only ldda allowed */
1821 helper_raise_exception(env, TT_ILL_INSN);
1822 return;
1823 case 0x04: /* Nucleus */
1824 case 0x0c: /* Nucleus Little Endian (LE) */
1825 {
1826 switch (size) {
1827 case 1:
1828 cpu_stb_nucleus(env, addr, val);
1829 break;
1830 case 2:
1831 cpu_stw_nucleus(env, addr, val);
1832 break;
1833 case 4:
1834 cpu_stl_nucleus(env, addr, val);
1835 break;
1836 default:
1837 case 8:
1838 cpu_stq_nucleus(env, addr, val);
1839 break;
1840 }
1841 break;
1842 }
1843
1844 case 0x4a: /* UPA config */
1845 /* XXX */
1846 return;
1847 case 0x45: /* LSU */
1848 {
1849 uint64_t oldreg;
1850
1851 oldreg = env->lsu;
1852 env->lsu = val & (DMMU_E | IMMU_E);
1853 /* Mappings generated during D/I MMU disabled mode are
1854 invalid in normal mode */
1855 if (oldreg != env->lsu) {
1856 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1857 oldreg, env->lsu);
1858 #ifdef DEBUG_MMU
1859 dump_mmu(stdout, fprintf, env);
1860 #endif
1861 tlb_flush(CPU(cpu), 1);
1862 }
1863 return;
1864 }
1865 case 0x50: /* I-MMU regs */
1866 {
1867 int reg = (addr >> 3) & 0xf;
1868 uint64_t oldreg;
1869
1870 oldreg = env->immuregs[reg];
1871 switch (reg) {
1872 case 0: /* RO */
1873 return;
1874 case 1: /* Not in I-MMU */
1875 case 2:
1876 return;
1877 case 3: /* SFSR */
1878 if ((val & 1) == 0) {
1879 val = 0; /* Clear SFSR */
1880 }
1881 env->immu.sfsr = val;
1882 break;
1883 case 4: /* RO */
1884 return;
1885 case 5: /* TSB access */
1886 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1887 PRIx64 "\n", env->immu.tsb, val);
1888 env->immu.tsb = val;
1889 break;
1890 case 6: /* Tag access */
1891 env->immu.tag_access = val;
1892 break;
1893 case 7:
1894 case 8:
1895 return;
1896 default:
1897 break;
1898 }
1899
1900 if (oldreg != env->immuregs[reg]) {
1901 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1902 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1903 }
1904 #ifdef DEBUG_MMU
1905 dump_mmu(stdout, fprintf, env);
1906 #endif
1907 return;
1908 }
1909 case 0x54: /* I-MMU data in */
1910 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1911 return;
1912 case 0x55: /* I-MMU data access */
1913 {
1914 /* TODO: auto demap */
1915
1916 unsigned int i = (addr >> 3) & 0x3f;
1917
1918 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1919
1920 #ifdef DEBUG_MMU
1921 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1922 dump_mmu(stdout, fprintf, env);
1923 #endif
1924 return;
1925 }
1926 case 0x57: /* I-MMU demap */
1927 demap_tlb(env->itlb, addr, "immu", env);
1928 return;
1929 case 0x58: /* D-MMU regs */
1930 {
1931 int reg = (addr >> 3) & 0xf;
1932 uint64_t oldreg;
1933
1934 oldreg = env->dmmuregs[reg];
1935 switch (reg) {
1936 case 0: /* RO */
1937 case 4:
1938 return;
1939 case 3: /* SFSR */
1940 if ((val & 1) == 0) {
1941 val = 0; /* Clear SFSR, Fault address */
1942 env->dmmu.sfar = 0;
1943 }
1944 env->dmmu.sfsr = val;
1945 break;
1946 case 1: /* Primary context */
1947 env->dmmu.mmu_primary_context = val;
1948 /* can be optimized to only flush MMU_USER_IDX
1949 and MMU_KERNEL_IDX entries */
1950 tlb_flush(CPU(cpu), 1);
1951 break;
1952 case 2: /* Secondary context */
1953 env->dmmu.mmu_secondary_context = val;
1954 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1955 and MMU_KERNEL_SECONDARY_IDX entries */
1956 tlb_flush(CPU(cpu), 1);
1957 break;
1958 case 5: /* TSB access */
1959 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1960 PRIx64 "\n", env->dmmu.tsb, val);
1961 env->dmmu.tsb = val;
1962 break;
1963 case 6: /* Tag access */
1964 env->dmmu.tag_access = val;
1965 break;
1966 case 7: /* Virtual Watchpoint */
1967 case 8: /* Physical Watchpoint */
1968 default:
1969 env->dmmuregs[reg] = val;
1970 break;
1971 }
1972
1973 if (oldreg != env->dmmuregs[reg]) {
1974 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1975 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1976 }
1977 #ifdef DEBUG_MMU
1978 dump_mmu(stdout, fprintf, env);
1979 #endif
1980 return;
1981 }
1982 case 0x5c: /* D-MMU data in */
1983 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1984 return;
1985 case 0x5d: /* D-MMU data access */
1986 {
1987 unsigned int i = (addr >> 3) & 0x3f;
1988
1989 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
1990
1991 #ifdef DEBUG_MMU
1992 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1993 dump_mmu(stdout, fprintf, env);
1994 #endif
1995 return;
1996 }
1997 case 0x5f: /* D-MMU demap */
1998 demap_tlb(env->dtlb, addr, "dmmu", env);
1999 return;
2000 case 0x49: /* Interrupt data receive */
2001 env->ivec_status = val & 0x20;
2002 return;
2003 case 0x46: /* D-cache data */
2004 case 0x47: /* D-cache tag access */
2005 case 0x4b: /* E-cache error enable */
2006 case 0x4c: /* E-cache asynchronous fault status */
2007 case 0x4d: /* E-cache asynchronous fault address */
2008 case 0x4e: /* E-cache tag data */
2009 case 0x66: /* I-cache instruction access */
2010 case 0x67: /* I-cache tag access */
2011 case 0x6e: /* I-cache predecode */
2012 case 0x6f: /* I-cache LRU etc. */
2013 case 0x76: /* E-cache tag */
2014 case 0x7e: /* E-cache tag */
2015 return;
2016 case 0x51: /* I-MMU 8k TSB pointer, RO */
2017 case 0x52: /* I-MMU 64k TSB pointer, RO */
2018 case 0x56: /* I-MMU tag read, RO */
2019 case 0x59: /* D-MMU 8k TSB pointer, RO */
2020 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2021 case 0x5b: /* D-MMU data pointer, RO */
2022 case 0x5e: /* D-MMU tag read, RO */
2023 case 0x48: /* Interrupt dispatch, RO */
2024 case 0x7f: /* Incoming interrupt vector, RO */
2025 case 0x82: /* Primary no-fault, RO */
2026 case 0x83: /* Secondary no-fault, RO */
2027 case 0x8a: /* Primary no-fault LE, RO */
2028 case 0x8b: /* Secondary no-fault LE, RO */
2029 default:
2030 cpu_unassigned_access(cs, addr, true, false, 1, size);
2031 return;
2032 }
2033 }
2034 #endif /* CONFIG_USER_ONLY */
2035
2036 void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd)
2037 {
2038 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2039 || (cpu_has_hypervisor(env)
2040 && asi >= 0x30 && asi < 0x80
2041 && !(env->hpstate & HS_PRIV))) {
2042 helper_raise_exception(env, TT_PRIV_ACT);
2043 }
2044
2045 addr = asi_address_mask(env, asi, addr);
2046
2047 switch (asi) {
2048 #if !defined(CONFIG_USER_ONLY)
2049 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2050 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2051 helper_check_align(env, addr, 0xf);
2052 if (rd == 0) {
2053 env->gregs[1] = cpu_ldq_nucleus(env, addr + 8);
2054 if (asi == 0x2c) {
2055 bswap64s(&env->gregs[1]);
2056 }
2057 } else if (rd < 8) {
2058 env->gregs[rd] = cpu_ldq_nucleus(env, addr);
2059 env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2060 if (asi == 0x2c) {
2061 bswap64s(&env->gregs[rd]);
2062 bswap64s(&env->gregs[rd + 1]);
2063 }
2064 } else {
2065 env->regwptr[rd] = cpu_ldq_nucleus(env, addr);
2066 env->regwptr[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2067 if (asi == 0x2c) {
2068 bswap64s(&env->regwptr[rd]);
2069 bswap64s(&env->regwptr[rd + 1]);
2070 }
2071 }
2072 break;
2073 #endif
2074 default:
2075 helper_check_align(env, addr, 0x3);
2076 if (rd == 0) {
2077 env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2078 } else if (rd < 8) {
2079 env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2080 env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2081 } else {
2082 env->regwptr[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2083 env->regwptr[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2084 }
2085 break;
2086 }
2087 }
2088
2089 void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2090 int rd)
2091 {
2092 unsigned int i;
2093 target_ulong val;
2094
2095 helper_check_align(env, addr, 3);
2096 addr = asi_address_mask(env, asi, addr);
2097
2098 switch (asi) {
2099 case 0xf0: /* UA2007/JPS1 Block load primary */
2100 case 0xf1: /* UA2007/JPS1 Block load secondary */
2101 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2102 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2103 if (rd & 7) {
2104 helper_raise_exception(env, TT_ILL_INSN);
2105 return;
2106 }
2107 helper_check_align(env, addr, 0x3f);
2108 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2109 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
2110 }
2111 return;
2112
2113 case 0x16: /* UA2007 Block load primary, user privilege */
2114 case 0x17: /* UA2007 Block load secondary, user privilege */
2115 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2116 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2117 case 0x70: /* JPS1 Block load primary, user privilege */
2118 case 0x71: /* JPS1 Block load secondary, user privilege */
2119 case 0x78: /* JPS1 Block load primary LE, user privilege */
2120 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2121 if (rd & 7) {
2122 helper_raise_exception(env, TT_ILL_INSN);
2123 return;
2124 }
2125 helper_check_align(env, addr, 0x3f);
2126 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2127 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
2128 }
2129 return;
2130
2131 default:
2132 break;
2133 }
2134
2135 switch (size) {
2136 default:
2137 case 4:
2138 val = helper_ld_asi(env, addr, asi, size, 0);
2139 if (rd & 1) {
2140 env->fpr[rd / 2].l.lower = val;
2141 } else {
2142 env->fpr[rd / 2].l.upper = val;
2143 }
2144 break;
2145 case 8:
2146 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
2147 break;
2148 case 16:
2149 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
2150 env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
2151 break;
2152 }
2153 }
2154
2155 void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2156 int rd)
2157 {
2158 unsigned int i;
2159 target_ulong val;
2160
2161 addr = asi_address_mask(env, asi, addr);
2162
2163 switch (asi) {
2164 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2165 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2166 case 0xf0: /* UA2007/JPS1 Block store primary */
2167 case 0xf1: /* UA2007/JPS1 Block store secondary */
2168 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2169 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2170 if (rd & 7) {
2171 helper_raise_exception(env, TT_ILL_INSN);
2172 return;
2173 }
2174 helper_check_align(env, addr, 0x3f);
2175 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2176 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
2177 }
2178
2179 return;
2180 case 0x16: /* UA2007 Block load primary, user privilege */
2181 case 0x17: /* UA2007 Block load secondary, user privilege */
2182 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2183 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2184 case 0x70: /* JPS1 Block store primary, user privilege */
2185 case 0x71: /* JPS1 Block store secondary, user privilege */
2186 case 0x78: /* JPS1 Block load primary LE, user privilege */
2187 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2188 if (rd & 7) {
2189 helper_raise_exception(env, TT_ILL_INSN);
2190 return;
2191 }
2192 helper_check_align(env, addr, 0x3f);
2193 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2194 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
2195 }
2196
2197 return;
2198 case 0xd2: /* 16-bit floating point load primary */
2199 case 0xd3: /* 16-bit floating point load secondary */
2200 case 0xda: /* 16-bit floating point load primary, LE */
2201 case 0xdb: /* 16-bit floating point load secondary, LE */
2202 helper_check_align(env, addr, 1);
2203 /* Fall through */
2204 case 0xd0: /* 8-bit floating point load primary */
2205 case 0xd1: /* 8-bit floating point load secondary */
2206 case 0xd8: /* 8-bit floating point load primary, LE */
2207 case 0xd9: /* 8-bit floating point load secondary, LE */
2208 val = env->fpr[rd / 2].l.lower;
2209 helper_st_asi(env, addr, val, asi & 0x8d, ((asi & 2) >> 1) + 1);
2210 return;
2211 default:
2212 helper_check_align(env, addr, 3);
2213 break;
2214 }
2215
2216 switch (size) {
2217 default:
2218 case 4:
2219 if (rd & 1) {
2220 val = env->fpr[rd / 2].l.lower;
2221 } else {
2222 val = env->fpr[rd / 2].l.upper;
2223 }
2224 helper_st_asi(env, addr, val, asi, size);
2225 break;
2226 case 8:
2227 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
2228 break;
2229 case 16:
2230 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
2231 helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
2232 break;
2233 }
2234 }
2235
2236 target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
2237 target_ulong val1, target_ulong val2,
2238 uint32_t asi)
2239 {
2240 target_ulong ret;
2241
2242 ret = helper_ld_asi(env, addr, asi, 8, 0);
2243 if (val2 == ret) {
2244 helper_st_asi(env, addr, val1, asi, 8);
2245 }
2246 return ret;
2247 }
2248 #endif /* TARGET_SPARC64 */
2249
2250 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2251 target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
2252 target_ulong val1, target_ulong val2, uint32_t asi)
2253 {
2254 target_ulong ret;
2255
2256 val2 &= 0xffffffffUL;
2257 ret = helper_ld_asi(env, addr, asi, 4, 0);
2258 ret &= 0xffffffffUL;
2259 if (val2 == ret) {
2260 helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
2261 }
2262 return ret;
2263 }
2264 #endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
2265
2266 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2267 {
2268 /* XXX add 128 bit load */
2269 CPU_QuadU u;
2270
2271 helper_check_align(env, addr, 7);
2272 #if !defined(CONFIG_USER_ONLY)
2273 switch (mem_idx) {
2274 case MMU_USER_IDX:
2275 u.ll.upper = cpu_ldq_user(env, addr);
2276 u.ll.lower = cpu_ldq_user(env, addr + 8);
2277 QT0 = u.q;
2278 break;
2279 case MMU_KERNEL_IDX:
2280 u.ll.upper = cpu_ldq_kernel(env, addr);
2281 u.ll.lower = cpu_ldq_kernel(env, addr + 8);
2282 QT0 = u.q;
2283 break;
2284 #ifdef TARGET_SPARC64
2285 case MMU_HYPV_IDX:
2286 u.ll.upper = cpu_ldq_hypv(env, addr);
2287 u.ll.lower = cpu_ldq_hypv(env, addr + 8);
2288 QT0 = u.q;
2289 break;
2290 #endif
2291 default:
2292 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2293 break;
2294 }
2295 #else
2296 u.ll.upper = cpu_ldq_data(env, address_mask(env, addr));
2297 u.ll.lower = cpu_ldq_data(env, address_mask(env, addr + 8));
2298 QT0 = u.q;
2299 #endif
2300 }
2301
2302 void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2303 {
2304 /* XXX add 128 bit store */
2305 CPU_QuadU u;
2306
2307 helper_check_align(env, addr, 7);
2308 #if !defined(CONFIG_USER_ONLY)
2309 switch (mem_idx) {
2310 case MMU_USER_IDX:
2311 u.q = QT0;
2312 cpu_stq_user(env, addr, u.ll.upper);
2313 cpu_stq_user(env, addr + 8, u.ll.lower);
2314 break;
2315 case MMU_KERNEL_IDX:
2316 u.q = QT0;
2317 cpu_stq_kernel(env, addr, u.ll.upper);
2318 cpu_stq_kernel(env, addr + 8, u.ll.lower);
2319 break;
2320 #ifdef TARGET_SPARC64
2321 case MMU_HYPV_IDX:
2322 u.q = QT0;
2323 cpu_stq_hypv(env, addr, u.ll.upper);
2324 cpu_stq_hypv(env, addr + 8, u.ll.lower);
2325 break;
2326 #endif
2327 default:
2328 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2329 break;
2330 }
2331 #else
2332 u.q = QT0;
2333 cpu_stq_data(env, address_mask(env, addr), u.ll.upper);
2334 cpu_stq_data(env, address_mask(env, addr + 8), u.ll.lower);
2335 #endif
2336 }
2337
2338 #if !defined(CONFIG_USER_ONLY)
2339 #ifndef TARGET_SPARC64
2340 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2341 bool is_write, bool is_exec, int is_asi,
2342 unsigned size)
2343 {
2344 SPARCCPU *cpu = SPARC_CPU(cs);
2345 CPUSPARCState *env = &cpu->env;
2346 int fault_type;
2347
2348 #ifdef DEBUG_UNASSIGNED
2349 if (is_asi) {
2350 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2351 " asi 0x%02x from " TARGET_FMT_lx "\n",
2352 is_exec ? "exec" : is_write ? "write" : "read", size,
2353 size == 1 ? "" : "s", addr, is_asi, env->pc);
2354 } else {
2355 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2356 " from " TARGET_FMT_lx "\n",
2357 is_exec ? "exec" : is_write ? "write" : "read", size,
2358 size == 1 ? "" : "s", addr, env->pc);
2359 }
2360 #endif
2361 /* Don't overwrite translation and access faults */
2362 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2363 if ((fault_type > 4) || (fault_type == 0)) {
2364 env->mmuregs[3] = 0; /* Fault status register */
2365 if (is_asi) {
2366 env->mmuregs[3] |= 1 << 16;
2367 }
2368 if (env->psrs) {
2369 env->mmuregs[3] |= 1 << 5;
2370 }
2371 if (is_exec) {
2372 env->mmuregs[3] |= 1 << 6;
2373 }
2374 if (is_write) {
2375 env->mmuregs[3] |= 1 << 7;
2376 }
2377 env->mmuregs[3] |= (5 << 2) | 2;
2378 /* SuperSPARC will never place instruction fault addresses in the FAR */
2379 if (!is_exec) {
2380 env->mmuregs[4] = addr; /* Fault address register */
2381 }
2382 }
2383 /* overflow (same type fault was not read before another fault) */
2384 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2385 env->mmuregs[3] |= 1;
2386 }
2387
2388 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2389 if (is_exec) {
2390 helper_raise_exception(env, TT_CODE_ACCESS);
2391 } else {
2392 helper_raise_exception(env, TT_DATA_ACCESS);
2393 }
2394 }
2395
2396 /* flush neverland mappings created during no-fault mode,
2397 so the sequential MMU faults report proper fault types */
2398 if (env->mmuregs[0] & MMU_NF) {
2399 tlb_flush(cs, 1);
2400 }
2401 }
2402 #else
2403 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2404 bool is_write, bool is_exec, int is_asi,
2405 unsigned size)
2406 {
2407 SPARCCPU *cpu = SPARC_CPU(cs);
2408 CPUSPARCState *env = &cpu->env;
2409
2410 #ifdef DEBUG_UNASSIGNED
2411 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2412 "\n", addr, env->pc);
2413 #endif
2414
2415 if (is_exec) {
2416 helper_raise_exception(env, TT_CODE_ACCESS);
2417 } else {
2418 helper_raise_exception(env, TT_DATA_ACCESS);
2419 }
2420 }
2421 #endif
2422 #endif
2423
2424 #if !defined(CONFIG_USER_ONLY)
2425 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs,
2426 vaddr addr, int is_write,
2427 int is_user, uintptr_t retaddr)
2428 {
2429 SPARCCPU *cpu = SPARC_CPU(cs);
2430 CPUSPARCState *env = &cpu->env;
2431
2432 #ifdef DEBUG_UNALIGNED
2433 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2434 "\n", addr, env->pc);
2435 #endif
2436 if (retaddr) {
2437 cpu_restore_state(CPU(cpu), retaddr);
2438 }
2439 helper_raise_exception(env, TT_UNALIGNED);
2440 }
2441
2442 /* try to fill the TLB and return an exception if error. If retaddr is
2443 NULL, it means that the function was called in C code (i.e. not
2444 from generated code or from helper.c) */
2445 /* XXX: fix it to restore all registers */
2446 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2447 uintptr_t retaddr)
2448 {
2449 int ret;
2450
2451 ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2452 if (ret) {
2453 if (retaddr) {
2454 cpu_restore_state(cs, retaddr);
2455 }
2456 cpu_loop_exit(cs);
2457 }
2458 }
2459 #endif
QEmu