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target-i386: Fix compiler warning
[qemu.git] / target-i386 / translate.c
blob307aabdd3026712c56bb2a8e049b39c1c88433c3
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30
31 #include "helper.h"
32 #define GEN_HELPER 1
33 #include "helper.h"
34
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
40
41 #ifdef TARGET_X86_64
42 #define X86_64_ONLY(x) x
43 #define X86_64_DEF(...) __VA_ARGS__
44 #define CODE64(s) ((s)->code64)
45 #define REX_X(s) ((s)->rex_x)
46 #define REX_B(s) ((s)->rex_b)
47 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
48 #if 1
49 #define BUGGY_64(x) NULL
50 #endif
51 #else
52 #define X86_64_ONLY(x) NULL
53 #define X86_64_DEF(...)
54 #define CODE64(s) 0
55 #define REX_X(s) 0
56 #define REX_B(s) 0
57 #endif
58
59 //#define MACRO_TEST 1
60
61 /* global register indexes */
62 static TCGv_ptr cpu_env;
63 static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
64 static TCGv_i32 cpu_cc_op;
65 static TCGv cpu_regs[CPU_NB_REGS];
66 /* local temps */
67 static TCGv cpu_T[2], cpu_T3;
68 /* local register indexes (only used inside old micro ops) */
69 static TCGv cpu_tmp0, cpu_tmp4;
70 static TCGv_ptr cpu_ptr0, cpu_ptr1;
71 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
72 static TCGv_i64 cpu_tmp1_i64;
73 static TCGv cpu_tmp5;
74
75 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
76
77 #include "gen-icount.h"
78
79 #ifdef TARGET_X86_64
80 static int x86_64_hregs;
81 #endif
82
83 typedef struct DisasContext {
84 /* current insn context */
85 int override; /* -1 if no override */
86 int prefix;
87 int aflag, dflag;
88 target_ulong pc; /* pc = eip + cs_base */
89 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
90 static state change (stop translation) */
91 /* current block context */
92 target_ulong cs_base; /* base of CS segment */
93 int pe; /* protected mode */
94 int code32; /* 32 bit code segment */
95 #ifdef TARGET_X86_64
96 int lma; /* long mode active */
97 int code64; /* 64 bit code segment */
98 int rex_x, rex_b;
99 #endif
100 int ss32; /* 32 bit stack segment */
101 int cc_op; /* current CC operation */
102 int addseg; /* non zero if either DS/ES/SS have a non zero base */
103 int f_st; /* currently unused */
104 int vm86; /* vm86 mode */
105 int cpl;
106 int iopl;
107 int tf; /* TF cpu flag */
108 int singlestep_enabled; /* "hardware" single step enabled */
109 int jmp_opt; /* use direct block chaining for direct jumps */
110 int mem_index; /* select memory access functions */
111 uint64_t flags; /* all execution flags */
112 struct TranslationBlock *tb;
113 int popl_esp_hack; /* for correct popl with esp base handling */
114 int rip_offset; /* only used in x86_64, but left for simplicity */
115 int cpuid_features;
116 int cpuid_ext_features;
117 int cpuid_ext2_features;
118 int cpuid_ext3_features;
119 } DisasContext;
120
121 static void gen_eob(DisasContext *s);
122 static void gen_jmp(DisasContext *s, target_ulong eip);
123 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
124
125 /* i386 arith/logic operations */
126 enum {
127 OP_ADDL,
128 OP_ORL,
129 OP_ADCL,
130 OP_SBBL,
131 OP_ANDL,
132 OP_SUBL,
133 OP_XORL,
134 OP_CMPL,
135 };
136
137 /* i386 shift ops */
138 enum {
139 OP_ROL,
140 OP_ROR,
141 OP_RCL,
142 OP_RCR,
143 OP_SHL,
144 OP_SHR,
145 OP_SHL1, /* undocumented */
146 OP_SAR = 7,
147 };
148
149 enum {
150 JCC_O,
151 JCC_B,
152 JCC_Z,
153 JCC_BE,
154 JCC_S,
155 JCC_P,
156 JCC_L,
157 JCC_LE,
158 };
159
160 /* operand size */
161 enum {
162 OT_BYTE = 0,
163 OT_WORD,
164 OT_LONG,
165 OT_QUAD,
166 };
167
168 enum {
169 /* I386 int registers */
170 OR_EAX, /* MUST be even numbered */
171 OR_ECX,
172 OR_EDX,
173 OR_EBX,
174 OR_ESP,
175 OR_EBP,
176 OR_ESI,
177 OR_EDI,
178
179 OR_TMP0 = 16, /* temporary operand register */
180 OR_TMP1,
181 OR_A0, /* temporary register used when doing address evaluation */
182 };
183
184 static inline void gen_op_movl_T0_0(void)
185 {
186 tcg_gen_movi_tl(cpu_T[0], 0);
187 }
188
189 static inline void gen_op_movl_T0_im(int32_t val)
190 {
191 tcg_gen_movi_tl(cpu_T[0], val);
192 }
193
194 static inline void gen_op_movl_T0_imu(uint32_t val)
195 {
196 tcg_gen_movi_tl(cpu_T[0], val);
197 }
198
199 static inline void gen_op_movl_T1_im(int32_t val)
200 {
201 tcg_gen_movi_tl(cpu_T[1], val);
202 }
203
204 static inline void gen_op_movl_T1_imu(uint32_t val)
205 {
206 tcg_gen_movi_tl(cpu_T[1], val);
207 }
208
209 static inline void gen_op_movl_A0_im(uint32_t val)
210 {
211 tcg_gen_movi_tl(cpu_A0, val);
212 }
213
214 #ifdef TARGET_X86_64
215 static inline void gen_op_movq_A0_im(int64_t val)
216 {
217 tcg_gen_movi_tl(cpu_A0, val);
218 }
219 #endif
220
221 static inline void gen_movtl_T0_im(target_ulong val)
222 {
223 tcg_gen_movi_tl(cpu_T[0], val);
224 }
225
226 static inline void gen_movtl_T1_im(target_ulong val)
227 {
228 tcg_gen_movi_tl(cpu_T[1], val);
229 }
230
231 static inline void gen_op_andl_T0_ffff(void)
232 {
233 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
234 }
235
236 static inline void gen_op_andl_T0_im(uint32_t val)
237 {
238 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
239 }
240
241 static inline void gen_op_movl_T0_T1(void)
242 {
243 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
244 }
245
246 static inline void gen_op_andl_A0_ffff(void)
247 {
248 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
249 }
250
251 #ifdef TARGET_X86_64
252
253 #define NB_OP_SIZES 4
254
255 #else /* !TARGET_X86_64 */
256
257 #define NB_OP_SIZES 3
258
259 #endif /* !TARGET_X86_64 */
260
261 #if defined(HOST_WORDS_BIGENDIAN)
262 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
263 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
264 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
265 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
266 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
267 #else
268 #define REG_B_OFFSET 0
269 #define REG_H_OFFSET 1
270 #define REG_W_OFFSET 0
271 #define REG_L_OFFSET 0
272 #define REG_LH_OFFSET 4
273 #endif
274
275 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
276 {
277 TCGv tmp;
278
279 switch(ot) {
280 case OT_BYTE:
281 tmp = tcg_temp_new();
282 tcg_gen_ext8u_tl(tmp, t0);
283 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
284 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xff);
285 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
286 } else {
287 tcg_gen_shli_tl(tmp, tmp, 8);
288 tcg_gen_andi_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], ~0xff00);
289 tcg_gen_or_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], tmp);
290 }
291 tcg_temp_free(tmp);
292 break;
293 case OT_WORD:
294 tmp = tcg_temp_new();
295 tcg_gen_ext16u_tl(tmp, t0);
296 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
297 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
298 tcg_temp_free(tmp);
299 break;
300 default: /* XXX this shouldn't be reached; abort? */
301 case OT_LONG:
302 /* For x86_64, this sets the higher half of register to zero.
303 For i386, this is equivalent to a mov. */
304 tcg_gen_ext32u_tl(cpu_regs[reg], t0);
305 break;
306 #ifdef TARGET_X86_64
307 case OT_QUAD:
308 tcg_gen_mov_tl(cpu_regs[reg], t0);
309 break;
310 #endif
311 }
312 }
313
314 static inline void gen_op_mov_reg_T0(int ot, int reg)
315 {
316 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
317 }
318
319 static inline void gen_op_mov_reg_T1(int ot, int reg)
320 {
321 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
322 }
323
324 static inline void gen_op_mov_reg_A0(int size, int reg)
325 {
326 TCGv tmp;
327
328 switch(size) {
329 case 0:
330 tmp = tcg_temp_new();
331 tcg_gen_ext16u_tl(tmp, cpu_A0);
332 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
333 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
334 tcg_temp_free(tmp);
335 break;
336 default: /* XXX this shouldn't be reached; abort? */
337 case 1:
338 /* For x86_64, this sets the higher half of register to zero.
339 For i386, this is equivalent to a mov. */
340 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
341 break;
342 #ifdef TARGET_X86_64
343 case 2:
344 tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
345 break;
346 #endif
347 }
348 }
349
350 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
351 {
352 switch(ot) {
353 case OT_BYTE:
354 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
355 goto std_case;
356 } else {
357 tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
358 tcg_gen_ext8u_tl(t0, t0);
359 }
360 break;
361 default:
362 std_case:
363 tcg_gen_mov_tl(t0, cpu_regs[reg]);
364 break;
365 }
366 }
367
368 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
369 {
370 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
371 }
372
373 static inline void gen_op_movl_A0_reg(int reg)
374 {
375 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
376 }
377
378 static inline void gen_op_addl_A0_im(int32_t val)
379 {
380 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
381 #ifdef TARGET_X86_64
382 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
383 #endif
384 }
385
386 #ifdef TARGET_X86_64
387 static inline void gen_op_addq_A0_im(int64_t val)
388 {
389 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
390 }
391 #endif
392
393 static void gen_add_A0_im(DisasContext *s, int val)
394 {
395 #ifdef TARGET_X86_64
396 if (CODE64(s))
397 gen_op_addq_A0_im(val);
398 else
399 #endif
400 gen_op_addl_A0_im(val);
401 }
402
403 static inline void gen_op_addl_T0_T1(void)
404 {
405 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
406 }
407
408 static inline void gen_op_jmp_T0(void)
409 {
410 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
411 }
412
413 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
414 {
415 switch(size) {
416 case 0:
417 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
418 tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
419 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
420 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
421 break;
422 case 1:
423 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
424 /* For x86_64, this sets the higher half of register to zero.
425 For i386, this is equivalent to a nop. */
426 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
427 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
428 break;
429 #ifdef TARGET_X86_64
430 case 2:
431 tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
432 break;
433 #endif
434 }
435 }
436
437 static inline void gen_op_add_reg_T0(int size, int reg)
438 {
439 switch(size) {
440 case 0:
441 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
442 tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
443 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
444 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
445 break;
446 case 1:
447 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
448 /* For x86_64, this sets the higher half of register to zero.
449 For i386, this is equivalent to a nop. */
450 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
451 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
452 break;
453 #ifdef TARGET_X86_64
454 case 2:
455 tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
456 break;
457 #endif
458 }
459 }
460
461 static inline void gen_op_set_cc_op(int32_t val)
462 {
463 tcg_gen_movi_i32(cpu_cc_op, val);
464 }
465
466 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
467 {
468 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
469 if (shift != 0)
470 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
471 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
472 /* For x86_64, this sets the higher half of register to zero.
473 For i386, this is equivalent to a nop. */
474 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
475 }
476
477 static inline void gen_op_movl_A0_seg(int reg)
478 {
479 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
480 }
481
482 static inline void gen_op_addl_A0_seg(int reg)
483 {
484 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
485 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
486 #ifdef TARGET_X86_64
487 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
488 #endif
489 }
490
491 #ifdef TARGET_X86_64
492 static inline void gen_op_movq_A0_seg(int reg)
493 {
494 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
495 }
496
497 static inline void gen_op_addq_A0_seg(int reg)
498 {
499 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
500 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
501 }
502
503 static inline void gen_op_movq_A0_reg(int reg)
504 {
505 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
506 }
507
508 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
509 {
510 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
511 if (shift != 0)
512 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
513 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
514 }
515 #endif
516
517 static inline void gen_op_lds_T0_A0(int idx)
518 {
519 int mem_index = (idx >> 2) - 1;
520 switch(idx & 3) {
521 case 0:
522 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
523 break;
524 case 1:
525 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
526 break;
527 default:
528 case 2:
529 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
530 break;
531 }
532 }
533
534 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
535 {
536 int mem_index = (idx >> 2) - 1;
537 switch(idx & 3) {
538 case 0:
539 tcg_gen_qemu_ld8u(t0, a0, mem_index);
540 break;
541 case 1:
542 tcg_gen_qemu_ld16u(t0, a0, mem_index);
543 break;
544 case 2:
545 tcg_gen_qemu_ld32u(t0, a0, mem_index);
546 break;
547 default:
548 case 3:
549 /* Should never happen on 32-bit targets. */
550 #ifdef TARGET_X86_64
551 tcg_gen_qemu_ld64(t0, a0, mem_index);
552 #endif
553 break;
554 }
555 }
556
557 /* XXX: always use ldu or lds */
558 static inline void gen_op_ld_T0_A0(int idx)
559 {
560 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
561 }
562
563 static inline void gen_op_ldu_T0_A0(int idx)
564 {
565 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
566 }
567
568 static inline void gen_op_ld_T1_A0(int idx)
569 {
570 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
571 }
572
573 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
574 {
575 int mem_index = (idx >> 2) - 1;
576 switch(idx & 3) {
577 case 0:
578 tcg_gen_qemu_st8(t0, a0, mem_index);
579 break;
580 case 1:
581 tcg_gen_qemu_st16(t0, a0, mem_index);
582 break;
583 case 2:
584 tcg_gen_qemu_st32(t0, a0, mem_index);
585 break;
586 default:
587 case 3:
588 /* Should never happen on 32-bit targets. */
589 #ifdef TARGET_X86_64
590 tcg_gen_qemu_st64(t0, a0, mem_index);
591 #endif
592 break;
593 }
594 }
595
596 static inline void gen_op_st_T0_A0(int idx)
597 {
598 gen_op_st_v(idx, cpu_T[0], cpu_A0);
599 }
600
601 static inline void gen_op_st_T1_A0(int idx)
602 {
603 gen_op_st_v(idx, cpu_T[1], cpu_A0);
604 }
605
606 static inline void gen_jmp_im(target_ulong pc)
607 {
608 tcg_gen_movi_tl(cpu_tmp0, pc);
609 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
610 }
611
612 static inline void gen_string_movl_A0_ESI(DisasContext *s)
613 {
614 int override;
615
616 override = s->override;
617 #ifdef TARGET_X86_64
618 if (s->aflag == 2) {
619 if (override >= 0) {
620 gen_op_movq_A0_seg(override);
621 gen_op_addq_A0_reg_sN(0, R_ESI);
622 } else {
623 gen_op_movq_A0_reg(R_ESI);
624 }
625 } else
626 #endif
627 if (s->aflag) {
628 /* 32 bit address */
629 if (s->addseg && override < 0)
630 override = R_DS;
631 if (override >= 0) {
632 gen_op_movl_A0_seg(override);
633 gen_op_addl_A0_reg_sN(0, R_ESI);
634 } else {
635 gen_op_movl_A0_reg(R_ESI);
636 }
637 } else {
638 /* 16 address, always override */
639 if (override < 0)
640 override = R_DS;
641 gen_op_movl_A0_reg(R_ESI);
642 gen_op_andl_A0_ffff();
643 gen_op_addl_A0_seg(override);
644 }
645 }
646
647 static inline void gen_string_movl_A0_EDI(DisasContext *s)
648 {
649 #ifdef TARGET_X86_64
650 if (s->aflag == 2) {
651 gen_op_movq_A0_reg(R_EDI);
652 } else
653 #endif
654 if (s->aflag) {
655 if (s->addseg) {
656 gen_op_movl_A0_seg(R_ES);
657 gen_op_addl_A0_reg_sN(0, R_EDI);
658 } else {
659 gen_op_movl_A0_reg(R_EDI);
660 }
661 } else {
662 gen_op_movl_A0_reg(R_EDI);
663 gen_op_andl_A0_ffff();
664 gen_op_addl_A0_seg(R_ES);
665 }
666 }
667
668 static inline void gen_op_movl_T0_Dshift(int ot)
669 {
670 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
671 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
672 };
673
674 static void gen_extu(int ot, TCGv reg)
675 {
676 switch(ot) {
677 case OT_BYTE:
678 tcg_gen_ext8u_tl(reg, reg);
679 break;
680 case OT_WORD:
681 tcg_gen_ext16u_tl(reg, reg);
682 break;
683 case OT_LONG:
684 tcg_gen_ext32u_tl(reg, reg);
685 break;
686 default:
687 break;
688 }
689 }
690
691 static void gen_exts(int ot, TCGv reg)
692 {
693 switch(ot) {
694 case OT_BYTE:
695 tcg_gen_ext8s_tl(reg, reg);
696 break;
697 case OT_WORD:
698 tcg_gen_ext16s_tl(reg, reg);
699 break;
700 case OT_LONG:
701 tcg_gen_ext32s_tl(reg, reg);
702 break;
703 default:
704 break;
705 }
706 }
707
708 static inline void gen_op_jnz_ecx(int size, int label1)
709 {
710 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
711 gen_extu(size + 1, cpu_tmp0);
712 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
713 }
714
715 static inline void gen_op_jz_ecx(int size, int label1)
716 {
717 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
718 gen_extu(size + 1, cpu_tmp0);
719 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
720 }
721
722 static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
723 {
724 switch (ot) {
725 case 0: gen_helper_inb(v, n); break;
726 case 1: gen_helper_inw(v, n); break;
727 case 2: gen_helper_inl(v, n); break;
728 }
729
730 }
731
732 static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
733 {
734 switch (ot) {
735 case 0: gen_helper_outb(v, n); break;
736 case 1: gen_helper_outw(v, n); break;
737 case 2: gen_helper_outl(v, n); break;
738 }
739
740 }
741
742 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
743 uint32_t svm_flags)
744 {
745 int state_saved;
746 target_ulong next_eip;
747
748 state_saved = 0;
749 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
750 if (s->cc_op != CC_OP_DYNAMIC)
751 gen_op_set_cc_op(s->cc_op);
752 gen_jmp_im(cur_eip);
753 state_saved = 1;
754 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
755 switch (ot) {
756 case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
757 case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
758 case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
759 }
760 }
761 if(s->flags & HF_SVMI_MASK) {
762 if (!state_saved) {
763 if (s->cc_op != CC_OP_DYNAMIC)
764 gen_op_set_cc_op(s->cc_op);
765 gen_jmp_im(cur_eip);
766 state_saved = 1;
767 }
768 svm_flags |= (1 << (4 + ot));
769 next_eip = s->pc - s->cs_base;
770 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
771 gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
772 tcg_const_i32(next_eip - cur_eip));
773 }
774 }
775
776 static inline void gen_movs(DisasContext *s, int ot)
777 {
778 gen_string_movl_A0_ESI(s);
779 gen_op_ld_T0_A0(ot + s->mem_index);
780 gen_string_movl_A0_EDI(s);
781 gen_op_st_T0_A0(ot + s->mem_index);
782 gen_op_movl_T0_Dshift(ot);
783 gen_op_add_reg_T0(s->aflag, R_ESI);
784 gen_op_add_reg_T0(s->aflag, R_EDI);
785 }
786
787 static inline void gen_update_cc_op(DisasContext *s)
788 {
789 if (s->cc_op != CC_OP_DYNAMIC) {
790 gen_op_set_cc_op(s->cc_op);
791 s->cc_op = CC_OP_DYNAMIC;
792 }
793 }
794
795 static void gen_op_update1_cc(void)
796 {
797 tcg_gen_discard_tl(cpu_cc_src);
798 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
799 }
800
801 static void gen_op_update2_cc(void)
802 {
803 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
804 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
805 }
806
807 static inline void gen_op_cmpl_T0_T1_cc(void)
808 {
809 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
810 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
811 }
812
813 static inline void gen_op_testl_T0_T1_cc(void)
814 {
815 tcg_gen_discard_tl(cpu_cc_src);
816 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
817 }
818
819 static void gen_op_update_neg_cc(void)
820 {
821 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
822 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
823 }
824
825 /* compute eflags.C to reg */
826 static void gen_compute_eflags_c(TCGv reg)
827 {
828 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
829 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
830 }
831
832 /* compute all eflags to cc_src */
833 static void gen_compute_eflags(TCGv reg)
834 {
835 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
836 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
837 }
838
839 static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
840 {
841 if (s->cc_op != CC_OP_DYNAMIC)
842 gen_op_set_cc_op(s->cc_op);
843 switch(jcc_op) {
844 case JCC_O:
845 gen_compute_eflags(cpu_T[0]);
846 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
847 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
848 break;
849 case JCC_B:
850 gen_compute_eflags_c(cpu_T[0]);
851 break;
852 case JCC_Z:
853 gen_compute_eflags(cpu_T[0]);
854 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
855 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
856 break;
857 case JCC_BE:
858 gen_compute_eflags(cpu_tmp0);
859 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
860 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
861 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
862 break;
863 case JCC_S:
864 gen_compute_eflags(cpu_T[0]);
865 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
866 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
867 break;
868 case JCC_P:
869 gen_compute_eflags(cpu_T[0]);
870 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
871 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
872 break;
873 case JCC_L:
874 gen_compute_eflags(cpu_tmp0);
875 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
876 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
877 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
878 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
879 break;
880 default:
881 case JCC_LE:
882 gen_compute_eflags(cpu_tmp0);
883 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
884 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
885 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
886 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
887 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
888 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
889 break;
890 }
891 }
892
893 /* return true if setcc_slow is not needed (WARNING: must be kept in
894 sync with gen_jcc1) */
895 static int is_fast_jcc_case(DisasContext *s, int b)
896 {
897 int jcc_op;
898 jcc_op = (b >> 1) & 7;
899 switch(s->cc_op) {
900 /* we optimize the cmp/jcc case */
901 case CC_OP_SUBB:
902 case CC_OP_SUBW:
903 case CC_OP_SUBL:
904 case CC_OP_SUBQ:
905 if (jcc_op == JCC_O || jcc_op == JCC_P)
906 goto slow_jcc;
907 break;
908
909 /* some jumps are easy to compute */
910 case CC_OP_ADDB:
911 case CC_OP_ADDW:
912 case CC_OP_ADDL:
913 case CC_OP_ADDQ:
914
915 case CC_OP_LOGICB:
916 case CC_OP_LOGICW:
917 case CC_OP_LOGICL:
918 case CC_OP_LOGICQ:
919
920 case CC_OP_INCB:
921 case CC_OP_INCW:
922 case CC_OP_INCL:
923 case CC_OP_INCQ:
924
925 case CC_OP_DECB:
926 case CC_OP_DECW:
927 case CC_OP_DECL:
928 case CC_OP_DECQ:
929
930 case CC_OP_SHLB:
931 case CC_OP_SHLW:
932 case CC_OP_SHLL:
933 case CC_OP_SHLQ:
934 if (jcc_op != JCC_Z && jcc_op != JCC_S)
935 goto slow_jcc;
936 break;
937 default:
938 slow_jcc:
939 return 0;
940 }
941 return 1;
942 }
943
944 /* generate a conditional jump to label 'l1' according to jump opcode
945 value 'b'. In the fast case, T0 is guaranted not to be used. */
946 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
947 {
948 int inv, jcc_op, size, cond;
949 TCGv t0;
950
951 inv = b & 1;
952 jcc_op = (b >> 1) & 7;
953
954 switch(cc_op) {
955 /* we optimize the cmp/jcc case */
956 case CC_OP_SUBB:
957 case CC_OP_SUBW:
958 case CC_OP_SUBL:
959 case CC_OP_SUBQ:
960
961 size = cc_op - CC_OP_SUBB;
962 switch(jcc_op) {
963 case JCC_Z:
964 fast_jcc_z:
965 switch(size) {
966 case 0:
967 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
968 t0 = cpu_tmp0;
969 break;
970 case 1:
971 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
972 t0 = cpu_tmp0;
973 break;
974 #ifdef TARGET_X86_64
975 case 2:
976 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
977 t0 = cpu_tmp0;
978 break;
979 #endif
980 default:
981 t0 = cpu_cc_dst;
982 break;
983 }
984 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
985 break;
986 case JCC_S:
987 fast_jcc_s:
988 switch(size) {
989 case 0:
990 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
991 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
992 0, l1);
993 break;
994 case 1:
995 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
996 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
997 0, l1);
998 break;
999 #ifdef TARGET_X86_64
1000 case 2:
1001 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
1002 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1003 0, l1);
1004 break;
1005 #endif
1006 default:
1007 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1008 0, l1);
1009 break;
1010 }
1011 break;
1012
1013 case JCC_B:
1014 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1015 goto fast_jcc_b;
1016 case JCC_BE:
1017 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1018 fast_jcc_b:
1019 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1020 switch(size) {
1021 case 0:
1022 t0 = cpu_tmp0;
1023 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1024 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1025 break;
1026 case 1:
1027 t0 = cpu_tmp0;
1028 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1029 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1030 break;
1031 #ifdef TARGET_X86_64
1032 case 2:
1033 t0 = cpu_tmp0;
1034 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1035 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1036 break;
1037 #endif
1038 default:
1039 t0 = cpu_cc_src;
1040 break;
1041 }
1042 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1043 break;
1044
1045 case JCC_L:
1046 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1047 goto fast_jcc_l;
1048 case JCC_LE:
1049 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1050 fast_jcc_l:
1051 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1052 switch(size) {
1053 case 0:
1054 t0 = cpu_tmp0;
1055 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1056 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1057 break;
1058 case 1:
1059 t0 = cpu_tmp0;
1060 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1061 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1062 break;
1063 #ifdef TARGET_X86_64
1064 case 2:
1065 t0 = cpu_tmp0;
1066 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1067 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1068 break;
1069 #endif
1070 default:
1071 t0 = cpu_cc_src;
1072 break;
1073 }
1074 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1075 break;
1076
1077 default:
1078 goto slow_jcc;
1079 }
1080 break;
1081
1082 /* some jumps are easy to compute */
1083 case CC_OP_ADDB:
1084 case CC_OP_ADDW:
1085 case CC_OP_ADDL:
1086 case CC_OP_ADDQ:
1087
1088 case CC_OP_ADCB:
1089 case CC_OP_ADCW:
1090 case CC_OP_ADCL:
1091 case CC_OP_ADCQ:
1092
1093 case CC_OP_SBBB:
1094 case CC_OP_SBBW:
1095 case CC_OP_SBBL:
1096 case CC_OP_SBBQ:
1097
1098 case CC_OP_LOGICB:
1099 case CC_OP_LOGICW:
1100 case CC_OP_LOGICL:
1101 case CC_OP_LOGICQ:
1102
1103 case CC_OP_INCB:
1104 case CC_OP_INCW:
1105 case CC_OP_INCL:
1106 case CC_OP_INCQ:
1107
1108 case CC_OP_DECB:
1109 case CC_OP_DECW:
1110 case CC_OP_DECL:
1111 case CC_OP_DECQ:
1112
1113 case CC_OP_SHLB:
1114 case CC_OP_SHLW:
1115 case CC_OP_SHLL:
1116 case CC_OP_SHLQ:
1117
1118 case CC_OP_SARB:
1119 case CC_OP_SARW:
1120 case CC_OP_SARL:
1121 case CC_OP_SARQ:
1122 switch(jcc_op) {
1123 case JCC_Z:
1124 size = (cc_op - CC_OP_ADDB) & 3;
1125 goto fast_jcc_z;
1126 case JCC_S:
1127 size = (cc_op - CC_OP_ADDB) & 3;
1128 goto fast_jcc_s;
1129 default:
1130 goto slow_jcc;
1131 }
1132 break;
1133 default:
1134 slow_jcc:
1135 gen_setcc_slow_T0(s, jcc_op);
1136 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1137 cpu_T[0], 0, l1);
1138 break;
1139 }
1140 }
1141
1142 /* XXX: does not work with gdbstub "ice" single step - not a
1143 serious problem */
1144 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1145 {
1146 int l1, l2;
1147
1148 l1 = gen_new_label();
1149 l2 = gen_new_label();
1150 gen_op_jnz_ecx(s->aflag, l1);
1151 gen_set_label(l2);
1152 gen_jmp_tb(s, next_eip, 1);
1153 gen_set_label(l1);
1154 return l2;
1155 }
1156
1157 static inline void gen_stos(DisasContext *s, int ot)
1158 {
1159 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1160 gen_string_movl_A0_EDI(s);
1161 gen_op_st_T0_A0(ot + s->mem_index);
1162 gen_op_movl_T0_Dshift(ot);
1163 gen_op_add_reg_T0(s->aflag, R_EDI);
1164 }
1165
1166 static inline void gen_lods(DisasContext *s, int ot)
1167 {
1168 gen_string_movl_A0_ESI(s);
1169 gen_op_ld_T0_A0(ot + s->mem_index);
1170 gen_op_mov_reg_T0(ot, R_EAX);
1171 gen_op_movl_T0_Dshift(ot);
1172 gen_op_add_reg_T0(s->aflag, R_ESI);
1173 }
1174
1175 static inline void gen_scas(DisasContext *s, int ot)
1176 {
1177 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1178 gen_string_movl_A0_EDI(s);
1179 gen_op_ld_T1_A0(ot + s->mem_index);
1180 gen_op_cmpl_T0_T1_cc();
1181 gen_op_movl_T0_Dshift(ot);
1182 gen_op_add_reg_T0(s->aflag, R_EDI);
1183 }
1184
1185 static inline void gen_cmps(DisasContext *s, int ot)
1186 {
1187 gen_string_movl_A0_ESI(s);
1188 gen_op_ld_T0_A0(ot + s->mem_index);
1189 gen_string_movl_A0_EDI(s);
1190 gen_op_ld_T1_A0(ot + s->mem_index);
1191 gen_op_cmpl_T0_T1_cc();
1192 gen_op_movl_T0_Dshift(ot);
1193 gen_op_add_reg_T0(s->aflag, R_ESI);
1194 gen_op_add_reg_T0(s->aflag, R_EDI);
1195 }
1196
1197 static inline void gen_ins(DisasContext *s, int ot)
1198 {
1199 if (use_icount)
1200 gen_io_start();
1201 gen_string_movl_A0_EDI(s);
1202 /* Note: we must do this dummy write first to be restartable in
1203 case of page fault. */
1204 gen_op_movl_T0_0();
1205 gen_op_st_T0_A0(ot + s->mem_index);
1206 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1207 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1208 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1209 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1210 gen_op_st_T0_A0(ot + s->mem_index);
1211 gen_op_movl_T0_Dshift(ot);
1212 gen_op_add_reg_T0(s->aflag, R_EDI);
1213 if (use_icount)
1214 gen_io_end();
1215 }
1216
1217 static inline void gen_outs(DisasContext *s, int ot)
1218 {
1219 if (use_icount)
1220 gen_io_start();
1221 gen_string_movl_A0_ESI(s);
1222 gen_op_ld_T0_A0(ot + s->mem_index);
1223
1224 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1225 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1226 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1227 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1228 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1229
1230 gen_op_movl_T0_Dshift(ot);
1231 gen_op_add_reg_T0(s->aflag, R_ESI);
1232 if (use_icount)
1233 gen_io_end();
1234 }
1235
1236 /* same method as Valgrind : we generate jumps to current or next
1237 instruction */
1238 #define GEN_REPZ(op) \
1239 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1240 target_ulong cur_eip, target_ulong next_eip) \
1241 { \
1242 int l2;\
1243 gen_update_cc_op(s); \
1244 l2 = gen_jz_ecx_string(s, next_eip); \
1245 gen_ ## op(s, ot); \
1246 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1247 /* a loop would cause two single step exceptions if ECX = 1 \
1248 before rep string_insn */ \
1249 if (!s->jmp_opt) \
1250 gen_op_jz_ecx(s->aflag, l2); \
1251 gen_jmp(s, cur_eip); \
1252 }
1253
1254 #define GEN_REPZ2(op) \
1255 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1256 target_ulong cur_eip, \
1257 target_ulong next_eip, \
1258 int nz) \
1259 { \
1260 int l2;\
1261 gen_update_cc_op(s); \
1262 l2 = gen_jz_ecx_string(s, next_eip); \
1263 gen_ ## op(s, ot); \
1264 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1265 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1266 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1267 if (!s->jmp_opt) \
1268 gen_op_jz_ecx(s->aflag, l2); \
1269 gen_jmp(s, cur_eip); \
1270 }
1271
1272 GEN_REPZ(movs)
1273 GEN_REPZ(stos)
1274 GEN_REPZ(lods)
1275 GEN_REPZ(ins)
1276 GEN_REPZ(outs)
1277 GEN_REPZ2(scas)
1278 GEN_REPZ2(cmps)
1279
1280 static void gen_helper_fp_arith_ST0_FT0(int op)
1281 {
1282 switch (op) {
1283 case 0: gen_helper_fadd_ST0_FT0(); break;
1284 case 1: gen_helper_fmul_ST0_FT0(); break;
1285 case 2: gen_helper_fcom_ST0_FT0(); break;
1286 case 3: gen_helper_fcom_ST0_FT0(); break;
1287 case 4: gen_helper_fsub_ST0_FT0(); break;
1288 case 5: gen_helper_fsubr_ST0_FT0(); break;
1289 case 6: gen_helper_fdiv_ST0_FT0(); break;
1290 case 7: gen_helper_fdivr_ST0_FT0(); break;
1291 }
1292 }
1293
1294 /* NOTE the exception in "r" op ordering */
1295 static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1296 {
1297 TCGv_i32 tmp = tcg_const_i32(opreg);
1298 switch (op) {
1299 case 0: gen_helper_fadd_STN_ST0(tmp); break;
1300 case 1: gen_helper_fmul_STN_ST0(tmp); break;
1301 case 4: gen_helper_fsubr_STN_ST0(tmp); break;
1302 case 5: gen_helper_fsub_STN_ST0(tmp); break;
1303 case 6: gen_helper_fdivr_STN_ST0(tmp); break;
1304 case 7: gen_helper_fdiv_STN_ST0(tmp); break;
1305 }
1306 }
1307
1308 /* if d == OR_TMP0, it means memory operand (address in A0) */
1309 static void gen_op(DisasContext *s1, int op, int ot, int d)
1310 {
1311 if (d != OR_TMP0) {
1312 gen_op_mov_TN_reg(ot, 0, d);
1313 } else {
1314 gen_op_ld_T0_A0(ot + s1->mem_index);
1315 }
1316 switch(op) {
1317 case OP_ADCL:
1318 if (s1->cc_op != CC_OP_DYNAMIC)
1319 gen_op_set_cc_op(s1->cc_op);
1320 gen_compute_eflags_c(cpu_tmp4);
1321 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1322 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1323 if (d != OR_TMP0)
1324 gen_op_mov_reg_T0(ot, d);
1325 else
1326 gen_op_st_T0_A0(ot + s1->mem_index);
1327 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1328 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1329 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1330 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1331 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1332 s1->cc_op = CC_OP_DYNAMIC;
1333 break;
1334 case OP_SBBL:
1335 if (s1->cc_op != CC_OP_DYNAMIC)
1336 gen_op_set_cc_op(s1->cc_op);
1337 gen_compute_eflags_c(cpu_tmp4);
1338 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1339 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1340 if (d != OR_TMP0)
1341 gen_op_mov_reg_T0(ot, d);
1342 else
1343 gen_op_st_T0_A0(ot + s1->mem_index);
1344 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1345 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1346 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1347 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1348 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1349 s1->cc_op = CC_OP_DYNAMIC;
1350 break;
1351 case OP_ADDL:
1352 gen_op_addl_T0_T1();
1353 if (d != OR_TMP0)
1354 gen_op_mov_reg_T0(ot, d);
1355 else
1356 gen_op_st_T0_A0(ot + s1->mem_index);
1357 gen_op_update2_cc();
1358 s1->cc_op = CC_OP_ADDB + ot;
1359 break;
1360 case OP_SUBL:
1361 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1362 if (d != OR_TMP0)
1363 gen_op_mov_reg_T0(ot, d);
1364 else
1365 gen_op_st_T0_A0(ot + s1->mem_index);
1366 gen_op_update2_cc();
1367 s1->cc_op = CC_OP_SUBB + ot;
1368 break;
1369 default:
1370 case OP_ANDL:
1371 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1372 if (d != OR_TMP0)
1373 gen_op_mov_reg_T0(ot, d);
1374 else
1375 gen_op_st_T0_A0(ot + s1->mem_index);
1376 gen_op_update1_cc();
1377 s1->cc_op = CC_OP_LOGICB + ot;
1378 break;
1379 case OP_ORL:
1380 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1381 if (d != OR_TMP0)
1382 gen_op_mov_reg_T0(ot, d);
1383 else
1384 gen_op_st_T0_A0(ot + s1->mem_index);
1385 gen_op_update1_cc();
1386 s1->cc_op = CC_OP_LOGICB + ot;
1387 break;
1388 case OP_XORL:
1389 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1390 if (d != OR_TMP0)
1391 gen_op_mov_reg_T0(ot, d);
1392 else
1393 gen_op_st_T0_A0(ot + s1->mem_index);
1394 gen_op_update1_cc();
1395 s1->cc_op = CC_OP_LOGICB + ot;
1396 break;
1397 case OP_CMPL:
1398 gen_op_cmpl_T0_T1_cc();
1399 s1->cc_op = CC_OP_SUBB + ot;
1400 break;
1401 }
1402 }
1403
1404 /* if d == OR_TMP0, it means memory operand (address in A0) */
1405 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1406 {
1407 if (d != OR_TMP0)
1408 gen_op_mov_TN_reg(ot, 0, d);
1409 else
1410 gen_op_ld_T0_A0(ot + s1->mem_index);
1411 if (s1->cc_op != CC_OP_DYNAMIC)
1412 gen_op_set_cc_op(s1->cc_op);
1413 if (c > 0) {
1414 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1415 s1->cc_op = CC_OP_INCB + ot;
1416 } else {
1417 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1418 s1->cc_op = CC_OP_DECB + ot;
1419 }
1420 if (d != OR_TMP0)
1421 gen_op_mov_reg_T0(ot, d);
1422 else
1423 gen_op_st_T0_A0(ot + s1->mem_index);
1424 gen_compute_eflags_c(cpu_cc_src);
1425 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1426 }
1427
1428 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1429 int is_right, int is_arith)
1430 {
1431 target_ulong mask;
1432 int shift_label;
1433 TCGv t0, t1;
1434
1435 if (ot == OT_QUAD)
1436 mask = 0x3f;
1437 else
1438 mask = 0x1f;
1439
1440 /* load */
1441 if (op1 == OR_TMP0)
1442 gen_op_ld_T0_A0(ot + s->mem_index);
1443 else
1444 gen_op_mov_TN_reg(ot, 0, op1);
1445
1446 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1447
1448 tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1449
1450 if (is_right) {
1451 if (is_arith) {
1452 gen_exts(ot, cpu_T[0]);
1453 tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1454 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1455 } else {
1456 gen_extu(ot, cpu_T[0]);
1457 tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1458 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1459 }
1460 } else {
1461 tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1462 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1463 }
1464
1465 /* store */
1466 if (op1 == OR_TMP0)
1467 gen_op_st_T0_A0(ot + s->mem_index);
1468 else
1469 gen_op_mov_reg_T0(ot, op1);
1470
1471 /* update eflags if non zero shift */
1472 if (s->cc_op != CC_OP_DYNAMIC)
1473 gen_op_set_cc_op(s->cc_op);
1474
1475 /* XXX: inefficient */
1476 t0 = tcg_temp_local_new();
1477 t1 = tcg_temp_local_new();
1478
1479 tcg_gen_mov_tl(t0, cpu_T[0]);
1480 tcg_gen_mov_tl(t1, cpu_T3);
1481
1482 shift_label = gen_new_label();
1483 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);
1484
1485 tcg_gen_mov_tl(cpu_cc_src, t1);
1486 tcg_gen_mov_tl(cpu_cc_dst, t0);
1487 if (is_right)
1488 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1489 else
1490 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1491
1492 gen_set_label(shift_label);
1493 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1494
1495 tcg_temp_free(t0);
1496 tcg_temp_free(t1);
1497 }
1498
1499 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1500 int is_right, int is_arith)
1501 {
1502 int mask;
1503
1504 if (ot == OT_QUAD)
1505 mask = 0x3f;
1506 else
1507 mask = 0x1f;
1508
1509 /* load */
1510 if (op1 == OR_TMP0)
1511 gen_op_ld_T0_A0(ot + s->mem_index);
1512 else
1513 gen_op_mov_TN_reg(ot, 0, op1);
1514
1515 op2 &= mask;
1516 if (op2 != 0) {
1517 if (is_right) {
1518 if (is_arith) {
1519 gen_exts(ot, cpu_T[0]);
1520 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1521 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1522 } else {
1523 gen_extu(ot, cpu_T[0]);
1524 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1525 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1526 }
1527 } else {
1528 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1529 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1530 }
1531 }
1532
1533 /* store */
1534 if (op1 == OR_TMP0)
1535 gen_op_st_T0_A0(ot + s->mem_index);
1536 else
1537 gen_op_mov_reg_T0(ot, op1);
1538
1539 /* update eflags if non zero shift */
1540 if (op2 != 0) {
1541 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1542 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1543 if (is_right)
1544 s->cc_op = CC_OP_SARB + ot;
1545 else
1546 s->cc_op = CC_OP_SHLB + ot;
1547 }
1548 }
1549
1550 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1551 {
1552 if (arg2 >= 0)
1553 tcg_gen_shli_tl(ret, arg1, arg2);
1554 else
1555 tcg_gen_shri_tl(ret, arg1, -arg2);
1556 }
1557
1558 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1559 int is_right)
1560 {
1561 target_ulong mask;
1562 int label1, label2, data_bits;
1563 TCGv t0, t1, t2, a0;
1564
1565 /* XXX: inefficient, but we must use local temps */
1566 t0 = tcg_temp_local_new();
1567 t1 = tcg_temp_local_new();
1568 t2 = tcg_temp_local_new();
1569 a0 = tcg_temp_local_new();
1570
1571 if (ot == OT_QUAD)
1572 mask = 0x3f;
1573 else
1574 mask = 0x1f;
1575
1576 /* load */
1577 if (op1 == OR_TMP0) {
1578 tcg_gen_mov_tl(a0, cpu_A0);
1579 gen_op_ld_v(ot + s->mem_index, t0, a0);
1580 } else {
1581 gen_op_mov_v_reg(ot, t0, op1);
1582 }
1583
1584 tcg_gen_mov_tl(t1, cpu_T[1]);
1585
1586 tcg_gen_andi_tl(t1, t1, mask);
1587
1588 /* Must test zero case to avoid using undefined behaviour in TCG
1589 shifts. */
1590 label1 = gen_new_label();
1591 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1592
1593 if (ot <= OT_WORD)
1594 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1595 else
1596 tcg_gen_mov_tl(cpu_tmp0, t1);
1597
1598 gen_extu(ot, t0);
1599 tcg_gen_mov_tl(t2, t0);
1600
1601 data_bits = 8 << ot;
1602 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1603 fix TCG definition) */
1604 if (is_right) {
1605 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1606 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1607 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1608 } else {
1609 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1610 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1611 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1612 }
1613 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1614
1615 gen_set_label(label1);
1616 /* store */
1617 if (op1 == OR_TMP0) {
1618 gen_op_st_v(ot + s->mem_index, t0, a0);
1619 } else {
1620 gen_op_mov_reg_v(ot, op1, t0);
1621 }
1622
1623 /* update eflags */
1624 if (s->cc_op != CC_OP_DYNAMIC)
1625 gen_op_set_cc_op(s->cc_op);
1626
1627 label2 = gen_new_label();
1628 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1629
1630 gen_compute_eflags(cpu_cc_src);
1631 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1632 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1633 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1634 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1635 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1636 if (is_right) {
1637 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1638 }
1639 tcg_gen_andi_tl(t0, t0, CC_C);
1640 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1641
1642 tcg_gen_discard_tl(cpu_cc_dst);
1643 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1644
1645 gen_set_label(label2);
1646 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1647
1648 tcg_temp_free(t0);
1649 tcg_temp_free(t1);
1650 tcg_temp_free(t2);
1651 tcg_temp_free(a0);
1652 }
1653
1654 static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1655 int is_right)
1656 {
1657 int mask;
1658 int data_bits;
1659 TCGv t0, t1, a0;
1660
1661 /* XXX: inefficient, but we must use local temps */
1662 t0 = tcg_temp_local_new();
1663 t1 = tcg_temp_local_new();
1664 a0 = tcg_temp_local_new();
1665
1666 if (ot == OT_QUAD)
1667 mask = 0x3f;
1668 else
1669 mask = 0x1f;
1670
1671 /* load */
1672 if (op1 == OR_TMP0) {
1673 tcg_gen_mov_tl(a0, cpu_A0);
1674 gen_op_ld_v(ot + s->mem_index, t0, a0);
1675 } else {
1676 gen_op_mov_v_reg(ot, t0, op1);
1677 }
1678
1679 gen_extu(ot, t0);
1680 tcg_gen_mov_tl(t1, t0);
1681
1682 op2 &= mask;
1683 data_bits = 8 << ot;
1684 if (op2 != 0) {
1685 int shift = op2 & ((1 << (3 + ot)) - 1);
1686 if (is_right) {
1687 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1688 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1689 }
1690 else {
1691 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1692 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1693 }
1694 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1695 }
1696
1697 /* store */
1698 if (op1 == OR_TMP0) {
1699 gen_op_st_v(ot + s->mem_index, t0, a0);
1700 } else {
1701 gen_op_mov_reg_v(ot, op1, t0);
1702 }
1703
1704 if (op2 != 0) {
1705 /* update eflags */
1706 if (s->cc_op != CC_OP_DYNAMIC)
1707 gen_op_set_cc_op(s->cc_op);
1708
1709 gen_compute_eflags(cpu_cc_src);
1710 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1711 tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1712 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1713 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1714 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1715 if (is_right) {
1716 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1717 }
1718 tcg_gen_andi_tl(t0, t0, CC_C);
1719 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1720
1721 tcg_gen_discard_tl(cpu_cc_dst);
1722 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1723 s->cc_op = CC_OP_EFLAGS;
1724 }
1725
1726 tcg_temp_free(t0);
1727 tcg_temp_free(t1);
1728 tcg_temp_free(a0);
1729 }
1730
1731 /* XXX: add faster immediate = 1 case */
1732 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1733 int is_right)
1734 {
1735 int label1;
1736
1737 if (s->cc_op != CC_OP_DYNAMIC)
1738 gen_op_set_cc_op(s->cc_op);
1739
1740 /* load */
1741 if (op1 == OR_TMP0)
1742 gen_op_ld_T0_A0(ot + s->mem_index);
1743 else
1744 gen_op_mov_TN_reg(ot, 0, op1);
1745
1746 if (is_right) {
1747 switch (ot) {
1748 case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1749 case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1750 case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1751 #ifdef TARGET_X86_64
1752 case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1753 #endif
1754 }
1755 } else {
1756 switch (ot) {
1757 case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1758 case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1759 case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1760 #ifdef TARGET_X86_64
1761 case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1762 #endif
1763 }
1764 }
1765 /* store */
1766 if (op1 == OR_TMP0)
1767 gen_op_st_T0_A0(ot + s->mem_index);
1768 else
1769 gen_op_mov_reg_T0(ot, op1);
1770
1771 /* update eflags */
1772 label1 = gen_new_label();
1773 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1774
1775 tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1776 tcg_gen_discard_tl(cpu_cc_dst);
1777 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1778
1779 gen_set_label(label1);
1780 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1781 }
1782
1783 /* XXX: add faster immediate case */
1784 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1785 int is_right)
1786 {
1787 int label1, label2, data_bits;
1788 target_ulong mask;
1789 TCGv t0, t1, t2, a0;
1790
1791 t0 = tcg_temp_local_new();
1792 t1 = tcg_temp_local_new();
1793 t2 = tcg_temp_local_new();
1794 a0 = tcg_temp_local_new();
1795
1796 if (ot == OT_QUAD)
1797 mask = 0x3f;
1798 else
1799 mask = 0x1f;
1800
1801 /* load */
1802 if (op1 == OR_TMP0) {
1803 tcg_gen_mov_tl(a0, cpu_A0);
1804 gen_op_ld_v(ot + s->mem_index, t0, a0);
1805 } else {
1806 gen_op_mov_v_reg(ot, t0, op1);
1807 }
1808
1809 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1810
1811 tcg_gen_mov_tl(t1, cpu_T[1]);
1812 tcg_gen_mov_tl(t2, cpu_T3);
1813
1814 /* Must test zero case to avoid using undefined behaviour in TCG
1815 shifts. */
1816 label1 = gen_new_label();
1817 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1818
1819 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1820 if (ot == OT_WORD) {
1821 /* Note: we implement the Intel behaviour for shift count > 16 */
1822 if (is_right) {
1823 tcg_gen_andi_tl(t0, t0, 0xffff);
1824 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1825 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1826 tcg_gen_ext32u_tl(t0, t0);
1827
1828 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1829
1830 /* only needed if count > 16, but a test would complicate */
1831 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1832 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1833
1834 tcg_gen_shr_tl(t0, t0, t2);
1835
1836 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1837 } else {
1838 /* XXX: not optimal */
1839 tcg_gen_andi_tl(t0, t0, 0xffff);
1840 tcg_gen_shli_tl(t1, t1, 16);
1841 tcg_gen_or_tl(t1, t1, t0);
1842 tcg_gen_ext32u_tl(t1, t1);
1843
1844 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1845 tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
1846 tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
1847 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
1848
1849 tcg_gen_shl_tl(t0, t0, t2);
1850 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1851 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1852 tcg_gen_or_tl(t0, t0, t1);
1853 }
1854 } else {
1855 data_bits = 8 << ot;
1856 if (is_right) {
1857 if (ot == OT_LONG)
1858 tcg_gen_ext32u_tl(t0, t0);
1859
1860 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1861
1862 tcg_gen_shr_tl(t0, t0, t2);
1863 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1864 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1865 tcg_gen_or_tl(t0, t0, t1);
1866
1867 } else {
1868 if (ot == OT_LONG)
1869 tcg_gen_ext32u_tl(t1, t1);
1870
1871 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1872
1873 tcg_gen_shl_tl(t0, t0, t2);
1874 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1875 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1876 tcg_gen_or_tl(t0, t0, t1);
1877 }
1878 }
1879 tcg_gen_mov_tl(t1, cpu_tmp4);
1880
1881 gen_set_label(label1);
1882 /* store */
1883 if (op1 == OR_TMP0) {
1884 gen_op_st_v(ot + s->mem_index, t0, a0);
1885 } else {
1886 gen_op_mov_reg_v(ot, op1, t0);
1887 }
1888
1889 /* update eflags */
1890 if (s->cc_op != CC_OP_DYNAMIC)
1891 gen_op_set_cc_op(s->cc_op);
1892
1893 label2 = gen_new_label();
1894 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1895
1896 tcg_gen_mov_tl(cpu_cc_src, t1);
1897 tcg_gen_mov_tl(cpu_cc_dst, t0);
1898 if (is_right) {
1899 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1900 } else {
1901 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1902 }
1903 gen_set_label(label2);
1904 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1905
1906 tcg_temp_free(t0);
1907 tcg_temp_free(t1);
1908 tcg_temp_free(t2);
1909 tcg_temp_free(a0);
1910 }
1911
1912 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1913 {
1914 if (s != OR_TMP1)
1915 gen_op_mov_TN_reg(ot, 1, s);
1916 switch(op) {
1917 case OP_ROL:
1918 gen_rot_rm_T1(s1, ot, d, 0);
1919 break;
1920 case OP_ROR:
1921 gen_rot_rm_T1(s1, ot, d, 1);
1922 break;
1923 case OP_SHL:
1924 case OP_SHL1:
1925 gen_shift_rm_T1(s1, ot, d, 0, 0);
1926 break;
1927 case OP_SHR:
1928 gen_shift_rm_T1(s1, ot, d, 1, 0);
1929 break;
1930 case OP_SAR:
1931 gen_shift_rm_T1(s1, ot, d, 1, 1);
1932 break;
1933 case OP_RCL:
1934 gen_rotc_rm_T1(s1, ot, d, 0);
1935 break;
1936 case OP_RCR:
1937 gen_rotc_rm_T1(s1, ot, d, 1);
1938 break;
1939 }
1940 }
1941
1942 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1943 {
1944 switch(op) {
1945 case OP_ROL:
1946 gen_rot_rm_im(s1, ot, d, c, 0);
1947 break;
1948 case OP_ROR:
1949 gen_rot_rm_im(s1, ot, d, c, 1);
1950 break;
1951 case OP_SHL:
1952 case OP_SHL1:
1953 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1954 break;
1955 case OP_SHR:
1956 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1957 break;
1958 case OP_SAR:
1959 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1960 break;
1961 default:
1962 /* currently not optimized */
1963 gen_op_movl_T1_im(c);
1964 gen_shift(s1, op, ot, d, OR_TMP1);
1965 break;
1966 }
1967 }
1968
1969 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1970 {
1971 target_long disp;
1972 int havesib;
1973 int base;
1974 int index;
1975 int scale;
1976 int opreg;
1977 int mod, rm, code, override, must_add_seg;
1978
1979 override = s->override;
1980 must_add_seg = s->addseg;
1981 if (override >= 0)
1982 must_add_seg = 1;
1983 mod = (modrm >> 6) & 3;
1984 rm = modrm & 7;
1985
1986 if (s->aflag) {
1987
1988 havesib = 0;
1989 base = rm;
1990 index = 0;
1991 scale = 0;
1992
1993 if (base == 4) {
1994 havesib = 1;
1995 code = ldub_code(s->pc++);
1996 scale = (code >> 6) & 3;
1997 index = ((code >> 3) & 7) | REX_X(s);
1998 base = (code & 7);
1999 }
2000 base |= REX_B(s);
2001
2002 switch (mod) {
2003 case 0:
2004 if ((base & 7) == 5) {
2005 base = -1;
2006 disp = (int32_t)ldl_code(s->pc);
2007 s->pc += 4;
2008 if (CODE64(s) && !havesib) {
2009 disp += s->pc + s->rip_offset;
2010 }
2011 } else {
2012 disp = 0;
2013 }
2014 break;
2015 case 1:
2016 disp = (int8_t)ldub_code(s->pc++);
2017 break;
2018 default:
2019 case 2:
2020 disp = ldl_code(s->pc);
2021 s->pc += 4;
2022 break;
2023 }
2024
2025 if (base >= 0) {
2026 /* for correct popl handling with esp */
2027 if (base == 4 && s->popl_esp_hack)
2028 disp += s->popl_esp_hack;
2029 #ifdef TARGET_X86_64
2030 if (s->aflag == 2) {
2031 gen_op_movq_A0_reg(base);
2032 if (disp != 0) {
2033 gen_op_addq_A0_im(disp);
2034 }
2035 } else
2036 #endif
2037 {
2038 gen_op_movl_A0_reg(base);
2039 if (disp != 0)
2040 gen_op_addl_A0_im(disp);
2041 }
2042 } else {
2043 #ifdef TARGET_X86_64
2044 if (s->aflag == 2) {
2045 gen_op_movq_A0_im(disp);
2046 } else
2047 #endif
2048 {
2049 gen_op_movl_A0_im(disp);
2050 }
2051 }
2052 /* index == 4 means no index */
2053 if (havesib && (index != 4)) {
2054 #ifdef TARGET_X86_64
2055 if (s->aflag == 2) {
2056 gen_op_addq_A0_reg_sN(scale, index);
2057 } else
2058 #endif
2059 {
2060 gen_op_addl_A0_reg_sN(scale, index);
2061 }
2062 }
2063 if (must_add_seg) {
2064 if (override < 0) {
2065 if (base == R_EBP || base == R_ESP)
2066 override = R_SS;
2067 else
2068 override = R_DS;
2069 }
2070 #ifdef TARGET_X86_64
2071 if (s->aflag == 2) {
2072 gen_op_addq_A0_seg(override);
2073 } else
2074 #endif
2075 {
2076 gen_op_addl_A0_seg(override);
2077 }
2078 }
2079 } else {
2080 switch (mod) {
2081 case 0:
2082 if (rm == 6) {
2083 disp = lduw_code(s->pc);
2084 s->pc += 2;
2085 gen_op_movl_A0_im(disp);
2086 rm = 0; /* avoid SS override */
2087 goto no_rm;
2088 } else {
2089 disp = 0;
2090 }
2091 break;
2092 case 1:
2093 disp = (int8_t)ldub_code(s->pc++);
2094 break;
2095 default:
2096 case 2:
2097 disp = lduw_code(s->pc);
2098 s->pc += 2;
2099 break;
2100 }
2101 switch(rm) {
2102 case 0:
2103 gen_op_movl_A0_reg(R_EBX);
2104 gen_op_addl_A0_reg_sN(0, R_ESI);
2105 break;
2106 case 1:
2107 gen_op_movl_A0_reg(R_EBX);
2108 gen_op_addl_A0_reg_sN(0, R_EDI);
2109 break;
2110 case 2:
2111 gen_op_movl_A0_reg(R_EBP);
2112 gen_op_addl_A0_reg_sN(0, R_ESI);
2113 break;
2114 case 3:
2115 gen_op_movl_A0_reg(R_EBP);
2116 gen_op_addl_A0_reg_sN(0, R_EDI);
2117 break;
2118 case 4:
2119 gen_op_movl_A0_reg(R_ESI);
2120 break;
2121 case 5:
2122 gen_op_movl_A0_reg(R_EDI);
2123 break;
2124 case 6:
2125 gen_op_movl_A0_reg(R_EBP);
2126 break;
2127 default:
2128 case 7:
2129 gen_op_movl_A0_reg(R_EBX);
2130 break;
2131 }
2132 if (disp != 0)
2133 gen_op_addl_A0_im(disp);
2134 gen_op_andl_A0_ffff();
2135 no_rm:
2136 if (must_add_seg) {
2137 if (override < 0) {
2138 if (rm == 2 || rm == 3 || rm == 6)
2139 override = R_SS;
2140 else
2141 override = R_DS;
2142 }
2143 gen_op_addl_A0_seg(override);
2144 }
2145 }
2146
2147 opreg = OR_A0;
2148 disp = 0;
2149 *reg_ptr = opreg;
2150 *offset_ptr = disp;
2151 }
2152
2153 static void gen_nop_modrm(DisasContext *s, int modrm)
2154 {
2155 int mod, rm, base, code;
2156
2157 mod = (modrm >> 6) & 3;
2158 if (mod == 3)
2159 return;
2160 rm = modrm & 7;
2161
2162 if (s->aflag) {
2163
2164 base = rm;
2165
2166 if (base == 4) {
2167 code = ldub_code(s->pc++);
2168 base = (code & 7);
2169 }
2170
2171 switch (mod) {
2172 case 0:
2173 if (base == 5) {
2174 s->pc += 4;
2175 }
2176 break;
2177 case 1:
2178 s->pc++;
2179 break;
2180 default:
2181 case 2:
2182 s->pc += 4;
2183 break;
2184 }
2185 } else {
2186 switch (mod) {
2187 case 0:
2188 if (rm == 6) {
2189 s->pc += 2;
2190 }
2191 break;
2192 case 1:
2193 s->pc++;
2194 break;
2195 default:
2196 case 2:
2197 s->pc += 2;
2198 break;
2199 }
2200 }
2201 }
2202
2203 /* used for LEA and MOV AX, mem */
2204 static void gen_add_A0_ds_seg(DisasContext *s)
2205 {
2206 int override, must_add_seg;
2207 must_add_seg = s->addseg;
2208 override = R_DS;
2209 if (s->override >= 0) {
2210 override = s->override;
2211 must_add_seg = 1;
2212 }
2213 if (must_add_seg) {
2214 #ifdef TARGET_X86_64
2215 if (CODE64(s)) {
2216 gen_op_addq_A0_seg(override);
2217 } else
2218 #endif
2219 {
2220 gen_op_addl_A0_seg(override);
2221 }
2222 }
2223 }
2224
2225 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2226 OR_TMP0 */
2227 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2228 {
2229 int mod, rm, opreg, disp;
2230
2231 mod = (modrm >> 6) & 3;
2232 rm = (modrm & 7) | REX_B(s);
2233 if (mod == 3) {
2234 if (is_store) {
2235 if (reg != OR_TMP0)
2236 gen_op_mov_TN_reg(ot, 0, reg);
2237 gen_op_mov_reg_T0(ot, rm);
2238 } else {
2239 gen_op_mov_TN_reg(ot, 0, rm);
2240 if (reg != OR_TMP0)
2241 gen_op_mov_reg_T0(ot, reg);
2242 }
2243 } else {
2244 gen_lea_modrm(s, modrm, &opreg, &disp);
2245 if (is_store) {
2246 if (reg != OR_TMP0)
2247 gen_op_mov_TN_reg(ot, 0, reg);
2248 gen_op_st_T0_A0(ot + s->mem_index);
2249 } else {
2250 gen_op_ld_T0_A0(ot + s->mem_index);
2251 if (reg != OR_TMP0)
2252 gen_op_mov_reg_T0(ot, reg);
2253 }
2254 }
2255 }
2256
2257 static inline uint32_t insn_get(DisasContext *s, int ot)
2258 {
2259 uint32_t ret;
2260
2261 switch(ot) {
2262 case OT_BYTE:
2263 ret = ldub_code(s->pc);
2264 s->pc++;
2265 break;
2266 case OT_WORD:
2267 ret = lduw_code(s->pc);
2268 s->pc += 2;
2269 break;
2270 default:
2271 case OT_LONG:
2272 ret = ldl_code(s->pc);
2273 s->pc += 4;
2274 break;
2275 }
2276 return ret;
2277 }
2278
2279 static inline int insn_const_size(unsigned int ot)
2280 {
2281 if (ot <= OT_LONG)
2282 return 1 << ot;
2283 else
2284 return 4;
2285 }
2286
2287 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2288 {
2289 TranslationBlock *tb;
2290 target_ulong pc;
2291
2292 pc = s->cs_base + eip;
2293 tb = s->tb;
2294 /* NOTE: we handle the case where the TB spans two pages here */
2295 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2296 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2297 /* jump to same page: we can use a direct jump */
2298 tcg_gen_goto_tb(tb_num);
2299 gen_jmp_im(eip);
2300 tcg_gen_exit_tb((long)tb + tb_num);
2301 } else {
2302 /* jump to another page: currently not optimized */
2303 gen_jmp_im(eip);
2304 gen_eob(s);
2305 }
2306 }
2307
2308 static inline void gen_jcc(DisasContext *s, int b,
2309 target_ulong val, target_ulong next_eip)
2310 {
2311 int l1, l2, cc_op;
2312
2313 cc_op = s->cc_op;
2314 if (s->cc_op != CC_OP_DYNAMIC) {
2315 gen_op_set_cc_op(s->cc_op);
2316 s->cc_op = CC_OP_DYNAMIC;
2317 }
2318 if (s->jmp_opt) {
2319 l1 = gen_new_label();
2320 gen_jcc1(s, cc_op, b, l1);
2321
2322 gen_goto_tb(s, 0, next_eip);
2323
2324 gen_set_label(l1);
2325 gen_goto_tb(s, 1, val);
2326 s->is_jmp = 3;
2327 } else {
2328
2329 l1 = gen_new_label();
2330 l2 = gen_new_label();
2331 gen_jcc1(s, cc_op, b, l1);
2332
2333 gen_jmp_im(next_eip);
2334 tcg_gen_br(l2);
2335
2336 gen_set_label(l1);
2337 gen_jmp_im(val);
2338 gen_set_label(l2);
2339 gen_eob(s);
2340 }
2341 }
2342
2343 static void gen_setcc(DisasContext *s, int b)
2344 {
2345 int inv, jcc_op, l1;
2346 TCGv t0;
2347
2348 if (is_fast_jcc_case(s, b)) {
2349 /* nominal case: we use a jump */
2350 /* XXX: make it faster by adding new instructions in TCG */
2351 t0 = tcg_temp_local_new();
2352 tcg_gen_movi_tl(t0, 0);
2353 l1 = gen_new_label();
2354 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2355 tcg_gen_movi_tl(t0, 1);
2356 gen_set_label(l1);
2357 tcg_gen_mov_tl(cpu_T[0], t0);
2358 tcg_temp_free(t0);
2359 } else {
2360 /* slow case: it is more efficient not to generate a jump,
2361 although it is questionnable whether this optimization is
2362 worth to */
2363 inv = b & 1;
2364 jcc_op = (b >> 1) & 7;
2365 gen_setcc_slow_T0(s, jcc_op);
2366 if (inv) {
2367 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2368 }
2369 }
2370 }
2371
2372 static inline void gen_op_movl_T0_seg(int seg_reg)
2373 {
2374 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2375 offsetof(CPUX86State,segs[seg_reg].selector));
2376 }
2377
2378 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2379 {
2380 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2381 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2382 offsetof(CPUX86State,segs[seg_reg].selector));
2383 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2384 tcg_gen_st_tl(cpu_T[0], cpu_env,
2385 offsetof(CPUX86State,segs[seg_reg].base));
2386 }
2387
2388 /* move T0 to seg_reg and compute if the CPU state may change. Never
2389 call this function with seg_reg == R_CS */
2390 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2391 {
2392 if (s->pe && !s->vm86) {
2393 /* XXX: optimize by finding processor state dynamically */
2394 if (s->cc_op != CC_OP_DYNAMIC)
2395 gen_op_set_cc_op(s->cc_op);
2396 gen_jmp_im(cur_eip);
2397 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2398 gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
2399 /* abort translation because the addseg value may change or
2400 because ss32 may change. For R_SS, translation must always
2401 stop as a special handling must be done to disable hardware
2402 interrupts for the next instruction */
2403 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2404 s->is_jmp = 3;
2405 } else {
2406 gen_op_movl_seg_T0_vm(seg_reg);
2407 if (seg_reg == R_SS)
2408 s->is_jmp = 3;
2409 }
2410 }
2411
2412 static inline int svm_is_rep(int prefixes)
2413 {
2414 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2415 }
2416
2417 static inline void
2418 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2419 uint32_t type, uint64_t param)
2420 {
2421 /* no SVM activated; fast case */
2422 if (likely(!(s->flags & HF_SVMI_MASK)))
2423 return;
2424 if (s->cc_op != CC_OP_DYNAMIC)
2425 gen_op_set_cc_op(s->cc_op);
2426 gen_jmp_im(pc_start - s->cs_base);
2427 gen_helper_svm_check_intercept_param(tcg_const_i32(type),
2428 tcg_const_i64(param));
2429 }
2430
2431 static inline void
2432 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2433 {
2434 gen_svm_check_intercept_param(s, pc_start, type, 0);
2435 }
2436
2437 static inline void gen_stack_update(DisasContext *s, int addend)
2438 {
2439 #ifdef TARGET_X86_64
2440 if (CODE64(s)) {
2441 gen_op_add_reg_im(2, R_ESP, addend);
2442 } else
2443 #endif
2444 if (s->ss32) {
2445 gen_op_add_reg_im(1, R_ESP, addend);
2446 } else {
2447 gen_op_add_reg_im(0, R_ESP, addend);
2448 }
2449 }
2450
2451 /* generate a push. It depends on ss32, addseg and dflag */
2452 static void gen_push_T0(DisasContext *s)
2453 {
2454 #ifdef TARGET_X86_64
2455 if (CODE64(s)) {
2456 gen_op_movq_A0_reg(R_ESP);
2457 if (s->dflag) {
2458 gen_op_addq_A0_im(-8);
2459 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2460 } else {
2461 gen_op_addq_A0_im(-2);
2462 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2463 }
2464 gen_op_mov_reg_A0(2, R_ESP);
2465 } else
2466 #endif
2467 {
2468 gen_op_movl_A0_reg(R_ESP);
2469 if (!s->dflag)
2470 gen_op_addl_A0_im(-2);
2471 else
2472 gen_op_addl_A0_im(-4);
2473 if (s->ss32) {
2474 if (s->addseg) {
2475 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2476 gen_op_addl_A0_seg(R_SS);
2477 }
2478 } else {
2479 gen_op_andl_A0_ffff();
2480 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2481 gen_op_addl_A0_seg(R_SS);
2482 }
2483 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2484 if (s->ss32 && !s->addseg)
2485 gen_op_mov_reg_A0(1, R_ESP);
2486 else
2487 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2488 }
2489 }
2490
2491 /* generate a push. It depends on ss32, addseg and dflag */
2492 /* slower version for T1, only used for call Ev */
2493 static void gen_push_T1(DisasContext *s)
2494 {
2495 #ifdef TARGET_X86_64
2496 if (CODE64(s)) {
2497 gen_op_movq_A0_reg(R_ESP);
2498 if (s->dflag) {
2499 gen_op_addq_A0_im(-8);
2500 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2501 } else {
2502 gen_op_addq_A0_im(-2);
2503 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2504 }
2505 gen_op_mov_reg_A0(2, R_ESP);
2506 } else
2507 #endif
2508 {
2509 gen_op_movl_A0_reg(R_ESP);
2510 if (!s->dflag)
2511 gen_op_addl_A0_im(-2);
2512 else
2513 gen_op_addl_A0_im(-4);
2514 if (s->ss32) {
2515 if (s->addseg) {
2516 gen_op_addl_A0_seg(R_SS);
2517 }
2518 } else {
2519 gen_op_andl_A0_ffff();
2520 gen_op_addl_A0_seg(R_SS);
2521 }
2522 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2523
2524 if (s->ss32 && !s->addseg)
2525 gen_op_mov_reg_A0(1, R_ESP);
2526 else
2527 gen_stack_update(s, (-2) << s->dflag);
2528 }
2529 }
2530
2531 /* two step pop is necessary for precise exceptions */
2532 static void gen_pop_T0(DisasContext *s)
2533 {
2534 #ifdef TARGET_X86_64
2535 if (CODE64(s)) {
2536 gen_op_movq_A0_reg(R_ESP);
2537 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2538 } else
2539 #endif
2540 {
2541 gen_op_movl_A0_reg(R_ESP);
2542 if (s->ss32) {
2543 if (s->addseg)
2544 gen_op_addl_A0_seg(R_SS);
2545 } else {
2546 gen_op_andl_A0_ffff();
2547 gen_op_addl_A0_seg(R_SS);
2548 }
2549 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2550 }
2551 }
2552
2553 static void gen_pop_update(DisasContext *s)
2554 {
2555 #ifdef TARGET_X86_64
2556 if (CODE64(s) && s->dflag) {
2557 gen_stack_update(s, 8);
2558 } else
2559 #endif
2560 {
2561 gen_stack_update(s, 2 << s->dflag);
2562 }
2563 }
2564
2565 static void gen_stack_A0(DisasContext *s)
2566 {
2567 gen_op_movl_A0_reg(R_ESP);
2568 if (!s->ss32)
2569 gen_op_andl_A0_ffff();
2570 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2571 if (s->addseg)
2572 gen_op_addl_A0_seg(R_SS);
2573 }
2574
2575 /* NOTE: wrap around in 16 bit not fully handled */
2576 static void gen_pusha(DisasContext *s)
2577 {
2578 int i;
2579 gen_op_movl_A0_reg(R_ESP);
2580 gen_op_addl_A0_im(-16 << s->dflag);
2581 if (!s->ss32)
2582 gen_op_andl_A0_ffff();
2583 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2584 if (s->addseg)
2585 gen_op_addl_A0_seg(R_SS);
2586 for(i = 0;i < 8; i++) {
2587 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2588 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2589 gen_op_addl_A0_im(2 << s->dflag);
2590 }
2591 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2592 }
2593
2594 /* NOTE: wrap around in 16 bit not fully handled */
2595 static void gen_popa(DisasContext *s)
2596 {
2597 int i;
2598 gen_op_movl_A0_reg(R_ESP);
2599 if (!s->ss32)
2600 gen_op_andl_A0_ffff();
2601 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2602 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2603 if (s->addseg)
2604 gen_op_addl_A0_seg(R_SS);
2605 for(i = 0;i < 8; i++) {
2606 /* ESP is not reloaded */
2607 if (i != 3) {
2608 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2609 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2610 }
2611 gen_op_addl_A0_im(2 << s->dflag);
2612 }
2613 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2614 }
2615
2616 static void gen_enter(DisasContext *s, int esp_addend, int level)
2617 {
2618 int ot, opsize;
2619
2620 level &= 0x1f;
2621 #ifdef TARGET_X86_64
2622 if (CODE64(s)) {
2623 ot = s->dflag ? OT_QUAD : OT_WORD;
2624 opsize = 1 << ot;
2625
2626 gen_op_movl_A0_reg(R_ESP);
2627 gen_op_addq_A0_im(-opsize);
2628 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2629
2630 /* push bp */
2631 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2632 gen_op_st_T0_A0(ot + s->mem_index);
2633 if (level) {
2634 /* XXX: must save state */
2635 gen_helper_enter64_level(tcg_const_i32(level),
2636 tcg_const_i32((ot == OT_QUAD)),
2637 cpu_T[1]);
2638 }
2639 gen_op_mov_reg_T1(ot, R_EBP);
2640 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2641 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2642 } else
2643 #endif
2644 {
2645 ot = s->dflag + OT_WORD;
2646 opsize = 2 << s->dflag;
2647
2648 gen_op_movl_A0_reg(R_ESP);
2649 gen_op_addl_A0_im(-opsize);
2650 if (!s->ss32)
2651 gen_op_andl_A0_ffff();
2652 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2653 if (s->addseg)
2654 gen_op_addl_A0_seg(R_SS);
2655 /* push bp */
2656 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2657 gen_op_st_T0_A0(ot + s->mem_index);
2658 if (level) {
2659 /* XXX: must save state */
2660 gen_helper_enter_level(tcg_const_i32(level),
2661 tcg_const_i32(s->dflag),
2662 cpu_T[1]);
2663 }
2664 gen_op_mov_reg_T1(ot, R_EBP);
2665 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2666 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2667 }
2668 }
2669
2670 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2671 {
2672 if (s->cc_op != CC_OP_DYNAMIC)
2673 gen_op_set_cc_op(s->cc_op);
2674 gen_jmp_im(cur_eip);
2675 gen_helper_raise_exception(tcg_const_i32(trapno));
2676 s->is_jmp = 3;
2677 }
2678
2679 /* an interrupt is different from an exception because of the
2680 privilege checks */
2681 static void gen_interrupt(DisasContext *s, int intno,
2682 target_ulong cur_eip, target_ulong next_eip)
2683 {
2684 if (s->cc_op != CC_OP_DYNAMIC)
2685 gen_op_set_cc_op(s->cc_op);
2686 gen_jmp_im(cur_eip);
2687 gen_helper_raise_interrupt(tcg_const_i32(intno),
2688 tcg_const_i32(next_eip - cur_eip));
2689 s->is_jmp = 3;
2690 }
2691
2692 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2693 {
2694 if (s->cc_op != CC_OP_DYNAMIC)
2695 gen_op_set_cc_op(s->cc_op);
2696 gen_jmp_im(cur_eip);
2697 gen_helper_debug();
2698 s->is_jmp = 3;
2699 }
2700
2701 /* generate a generic end of block. Trace exception is also generated
2702 if needed */
2703 static void gen_eob(DisasContext *s)
2704 {
2705 if (s->cc_op != CC_OP_DYNAMIC)
2706 gen_op_set_cc_op(s->cc_op);
2707 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2708 gen_helper_reset_inhibit_irq();
2709 }
2710 if (s->tb->flags & HF_RF_MASK) {
2711 gen_helper_reset_rf();
2712 }
2713 if (s->singlestep_enabled) {
2714 gen_helper_debug();
2715 } else if (s->tf) {
2716 gen_helper_single_step();
2717 } else {
2718 tcg_gen_exit_tb(0);
2719 }
2720 s->is_jmp = 3;
2721 }
2722
2723 /* generate a jump to eip. No segment change must happen before as a
2724 direct call to the next block may occur */
2725 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2726 {
2727 if (s->jmp_opt) {
2728 if (s->cc_op != CC_OP_DYNAMIC) {
2729 gen_op_set_cc_op(s->cc_op);
2730 s->cc_op = CC_OP_DYNAMIC;
2731 }
2732 gen_goto_tb(s, tb_num, eip);
2733 s->is_jmp = 3;
2734 } else {
2735 gen_jmp_im(eip);
2736 gen_eob(s);
2737 }
2738 }
2739
2740 static void gen_jmp(DisasContext *s, target_ulong eip)
2741 {
2742 gen_jmp_tb(s, eip, 0);
2743 }
2744
2745 static inline void gen_ldq_env_A0(int idx, int offset)
2746 {
2747 int mem_index = (idx >> 2) - 1;
2748 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2749 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2750 }
2751
2752 static inline void gen_stq_env_A0(int idx, int offset)
2753 {
2754 int mem_index = (idx >> 2) - 1;
2755 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2756 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2757 }
2758
2759 static inline void gen_ldo_env_A0(int idx, int offset)
2760 {
2761 int mem_index = (idx >> 2) - 1;
2762 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2763 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2764 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2765 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2766 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2767 }
2768
2769 static inline void gen_sto_env_A0(int idx, int offset)
2770 {
2771 int mem_index = (idx >> 2) - 1;
2772 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2773 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2774 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2775 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2776 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2777 }
2778
2779 static inline void gen_op_movo(int d_offset, int s_offset)
2780 {
2781 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2782 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2783 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2784 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2785 }
2786
2787 static inline void gen_op_movq(int d_offset, int s_offset)
2788 {
2789 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2790 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2791 }
2792
2793 static inline void gen_op_movl(int d_offset, int s_offset)
2794 {
2795 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2796 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2797 }
2798
2799 static inline void gen_op_movq_env_0(int d_offset)
2800 {
2801 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2802 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2803 }
2804
2805 #define SSE_SPECIAL ((void *)1)
2806 #define SSE_DUMMY ((void *)2)
2807
2808 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2809 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2810 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2811
2812 static void *sse_op_table1[256][4] = {
2813 /* 3DNow! extensions */
2814 [0x0e] = { SSE_DUMMY }, /* femms */
2815 [0x0f] = { SSE_DUMMY }, /* pf... */
2816 /* pure SSE operations */
2817 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2818 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2819 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2820 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2821 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2822 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2823 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2824 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2825
2826 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2827 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2828 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2829 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
2830 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2831 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2832 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2833 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2834 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2835 [0x51] = SSE_FOP(sqrt),
2836 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2837 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2838 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2839 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2840 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2841 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2842 [0x58] = SSE_FOP(add),
2843 [0x59] = SSE_FOP(mul),
2844 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2845 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2846 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2847 [0x5c] = SSE_FOP(sub),
2848 [0x5d] = SSE_FOP(min),
2849 [0x5e] = SSE_FOP(div),
2850 [0x5f] = SSE_FOP(max),
2851
2852 [0xc2] = SSE_FOP(cmpeq),
2853 [0xc6] = { gen_helper_shufps, gen_helper_shufpd },
2854
2855 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2856 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2857
2858 /* MMX ops and their SSE extensions */
2859 [0x60] = MMX_OP2(punpcklbw),
2860 [0x61] = MMX_OP2(punpcklwd),
2861 [0x62] = MMX_OP2(punpckldq),
2862 [0x63] = MMX_OP2(packsswb),
2863 [0x64] = MMX_OP2(pcmpgtb),
2864 [0x65] = MMX_OP2(pcmpgtw),
2865 [0x66] = MMX_OP2(pcmpgtl),
2866 [0x67] = MMX_OP2(packuswb),
2867 [0x68] = MMX_OP2(punpckhbw),
2868 [0x69] = MMX_OP2(punpckhwd),
2869 [0x6a] = MMX_OP2(punpckhdq),
2870 [0x6b] = MMX_OP2(packssdw),
2871 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2872 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
2873 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2874 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2875 [0x70] = { gen_helper_pshufw_mmx,
2876 gen_helper_pshufd_xmm,
2877 gen_helper_pshufhw_xmm,
2878 gen_helper_pshuflw_xmm },
2879 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2880 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2881 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2882 [0x74] = MMX_OP2(pcmpeqb),
2883 [0x75] = MMX_OP2(pcmpeqw),
2884 [0x76] = MMX_OP2(pcmpeql),
2885 [0x77] = { SSE_DUMMY }, /* emms */
2886 [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
2887 [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
2888 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2889 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
2890 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2891 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2892 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2893 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2894 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
2895 [0xd1] = MMX_OP2(psrlw),
2896 [0xd2] = MMX_OP2(psrld),
2897 [0xd3] = MMX_OP2(psrlq),
2898 [0xd4] = MMX_OP2(paddq),
2899 [0xd5] = MMX_OP2(pmullw),
2900 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2901 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2902 [0xd8] = MMX_OP2(psubusb),
2903 [0xd9] = MMX_OP2(psubusw),
2904 [0xda] = MMX_OP2(pminub),
2905 [0xdb] = MMX_OP2(pand),
2906 [0xdc] = MMX_OP2(paddusb),
2907 [0xdd] = MMX_OP2(paddusw),
2908 [0xde] = MMX_OP2(pmaxub),
2909 [0xdf] = MMX_OP2(pandn),
2910 [0xe0] = MMX_OP2(pavgb),
2911 [0xe1] = MMX_OP2(psraw),
2912 [0xe2] = MMX_OP2(psrad),
2913 [0xe3] = MMX_OP2(pavgw),
2914 [0xe4] = MMX_OP2(pmulhuw),
2915 [0xe5] = MMX_OP2(pmulhw),
2916 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2917 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2918 [0xe8] = MMX_OP2(psubsb),
2919 [0xe9] = MMX_OP2(psubsw),
2920 [0xea] = MMX_OP2(pminsw),
2921 [0xeb] = MMX_OP2(por),
2922 [0xec] = MMX_OP2(paddsb),
2923 [0xed] = MMX_OP2(paddsw),
2924 [0xee] = MMX_OP2(pmaxsw),
2925 [0xef] = MMX_OP2(pxor),
2926 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2927 [0xf1] = MMX_OP2(psllw),
2928 [0xf2] = MMX_OP2(pslld),
2929 [0xf3] = MMX_OP2(psllq),
2930 [0xf4] = MMX_OP2(pmuludq),
2931 [0xf5] = MMX_OP2(pmaddwd),
2932 [0xf6] = MMX_OP2(psadbw),
2933 [0xf7] = MMX_OP2(maskmov),
2934 [0xf8] = MMX_OP2(psubb),
2935 [0xf9] = MMX_OP2(psubw),
2936 [0xfa] = MMX_OP2(psubl),
2937 [0xfb] = MMX_OP2(psubq),
2938 [0xfc] = MMX_OP2(paddb),
2939 [0xfd] = MMX_OP2(paddw),
2940 [0xfe] = MMX_OP2(paddl),
2941 };
2942
2943 static void *sse_op_table2[3 * 8][2] = {
2944 [0 + 2] = MMX_OP2(psrlw),
2945 [0 + 4] = MMX_OP2(psraw),
2946 [0 + 6] = MMX_OP2(psllw),
2947 [8 + 2] = MMX_OP2(psrld),
2948 [8 + 4] = MMX_OP2(psrad),
2949 [8 + 6] = MMX_OP2(pslld),
2950 [16 + 2] = MMX_OP2(psrlq),
2951 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
2952 [16 + 6] = MMX_OP2(psllq),
2953 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
2954 };
2955
2956 static void *sse_op_table3[4 * 3] = {
2957 gen_helper_cvtsi2ss,
2958 gen_helper_cvtsi2sd,
2959 X86_64_ONLY(gen_helper_cvtsq2ss),
2960 X86_64_ONLY(gen_helper_cvtsq2sd),
2961
2962 gen_helper_cvttss2si,
2963 gen_helper_cvttsd2si,
2964 X86_64_ONLY(gen_helper_cvttss2sq),
2965 X86_64_ONLY(gen_helper_cvttsd2sq),
2966
2967 gen_helper_cvtss2si,
2968 gen_helper_cvtsd2si,
2969 X86_64_ONLY(gen_helper_cvtss2sq),
2970 X86_64_ONLY(gen_helper_cvtsd2sq),
2971 };
2972
2973 static void *sse_op_table4[8][4] = {
2974 SSE_FOP(cmpeq),
2975 SSE_FOP(cmplt),
2976 SSE_FOP(cmple),
2977 SSE_FOP(cmpunord),
2978 SSE_FOP(cmpneq),
2979 SSE_FOP(cmpnlt),
2980 SSE_FOP(cmpnle),
2981 SSE_FOP(cmpord),
2982 };
2983
2984 static void *sse_op_table5[256] = {
2985 [0x0c] = gen_helper_pi2fw,
2986 [0x0d] = gen_helper_pi2fd,
2987 [0x1c] = gen_helper_pf2iw,
2988 [0x1d] = gen_helper_pf2id,
2989 [0x8a] = gen_helper_pfnacc,
2990 [0x8e] = gen_helper_pfpnacc,
2991 [0x90] = gen_helper_pfcmpge,
2992 [0x94] = gen_helper_pfmin,
2993 [0x96] = gen_helper_pfrcp,
2994 [0x97] = gen_helper_pfrsqrt,
2995 [0x9a] = gen_helper_pfsub,
2996 [0x9e] = gen_helper_pfadd,
2997 [0xa0] = gen_helper_pfcmpgt,
2998 [0xa4] = gen_helper_pfmax,
2999 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
3000 [0xa7] = gen_helper_movq, /* pfrsqit1 */
3001 [0xaa] = gen_helper_pfsubr,
3002 [0xae] = gen_helper_pfacc,
3003 [0xb0] = gen_helper_pfcmpeq,
3004 [0xb4] = gen_helper_pfmul,
3005 [0xb6] = gen_helper_movq, /* pfrcpit2 */
3006 [0xb7] = gen_helper_pmulhrw_mmx,
3007 [0xbb] = gen_helper_pswapd,
3008 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3009 };
3010
3011 struct sse_op_helper_s {
3012 void *op[2]; uint32_t ext_mask;
3013 };
3014 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3015 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3016 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3017 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3018 static struct sse_op_helper_s sse_op_table6[256] = {
3019 [0x00] = SSSE3_OP(pshufb),
3020 [0x01] = SSSE3_OP(phaddw),
3021 [0x02] = SSSE3_OP(phaddd),
3022 [0x03] = SSSE3_OP(phaddsw),
3023 [0x04] = SSSE3_OP(pmaddubsw),
3024 [0x05] = SSSE3_OP(phsubw),
3025 [0x06] = SSSE3_OP(phsubd),
3026 [0x07] = SSSE3_OP(phsubsw),
3027 [0x08] = SSSE3_OP(psignb),
3028 [0x09] = SSSE3_OP(psignw),
3029 [0x0a] = SSSE3_OP(psignd),
3030 [0x0b] = SSSE3_OP(pmulhrsw),
3031 [0x10] = SSE41_OP(pblendvb),
3032 [0x14] = SSE41_OP(blendvps),
3033 [0x15] = SSE41_OP(blendvpd),
3034 [0x17] = SSE41_OP(ptest),
3035 [0x1c] = SSSE3_OP(pabsb),
3036 [0x1d] = SSSE3_OP(pabsw),
3037 [0x1e] = SSSE3_OP(pabsd),
3038 [0x20] = SSE41_OP(pmovsxbw),
3039 [0x21] = SSE41_OP(pmovsxbd),
3040 [0x22] = SSE41_OP(pmovsxbq),
3041 [0x23] = SSE41_OP(pmovsxwd),
3042 [0x24] = SSE41_OP(pmovsxwq),
3043 [0x25] = SSE41_OP(pmovsxdq),
3044 [0x28] = SSE41_OP(pmuldq),
3045 [0x29] = SSE41_OP(pcmpeqq),
3046 [0x2a] = SSE41_SPECIAL, /* movntqda */
3047 [0x2b] = SSE41_OP(packusdw),
3048 [0x30] = SSE41_OP(pmovzxbw),
3049 [0x31] = SSE41_OP(pmovzxbd),
3050 [0x32] = SSE41_OP(pmovzxbq),
3051 [0x33] = SSE41_OP(pmovzxwd),
3052 [0x34] = SSE41_OP(pmovzxwq),
3053 [0x35] = SSE41_OP(pmovzxdq),
3054 [0x37] = SSE42_OP(pcmpgtq),
3055 [0x38] = SSE41_OP(pminsb),
3056 [0x39] = SSE41_OP(pminsd),
3057 [0x3a] = SSE41_OP(pminuw),
3058 [0x3b] = SSE41_OP(pminud),
3059 [0x3c] = SSE41_OP(pmaxsb),
3060 [0x3d] = SSE41_OP(pmaxsd),
3061 [0x3e] = SSE41_OP(pmaxuw),
3062 [0x3f] = SSE41_OP(pmaxud),
3063 [0x40] = SSE41_OP(pmulld),
3064 [0x41] = SSE41_OP(phminposuw),
3065 };
3066
3067 static struct sse_op_helper_s sse_op_table7[256] = {
3068 [0x08] = SSE41_OP(roundps),
3069 [0x09] = SSE41_OP(roundpd),
3070 [0x0a] = SSE41_OP(roundss),
3071 [0x0b] = SSE41_OP(roundsd),
3072 [0x0c] = SSE41_OP(blendps),
3073 [0x0d] = SSE41_OP(blendpd),
3074 [0x0e] = SSE41_OP(pblendw),
3075 [0x0f] = SSSE3_OP(palignr),
3076 [0x14] = SSE41_SPECIAL, /* pextrb */
3077 [0x15] = SSE41_SPECIAL, /* pextrw */
3078 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3079 [0x17] = SSE41_SPECIAL, /* extractps */
3080 [0x20] = SSE41_SPECIAL, /* pinsrb */
3081 [0x21] = SSE41_SPECIAL, /* insertps */
3082 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3083 [0x40] = SSE41_OP(dpps),
3084 [0x41] = SSE41_OP(dppd),
3085 [0x42] = SSE41_OP(mpsadbw),
3086 [0x60] = SSE42_OP(pcmpestrm),
3087 [0x61] = SSE42_OP(pcmpestri),
3088 [0x62] = SSE42_OP(pcmpistrm),
3089 [0x63] = SSE42_OP(pcmpistri),
3090 };
3091
3092 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3093 {
3094 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3095 int modrm, mod, rm, reg, reg_addr, offset_addr;
3096 void *sse_op2;
3097
3098 b &= 0xff;
3099 if (s->prefix & PREFIX_DATA)
3100 b1 = 1;
3101 else if (s->prefix & PREFIX_REPZ)
3102 b1 = 2;
3103 else if (s->prefix & PREFIX_REPNZ)
3104 b1 = 3;
3105 else
3106 b1 = 0;
3107 sse_op2 = sse_op_table1[b][b1];
3108 if (!sse_op2)
3109 goto illegal_op;
3110 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3111 is_xmm = 1;
3112 } else {
3113 if (b1 == 0) {
3114 /* MMX case */
3115 is_xmm = 0;
3116 } else {
3117 is_xmm = 1;
3118 }
3119 }
3120 /* simple MMX/SSE operation */
3121 if (s->flags & HF_TS_MASK) {
3122 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3123 return;
3124 }
3125 if (s->flags & HF_EM_MASK) {
3126 illegal_op:
3127 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3128 return;
3129 }
3130 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3131 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3132 goto illegal_op;
3133 if (b == 0x0e) {
3134 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3135 goto illegal_op;
3136 /* femms */
3137 gen_helper_emms();
3138 return;
3139 }
3140 if (b == 0x77) {
3141 /* emms */
3142 gen_helper_emms();
3143 return;
3144 }
3145 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3146 the static cpu state) */
3147 if (!is_xmm) {
3148 gen_helper_enter_mmx();
3149 }
3150
3151 modrm = ldub_code(s->pc++);
3152 reg = ((modrm >> 3) & 7);
3153 if (is_xmm)
3154 reg |= rex_r;
3155 mod = (modrm >> 6) & 3;
3156 if (sse_op2 == SSE_SPECIAL) {
3157 b |= (b1 << 8);
3158 switch(b) {
3159 case 0x0e7: /* movntq */
3160 if (mod == 3)
3161 goto illegal_op;
3162 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3163 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3164 break;
3165 case 0x1e7: /* movntdq */
3166 case 0x02b: /* movntps */
3167 case 0x12b: /* movntps */
3168 if (mod == 3)
3169 goto illegal_op;
3170 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3171 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3172 break;
3173 case 0x3f0: /* lddqu */
3174 if (mod == 3)
3175 goto illegal_op;
3176 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3177 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3178 break;
3179 case 0x22b: /* movntss */
3180 case 0x32b: /* movntsd */
3181 if (mod == 3)
3182 goto illegal_op;
3183 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3184 if (b1 & 1) {
3185 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
3186 xmm_regs[reg]));
3187 } else {
3188 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3189 xmm_regs[reg].XMM_L(0)));
3190 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3191 }
3192 break;
3193 case 0x6e: /* movd mm, ea */
3194 #ifdef TARGET_X86_64
3195 if (s->dflag == 2) {
3196 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3197 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3198 } else
3199 #endif
3200 {
3201 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3202 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3203 offsetof(CPUX86State,fpregs[reg].mmx));
3204 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3205 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3206 }
3207 break;
3208 case 0x16e: /* movd xmm, ea */
3209 #ifdef TARGET_X86_64
3210 if (s->dflag == 2) {
3211 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3212 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3213 offsetof(CPUX86State,xmm_regs[reg]));
3214 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3215 } else
3216 #endif
3217 {
3218 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3219 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3220 offsetof(CPUX86State,xmm_regs[reg]));
3221 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3222 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3223 }
3224 break;
3225 case 0x6f: /* movq mm, ea */
3226 if (mod != 3) {
3227 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3228 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3229 } else {
3230 rm = (modrm & 7);
3231 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3232 offsetof(CPUX86State,fpregs[rm].mmx));
3233 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3234 offsetof(CPUX86State,fpregs[reg].mmx));
3235 }
3236 break;
3237 case 0x010: /* movups */
3238 case 0x110: /* movupd */
3239 case 0x028: /* movaps */
3240 case 0x128: /* movapd */
3241 case 0x16f: /* movdqa xmm, ea */
3242 case 0x26f: /* movdqu xmm, ea */
3243 if (mod != 3) {
3244 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3245 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3246 } else {
3247 rm = (modrm & 7) | REX_B(s);
3248 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3249 offsetof(CPUX86State,xmm_regs[rm]));
3250 }
3251 break;
3252 case 0x210: /* movss xmm, ea */
3253 if (mod != 3) {
3254 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3255 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3256 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3257 gen_op_movl_T0_0();
3258 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3259 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3260 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3261 } else {
3262 rm = (modrm & 7) | REX_B(s);
3263 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3264 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3265 }
3266 break;
3267 case 0x310: /* movsd xmm, ea */
3268 if (mod != 3) {
3269 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3270 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3271 gen_op_movl_T0_0();
3272 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3273 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3274 } else {
3275 rm = (modrm & 7) | REX_B(s);
3276 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3277 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3278 }
3279 break;
3280 case 0x012: /* movlps */
3281 case 0x112: /* movlpd */
3282 if (mod != 3) {
3283 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3284 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3285 } else {
3286 /* movhlps */
3287 rm = (modrm & 7) | REX_B(s);
3288 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3289 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3290 }
3291 break;
3292 case 0x212: /* movsldup */
3293 if (mod != 3) {
3294 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3295 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3296 } else {
3297 rm = (modrm & 7) | REX_B(s);
3298 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3299 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3300 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3301 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3302 }
3303 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3304 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3305 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3306 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3307 break;
3308 case 0x312: /* movddup */
3309 if (mod != 3) {
3310 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3311 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3312 } else {
3313 rm = (modrm & 7) | REX_B(s);
3314 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3315 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3316 }
3317 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3318 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3319 break;
3320 case 0x016: /* movhps */
3321 case 0x116: /* movhpd */
3322 if (mod != 3) {
3323 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3324 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3325 } else {
3326 /* movlhps */
3327 rm = (modrm & 7) | REX_B(s);
3328 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3329 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3330 }
3331 break;
3332 case 0x216: /* movshdup */
3333 if (mod != 3) {
3334 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3335 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3336 } else {
3337 rm = (modrm & 7) | REX_B(s);
3338 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3339 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3340 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3341 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3342 }
3343 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3344 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3345 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3346 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3347 break;
3348 case 0x178:
3349 case 0x378:
3350 {
3351 int bit_index, field_length;
3352
3353 if (b1 == 1 && reg != 0)
3354 goto illegal_op;
3355 field_length = ldub_code(s->pc++) & 0x3F;
3356 bit_index = ldub_code(s->pc++) & 0x3F;
3357 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3358 offsetof(CPUX86State,xmm_regs[reg]));
3359 if (b1 == 1)
3360 gen_helper_extrq_i(cpu_ptr0, tcg_const_i32(bit_index),
3361 tcg_const_i32(field_length));
3362 else
3363 gen_helper_insertq_i(cpu_ptr0, tcg_const_i32(bit_index),
3364 tcg_const_i32(field_length));
3365 }
3366 break;
3367 case 0x7e: /* movd ea, mm */
3368 #ifdef TARGET_X86_64
3369 if (s->dflag == 2) {
3370 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3371 offsetof(CPUX86State,fpregs[reg].mmx));
3372 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3373 } else
3374 #endif
3375 {
3376 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3377 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3378 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3379 }
3380 break;
3381 case 0x17e: /* movd ea, xmm */
3382 #ifdef TARGET_X86_64
3383 if (s->dflag == 2) {
3384 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3385 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3386 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3387 } else
3388 #endif
3389 {
3390 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3391 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3392 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3393 }
3394 break;
3395 case 0x27e: /* movq xmm, ea */
3396 if (mod != 3) {
3397 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3398 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3399 } else {
3400 rm = (modrm & 7) | REX_B(s);
3401 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3402 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3403 }
3404 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3405 break;
3406 case 0x7f: /* movq ea, mm */
3407 if (mod != 3) {
3408 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3409 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3410 } else {
3411 rm = (modrm & 7);
3412 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3413 offsetof(CPUX86State,fpregs[reg].mmx));
3414 }
3415 break;
3416 case 0x011: /* movups */
3417 case 0x111: /* movupd */
3418 case 0x029: /* movaps */
3419 case 0x129: /* movapd */
3420 case 0x17f: /* movdqa ea, xmm */
3421 case 0x27f: /* movdqu ea, xmm */
3422 if (mod != 3) {
3423 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3424 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3425 } else {
3426 rm = (modrm & 7) | REX_B(s);
3427 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3428 offsetof(CPUX86State,xmm_regs[reg]));
3429 }
3430 break;
3431 case 0x211: /* movss ea, xmm */
3432 if (mod != 3) {
3433 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3434 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3435 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3436 } else {
3437 rm = (modrm & 7) | REX_B(s);
3438 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3439 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3440 }
3441 break;
3442 case 0x311: /* movsd ea, xmm */
3443 if (mod != 3) {
3444 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3445 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3446 } else {
3447 rm = (modrm & 7) | REX_B(s);
3448 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3449 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3450 }
3451 break;
3452 case 0x013: /* movlps */
3453 case 0x113: /* movlpd */
3454 if (mod != 3) {
3455 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3456 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3457 } else {
3458 goto illegal_op;
3459 }
3460 break;
3461 case 0x017: /* movhps */
3462 case 0x117: /* movhpd */
3463 if (mod != 3) {
3464 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3465 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3466 } else {
3467 goto illegal_op;
3468 }
3469 break;
3470 case 0x71: /* shift mm, im */
3471 case 0x72:
3472 case 0x73:
3473 case 0x171: /* shift xmm, im */
3474 case 0x172:
3475 case 0x173:
3476 val = ldub_code(s->pc++);
3477 if (is_xmm) {
3478 gen_op_movl_T0_im(val);
3479 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3480 gen_op_movl_T0_0();
3481 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3482 op1_offset = offsetof(CPUX86State,xmm_t0);
3483 } else {
3484 gen_op_movl_T0_im(val);
3485 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3486 gen_op_movl_T0_0();
3487 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3488 op1_offset = offsetof(CPUX86State,mmx_t0);
3489 }
3490 sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3491 if (!sse_op2)
3492 goto illegal_op;
3493 if (is_xmm) {
3494 rm = (modrm & 7) | REX_B(s);
3495 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3496 } else {
3497 rm = (modrm & 7);
3498 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3499 }
3500 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3501 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3502 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3503 break;
3504 case 0x050: /* movmskps */
3505 rm = (modrm & 7) | REX_B(s);
3506 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3507 offsetof(CPUX86State,xmm_regs[rm]));
3508 gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0);
3509 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3510 gen_op_mov_reg_T0(OT_LONG, reg);
3511 break;
3512 case 0x150: /* movmskpd */
3513 rm = (modrm & 7) | REX_B(s);
3514 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3515 offsetof(CPUX86State,xmm_regs[rm]));
3516 gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0);
3517 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3518 gen_op_mov_reg_T0(OT_LONG, reg);
3519 break;
3520 case 0x02a: /* cvtpi2ps */
3521 case 0x12a: /* cvtpi2pd */
3522 gen_helper_enter_mmx();
3523 if (mod != 3) {
3524 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3525 op2_offset = offsetof(CPUX86State,mmx_t0);
3526 gen_ldq_env_A0(s->mem_index, op2_offset);
3527 } else {
3528 rm = (modrm & 7);
3529 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3530 }
3531 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3532 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3533 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3534 switch(b >> 8) {
3535 case 0x0:
3536 gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1);
3537 break;
3538 default:
3539 case 0x1:
3540 gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1);
3541 break;
3542 }
3543 break;
3544 case 0x22a: /* cvtsi2ss */
3545 case 0x32a: /* cvtsi2sd */
3546 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3547 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3548 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3549 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3550 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3551 if (ot == OT_LONG) {
3552 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3553 ((void (*)(TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_tmp2_i32);
3554 } else {
3555 ((void (*)(TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_T[0]);
3556 }
3557 break;
3558 case 0x02c: /* cvttps2pi */
3559 case 0x12c: /* cvttpd2pi */
3560 case 0x02d: /* cvtps2pi */
3561 case 0x12d: /* cvtpd2pi */
3562 gen_helper_enter_mmx();
3563 if (mod != 3) {
3564 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3565 op2_offset = offsetof(CPUX86State,xmm_t0);
3566 gen_ldo_env_A0(s->mem_index, op2_offset);
3567 } else {
3568 rm = (modrm & 7) | REX_B(s);
3569 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3570 }
3571 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3572 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3573 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3574 switch(b) {
3575 case 0x02c:
3576 gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1);
3577 break;
3578 case 0x12c:
3579 gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1);
3580 break;
3581 case 0x02d:
3582 gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1);
3583 break;
3584 case 0x12d:
3585 gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1);
3586 break;
3587 }
3588 break;
3589 case 0x22c: /* cvttss2si */
3590 case 0x32c: /* cvttsd2si */
3591 case 0x22d: /* cvtss2si */
3592 case 0x32d: /* cvtsd2si */
3593 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3594 if (mod != 3) {
3595 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3596 if ((b >> 8) & 1) {
3597 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3598 } else {
3599 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3600 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3601 }
3602 op2_offset = offsetof(CPUX86State,xmm_t0);
3603 } else {
3604 rm = (modrm & 7) | REX_B(s);
3605 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3606 }
3607 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3608 (b & 1) * 4];
3609 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3610 if (ot == OT_LONG) {
3611 ((void (*)(TCGv_i32, TCGv_ptr))sse_op2)(cpu_tmp2_i32, cpu_ptr0);
3612 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3613 } else {
3614 ((void (*)(TCGv, TCGv_ptr))sse_op2)(cpu_T[0], cpu_ptr0);
3615 }
3616 gen_op_mov_reg_T0(ot, reg);
3617 break;
3618 case 0xc4: /* pinsrw */
3619 case 0x1c4:
3620 s->rip_offset = 1;
3621 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3622 val = ldub_code(s->pc++);
3623 if (b1) {
3624 val &= 7;
3625 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3626 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3627 } else {
3628 val &= 3;
3629 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3630 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3631 }
3632 break;
3633 case 0xc5: /* pextrw */
3634 case 0x1c5:
3635 if (mod != 3)
3636 goto illegal_op;
3637 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3638 val = ldub_code(s->pc++);
3639 if (b1) {
3640 val &= 7;
3641 rm = (modrm & 7) | REX_B(s);
3642 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3643 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3644 } else {
3645 val &= 3;
3646 rm = (modrm & 7);
3647 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3648 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3649 }
3650 reg = ((modrm >> 3) & 7) | rex_r;
3651 gen_op_mov_reg_T0(ot, reg);
3652 break;
3653 case 0x1d6: /* movq ea, xmm */
3654 if (mod != 3) {
3655 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3656 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3657 } else {
3658 rm = (modrm & 7) | REX_B(s);
3659 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3660 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3661 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3662 }
3663 break;
3664 case 0x2d6: /* movq2dq */
3665 gen_helper_enter_mmx();
3666 rm = (modrm & 7);
3667 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3668 offsetof(CPUX86State,fpregs[rm].mmx));
3669 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3670 break;
3671 case 0x3d6: /* movdq2q */
3672 gen_helper_enter_mmx();
3673 rm = (modrm & 7) | REX_B(s);
3674 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3675 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3676 break;
3677 case 0xd7: /* pmovmskb */
3678 case 0x1d7:
3679 if (mod != 3)
3680 goto illegal_op;
3681 if (b1) {
3682 rm = (modrm & 7) | REX_B(s);
3683 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3684 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0);
3685 } else {
3686 rm = (modrm & 7);
3687 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3688 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0);
3689 }
3690 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3691 reg = ((modrm >> 3) & 7) | rex_r;
3692 gen_op_mov_reg_T0(OT_LONG, reg);
3693 break;
3694 case 0x138:
3695 if (s->prefix & PREFIX_REPNZ)
3696 goto crc32;
3697 case 0x038:
3698 b = modrm;
3699 modrm = ldub_code(s->pc++);
3700 rm = modrm & 7;
3701 reg = ((modrm >> 3) & 7) | rex_r;
3702 mod = (modrm >> 6) & 3;
3703
3704 sse_op2 = sse_op_table6[b].op[b1];
3705 if (!sse_op2)
3706 goto illegal_op;
3707 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3708 goto illegal_op;
3709
3710 if (b1) {
3711 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3712 if (mod == 3) {
3713 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3714 } else {
3715 op2_offset = offsetof(CPUX86State,xmm_t0);
3716 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3717 switch (b) {
3718 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3719 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3720 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3721 gen_ldq_env_A0(s->mem_index, op2_offset +
3722 offsetof(XMMReg, XMM_Q(0)));
3723 break;
3724 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3725 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3726 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3727 (s->mem_index >> 2) - 1);
3728 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3729 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3730 offsetof(XMMReg, XMM_L(0)));
3731 break;
3732 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3733 tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3734 (s->mem_index >> 2) - 1);
3735 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3736 offsetof(XMMReg, XMM_W(0)));
3737 break;
3738 case 0x2a: /* movntqda */
3739 gen_ldo_env_A0(s->mem_index, op1_offset);
3740 return;
3741 default:
3742 gen_ldo_env_A0(s->mem_index, op2_offset);
3743 }
3744 }
3745 } else {
3746 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3747 if (mod == 3) {
3748 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3749 } else {
3750 op2_offset = offsetof(CPUX86State,mmx_t0);
3751 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3752 gen_ldq_env_A0(s->mem_index, op2_offset);
3753 }
3754 }
3755 if (sse_op2 == SSE_SPECIAL)
3756 goto illegal_op;
3757
3758 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3759 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3760 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3761
3762 if (b == 0x17)
3763 s->cc_op = CC_OP_EFLAGS;
3764 break;
3765 case 0x338: /* crc32 */
3766 crc32:
3767 b = modrm;
3768 modrm = ldub_code(s->pc++);
3769 reg = ((modrm >> 3) & 7) | rex_r;
3770
3771 if (b != 0xf0 && b != 0xf1)
3772 goto illegal_op;
3773 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3774 goto illegal_op;
3775
3776 if (b == 0xf0)
3777 ot = OT_BYTE;
3778 else if (b == 0xf1 && s->dflag != 2)
3779 if (s->prefix & PREFIX_DATA)
3780 ot = OT_WORD;
3781 else
3782 ot = OT_LONG;
3783 else
3784 ot = OT_QUAD;
3785
3786 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3787 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3788 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3789 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3790 cpu_T[0], tcg_const_i32(8 << ot));
3791
3792 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3793 gen_op_mov_reg_T0(ot, reg);
3794 break;
3795 case 0x03a:
3796 case 0x13a:
3797 b = modrm;
3798 modrm = ldub_code(s->pc++);
3799 rm = modrm & 7;
3800 reg = ((modrm >> 3) & 7) | rex_r;
3801 mod = (modrm >> 6) & 3;
3802
3803 sse_op2 = sse_op_table7[b].op[b1];
3804 if (!sse_op2)
3805 goto illegal_op;
3806 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3807 goto illegal_op;
3808
3809 if (sse_op2 == SSE_SPECIAL) {
3810 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3811 rm = (modrm & 7) | REX_B(s);
3812 if (mod != 3)
3813 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3814 reg = ((modrm >> 3) & 7) | rex_r;
3815 val = ldub_code(s->pc++);
3816 switch (b) {
3817 case 0x14: /* pextrb */
3818 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3819 xmm_regs[reg].XMM_B(val & 15)));
3820 if (mod == 3)
3821 gen_op_mov_reg_T0(ot, rm);
3822 else
3823 tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3824 (s->mem_index >> 2) - 1);
3825 break;
3826 case 0x15: /* pextrw */
3827 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3828 xmm_regs[reg].XMM_W(val & 7)));
3829 if (mod == 3)
3830 gen_op_mov_reg_T0(ot, rm);
3831 else
3832 tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3833 (s->mem_index >> 2) - 1);
3834 break;
3835 case 0x16:
3836 if (ot == OT_LONG) { /* pextrd */
3837 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3838 offsetof(CPUX86State,
3839 xmm_regs[reg].XMM_L(val & 3)));
3840 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3841 if (mod == 3)
3842 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
3843 else
3844 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3845 (s->mem_index >> 2) - 1);
3846 } else { /* pextrq */
3847 #ifdef TARGET_X86_64
3848 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3849 offsetof(CPUX86State,
3850 xmm_regs[reg].XMM_Q(val & 1)));
3851 if (mod == 3)
3852 gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3853 else
3854 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3855 (s->mem_index >> 2) - 1);
3856 #else
3857 goto illegal_op;
3858 #endif
3859 }
3860 break;
3861 case 0x17: /* extractps */
3862 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3863 xmm_regs[reg].XMM_L(val & 3)));
3864 if (mod == 3)
3865 gen_op_mov_reg_T0(ot, rm);
3866 else
3867 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3868 (s->mem_index >> 2) - 1);
3869 break;
3870 case 0x20: /* pinsrb */
3871 if (mod == 3)
3872 gen_op_mov_TN_reg(OT_LONG, 0, rm);
3873 else
3874 tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
3875 (s->mem_index >> 2) - 1);
3876 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
3877 xmm_regs[reg].XMM_B(val & 15)));
3878 break;
3879 case 0x21: /* insertps */
3880 if (mod == 3) {
3881 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3882 offsetof(CPUX86State,xmm_regs[rm]
3883 .XMM_L((val >> 6) & 3)));
3884 } else {
3885 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3886 (s->mem_index >> 2) - 1);
3887 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3888 }
3889 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3890 offsetof(CPUX86State,xmm_regs[reg]
3891 .XMM_L((val >> 4) & 3)));
3892 if ((val >> 0) & 1)
3893 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3894 cpu_env, offsetof(CPUX86State,
3895 xmm_regs[reg].XMM_L(0)));
3896 if ((val >> 1) & 1)
3897 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3898 cpu_env, offsetof(CPUX86State,
3899 xmm_regs[reg].XMM_L(1)));
3900 if ((val >> 2) & 1)
3901 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3902 cpu_env, offsetof(CPUX86State,
3903 xmm_regs[reg].XMM_L(2)));
3904 if ((val >> 3) & 1)
3905 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3906 cpu_env, offsetof(CPUX86State,
3907 xmm_regs[reg].XMM_L(3)));
3908 break;
3909 case 0x22:
3910 if (ot == OT_LONG) { /* pinsrd */
3911 if (mod == 3)
3912 gen_op_mov_v_reg(ot, cpu_tmp0, rm);
3913 else
3914 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3915 (s->mem_index >> 2) - 1);
3916 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3917 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3918 offsetof(CPUX86State,
3919 xmm_regs[reg].XMM_L(val & 3)));
3920 } else { /* pinsrq */
3921 #ifdef TARGET_X86_64
3922 if (mod == 3)
3923 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
3924 else
3925 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
3926 (s->mem_index >> 2) - 1);
3927 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3928 offsetof(CPUX86State,
3929 xmm_regs[reg].XMM_Q(val & 1)));
3930 #else
3931 goto illegal_op;
3932 #endif
3933 }
3934 break;
3935 }
3936 return;
3937 }
3938
3939 if (b1) {
3940 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3941 if (mod == 3) {
3942 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3943 } else {
3944 op2_offset = offsetof(CPUX86State,xmm_t0);
3945 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3946 gen_ldo_env_A0(s->mem_index, op2_offset);
3947 }
3948 } else {
3949 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3950 if (mod == 3) {
3951 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3952 } else {
3953 op2_offset = offsetof(CPUX86State,mmx_t0);
3954 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3955 gen_ldq_env_A0(s->mem_index, op2_offset);
3956 }
3957 }
3958 val = ldub_code(s->pc++);
3959
3960 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
3961 s->cc_op = CC_OP_EFLAGS;
3962
3963 if (s->dflag == 2)
3964 /* The helper must use entire 64-bit gp registers */
3965 val |= 1 << 8;
3966 }
3967
3968 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3969 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3970 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3971 break;
3972 default:
3973 goto illegal_op;
3974 }
3975 } else {
3976 /* generic MMX or SSE operation */
3977 switch(b) {
3978 case 0x70: /* pshufx insn */
3979 case 0xc6: /* pshufx insn */
3980 case 0xc2: /* compare insns */
3981 s->rip_offset = 1;
3982 break;
3983 default:
3984 break;
3985 }
3986 if (is_xmm) {
3987 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3988 if (mod != 3) {
3989 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3990 op2_offset = offsetof(CPUX86State,xmm_t0);
3991 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
3992 b == 0xc2)) {
3993 /* specific case for SSE single instructions */
3994 if (b1 == 2) {
3995 /* 32 bit access */
3996 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3997 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3998 } else {
3999 /* 64 bit access */
4000 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
4001 }
4002 } else {
4003 gen_ldo_env_A0(s->mem_index, op2_offset);
4004 }
4005 } else {
4006 rm = (modrm & 7) | REX_B(s);
4007 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
4008 }
4009 } else {
4010 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4011 if (mod != 3) {
4012 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4013 op2_offset = offsetof(CPUX86State,mmx_t0);
4014 gen_ldq_env_A0(s->mem_index, op2_offset);
4015 } else {
4016 rm = (modrm & 7);
4017 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4018 }
4019 }
4020 switch(b) {
4021 case 0x0f: /* 3DNow! data insns */
4022 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
4023 goto illegal_op;
4024 val = ldub_code(s->pc++);
4025 sse_op2 = sse_op_table5[val];
4026 if (!sse_op2)
4027 goto illegal_op;
4028 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4029 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4030 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4031 break;
4032 case 0x70: /* pshufx insn */
4033 case 0xc6: /* pshufx insn */
4034 val = ldub_code(s->pc++);
4035 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4036 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4037 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4038 break;
4039 case 0xc2:
4040 /* compare insns */
4041 val = ldub_code(s->pc++);
4042 if (val >= 8)
4043 goto illegal_op;
4044 sse_op2 = sse_op_table4[val][b1];
4045 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4046 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4047 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4048 break;
4049 case 0xf7:
4050 /* maskmov : we must prepare A0 */
4051 if (mod != 3)
4052 goto illegal_op;
4053 #ifdef TARGET_X86_64
4054 if (s->aflag == 2) {
4055 gen_op_movq_A0_reg(R_EDI);
4056 } else
4057 #endif
4058 {
4059 gen_op_movl_A0_reg(R_EDI);
4060 if (s->aflag == 0)
4061 gen_op_andl_A0_ffff();
4062 }
4063 gen_add_A0_ds_seg(s);
4064
4065 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4066 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4067 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_ptr1, cpu_A0);
4068 break;
4069 default:
4070 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4071 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4072 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4073 break;
4074 }
4075 if (b == 0x2e || b == 0x2f) {
4076 s->cc_op = CC_OP_EFLAGS;
4077 }
4078 }
4079 }
4080
4081 /* convert one instruction. s->is_jmp is set if the translation must
4082 be stopped. Return the next pc value */
4083 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4084 {
4085 int b, prefixes, aflag, dflag;
4086 int shift, ot;
4087 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4088 target_ulong next_eip, tval;
4089 int rex_w, rex_r;
4090
4091 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
4092 tcg_gen_debug_insn_start(pc_start);
4093 s->pc = pc_start;
4094 prefixes = 0;
4095 aflag = s->code32;
4096 dflag = s->code32;
4097 s->override = -1;
4098 rex_w = -1;
4099 rex_r = 0;
4100 #ifdef TARGET_X86_64
4101 s->rex_x = 0;
4102 s->rex_b = 0;
4103 x86_64_hregs = 0;
4104 #endif
4105 s->rip_offset = 0; /* for relative ip address */
4106 next_byte:
4107 b = ldub_code(s->pc);
4108 s->pc++;
4109 /* check prefixes */
4110 #ifdef TARGET_X86_64
4111 if (CODE64(s)) {
4112 switch (b) {
4113 case 0xf3:
4114 prefixes |= PREFIX_REPZ;
4115 goto next_byte;
4116 case 0xf2:
4117 prefixes |= PREFIX_REPNZ;
4118 goto next_byte;
4119 case 0xf0:
4120 prefixes |= PREFIX_LOCK;
4121 goto next_byte;
4122 case 0x2e:
4123 s->override = R_CS;
4124 goto next_byte;
4125 case 0x36:
4126 s->override = R_SS;
4127 goto next_byte;
4128 case 0x3e:
4129 s->override = R_DS;
4130 goto next_byte;
4131 case 0x26:
4132 s->override = R_ES;
4133 goto next_byte;
4134 case 0x64:
4135 s->override = R_FS;
4136 goto next_byte;
4137 case 0x65:
4138 s->override = R_GS;
4139 goto next_byte;
4140 case 0x66:
4141 prefixes |= PREFIX_DATA;
4142 goto next_byte;
4143 case 0x67:
4144 prefixes |= PREFIX_ADR;
4145 goto next_byte;
4146 case 0x40 ... 0x4f:
4147 /* REX prefix */
4148 rex_w = (b >> 3) & 1;
4149 rex_r = (b & 0x4) << 1;
4150 s->rex_x = (b & 0x2) << 2;
4151 REX_B(s) = (b & 0x1) << 3;
4152 x86_64_hregs = 1; /* select uniform byte register addressing */
4153 goto next_byte;
4154 }
4155 if (rex_w == 1) {
4156 /* 0x66 is ignored if rex.w is set */
4157 dflag = 2;
4158 } else {
4159 if (prefixes & PREFIX_DATA)
4160 dflag ^= 1;
4161 }
4162 if (!(prefixes & PREFIX_ADR))
4163 aflag = 2;
4164 } else
4165 #endif
4166 {
4167 switch (b) {
4168 case 0xf3:
4169 prefixes |= PREFIX_REPZ;
4170 goto next_byte;
4171 case 0xf2:
4172 prefixes |= PREFIX_REPNZ;
4173 goto next_byte;
4174 case 0xf0:
4175 prefixes |= PREFIX_LOCK;
4176 goto next_byte;
4177 case 0x2e:
4178 s->override = R_CS;
4179 goto next_byte;
4180 case 0x36:
4181 s->override = R_SS;
4182 goto next_byte;
4183 case 0x3e:
4184 s->override = R_DS;
4185 goto next_byte;
4186 case 0x26:
4187 s->override = R_ES;
4188 goto next_byte;
4189 case 0x64:
4190 s->override = R_FS;
4191 goto next_byte;
4192 case 0x65:
4193 s->override = R_GS;
4194 goto next_byte;
4195 case 0x66:
4196 prefixes |= PREFIX_DATA;
4197 goto next_byte;
4198 case 0x67:
4199 prefixes |= PREFIX_ADR;
4200 goto next_byte;
4201 }
4202 if (prefixes & PREFIX_DATA)
4203 dflag ^= 1;
4204 if (prefixes & PREFIX_ADR)
4205 aflag ^= 1;
4206 }
4207
4208 s->prefix = prefixes;
4209 s->aflag = aflag;
4210 s->dflag = dflag;
4211
4212 /* lock generation */
4213 if (prefixes & PREFIX_LOCK)
4214 gen_helper_lock();
4215
4216 /* now check op code */
4217 reswitch:
4218 switch(b) {
4219 case 0x0f:
4220 /**************************/
4221 /* extended op code */
4222 b = ldub_code(s->pc++) | 0x100;
4223 goto reswitch;
4224
4225 /**************************/
4226 /* arith & logic */
4227 case 0x00 ... 0x05:
4228 case 0x08 ... 0x0d:
4229 case 0x10 ... 0x15:
4230 case 0x18 ... 0x1d:
4231 case 0x20 ... 0x25:
4232 case 0x28 ... 0x2d:
4233 case 0x30 ... 0x35:
4234 case 0x38 ... 0x3d:
4235 {
4236 int op, f, val;
4237 op = (b >> 3) & 7;
4238 f = (b >> 1) & 3;
4239
4240 if ((b & 1) == 0)
4241 ot = OT_BYTE;
4242 else
4243 ot = dflag + OT_WORD;
4244
4245 switch(f) {
4246 case 0: /* OP Ev, Gv */
4247 modrm = ldub_code(s->pc++);
4248 reg = ((modrm >> 3) & 7) | rex_r;
4249 mod = (modrm >> 6) & 3;
4250 rm = (modrm & 7) | REX_B(s);
4251 if (mod != 3) {
4252 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4253 opreg = OR_TMP0;
4254 } else if (op == OP_XORL && rm == reg) {
4255 xor_zero:
4256 /* xor reg, reg optimisation */
4257 gen_op_movl_T0_0();
4258 s->cc_op = CC_OP_LOGICB + ot;
4259 gen_op_mov_reg_T0(ot, reg);
4260 gen_op_update1_cc();
4261 break;
4262 } else {
4263 opreg = rm;
4264 }
4265 gen_op_mov_TN_reg(ot, 1, reg);
4266 gen_op(s, op, ot, opreg);
4267 break;
4268 case 1: /* OP Gv, Ev */
4269 modrm = ldub_code(s->pc++);
4270 mod = (modrm >> 6) & 3;
4271 reg = ((modrm >> 3) & 7) | rex_r;
4272 rm = (modrm & 7) | REX_B(s);
4273 if (mod != 3) {
4274 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4275 gen_op_ld_T1_A0(ot + s->mem_index);
4276 } else if (op == OP_XORL && rm == reg) {
4277 goto xor_zero;
4278 } else {
4279 gen_op_mov_TN_reg(ot, 1, rm);
4280 }
4281 gen_op(s, op, ot, reg);
4282 break;
4283 case 2: /* OP A, Iv */
4284 val = insn_get(s, ot);
4285 gen_op_movl_T1_im(val);
4286 gen_op(s, op, ot, OR_EAX);
4287 break;
4288 }
4289 }
4290 break;
4291
4292 case 0x82:
4293 if (CODE64(s))
4294 goto illegal_op;
4295 case 0x80: /* GRP1 */
4296 case 0x81:
4297 case 0x83:
4298 {
4299 int val;
4300
4301 if ((b & 1) == 0)
4302 ot = OT_BYTE;
4303 else
4304 ot = dflag + OT_WORD;
4305
4306 modrm = ldub_code(s->pc++);
4307 mod = (modrm >> 6) & 3;
4308 rm = (modrm & 7) | REX_B(s);
4309 op = (modrm >> 3) & 7;
4310
4311 if (mod != 3) {
4312 if (b == 0x83)
4313 s->rip_offset = 1;
4314 else
4315 s->rip_offset = insn_const_size(ot);
4316 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4317 opreg = OR_TMP0;
4318 } else {
4319 opreg = rm;
4320 }
4321
4322 switch(b) {
4323 default:
4324 case 0x80:
4325 case 0x81:
4326 case 0x82:
4327 val = insn_get(s, ot);
4328 break;
4329 case 0x83:
4330 val = (int8_t)insn_get(s, OT_BYTE);
4331 break;
4332 }
4333 gen_op_movl_T1_im(val);
4334 gen_op(s, op, ot, opreg);
4335 }
4336 break;
4337
4338 /**************************/
4339 /* inc, dec, and other misc arith */
4340 case 0x40 ... 0x47: /* inc Gv */
4341 ot = dflag ? OT_LONG : OT_WORD;
4342 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4343 break;
4344 case 0x48 ... 0x4f: /* dec Gv */
4345 ot = dflag ? OT_LONG : OT_WORD;
4346 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4347 break;
4348 case 0xf6: /* GRP3 */
4349 case 0xf7:
4350 if ((b & 1) == 0)
4351 ot = OT_BYTE;
4352 else
4353 ot = dflag + OT_WORD;
4354
4355 modrm = ldub_code(s->pc++);
4356 mod = (modrm >> 6) & 3;
4357 rm = (modrm & 7) | REX_B(s);
4358 op = (modrm >> 3) & 7;
4359 if (mod != 3) {
4360 if (op == 0)
4361 s->rip_offset = insn_const_size(ot);
4362 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4363 gen_op_ld_T0_A0(ot + s->mem_index);
4364 } else {
4365 gen_op_mov_TN_reg(ot, 0, rm);
4366 }
4367
4368 switch(op) {
4369 case 0: /* test */
4370 val = insn_get(s, ot);
4371 gen_op_movl_T1_im(val);
4372 gen_op_testl_T0_T1_cc();
4373 s->cc_op = CC_OP_LOGICB + ot;
4374 break;
4375 case 2: /* not */
4376 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
4377 if (mod != 3) {
4378 gen_op_st_T0_A0(ot + s->mem_index);
4379 } else {
4380 gen_op_mov_reg_T0(ot, rm);
4381 }
4382 break;
4383 case 3: /* neg */
4384 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4385 if (mod != 3) {
4386 gen_op_st_T0_A0(ot + s->mem_index);
4387 } else {
4388 gen_op_mov_reg_T0(ot, rm);
4389 }
4390 gen_op_update_neg_cc();
4391 s->cc_op = CC_OP_SUBB + ot;
4392 break;
4393 case 4: /* mul */
4394 switch(ot) {
4395 case OT_BYTE:
4396 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4397 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4398 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4399 /* XXX: use 32 bit mul which could be faster */
4400 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4401 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4402 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4403 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4404 s->cc_op = CC_OP_MULB;
4405 break;
4406 case OT_WORD:
4407 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4408 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4409 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4410 /* XXX: use 32 bit mul which could be faster */
4411 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4412 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4413 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4414 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4415 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4416 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4417 s->cc_op = CC_OP_MULW;
4418 break;
4419 default:
4420 case OT_LONG:
4421 #ifdef TARGET_X86_64
4422 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4423 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4424 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4425 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4426 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4427 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4428 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4429 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4430 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4431 #else
4432 {
4433 TCGv_i64 t0, t1;
4434 t0 = tcg_temp_new_i64();
4435 t1 = tcg_temp_new_i64();
4436 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4437 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4438 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4439 tcg_gen_mul_i64(t0, t0, t1);
4440 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4441 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4442 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4443 tcg_gen_shri_i64(t0, t0, 32);
4444 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4445 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4446 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4447 }
4448 #endif
4449 s->cc_op = CC_OP_MULL;
4450 break;
4451 #ifdef TARGET_X86_64
4452 case OT_QUAD:
4453 gen_helper_mulq_EAX_T0(cpu_T[0]);
4454 s->cc_op = CC_OP_MULQ;
4455 break;
4456 #endif
4457 }
4458 break;
4459 case 5: /* imul */
4460 switch(ot) {
4461 case OT_BYTE:
4462 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4463 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4464 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4465 /* XXX: use 32 bit mul which could be faster */
4466 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4467 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4468 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4469 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4470 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4471 s->cc_op = CC_OP_MULB;
4472 break;
4473 case OT_WORD:
4474 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4475 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4476 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4477 /* XXX: use 32 bit mul which could be faster */
4478 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4479 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4480 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4481 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4482 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4483 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4484 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4485 s->cc_op = CC_OP_MULW;
4486 break;
4487 default:
4488 case OT_LONG:
4489 #ifdef TARGET_X86_64
4490 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4491 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4492 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4493 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4494 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4495 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4496 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4497 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4498 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4499 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4500 #else
4501 {
4502 TCGv_i64 t0, t1;
4503 t0 = tcg_temp_new_i64();
4504 t1 = tcg_temp_new_i64();
4505 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4506 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4507 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4508 tcg_gen_mul_i64(t0, t0, t1);
4509 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4510 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4511 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4512 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4513 tcg_gen_shri_i64(t0, t0, 32);
4514 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4515 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4516 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4517 }
4518 #endif
4519 s->cc_op = CC_OP_MULL;
4520 break;
4521 #ifdef TARGET_X86_64
4522 case OT_QUAD:
4523 gen_helper_imulq_EAX_T0(cpu_T[0]);
4524 s->cc_op = CC_OP_MULQ;
4525 break;
4526 #endif
4527 }
4528 break;
4529 case 6: /* div */
4530 switch(ot) {
4531 case OT_BYTE:
4532 gen_jmp_im(pc_start - s->cs_base);
4533 gen_helper_divb_AL(cpu_T[0]);
4534 break;
4535 case OT_WORD:
4536 gen_jmp_im(pc_start - s->cs_base);
4537 gen_helper_divw_AX(cpu_T[0]);
4538 break;
4539 default:
4540 case OT_LONG:
4541 gen_jmp_im(pc_start - s->cs_base);
4542 gen_helper_divl_EAX(cpu_T[0]);
4543 break;
4544 #ifdef TARGET_X86_64
4545 case OT_QUAD:
4546 gen_jmp_im(pc_start - s->cs_base);
4547 gen_helper_divq_EAX(cpu_T[0]);
4548 break;
4549 #endif
4550 }
4551 break;
4552 case 7: /* idiv */
4553 switch(ot) {
4554 case OT_BYTE:
4555 gen_jmp_im(pc_start - s->cs_base);
4556 gen_helper_idivb_AL(cpu_T[0]);
4557 break;
4558 case OT_WORD:
4559 gen_jmp_im(pc_start - s->cs_base);
4560 gen_helper_idivw_AX(cpu_T[0]);
4561 break;
4562 default:
4563 case OT_LONG:
4564 gen_jmp_im(pc_start - s->cs_base);
4565 gen_helper_idivl_EAX(cpu_T[0]);
4566 break;
4567 #ifdef TARGET_X86_64
4568 case OT_QUAD:
4569 gen_jmp_im(pc_start - s->cs_base);
4570 gen_helper_idivq_EAX(cpu_T[0]);
4571 break;
4572 #endif
4573 }
4574 break;
4575 default:
4576 goto illegal_op;
4577 }
4578 break;
4579
4580 case 0xfe: /* GRP4 */
4581 case 0xff: /* GRP5 */
4582 if ((b & 1) == 0)
4583 ot = OT_BYTE;
4584 else
4585 ot = dflag + OT_WORD;
4586
4587 modrm = ldub_code(s->pc++);
4588 mod = (modrm >> 6) & 3;
4589 rm = (modrm & 7) | REX_B(s);
4590 op = (modrm >> 3) & 7;
4591 if (op >= 2 && b == 0xfe) {
4592 goto illegal_op;
4593 }
4594 if (CODE64(s)) {
4595 if (op == 2 || op == 4) {
4596 /* operand size for jumps is 64 bit */
4597 ot = OT_QUAD;
4598 } else if (op == 3 || op == 5) {
4599 ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
4600 } else if (op == 6) {
4601 /* default push size is 64 bit */
4602 ot = dflag ? OT_QUAD : OT_WORD;
4603 }
4604 }
4605 if (mod != 3) {
4606 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4607 if (op >= 2 && op != 3 && op != 5)
4608 gen_op_ld_T0_A0(ot + s->mem_index);
4609 } else {
4610 gen_op_mov_TN_reg(ot, 0, rm);
4611 }
4612
4613 switch(op) {
4614 case 0: /* inc Ev */
4615 if (mod != 3)
4616 opreg = OR_TMP0;
4617 else
4618 opreg = rm;
4619 gen_inc(s, ot, opreg, 1);
4620 break;
4621 case 1: /* dec Ev */
4622 if (mod != 3)
4623 opreg = OR_TMP0;
4624 else
4625 opreg = rm;
4626 gen_inc(s, ot, opreg, -1);
4627 break;
4628 case 2: /* call Ev */
4629 /* XXX: optimize if memory (no 'and' is necessary) */
4630 if (s->dflag == 0)
4631 gen_op_andl_T0_ffff();
4632 next_eip = s->pc - s->cs_base;
4633 gen_movtl_T1_im(next_eip);
4634 gen_push_T1(s);
4635 gen_op_jmp_T0();
4636 gen_eob(s);
4637 break;
4638 case 3: /* lcall Ev */
4639 gen_op_ld_T1_A0(ot + s->mem_index);
4640 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4641 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4642 do_lcall:
4643 if (s->pe && !s->vm86) {
4644 if (s->cc_op != CC_OP_DYNAMIC)
4645 gen_op_set_cc_op(s->cc_op);
4646 gen_jmp_im(pc_start - s->cs_base);
4647 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4648 gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1],
4649 tcg_const_i32(dflag),
4650 tcg_const_i32(s->pc - pc_start));
4651 } else {
4652 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4653 gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1],
4654 tcg_const_i32(dflag),
4655 tcg_const_i32(s->pc - s->cs_base));
4656 }
4657 gen_eob(s);
4658 break;
4659 case 4: /* jmp Ev */
4660 if (s->dflag == 0)
4661 gen_op_andl_T0_ffff();
4662 gen_op_jmp_T0();
4663 gen_eob(s);
4664 break;
4665 case 5: /* ljmp Ev */
4666 gen_op_ld_T1_A0(ot + s->mem_index);
4667 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4668 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4669 do_ljmp:
4670 if (s->pe && !s->vm86) {
4671 if (s->cc_op != CC_OP_DYNAMIC)
4672 gen_op_set_cc_op(s->cc_op);
4673 gen_jmp_im(pc_start - s->cs_base);
4674 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4675 gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1],
4676 tcg_const_i32(s->pc - pc_start));
4677 } else {
4678 gen_op_movl_seg_T0_vm(R_CS);
4679 gen_op_movl_T0_T1();
4680 gen_op_jmp_T0();
4681 }
4682 gen_eob(s);
4683 break;
4684 case 6: /* push Ev */
4685 gen_push_T0(s);
4686 break;
4687 default:
4688 goto illegal_op;
4689 }
4690 break;
4691
4692 case 0x84: /* test Ev, Gv */
4693 case 0x85:
4694 if ((b & 1) == 0)
4695 ot = OT_BYTE;
4696 else
4697 ot = dflag + OT_WORD;
4698
4699 modrm = ldub_code(s->pc++);
4700 reg = ((modrm >> 3) & 7) | rex_r;
4701
4702 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4703 gen_op_mov_TN_reg(ot, 1, reg);
4704 gen_op_testl_T0_T1_cc();
4705 s->cc_op = CC_OP_LOGICB + ot;
4706 break;
4707
4708 case 0xa8: /* test eAX, Iv */
4709 case 0xa9:
4710 if ((b & 1) == 0)
4711 ot = OT_BYTE;
4712 else
4713 ot = dflag + OT_WORD;
4714 val = insn_get(s, ot);
4715
4716 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4717 gen_op_movl_T1_im(val);
4718 gen_op_testl_T0_T1_cc();
4719 s->cc_op = CC_OP_LOGICB + ot;
4720 break;
4721
4722 case 0x98: /* CWDE/CBW */
4723 #ifdef TARGET_X86_64
4724 if (dflag == 2) {
4725 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4726 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4727 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4728 } else
4729 #endif
4730 if (dflag == 1) {
4731 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4732 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4733 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4734 } else {
4735 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4736 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4737 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4738 }
4739 break;
4740 case 0x99: /* CDQ/CWD */
4741 #ifdef TARGET_X86_64
4742 if (dflag == 2) {
4743 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4744 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4745 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4746 } else
4747 #endif
4748 if (dflag == 1) {
4749 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4750 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4751 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4752 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4753 } else {
4754 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4755 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4756 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4757 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4758 }
4759 break;
4760 case 0x1af: /* imul Gv, Ev */
4761 case 0x69: /* imul Gv, Ev, I */
4762 case 0x6b:
4763 ot = dflag + OT_WORD;
4764 modrm = ldub_code(s->pc++);
4765 reg = ((modrm >> 3) & 7) | rex_r;
4766 if (b == 0x69)
4767 s->rip_offset = insn_const_size(ot);
4768 else if (b == 0x6b)
4769 s->rip_offset = 1;
4770 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4771 if (b == 0x69) {
4772 val = insn_get(s, ot);
4773 gen_op_movl_T1_im(val);
4774 } else if (b == 0x6b) {
4775 val = (int8_t)insn_get(s, OT_BYTE);
4776 gen_op_movl_T1_im(val);
4777 } else {
4778 gen_op_mov_TN_reg(ot, 1, reg);
4779 }
4780
4781 #ifdef TARGET_X86_64
4782 if (ot == OT_QUAD) {
4783 gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]);
4784 } else
4785 #endif
4786 if (ot == OT_LONG) {
4787 #ifdef TARGET_X86_64
4788 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4789 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4790 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4791 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4792 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4793 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4794 #else
4795 {
4796 TCGv_i64 t0, t1;
4797 t0 = tcg_temp_new_i64();
4798 t1 = tcg_temp_new_i64();
4799 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4800 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4801 tcg_gen_mul_i64(t0, t0, t1);
4802 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4803 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4804 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4805 tcg_gen_shri_i64(t0, t0, 32);
4806 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4807 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4808 }
4809 #endif
4810 } else {
4811 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4812 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4813 /* XXX: use 32 bit mul which could be faster */
4814 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4815 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4816 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4817 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4818 }
4819 gen_op_mov_reg_T0(ot, reg);
4820 s->cc_op = CC_OP_MULB + ot;
4821 break;
4822 case 0x1c0:
4823 case 0x1c1: /* xadd Ev, Gv */
4824 if ((b & 1) == 0)
4825 ot = OT_BYTE;
4826 else
4827 ot = dflag + OT_WORD;
4828 modrm = ldub_code(s->pc++);
4829 reg = ((modrm >> 3) & 7) | rex_r;
4830 mod = (modrm >> 6) & 3;
4831 if (mod == 3) {
4832 rm = (modrm & 7) | REX_B(s);
4833 gen_op_mov_TN_reg(ot, 0, reg);
4834 gen_op_mov_TN_reg(ot, 1, rm);
4835 gen_op_addl_T0_T1();
4836 gen_op_mov_reg_T1(ot, reg);
4837 gen_op_mov_reg_T0(ot, rm);
4838 } else {
4839 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4840 gen_op_mov_TN_reg(ot, 0, reg);
4841 gen_op_ld_T1_A0(ot + s->mem_index);
4842 gen_op_addl_T0_T1();
4843 gen_op_st_T0_A0(ot + s->mem_index);
4844 gen_op_mov_reg_T1(ot, reg);
4845 }
4846 gen_op_update2_cc();
4847 s->cc_op = CC_OP_ADDB + ot;
4848 break;
4849 case 0x1b0:
4850 case 0x1b1: /* cmpxchg Ev, Gv */
4851 {
4852 int label1, label2;
4853 TCGv t0, t1, t2, a0;
4854
4855 if ((b & 1) == 0)
4856 ot = OT_BYTE;
4857 else
4858 ot = dflag + OT_WORD;
4859 modrm = ldub_code(s->pc++);
4860 reg = ((modrm >> 3) & 7) | rex_r;
4861 mod = (modrm >> 6) & 3;
4862 t0 = tcg_temp_local_new();
4863 t1 = tcg_temp_local_new();
4864 t2 = tcg_temp_local_new();
4865 a0 = tcg_temp_local_new();
4866 gen_op_mov_v_reg(ot, t1, reg);
4867 if (mod == 3) {
4868 rm = (modrm & 7) | REX_B(s);
4869 gen_op_mov_v_reg(ot, t0, rm);
4870 } else {
4871 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4872 tcg_gen_mov_tl(a0, cpu_A0);
4873 gen_op_ld_v(ot + s->mem_index, t0, a0);
4874 rm = 0; /* avoid warning */
4875 }
4876 label1 = gen_new_label();
4877 tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0);
4878 gen_extu(ot, t2);
4879 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4880 if (mod == 3) {
4881 label2 = gen_new_label();
4882 gen_op_mov_reg_v(ot, R_EAX, t0);
4883 tcg_gen_br(label2);
4884 gen_set_label(label1);
4885 gen_op_mov_reg_v(ot, rm, t1);
4886 gen_set_label(label2);
4887 } else {
4888 tcg_gen_mov_tl(t1, t0);
4889 gen_op_mov_reg_v(ot, R_EAX, t0);
4890 gen_set_label(label1);
4891 /* always store */
4892 gen_op_st_v(ot + s->mem_index, t1, a0);
4893 }
4894 tcg_gen_mov_tl(cpu_cc_src, t0);
4895 tcg_gen_mov_tl(cpu_cc_dst, t2);
4896 s->cc_op = CC_OP_SUBB + ot;
4897 tcg_temp_free(t0);
4898 tcg_temp_free(t1);
4899 tcg_temp_free(t2);
4900 tcg_temp_free(a0);
4901 }
4902 break;
4903 case 0x1c7: /* cmpxchg8b */
4904 modrm = ldub_code(s->pc++);
4905 mod = (modrm >> 6) & 3;
4906 if ((mod == 3) || ((modrm & 0x38) != 0x8))
4907 goto illegal_op;
4908 #ifdef TARGET_X86_64
4909 if (dflag == 2) {
4910 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4911 goto illegal_op;
4912 gen_jmp_im(pc_start - s->cs_base);
4913 if (s->cc_op != CC_OP_DYNAMIC)
4914 gen_op_set_cc_op(s->cc_op);
4915 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4916 gen_helper_cmpxchg16b(cpu_A0);
4917 } else
4918 #endif
4919 {
4920 if (!(s->cpuid_features & CPUID_CX8))
4921 goto illegal_op;
4922 gen_jmp_im(pc_start - s->cs_base);
4923 if (s->cc_op != CC_OP_DYNAMIC)
4924 gen_op_set_cc_op(s->cc_op);
4925 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4926 gen_helper_cmpxchg8b(cpu_A0);
4927 }
4928 s->cc_op = CC_OP_EFLAGS;
4929 break;
4930
4931 /**************************/
4932 /* push/pop */
4933 case 0x50 ... 0x57: /* push */
4934 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
4935 gen_push_T0(s);
4936 break;
4937 case 0x58 ... 0x5f: /* pop */
4938 if (CODE64(s)) {
4939 ot = dflag ? OT_QUAD : OT_WORD;
4940 } else {
4941 ot = dflag + OT_WORD;
4942 }
4943 gen_pop_T0(s);
4944 /* NOTE: order is important for pop %sp */
4945 gen_pop_update(s);
4946 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
4947 break;
4948 case 0x60: /* pusha */
4949 if (CODE64(s))
4950 goto illegal_op;
4951 gen_pusha(s);
4952 break;
4953 case 0x61: /* popa */
4954 if (CODE64(s))
4955 goto illegal_op;
4956 gen_popa(s);
4957 break;
4958 case 0x68: /* push Iv */
4959 case 0x6a:
4960 if (CODE64(s)) {
4961 ot = dflag ? OT_QUAD : OT_WORD;
4962 } else {
4963 ot = dflag + OT_WORD;
4964 }
4965 if (b == 0x68)
4966 val = insn_get(s, ot);
4967 else
4968 val = (int8_t)insn_get(s, OT_BYTE);
4969 gen_op_movl_T0_im(val);
4970 gen_push_T0(s);
4971 break;
4972 case 0x8f: /* pop Ev */
4973 if (CODE64(s)) {
4974 ot = dflag ? OT_QUAD : OT_WORD;
4975 } else {
4976 ot = dflag + OT_WORD;
4977 }
4978 modrm = ldub_code(s->pc++);
4979 mod = (modrm >> 6) & 3;
4980 gen_pop_T0(s);
4981 if (mod == 3) {
4982 /* NOTE: order is important for pop %sp */
4983 gen_pop_update(s);
4984 rm = (modrm & 7) | REX_B(s);
4985 gen_op_mov_reg_T0(ot, rm);
4986 } else {
4987 /* NOTE: order is important too for MMU exceptions */
4988 s->popl_esp_hack = 1 << ot;
4989 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4990 s->popl_esp_hack = 0;
4991 gen_pop_update(s);
4992 }
4993 break;
4994 case 0xc8: /* enter */
4995 {
4996 int level;
4997 val = lduw_code(s->pc);
4998 s->pc += 2;
4999 level = ldub_code(s->pc++);
5000 gen_enter(s, val, level);
5001 }
5002 break;
5003 case 0xc9: /* leave */
5004 /* XXX: exception not precise (ESP is updated before potential exception) */
5005 if (CODE64(s)) {
5006 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
5007 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
5008 } else if (s->ss32) {
5009 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
5010 gen_op_mov_reg_T0(OT_LONG, R_ESP);
5011 } else {
5012 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
5013 gen_op_mov_reg_T0(OT_WORD, R_ESP);
5014 }
5015 gen_pop_T0(s);
5016 if (CODE64(s)) {
5017 ot = dflag ? OT_QUAD : OT_WORD;
5018 } else {
5019 ot = dflag + OT_WORD;
5020 }
5021 gen_op_mov_reg_T0(ot, R_EBP);
5022 gen_pop_update(s);
5023 break;
5024 case 0x06: /* push es */
5025 case 0x0e: /* push cs */
5026 case 0x16: /* push ss */
5027 case 0x1e: /* push ds */
5028 if (CODE64(s))
5029 goto illegal_op;
5030 gen_op_movl_T0_seg(b >> 3);
5031 gen_push_T0(s);
5032 break;
5033 case 0x1a0: /* push fs */
5034 case 0x1a8: /* push gs */
5035 gen_op_movl_T0_seg((b >> 3) & 7);
5036 gen_push_T0(s);
5037 break;
5038 case 0x07: /* pop es */
5039 case 0x17: /* pop ss */
5040 case 0x1f: /* pop ds */
5041 if (CODE64(s))
5042 goto illegal_op;
5043 reg = b >> 3;
5044 gen_pop_T0(s);
5045 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5046 gen_pop_update(s);
5047 if (reg == R_SS) {
5048 /* if reg == SS, inhibit interrupts/trace. */
5049 /* If several instructions disable interrupts, only the
5050 _first_ does it */
5051 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5052 gen_helper_set_inhibit_irq();
5053 s->tf = 0;
5054 }
5055 if (s->is_jmp) {
5056 gen_jmp_im(s->pc - s->cs_base);
5057 gen_eob(s);
5058 }
5059 break;
5060 case 0x1a1: /* pop fs */
5061 case 0x1a9: /* pop gs */
5062 gen_pop_T0(s);
5063 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5064 gen_pop_update(s);
5065 if (s->is_jmp) {
5066 gen_jmp_im(s->pc - s->cs_base);
5067 gen_eob(s);
5068 }
5069 break;
5070
5071 /**************************/
5072 /* mov */
5073 case 0x88:
5074 case 0x89: /* mov Gv, Ev */
5075 if ((b & 1) == 0)
5076 ot = OT_BYTE;
5077 else
5078 ot = dflag + OT_WORD;
5079 modrm = ldub_code(s->pc++);
5080 reg = ((modrm >> 3) & 7) | rex_r;
5081
5082 /* generate a generic store */
5083 gen_ldst_modrm(s, modrm, ot, reg, 1);
5084 break;
5085 case 0xc6:
5086 case 0xc7: /* mov Ev, Iv */
5087 if ((b & 1) == 0)
5088 ot = OT_BYTE;
5089 else
5090 ot = dflag + OT_WORD;
5091 modrm = ldub_code(s->pc++);
5092 mod = (modrm >> 6) & 3;
5093 if (mod != 3) {
5094 s->rip_offset = insn_const_size(ot);
5095 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5096 }
5097 val = insn_get(s, ot);
5098 gen_op_movl_T0_im(val);
5099 if (mod != 3)
5100 gen_op_st_T0_A0(ot + s->mem_index);
5101 else
5102 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
5103 break;
5104 case 0x8a:
5105 case 0x8b: /* mov Ev, Gv */
5106 if ((b & 1) == 0)
5107 ot = OT_BYTE;
5108 else
5109 ot = OT_WORD + dflag;
5110 modrm = ldub_code(s->pc++);
5111 reg = ((modrm >> 3) & 7) | rex_r;
5112
5113 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5114 gen_op_mov_reg_T0(ot, reg);
5115 break;
5116 case 0x8e: /* mov seg, Gv */
5117 modrm = ldub_code(s->pc++);
5118 reg = (modrm >> 3) & 7;
5119 if (reg >= 6 || reg == R_CS)
5120 goto illegal_op;
5121 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5122 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5123 if (reg == R_SS) {
5124 /* if reg == SS, inhibit interrupts/trace */
5125 /* If several instructions disable interrupts, only the
5126 _first_ does it */
5127 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5128 gen_helper_set_inhibit_irq();
5129 s->tf = 0;
5130 }
5131 if (s->is_jmp) {
5132 gen_jmp_im(s->pc - s->cs_base);
5133 gen_eob(s);
5134 }
5135 break;
5136 case 0x8c: /* mov Gv, seg */
5137 modrm = ldub_code(s->pc++);
5138 reg = (modrm >> 3) & 7;
5139 mod = (modrm >> 6) & 3;
5140 if (reg >= 6)
5141 goto illegal_op;
5142 gen_op_movl_T0_seg(reg);
5143 if (mod == 3)
5144 ot = OT_WORD + dflag;
5145 else
5146 ot = OT_WORD;
5147 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5148 break;
5149
5150 case 0x1b6: /* movzbS Gv, Eb */
5151 case 0x1b7: /* movzwS Gv, Eb */
5152 case 0x1be: /* movsbS Gv, Eb */
5153 case 0x1bf: /* movswS Gv, Eb */
5154 {
5155 int d_ot;
5156 /* d_ot is the size of destination */
5157 d_ot = dflag + OT_WORD;
5158 /* ot is the size of source */
5159 ot = (b & 1) + OT_BYTE;
5160 modrm = ldub_code(s->pc++);
5161 reg = ((modrm >> 3) & 7) | rex_r;
5162 mod = (modrm >> 6) & 3;
5163 rm = (modrm & 7) | REX_B(s);
5164
5165 if (mod == 3) {
5166 gen_op_mov_TN_reg(ot, 0, rm);
5167 switch(ot | (b & 8)) {
5168 case OT_BYTE:
5169 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
5170 break;
5171 case OT_BYTE | 8:
5172 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
5173 break;
5174 case OT_WORD:
5175 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
5176 break;
5177 default:
5178 case OT_WORD | 8:
5179 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5180 break;
5181 }
5182 gen_op_mov_reg_T0(d_ot, reg);
5183 } else {
5184 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5185 if (b & 8) {
5186 gen_op_lds_T0_A0(ot + s->mem_index);
5187 } else {
5188 gen_op_ldu_T0_A0(ot + s->mem_index);
5189 }
5190 gen_op_mov_reg_T0(d_ot, reg);
5191 }
5192 }
5193 break;
5194
5195 case 0x8d: /* lea */
5196 ot = dflag + OT_WORD;
5197 modrm = ldub_code(s->pc++);
5198 mod = (modrm >> 6) & 3;
5199 if (mod == 3)
5200 goto illegal_op;
5201 reg = ((modrm >> 3) & 7) | rex_r;
5202 /* we must ensure that no segment is added */
5203 s->override = -1;
5204 val = s->addseg;
5205 s->addseg = 0;
5206 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5207 s->addseg = val;
5208 gen_op_mov_reg_A0(ot - OT_WORD, reg);
5209 break;
5210
5211 case 0xa0: /* mov EAX, Ov */
5212 case 0xa1:
5213 case 0xa2: /* mov Ov, EAX */
5214 case 0xa3:
5215 {
5216 target_ulong offset_addr;
5217
5218 if ((b & 1) == 0)
5219 ot = OT_BYTE;
5220 else
5221 ot = dflag + OT_WORD;
5222 #ifdef TARGET_X86_64
5223 if (s->aflag == 2) {
5224 offset_addr = ldq_code(s->pc);
5225 s->pc += 8;
5226 gen_op_movq_A0_im(offset_addr);
5227 } else
5228 #endif
5229 {
5230 if (s->aflag) {
5231 offset_addr = insn_get(s, OT_LONG);
5232 } else {
5233 offset_addr = insn_get(s, OT_WORD);
5234 }
5235 gen_op_movl_A0_im(offset_addr);
5236 }
5237 gen_add_A0_ds_seg(s);
5238 if ((b & 2) == 0) {
5239 gen_op_ld_T0_A0(ot + s->mem_index);
5240 gen_op_mov_reg_T0(ot, R_EAX);
5241 } else {
5242 gen_op_mov_TN_reg(ot, 0, R_EAX);
5243 gen_op_st_T0_A0(ot + s->mem_index);
5244 }
5245 }
5246 break;
5247 case 0xd7: /* xlat */
5248 #ifdef TARGET_X86_64
5249 if (s->aflag == 2) {
5250 gen_op_movq_A0_reg(R_EBX);
5251 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5252 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5253 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5254 } else
5255 #endif
5256 {
5257 gen_op_movl_A0_reg(R_EBX);
5258 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5259 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5260 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5261 if (s->aflag == 0)
5262 gen_op_andl_A0_ffff();
5263 else
5264 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
5265 }
5266 gen_add_A0_ds_seg(s);
5267 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5268 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
5269 break;
5270 case 0xb0 ... 0xb7: /* mov R, Ib */
5271 val = insn_get(s, OT_BYTE);
5272 gen_op_movl_T0_im(val);
5273 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
5274 break;
5275 case 0xb8 ... 0xbf: /* mov R, Iv */
5276 #ifdef TARGET_X86_64
5277 if (dflag == 2) {
5278 uint64_t tmp;
5279 /* 64 bit case */
5280 tmp = ldq_code(s->pc);
5281 s->pc += 8;
5282 reg = (b & 7) | REX_B(s);
5283 gen_movtl_T0_im(tmp);
5284 gen_op_mov_reg_T0(OT_QUAD, reg);
5285 } else
5286 #endif
5287 {
5288 ot = dflag ? OT_LONG : OT_WORD;
5289 val = insn_get(s, ot);
5290 reg = (b & 7) | REX_B(s);
5291 gen_op_movl_T0_im(val);
5292 gen_op_mov_reg_T0(ot, reg);
5293 }
5294 break;
5295
5296 case 0x91 ... 0x97: /* xchg R, EAX */
5297 ot = dflag + OT_WORD;
5298 reg = (b & 7) | REX_B(s);
5299 rm = R_EAX;
5300 goto do_xchg_reg;
5301 case 0x86:
5302 case 0x87: /* xchg Ev, Gv */
5303 if ((b & 1) == 0)
5304 ot = OT_BYTE;
5305 else
5306 ot = dflag + OT_WORD;
5307 modrm = ldub_code(s->pc++);
5308 reg = ((modrm >> 3) & 7) | rex_r;
5309 mod = (modrm >> 6) & 3;
5310 if (mod == 3) {
5311 rm = (modrm & 7) | REX_B(s);
5312 do_xchg_reg:
5313 gen_op_mov_TN_reg(ot, 0, reg);
5314 gen_op_mov_TN_reg(ot, 1, rm);
5315 gen_op_mov_reg_T0(ot, rm);
5316 gen_op_mov_reg_T1(ot, reg);
5317 } else {
5318 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5319 gen_op_mov_TN_reg(ot, 0, reg);
5320 /* for xchg, lock is implicit */
5321 if (!(prefixes & PREFIX_LOCK))
5322 gen_helper_lock();
5323 gen_op_ld_T1_A0(ot + s->mem_index);
5324 gen_op_st_T0_A0(ot + s->mem_index);
5325 if (!(prefixes & PREFIX_LOCK))
5326 gen_helper_unlock();
5327 gen_op_mov_reg_T1(ot, reg);
5328 }
5329 break;
5330 case 0xc4: /* les Gv */
5331 if (CODE64(s))
5332 goto illegal_op;
5333 op = R_ES;
5334 goto do_lxx;
5335 case 0xc5: /* lds Gv */
5336 if (CODE64(s))
5337 goto illegal_op;
5338 op = R_DS;
5339 goto do_lxx;
5340 case 0x1b2: /* lss Gv */
5341 op = R_SS;
5342 goto do_lxx;
5343 case 0x1b4: /* lfs Gv */
5344 op = R_FS;
5345 goto do_lxx;
5346 case 0x1b5: /* lgs Gv */
5347 op = R_GS;
5348 do_lxx:
5349 ot = dflag ? OT_LONG : OT_WORD;
5350 modrm = ldub_code(s->pc++);
5351 reg = ((modrm >> 3) & 7) | rex_r;
5352 mod = (modrm >> 6) & 3;
5353 if (mod == 3)
5354 goto illegal_op;
5355 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5356 gen_op_ld_T1_A0(ot + s->mem_index);
5357 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5358 /* load the segment first to handle exceptions properly */
5359 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
5360 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5361 /* then put the data */
5362 gen_op_mov_reg_T1(ot, reg);
5363 if (s->is_jmp) {
5364 gen_jmp_im(s->pc - s->cs_base);
5365 gen_eob(s);
5366 }
5367 break;
5368
5369 /************************/
5370 /* shifts */
5371 case 0xc0:
5372 case 0xc1:
5373 /* shift Ev,Ib */
5374 shift = 2;
5375 grp2:
5376 {
5377 if ((b & 1) == 0)
5378 ot = OT_BYTE;
5379 else
5380 ot = dflag + OT_WORD;
5381
5382 modrm = ldub_code(s->pc++);
5383 mod = (modrm >> 6) & 3;
5384 op = (modrm >> 3) & 7;
5385
5386 if (mod != 3) {
5387 if (shift == 2) {
5388 s->rip_offset = 1;
5389 }
5390 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5391 opreg = OR_TMP0;
5392 } else {
5393 opreg = (modrm & 7) | REX_B(s);
5394 }
5395
5396 /* simpler op */
5397 if (shift == 0) {
5398 gen_shift(s, op, ot, opreg, OR_ECX);
5399 } else {
5400 if (shift == 2) {
5401 shift = ldub_code(s->pc++);
5402 }
5403 gen_shifti(s, op, ot, opreg, shift);
5404 }
5405 }
5406 break;
5407 case 0xd0:
5408 case 0xd1:
5409 /* shift Ev,1 */
5410 shift = 1;
5411 goto grp2;
5412 case 0xd2:
5413 case 0xd3:
5414 /* shift Ev,cl */
5415 shift = 0;
5416 goto grp2;
5417
5418 case 0x1a4: /* shld imm */
5419 op = 0;
5420 shift = 1;
5421 goto do_shiftd;
5422 case 0x1a5: /* shld cl */
5423 op = 0;
5424 shift = 0;
5425 goto do_shiftd;
5426 case 0x1ac: /* shrd imm */
5427 op = 1;
5428 shift = 1;
5429 goto do_shiftd;
5430 case 0x1ad: /* shrd cl */
5431 op = 1;
5432 shift = 0;
5433 do_shiftd:
5434 ot = dflag + OT_WORD;
5435 modrm = ldub_code(s->pc++);
5436 mod = (modrm >> 6) & 3;
5437 rm = (modrm & 7) | REX_B(s);
5438 reg = ((modrm >> 3) & 7) | rex_r;
5439 if (mod != 3) {
5440 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5441 opreg = OR_TMP0;
5442 } else {
5443 opreg = rm;
5444 }
5445 gen_op_mov_TN_reg(ot, 1, reg);
5446
5447 if (shift) {
5448 val = ldub_code(s->pc++);
5449 tcg_gen_movi_tl(cpu_T3, val);
5450 } else {
5451 tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
5452 }
5453 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5454 break;
5455
5456 /************************/
5457 /* floats */
5458 case 0xd8 ... 0xdf:
5459 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5460 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5461 /* XXX: what to do if illegal op ? */
5462 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5463 break;
5464 }
5465 modrm = ldub_code(s->pc++);
5466 mod = (modrm >> 6) & 3;
5467 rm = modrm & 7;
5468 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5469 if (mod != 3) {
5470 /* memory op */
5471 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5472 switch(op) {
5473 case 0x00 ... 0x07: /* fxxxs */
5474 case 0x10 ... 0x17: /* fixxxl */
5475 case 0x20 ... 0x27: /* fxxxl */
5476 case 0x30 ... 0x37: /* fixxx */
5477 {
5478 int op1;
5479 op1 = op & 7;
5480
5481 switch(op >> 4) {
5482 case 0:
5483 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5484 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5485 gen_helper_flds_FT0(cpu_tmp2_i32);
5486 break;
5487 case 1:
5488 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5489 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5490 gen_helper_fildl_FT0(cpu_tmp2_i32);
5491 break;
5492 case 2:
5493 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5494 (s->mem_index >> 2) - 1);
5495 gen_helper_fldl_FT0(cpu_tmp1_i64);
5496 break;
5497 case 3:
5498 default:
5499 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5500 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5501 gen_helper_fildl_FT0(cpu_tmp2_i32);
5502 break;
5503 }
5504
5505 gen_helper_fp_arith_ST0_FT0(op1);
5506 if (op1 == 3) {
5507 /* fcomp needs pop */
5508 gen_helper_fpop();
5509 }
5510 }
5511 break;
5512 case 0x08: /* flds */
5513 case 0x0a: /* fsts */
5514 case 0x0b: /* fstps */
5515 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5516 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5517 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5518 switch(op & 7) {
5519 case 0:
5520 switch(op >> 4) {
5521 case 0:
5522 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5523 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5524 gen_helper_flds_ST0(cpu_tmp2_i32);
5525 break;
5526 case 1:
5527 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5528 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5529 gen_helper_fildl_ST0(cpu_tmp2_i32);
5530 break;
5531 case 2:
5532 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5533 (s->mem_index >> 2) - 1);
5534 gen_helper_fldl_ST0(cpu_tmp1_i64);
5535 break;
5536 case 3:
5537 default:
5538 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5539 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5540 gen_helper_fildl_ST0(cpu_tmp2_i32);
5541 break;
5542 }
5543 break;
5544 case 1:
5545 /* XXX: the corresponding CPUID bit must be tested ! */
5546 switch(op >> 4) {
5547 case 1:
5548 gen_helper_fisttl_ST0(cpu_tmp2_i32);
5549 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5550 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5551 break;
5552 case 2:
5553 gen_helper_fisttll_ST0(cpu_tmp1_i64);
5554 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5555 (s->mem_index >> 2) - 1);
5556 break;
5557 case 3:
5558 default:
5559 gen_helper_fistt_ST0(cpu_tmp2_i32);
5560 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5561 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5562 break;
5563 }
5564 gen_helper_fpop();
5565 break;
5566 default:
5567 switch(op >> 4) {
5568 case 0:
5569 gen_helper_fsts_ST0(cpu_tmp2_i32);
5570 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5571 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5572 break;
5573 case 1:
5574 gen_helper_fistl_ST0(cpu_tmp2_i32);
5575 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5576 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5577 break;
5578 case 2:
5579 gen_helper_fstl_ST0(cpu_tmp1_i64);
5580 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5581 (s->mem_index >> 2) - 1);
5582 break;
5583 case 3:
5584 default:
5585 gen_helper_fist_ST0(cpu_tmp2_i32);
5586 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5587 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5588 break;
5589 }
5590 if ((op & 7) == 3)
5591 gen_helper_fpop();
5592 break;
5593 }
5594 break;
5595 case 0x0c: /* fldenv mem */
5596 if (s->cc_op != CC_OP_DYNAMIC)
5597 gen_op_set_cc_op(s->cc_op);
5598 gen_jmp_im(pc_start - s->cs_base);
5599 gen_helper_fldenv(
5600 cpu_A0, tcg_const_i32(s->dflag));
5601 break;
5602 case 0x0d: /* fldcw mem */
5603 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5604 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5605 gen_helper_fldcw(cpu_tmp2_i32);
5606 break;
5607 case 0x0e: /* fnstenv mem */
5608 if (s->cc_op != CC_OP_DYNAMIC)
5609 gen_op_set_cc_op(s->cc_op);
5610 gen_jmp_im(pc_start - s->cs_base);
5611 gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag));
5612 break;
5613 case 0x0f: /* fnstcw mem */
5614 gen_helper_fnstcw(cpu_tmp2_i32);
5615 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5616 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5617 break;
5618 case 0x1d: /* fldt mem */
5619 if (s->cc_op != CC_OP_DYNAMIC)
5620 gen_op_set_cc_op(s->cc_op);
5621 gen_jmp_im(pc_start - s->cs_base);
5622 gen_helper_fldt_ST0(cpu_A0);
5623 break;
5624 case 0x1f: /* fstpt mem */
5625 if (s->cc_op != CC_OP_DYNAMIC)
5626 gen_op_set_cc_op(s->cc_op);
5627 gen_jmp_im(pc_start - s->cs_base);
5628 gen_helper_fstt_ST0(cpu_A0);
5629 gen_helper_fpop();
5630 break;
5631 case 0x2c: /* frstor mem */
5632 if (s->cc_op != CC_OP_DYNAMIC)
5633 gen_op_set_cc_op(s->cc_op);
5634 gen_jmp_im(pc_start - s->cs_base);
5635 gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag));
5636 break;
5637 case 0x2e: /* fnsave mem */
5638 if (s->cc_op != CC_OP_DYNAMIC)
5639 gen_op_set_cc_op(s->cc_op);
5640 gen_jmp_im(pc_start - s->cs_base);
5641 gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag));
5642 break;
5643 case 0x2f: /* fnstsw mem */
5644 gen_helper_fnstsw(cpu_tmp2_i32);
5645 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5646 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5647 break;
5648 case 0x3c: /* fbld */
5649 if (s->cc_op != CC_OP_DYNAMIC)
5650 gen_op_set_cc_op(s->cc_op);
5651 gen_jmp_im(pc_start - s->cs_base);
5652 gen_helper_fbld_ST0(cpu_A0);
5653 break;
5654 case 0x3e: /* fbstp */
5655 if (s->cc_op != CC_OP_DYNAMIC)
5656 gen_op_set_cc_op(s->cc_op);
5657 gen_jmp_im(pc_start - s->cs_base);
5658 gen_helper_fbst_ST0(cpu_A0);
5659 gen_helper_fpop();
5660 break;
5661 case 0x3d: /* fildll */
5662 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5663 (s->mem_index >> 2) - 1);
5664 gen_helper_fildll_ST0(cpu_tmp1_i64);
5665 break;
5666 case 0x3f: /* fistpll */
5667 gen_helper_fistll_ST0(cpu_tmp1_i64);
5668 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5669 (s->mem_index >> 2) - 1);
5670 gen_helper_fpop();
5671 break;
5672 default:
5673 goto illegal_op;
5674 }
5675 } else {
5676 /* register float ops */
5677 opreg = rm;
5678
5679 switch(op) {
5680 case 0x08: /* fld sti */
5681 gen_helper_fpush();
5682 gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7));
5683 break;
5684 case 0x09: /* fxchg sti */
5685 case 0x29: /* fxchg4 sti, undocumented op */
5686 case 0x39: /* fxchg7 sti, undocumented op */
5687 gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg));
5688 break;
5689 case 0x0a: /* grp d9/2 */
5690 switch(rm) {
5691 case 0: /* fnop */
5692 /* check exceptions (FreeBSD FPU probe) */
5693 if (s->cc_op != CC_OP_DYNAMIC)
5694 gen_op_set_cc_op(s->cc_op);
5695 gen_jmp_im(pc_start - s->cs_base);
5696 gen_helper_fwait();
5697 break;
5698 default:
5699 goto illegal_op;
5700 }
5701 break;
5702 case 0x0c: /* grp d9/4 */
5703 switch(rm) {
5704 case 0: /* fchs */
5705 gen_helper_fchs_ST0();
5706 break;
5707 case 1: /* fabs */
5708 gen_helper_fabs_ST0();
5709 break;
5710 case 4: /* ftst */
5711 gen_helper_fldz_FT0();
5712 gen_helper_fcom_ST0_FT0();
5713 break;
5714 case 5: /* fxam */
5715 gen_helper_fxam_ST0();
5716 break;
5717 default:
5718 goto illegal_op;
5719 }
5720 break;
5721 case 0x0d: /* grp d9/5 */
5722 {
5723 switch(rm) {
5724 case 0:
5725 gen_helper_fpush();
5726 gen_helper_fld1_ST0();
5727 break;
5728 case 1:
5729 gen_helper_fpush();
5730 gen_helper_fldl2t_ST0();
5731 break;
5732 case 2:
5733 gen_helper_fpush();
5734 gen_helper_fldl2e_ST0();
5735 break;
5736 case 3:
5737 gen_helper_fpush();
5738 gen_helper_fldpi_ST0();
5739 break;
5740 case 4:
5741 gen_helper_fpush();
5742 gen_helper_fldlg2_ST0();
5743 break;
5744 case 5:
5745 gen_helper_fpush();
5746 gen_helper_fldln2_ST0();
5747 break;
5748 case 6:
5749 gen_helper_fpush();
5750 gen_helper_fldz_ST0();
5751 break;
5752 default:
5753 goto illegal_op;
5754 }
5755 }
5756 break;
5757 case 0x0e: /* grp d9/6 */
5758 switch(rm) {
5759 case 0: /* f2xm1 */
5760 gen_helper_f2xm1();
5761 break;
5762 case 1: /* fyl2x */
5763 gen_helper_fyl2x();
5764 break;
5765 case 2: /* fptan */
5766 gen_helper_fptan();
5767 break;
5768 case 3: /* fpatan */
5769 gen_helper_fpatan();
5770 break;
5771 case 4: /* fxtract */
5772 gen_helper_fxtract();
5773 break;
5774 case 5: /* fprem1 */
5775 gen_helper_fprem1();
5776 break;
5777 case 6: /* fdecstp */
5778 gen_helper_fdecstp();
5779 break;
5780 default:
5781 case 7: /* fincstp */
5782 gen_helper_fincstp();
5783 break;
5784 }
5785 break;
5786 case 0x0f: /* grp d9/7 */
5787 switch(rm) {
5788 case 0: /* fprem */
5789 gen_helper_fprem();
5790 break;
5791 case 1: /* fyl2xp1 */
5792 gen_helper_fyl2xp1();
5793 break;
5794 case 2: /* fsqrt */
5795 gen_helper_fsqrt();
5796 break;
5797 case 3: /* fsincos */
5798 gen_helper_fsincos();
5799 break;
5800 case 5: /* fscale */
5801 gen_helper_fscale();
5802 break;
5803 case 4: /* frndint */
5804 gen_helper_frndint();
5805 break;
5806 case 6: /* fsin */
5807 gen_helper_fsin();
5808 break;
5809 default:
5810 case 7: /* fcos */
5811 gen_helper_fcos();
5812 break;
5813 }
5814 break;
5815 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5816 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5817 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5818 {
5819 int op1;
5820
5821 op1 = op & 7;
5822 if (op >= 0x20) {
5823 gen_helper_fp_arith_STN_ST0(op1, opreg);
5824 if (op >= 0x30)
5825 gen_helper_fpop();
5826 } else {
5827 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5828 gen_helper_fp_arith_ST0_FT0(op1);
5829 }
5830 }
5831 break;
5832 case 0x02: /* fcom */
5833 case 0x22: /* fcom2, undocumented op */
5834 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5835 gen_helper_fcom_ST0_FT0();
5836 break;
5837 case 0x03: /* fcomp */
5838 case 0x23: /* fcomp3, undocumented op */
5839 case 0x32: /* fcomp5, undocumented op */
5840 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5841 gen_helper_fcom_ST0_FT0();
5842 gen_helper_fpop();
5843 break;
5844 case 0x15: /* da/5 */
5845 switch(rm) {
5846 case 1: /* fucompp */
5847 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5848 gen_helper_fucom_ST0_FT0();
5849 gen_helper_fpop();
5850 gen_helper_fpop();
5851 break;
5852 default:
5853 goto illegal_op;
5854 }
5855 break;
5856 case 0x1c:
5857 switch(rm) {
5858 case 0: /* feni (287 only, just do nop here) */
5859 break;
5860 case 1: /* fdisi (287 only, just do nop here) */
5861 break;
5862 case 2: /* fclex */
5863 gen_helper_fclex();
5864 break;
5865 case 3: /* fninit */
5866 gen_helper_fninit();
5867 break;
5868 case 4: /* fsetpm (287 only, just do nop here) */
5869 break;
5870 default:
5871 goto illegal_op;
5872 }
5873 break;
5874 case 0x1d: /* fucomi */
5875 if (s->cc_op != CC_OP_DYNAMIC)
5876 gen_op_set_cc_op(s->cc_op);
5877 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5878 gen_helper_fucomi_ST0_FT0();
5879 s->cc_op = CC_OP_EFLAGS;
5880 break;
5881 case 0x1e: /* fcomi */
5882 if (s->cc_op != CC_OP_DYNAMIC)
5883 gen_op_set_cc_op(s->cc_op);
5884 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5885 gen_helper_fcomi_ST0_FT0();
5886 s->cc_op = CC_OP_EFLAGS;
5887 break;
5888 case 0x28: /* ffree sti */
5889 gen_helper_ffree_STN(tcg_const_i32(opreg));
5890 break;
5891 case 0x2a: /* fst sti */
5892 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5893 break;
5894 case 0x2b: /* fstp sti */
5895 case 0x0b: /* fstp1 sti, undocumented op */
5896 case 0x3a: /* fstp8 sti, undocumented op */
5897 case 0x3b: /* fstp9 sti, undocumented op */
5898 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5899 gen_helper_fpop();
5900 break;
5901 case 0x2c: /* fucom st(i) */
5902 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5903 gen_helper_fucom_ST0_FT0();
5904 break;
5905 case 0x2d: /* fucomp st(i) */
5906 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5907 gen_helper_fucom_ST0_FT0();
5908 gen_helper_fpop();
5909 break;
5910 case 0x33: /* de/3 */
5911 switch(rm) {
5912 case 1: /* fcompp */
5913 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5914 gen_helper_fcom_ST0_FT0();
5915 gen_helper_fpop();
5916 gen_helper_fpop();
5917 break;
5918 default:
5919 goto illegal_op;
5920 }
5921 break;
5922 case 0x38: /* ffreep sti, undocumented op */
5923 gen_helper_ffree_STN(tcg_const_i32(opreg));
5924 gen_helper_fpop();
5925 break;
5926 case 0x3c: /* df/4 */
5927 switch(rm) {
5928 case 0:
5929 gen_helper_fnstsw(cpu_tmp2_i32);
5930 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5931 gen_op_mov_reg_T0(OT_WORD, R_EAX);
5932 break;
5933 default:
5934 goto illegal_op;
5935 }
5936 break;
5937 case 0x3d: /* fucomip */
5938 if (s->cc_op != CC_OP_DYNAMIC)
5939 gen_op_set_cc_op(s->cc_op);
5940 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5941 gen_helper_fucomi_ST0_FT0();
5942 gen_helper_fpop();
5943 s->cc_op = CC_OP_EFLAGS;
5944 break;
5945 case 0x3e: /* fcomip */
5946 if (s->cc_op != CC_OP_DYNAMIC)
5947 gen_op_set_cc_op(s->cc_op);
5948 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5949 gen_helper_fcomi_ST0_FT0();
5950 gen_helper_fpop();
5951 s->cc_op = CC_OP_EFLAGS;
5952 break;
5953 case 0x10 ... 0x13: /* fcmovxx */
5954 case 0x18 ... 0x1b:
5955 {
5956 int op1, l1;
5957 static const uint8_t fcmov_cc[8] = {
5958 (JCC_B << 1),
5959 (JCC_Z << 1),
5960 (JCC_BE << 1),
5961 (JCC_P << 1),
5962 };
5963 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
5964 l1 = gen_new_label();
5965 gen_jcc1(s, s->cc_op, op1, l1);
5966 gen_helper_fmov_ST0_STN(tcg_const_i32(opreg));
5967 gen_set_label(l1);
5968 }
5969 break;
5970 default:
5971 goto illegal_op;
5972 }
5973 }
5974 break;
5975 /************************/
5976 /* string ops */
5977
5978 case 0xa4: /* movsS */
5979 case 0xa5:
5980 if ((b & 1) == 0)
5981 ot = OT_BYTE;
5982 else
5983 ot = dflag + OT_WORD;
5984
5985 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5986 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5987 } else {
5988 gen_movs(s, ot);
5989 }
5990 break;
5991
5992 case 0xaa: /* stosS */
5993 case 0xab:
5994 if ((b & 1) == 0)
5995 ot = OT_BYTE;
5996 else
5997 ot = dflag + OT_WORD;
5998
5999 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6000 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6001 } else {
6002 gen_stos(s, ot);
6003 }
6004 break;
6005 case 0xac: /* lodsS */
6006 case 0xad:
6007 if ((b & 1) == 0)
6008 ot = OT_BYTE;
6009 else
6010 ot = dflag + OT_WORD;
6011 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6012 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6013 } else {
6014 gen_lods(s, ot);
6015 }
6016 break;
6017 case 0xae: /* scasS */
6018 case 0xaf:
6019 if ((b & 1) == 0)
6020 ot = OT_BYTE;
6021 else
6022 ot = dflag + OT_WORD;
6023 if (prefixes & PREFIX_REPNZ) {
6024 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6025 } else if (prefixes & PREFIX_REPZ) {
6026 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6027 } else {
6028 gen_scas(s, ot);
6029 s->cc_op = CC_OP_SUBB + ot;
6030 }
6031 break;
6032
6033 case 0xa6: /* cmpsS */
6034 case 0xa7:
6035 if ((b & 1) == 0)
6036 ot = OT_BYTE;
6037 else
6038 ot = dflag + OT_WORD;
6039 if (prefixes & PREFIX_REPNZ) {
6040 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6041 } else if (prefixes & PREFIX_REPZ) {
6042 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6043 } else {
6044 gen_cmps(s, ot);
6045 s->cc_op = CC_OP_SUBB + ot;
6046 }
6047 break;
6048 case 0x6c: /* insS */
6049 case 0x6d:
6050 if ((b & 1) == 0)
6051 ot = OT_BYTE;
6052 else
6053 ot = dflag ? OT_LONG : OT_WORD;
6054 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6055 gen_op_andl_T0_ffff();
6056 gen_check_io(s, ot, pc_start - s->cs_base,
6057 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
6058 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6059 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6060 } else {
6061 gen_ins(s, ot);
6062 if (use_icount) {
6063 gen_jmp(s, s->pc - s->cs_base);
6064 }
6065 }
6066 break;
6067 case 0x6e: /* outsS */
6068 case 0x6f:
6069 if ((b & 1) == 0)
6070 ot = OT_BYTE;
6071 else
6072 ot = dflag ? OT_LONG : OT_WORD;
6073 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6074 gen_op_andl_T0_ffff();
6075 gen_check_io(s, ot, pc_start - s->cs_base,
6076 svm_is_rep(prefixes) | 4);
6077 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6078 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6079 } else {
6080 gen_outs(s, ot);
6081 if (use_icount) {
6082 gen_jmp(s, s->pc - s->cs_base);
6083 }
6084 }
6085 break;
6086
6087 /************************/
6088 /* port I/O */
6089
6090 case 0xe4:
6091 case 0xe5:
6092 if ((b & 1) == 0)
6093 ot = OT_BYTE;
6094 else
6095 ot = dflag ? OT_LONG : OT_WORD;
6096 val = ldub_code(s->pc++);
6097 gen_op_movl_T0_im(val);
6098 gen_check_io(s, ot, pc_start - s->cs_base,
6099 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6100 if (use_icount)
6101 gen_io_start();
6102 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6103 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6104 gen_op_mov_reg_T1(ot, R_EAX);
6105 if (use_icount) {
6106 gen_io_end();
6107 gen_jmp(s, s->pc - s->cs_base);
6108 }
6109 break;
6110 case 0xe6:
6111 case 0xe7:
6112 if ((b & 1) == 0)
6113 ot = OT_BYTE;
6114 else
6115 ot = dflag ? OT_LONG : OT_WORD;
6116 val = ldub_code(s->pc++);
6117 gen_op_movl_T0_im(val);
6118 gen_check_io(s, ot, pc_start - s->cs_base,
6119 svm_is_rep(prefixes));
6120 gen_op_mov_TN_reg(ot, 1, R_EAX);
6121
6122 if (use_icount)
6123 gen_io_start();
6124 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6125 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6126 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6127 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6128 if (use_icount) {
6129 gen_io_end();
6130 gen_jmp(s, s->pc - s->cs_base);
6131 }
6132 break;
6133 case 0xec:
6134 case 0xed:
6135 if ((b & 1) == 0)
6136 ot = OT_BYTE;
6137 else
6138 ot = dflag ? OT_LONG : OT_WORD;
6139 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6140 gen_op_andl_T0_ffff();
6141 gen_check_io(s, ot, pc_start - s->cs_base,
6142 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6143 if (use_icount)
6144 gen_io_start();
6145 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6146 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6147 gen_op_mov_reg_T1(ot, R_EAX);
6148 if (use_icount) {
6149 gen_io_end();
6150 gen_jmp(s, s->pc - s->cs_base);
6151 }
6152 break;
6153 case 0xee:
6154 case 0xef:
6155 if ((b & 1) == 0)
6156 ot = OT_BYTE;
6157 else
6158 ot = dflag ? OT_LONG : OT_WORD;
6159 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6160 gen_op_andl_T0_ffff();
6161 gen_check_io(s, ot, pc_start - s->cs_base,
6162 svm_is_rep(prefixes));
6163 gen_op_mov_TN_reg(ot, 1, R_EAX);
6164
6165 if (use_icount)
6166 gen_io_start();
6167 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6168 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6169 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6170 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6171 if (use_icount) {
6172 gen_io_end();
6173 gen_jmp(s, s->pc - s->cs_base);
6174 }
6175 break;
6176
6177 /************************/
6178 /* control */
6179 case 0xc2: /* ret im */
6180 val = ldsw_code(s->pc);
6181 s->pc += 2;
6182 gen_pop_T0(s);
6183 if (CODE64(s) && s->dflag)
6184 s->dflag = 2;
6185 gen_stack_update(s, val + (2 << s->dflag));
6186 if (s->dflag == 0)
6187 gen_op_andl_T0_ffff();
6188 gen_op_jmp_T0();
6189 gen_eob(s);
6190 break;
6191 case 0xc3: /* ret */
6192 gen_pop_T0(s);
6193 gen_pop_update(s);
6194 if (s->dflag == 0)
6195 gen_op_andl_T0_ffff();
6196 gen_op_jmp_T0();
6197 gen_eob(s);
6198 break;
6199 case 0xca: /* lret im */
6200 val = ldsw_code(s->pc);
6201 s->pc += 2;
6202 do_lret:
6203 if (s->pe && !s->vm86) {
6204 if (s->cc_op != CC_OP_DYNAMIC)
6205 gen_op_set_cc_op(s->cc_op);
6206 gen_jmp_im(pc_start - s->cs_base);
6207 gen_helper_lret_protected(tcg_const_i32(s->dflag),
6208 tcg_const_i32(val));
6209 } else {
6210 gen_stack_A0(s);
6211 /* pop offset */
6212 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6213 if (s->dflag == 0)
6214 gen_op_andl_T0_ffff();
6215 /* NOTE: keeping EIP updated is not a problem in case of
6216 exception */
6217 gen_op_jmp_T0();
6218 /* pop selector */
6219 gen_op_addl_A0_im(2 << s->dflag);
6220 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6221 gen_op_movl_seg_T0_vm(R_CS);
6222 /* add stack offset */
6223 gen_stack_update(s, val + (4 << s->dflag));
6224 }
6225 gen_eob(s);
6226 break;
6227 case 0xcb: /* lret */
6228 val = 0;
6229 goto do_lret;
6230 case 0xcf: /* iret */
6231 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
6232 if (!s->pe) {
6233 /* real mode */
6234 gen_helper_iret_real(tcg_const_i32(s->dflag));
6235 s->cc_op = CC_OP_EFLAGS;
6236 } else if (s->vm86) {
6237 if (s->iopl != 3) {
6238 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6239 } else {
6240 gen_helper_iret_real(tcg_const_i32(s->dflag));
6241 s->cc_op = CC_OP_EFLAGS;
6242 }
6243 } else {
6244 if (s->cc_op != CC_OP_DYNAMIC)
6245 gen_op_set_cc_op(s->cc_op);
6246 gen_jmp_im(pc_start - s->cs_base);
6247 gen_helper_iret_protected(tcg_const_i32(s->dflag),
6248 tcg_const_i32(s->pc - s->cs_base));
6249 s->cc_op = CC_OP_EFLAGS;
6250 }
6251 gen_eob(s);
6252 break;
6253 case 0xe8: /* call im */
6254 {
6255 if (dflag)
6256 tval = (int32_t)insn_get(s, OT_LONG);
6257 else
6258 tval = (int16_t)insn_get(s, OT_WORD);
6259 next_eip = s->pc - s->cs_base;
6260 tval += next_eip;
6261 if (s->dflag == 0)
6262 tval &= 0xffff;
6263 else if(!CODE64(s))
6264 tval &= 0xffffffff;
6265 gen_movtl_T0_im(next_eip);
6266 gen_push_T0(s);
6267 gen_jmp(s, tval);
6268 }
6269 break;
6270 case 0x9a: /* lcall im */
6271 {
6272 unsigned int selector, offset;
6273
6274 if (CODE64(s))
6275 goto illegal_op;
6276 ot = dflag ? OT_LONG : OT_WORD;
6277 offset = insn_get(s, ot);
6278 selector = insn_get(s, OT_WORD);
6279
6280 gen_op_movl_T0_im(selector);
6281 gen_op_movl_T1_imu(offset);
6282 }
6283 goto do_lcall;
6284 case 0xe9: /* jmp im */
6285 if (dflag)
6286 tval = (int32_t)insn_get(s, OT_LONG);
6287 else
6288 tval = (int16_t)insn_get(s, OT_WORD);
6289 tval += s->pc - s->cs_base;
6290 if (s->dflag == 0)
6291 tval &= 0xffff;
6292 else if(!CODE64(s))
6293 tval &= 0xffffffff;
6294 gen_jmp(s, tval);
6295 break;
6296 case 0xea: /* ljmp im */
6297 {
6298 unsigned int selector, offset;
6299
6300 if (CODE64(s))
6301 goto illegal_op;
6302 ot = dflag ? OT_LONG : OT_WORD;
6303 offset = insn_get(s, ot);
6304 selector = insn_get(s, OT_WORD);
6305
6306 gen_op_movl_T0_im(selector);
6307 gen_op_movl_T1_imu(offset);
6308 }
6309 goto do_ljmp;
6310 case 0xeb: /* jmp Jb */
6311 tval = (int8_t)insn_get(s, OT_BYTE);
6312 tval += s->pc - s->cs_base;
6313 if (s->dflag == 0)
6314 tval &= 0xffff;
6315 gen_jmp(s, tval);
6316 break;
6317 case 0x70 ... 0x7f: /* jcc Jb */
6318 tval = (int8_t)insn_get(s, OT_BYTE);
6319 goto do_jcc;
6320 case 0x180 ... 0x18f: /* jcc Jv */
6321 if (dflag) {
6322 tval = (int32_t)insn_get(s, OT_LONG);
6323 } else {
6324 tval = (int16_t)insn_get(s, OT_WORD);
6325 }
6326 do_jcc:
6327 next_eip = s->pc - s->cs_base;
6328 tval += next_eip;
6329 if (s->dflag == 0)
6330 tval &= 0xffff;
6331 gen_jcc(s, b, tval, next_eip);
6332 break;
6333
6334 case 0x190 ... 0x19f: /* setcc Gv */
6335 modrm = ldub_code(s->pc++);
6336 gen_setcc(s, b);
6337 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
6338 break;
6339 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6340 {
6341 int l1;
6342 TCGv t0;
6343
6344 ot = dflag + OT_WORD;
6345 modrm = ldub_code(s->pc++);
6346 reg = ((modrm >> 3) & 7) | rex_r;
6347 mod = (modrm >> 6) & 3;
6348 t0 = tcg_temp_local_new();
6349 if (mod != 3) {
6350 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6351 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6352 } else {
6353 rm = (modrm & 7) | REX_B(s);
6354 gen_op_mov_v_reg(ot, t0, rm);
6355 }
6356 #ifdef TARGET_X86_64
6357 if (ot == OT_LONG) {
6358 /* XXX: specific Intel behaviour ? */
6359 l1 = gen_new_label();
6360 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6361 tcg_gen_mov_tl(cpu_regs[reg], t0);
6362 gen_set_label(l1);
6363 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]);
6364 } else
6365 #endif
6366 {
6367 l1 = gen_new_label();
6368 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6369 gen_op_mov_reg_v(ot, reg, t0);
6370 gen_set_label(l1);
6371 }
6372 tcg_temp_free(t0);
6373 }
6374 break;
6375
6376 /************************/
6377 /* flags */
6378 case 0x9c: /* pushf */
6379 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6380 if (s->vm86 && s->iopl != 3) {
6381 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6382 } else {
6383 if (s->cc_op != CC_OP_DYNAMIC)
6384 gen_op_set_cc_op(s->cc_op);
6385 gen_helper_read_eflags(cpu_T[0]);
6386 gen_push_T0(s);
6387 }
6388 break;
6389 case 0x9d: /* popf */
6390 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6391 if (s->vm86 && s->iopl != 3) {
6392 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6393 } else {
6394 gen_pop_T0(s);
6395 if (s->cpl == 0) {
6396 if (s->dflag) {
6397 gen_helper_write_eflags(cpu_T[0],
6398 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
6399 } else {
6400 gen_helper_write_eflags(cpu_T[0],
6401 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
6402 }
6403 } else {
6404 if (s->cpl <= s->iopl) {
6405 if (s->dflag) {
6406 gen_helper_write_eflags(cpu_T[0],
6407 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
6408 } else {
6409 gen_helper_write_eflags(cpu_T[0],
6410 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
6411 }
6412 } else {
6413 if (s->dflag) {
6414 gen_helper_write_eflags(cpu_T[0],
6415 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
6416 } else {
6417 gen_helper_write_eflags(cpu_T[0],
6418 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
6419 }
6420 }
6421 }
6422 gen_pop_update(s);
6423 s->cc_op = CC_OP_EFLAGS;
6424 /* abort translation because TF flag may change */
6425 gen_jmp_im(s->pc - s->cs_base);
6426 gen_eob(s);
6427 }
6428 break;
6429 case 0x9e: /* sahf */
6430 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6431 goto illegal_op;
6432 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
6433 if (s->cc_op != CC_OP_DYNAMIC)
6434 gen_op_set_cc_op(s->cc_op);
6435 gen_compute_eflags(cpu_cc_src);
6436 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6437 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6438 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6439 s->cc_op = CC_OP_EFLAGS;
6440 break;
6441 case 0x9f: /* lahf */
6442 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6443 goto illegal_op;
6444 if (s->cc_op != CC_OP_DYNAMIC)
6445 gen_op_set_cc_op(s->cc_op);
6446 gen_compute_eflags(cpu_T[0]);
6447 /* Note: gen_compute_eflags() only gives the condition codes */
6448 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
6449 gen_op_mov_reg_T0(OT_BYTE, R_AH);
6450 break;
6451 case 0xf5: /* cmc */
6452 if (s->cc_op != CC_OP_DYNAMIC)
6453 gen_op_set_cc_op(s->cc_op);
6454 gen_compute_eflags(cpu_cc_src);
6455 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6456 s->cc_op = CC_OP_EFLAGS;
6457 break;
6458 case 0xf8: /* clc */
6459 if (s->cc_op != CC_OP_DYNAMIC)
6460 gen_op_set_cc_op(s->cc_op);
6461 gen_compute_eflags(cpu_cc_src);
6462 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6463 s->cc_op = CC_OP_EFLAGS;
6464 break;
6465 case 0xf9: /* stc */
6466 if (s->cc_op != CC_OP_DYNAMIC)
6467 gen_op_set_cc_op(s->cc_op);
6468 gen_compute_eflags(cpu_cc_src);
6469 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6470 s->cc_op = CC_OP_EFLAGS;
6471 break;
6472 case 0xfc: /* cld */
6473 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6474 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6475 break;
6476 case 0xfd: /* std */
6477 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6478 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6479 break;
6480
6481 /************************/
6482 /* bit operations */
6483 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6484 ot = dflag + OT_WORD;
6485 modrm = ldub_code(s->pc++);
6486 op = (modrm >> 3) & 7;
6487 mod = (modrm >> 6) & 3;
6488 rm = (modrm & 7) | REX_B(s);
6489 if (mod != 3) {
6490 s->rip_offset = 1;
6491 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6492 gen_op_ld_T0_A0(ot + s->mem_index);
6493 } else {
6494 gen_op_mov_TN_reg(ot, 0, rm);
6495 }
6496 /* load shift */
6497 val = ldub_code(s->pc++);
6498 gen_op_movl_T1_im(val);
6499 if (op < 4)
6500 goto illegal_op;
6501 op -= 4;
6502 goto bt_op;
6503 case 0x1a3: /* bt Gv, Ev */
6504 op = 0;
6505 goto do_btx;
6506 case 0x1ab: /* bts */
6507 op = 1;
6508 goto do_btx;
6509 case 0x1b3: /* btr */
6510 op = 2;
6511 goto do_btx;
6512 case 0x1bb: /* btc */
6513 op = 3;
6514 do_btx:
6515 ot = dflag + OT_WORD;
6516 modrm = ldub_code(s->pc++);
6517 reg = ((modrm >> 3) & 7) | rex_r;
6518 mod = (modrm >> 6) & 3;
6519 rm = (modrm & 7) | REX_B(s);
6520 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6521 if (mod != 3) {
6522 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6523 /* specific case: we need to add a displacement */
6524 gen_exts(ot, cpu_T[1]);
6525 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6526 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6527 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6528 gen_op_ld_T0_A0(ot + s->mem_index);
6529 } else {
6530 gen_op_mov_TN_reg(ot, 0, rm);
6531 }
6532 bt_op:
6533 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6534 switch(op) {
6535 case 0:
6536 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6537 tcg_gen_movi_tl(cpu_cc_dst, 0);
6538 break;
6539 case 1:
6540 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6541 tcg_gen_movi_tl(cpu_tmp0, 1);
6542 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6543 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6544 break;
6545 case 2:
6546 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6547 tcg_gen_movi_tl(cpu_tmp0, 1);
6548 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6549 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6550 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6551 break;
6552 default:
6553 case 3:
6554 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6555 tcg_gen_movi_tl(cpu_tmp0, 1);
6556 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6557 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6558 break;
6559 }
6560 s->cc_op = CC_OP_SARB + ot;
6561 if (op != 0) {
6562 if (mod != 3)
6563 gen_op_st_T0_A0(ot + s->mem_index);
6564 else
6565 gen_op_mov_reg_T0(ot, rm);
6566 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6567 tcg_gen_movi_tl(cpu_cc_dst, 0);
6568 }
6569 break;
6570 case 0x1bc: /* bsf */
6571 case 0x1bd: /* bsr */
6572 {
6573 int label1;
6574 TCGv t0;
6575
6576 ot = dflag + OT_WORD;
6577 modrm = ldub_code(s->pc++);
6578 reg = ((modrm >> 3) & 7) | rex_r;
6579 gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0);
6580 gen_extu(ot, cpu_T[0]);
6581 t0 = tcg_temp_local_new();
6582 tcg_gen_mov_tl(t0, cpu_T[0]);
6583 if ((b & 1) && (prefixes & PREFIX_REPZ) &&
6584 (s->cpuid_ext3_features & CPUID_EXT3_ABM)) {
6585 switch(ot) {
6586 case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0,
6587 tcg_const_i32(16)); break;
6588 case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0,
6589 tcg_const_i32(32)); break;
6590 case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0,
6591 tcg_const_i32(64)); break;
6592 }
6593 gen_op_mov_reg_T0(ot, reg);
6594 } else {
6595 label1 = gen_new_label();
6596 tcg_gen_movi_tl(cpu_cc_dst, 0);
6597 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6598 if (b & 1) {
6599 gen_helper_bsr(cpu_T[0], t0);
6600 } else {
6601 gen_helper_bsf(cpu_T[0], t0);
6602 }
6603 gen_op_mov_reg_T0(ot, reg);
6604 tcg_gen_movi_tl(cpu_cc_dst, 1);
6605 gen_set_label(label1);
6606 tcg_gen_discard_tl(cpu_cc_src);
6607 s->cc_op = CC_OP_LOGICB + ot;
6608 }
6609 tcg_temp_free(t0);
6610 }
6611 break;
6612 /************************/
6613 /* bcd */
6614 case 0x27: /* daa */
6615 if (CODE64(s))
6616 goto illegal_op;
6617 if (s->cc_op != CC_OP_DYNAMIC)
6618 gen_op_set_cc_op(s->cc_op);
6619 gen_helper_daa();
6620 s->cc_op = CC_OP_EFLAGS;
6621 break;
6622 case 0x2f: /* das */
6623 if (CODE64(s))
6624 goto illegal_op;
6625 if (s->cc_op != CC_OP_DYNAMIC)
6626 gen_op_set_cc_op(s->cc_op);
6627 gen_helper_das();
6628 s->cc_op = CC_OP_EFLAGS;
6629 break;
6630 case 0x37: /* aaa */
6631 if (CODE64(s))
6632 goto illegal_op;
6633 if (s->cc_op != CC_OP_DYNAMIC)
6634 gen_op_set_cc_op(s->cc_op);
6635 gen_helper_aaa();
6636 s->cc_op = CC_OP_EFLAGS;
6637 break;
6638 case 0x3f: /* aas */
6639 if (CODE64(s))
6640 goto illegal_op;
6641 if (s->cc_op != CC_OP_DYNAMIC)
6642 gen_op_set_cc_op(s->cc_op);
6643 gen_helper_aas();
6644 s->cc_op = CC_OP_EFLAGS;
6645 break;
6646 case 0xd4: /* aam */
6647 if (CODE64(s))
6648 goto illegal_op;
6649 val = ldub_code(s->pc++);
6650 if (val == 0) {
6651 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6652 } else {
6653 gen_helper_aam(tcg_const_i32(val));
6654 s->cc_op = CC_OP_LOGICB;
6655 }
6656 break;
6657 case 0xd5: /* aad */
6658 if (CODE64(s))
6659 goto illegal_op;
6660 val = ldub_code(s->pc++);
6661 gen_helper_aad(tcg_const_i32(val));
6662 s->cc_op = CC_OP_LOGICB;
6663 break;
6664 /************************/
6665 /* misc */
6666 case 0x90: /* nop */
6667 /* XXX: xchg + rex handling */
6668 /* XXX: correct lock test for all insn */
6669 if (prefixes & PREFIX_LOCK)
6670 goto illegal_op;
6671 if (prefixes & PREFIX_REPZ) {
6672 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6673 }
6674 break;
6675 case 0x9b: /* fwait */
6676 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6677 (HF_MP_MASK | HF_TS_MASK)) {
6678 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6679 } else {
6680 if (s->cc_op != CC_OP_DYNAMIC)
6681 gen_op_set_cc_op(s->cc_op);
6682 gen_jmp_im(pc_start - s->cs_base);
6683 gen_helper_fwait();
6684 }
6685 break;
6686 case 0xcc: /* int3 */
6687 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6688 break;
6689 case 0xcd: /* int N */
6690 val = ldub_code(s->pc++);
6691 if (s->vm86 && s->iopl != 3) {
6692 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6693 } else {
6694 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6695 }
6696 break;
6697 case 0xce: /* into */
6698 if (CODE64(s))
6699 goto illegal_op;
6700 if (s->cc_op != CC_OP_DYNAMIC)
6701 gen_op_set_cc_op(s->cc_op);
6702 gen_jmp_im(pc_start - s->cs_base);
6703 gen_helper_into(tcg_const_i32(s->pc - pc_start));
6704 break;
6705 #ifdef WANT_ICEBP
6706 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6707 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6708 #if 1
6709 gen_debug(s, pc_start - s->cs_base);
6710 #else
6711 /* start debug */
6712 tb_flush(cpu_single_env);
6713 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6714 #endif
6715 break;
6716 #endif
6717 case 0xfa: /* cli */
6718 if (!s->vm86) {
6719 if (s->cpl <= s->iopl) {
6720 gen_helper_cli();
6721 } else {
6722 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6723 }
6724 } else {
6725 if (s->iopl == 3) {
6726 gen_helper_cli();
6727 } else {
6728 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6729 }
6730 }
6731 break;
6732 case 0xfb: /* sti */
6733 if (!s->vm86) {
6734 if (s->cpl <= s->iopl) {
6735 gen_sti:
6736 gen_helper_sti();
6737 /* interruptions are enabled only the first insn after sti */
6738 /* If several instructions disable interrupts, only the
6739 _first_ does it */
6740 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6741 gen_helper_set_inhibit_irq();
6742 /* give a chance to handle pending irqs */
6743 gen_jmp_im(s->pc - s->cs_base);
6744 gen_eob(s);
6745 } else {
6746 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6747 }
6748 } else {
6749 if (s->iopl == 3) {
6750 goto gen_sti;
6751 } else {
6752 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6753 }
6754 }
6755 break;
6756 case 0x62: /* bound */
6757 if (CODE64(s))
6758 goto illegal_op;
6759 ot = dflag ? OT_LONG : OT_WORD;
6760 modrm = ldub_code(s->pc++);
6761 reg = (modrm >> 3) & 7;
6762 mod = (modrm >> 6) & 3;
6763 if (mod == 3)
6764 goto illegal_op;
6765 gen_op_mov_TN_reg(ot, 0, reg);
6766 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6767 gen_jmp_im(pc_start - s->cs_base);
6768 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6769 if (ot == OT_WORD)
6770 gen_helper_boundw(cpu_A0, cpu_tmp2_i32);
6771 else
6772 gen_helper_boundl(cpu_A0, cpu_tmp2_i32);
6773 break;
6774 case 0x1c8 ... 0x1cf: /* bswap reg */
6775 reg = (b & 7) | REX_B(s);
6776 #ifdef TARGET_X86_64
6777 if (dflag == 2) {
6778 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6779 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6780 gen_op_mov_reg_T0(OT_QUAD, reg);
6781 } else
6782 #endif
6783 {
6784 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6785 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6786 tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
6787 gen_op_mov_reg_T0(OT_LONG, reg);
6788 }
6789 break;
6790 case 0xd6: /* salc */
6791 if (CODE64(s))
6792 goto illegal_op;
6793 if (s->cc_op != CC_OP_DYNAMIC)
6794 gen_op_set_cc_op(s->cc_op);
6795 gen_compute_eflags_c(cpu_T[0]);
6796 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6797 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6798 break;
6799 case 0xe0: /* loopnz */
6800 case 0xe1: /* loopz */
6801 case 0xe2: /* loop */
6802 case 0xe3: /* jecxz */
6803 {
6804 int l1, l2, l3;
6805
6806 tval = (int8_t)insn_get(s, OT_BYTE);
6807 next_eip = s->pc - s->cs_base;
6808 tval += next_eip;
6809 if (s->dflag == 0)
6810 tval &= 0xffff;
6811
6812 l1 = gen_new_label();
6813 l2 = gen_new_label();
6814 l3 = gen_new_label();
6815 b &= 3;
6816 switch(b) {
6817 case 0: /* loopnz */
6818 case 1: /* loopz */
6819 if (s->cc_op != CC_OP_DYNAMIC)
6820 gen_op_set_cc_op(s->cc_op);
6821 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6822 gen_op_jz_ecx(s->aflag, l3);
6823 gen_compute_eflags(cpu_tmp0);
6824 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6825 if (b == 0) {
6826 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
6827 } else {
6828 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
6829 }
6830 break;
6831 case 2: /* loop */
6832 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6833 gen_op_jnz_ecx(s->aflag, l1);
6834 break;
6835 default:
6836 case 3: /* jcxz */
6837 gen_op_jz_ecx(s->aflag, l1);
6838 break;
6839 }
6840
6841 gen_set_label(l3);
6842 gen_jmp_im(next_eip);
6843 tcg_gen_br(l2);
6844
6845 gen_set_label(l1);
6846 gen_jmp_im(tval);
6847 gen_set_label(l2);
6848 gen_eob(s);
6849 }
6850 break;
6851 case 0x130: /* wrmsr */
6852 case 0x132: /* rdmsr */
6853 if (s->cpl != 0) {
6854 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6855 } else {
6856 if (s->cc_op != CC_OP_DYNAMIC)
6857 gen_op_set_cc_op(s->cc_op);
6858 gen_jmp_im(pc_start - s->cs_base);
6859 if (b & 2) {
6860 gen_helper_rdmsr();
6861 } else {
6862 gen_helper_wrmsr();
6863 }
6864 }
6865 break;
6866 case 0x131: /* rdtsc */
6867 if (s->cc_op != CC_OP_DYNAMIC)
6868 gen_op_set_cc_op(s->cc_op);
6869 gen_jmp_im(pc_start - s->cs_base);
6870 if (use_icount)
6871 gen_io_start();
6872 gen_helper_rdtsc();
6873 if (use_icount) {
6874 gen_io_end();
6875 gen_jmp(s, s->pc - s->cs_base);
6876 }
6877 break;
6878 case 0x133: /* rdpmc */
6879 if (s->cc_op != CC_OP_DYNAMIC)
6880 gen_op_set_cc_op(s->cc_op);
6881 gen_jmp_im(pc_start - s->cs_base);
6882 gen_helper_rdpmc();
6883 break;
6884 case 0x134: /* sysenter */
6885 /* For Intel SYSENTER is valid on 64-bit */
6886 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6887 goto illegal_op;
6888 if (!s->pe) {
6889 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6890 } else {
6891 if (s->cc_op != CC_OP_DYNAMIC) {
6892 gen_op_set_cc_op(s->cc_op);
6893 s->cc_op = CC_OP_DYNAMIC;
6894 }
6895 gen_jmp_im(pc_start - s->cs_base);
6896 gen_helper_sysenter();
6897 gen_eob(s);
6898 }
6899 break;
6900 case 0x135: /* sysexit */
6901 /* For Intel SYSEXIT is valid on 64-bit */
6902 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6903 goto illegal_op;
6904 if (!s->pe) {
6905 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6906 } else {
6907 if (s->cc_op != CC_OP_DYNAMIC) {
6908 gen_op_set_cc_op(s->cc_op);
6909 s->cc_op = CC_OP_DYNAMIC;
6910 }
6911 gen_jmp_im(pc_start - s->cs_base);
6912 gen_helper_sysexit(tcg_const_i32(dflag));
6913 gen_eob(s);
6914 }
6915 break;
6916 #ifdef TARGET_X86_64
6917 case 0x105: /* syscall */
6918 /* XXX: is it usable in real mode ? */
6919 if (s->cc_op != CC_OP_DYNAMIC) {
6920 gen_op_set_cc_op(s->cc_op);
6921 s->cc_op = CC_OP_DYNAMIC;
6922 }
6923 gen_jmp_im(pc_start - s->cs_base);
6924 gen_helper_syscall(tcg_const_i32(s->pc - pc_start));
6925 gen_eob(s);
6926 break;
6927 case 0x107: /* sysret */
6928 if (!s->pe) {
6929 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6930 } else {
6931 if (s->cc_op != CC_OP_DYNAMIC) {
6932 gen_op_set_cc_op(s->cc_op);
6933 s->cc_op = CC_OP_DYNAMIC;
6934 }
6935 gen_jmp_im(pc_start - s->cs_base);
6936 gen_helper_sysret(tcg_const_i32(s->dflag));
6937 /* condition codes are modified only in long mode */
6938 if (s->lma)
6939 s->cc_op = CC_OP_EFLAGS;
6940 gen_eob(s);
6941 }
6942 break;
6943 #endif
6944 case 0x1a2: /* cpuid */
6945 if (s->cc_op != CC_OP_DYNAMIC)
6946 gen_op_set_cc_op(s->cc_op);
6947 gen_jmp_im(pc_start - s->cs_base);
6948 gen_helper_cpuid();
6949 break;
6950 case 0xf4: /* hlt */
6951 if (s->cpl != 0) {
6952 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6953 } else {
6954 if (s->cc_op != CC_OP_DYNAMIC)
6955 gen_op_set_cc_op(s->cc_op);
6956 gen_jmp_im(pc_start - s->cs_base);
6957 gen_helper_hlt(tcg_const_i32(s->pc - pc_start));
6958 s->is_jmp = 3;
6959 }
6960 break;
6961 case 0x100:
6962 modrm = ldub_code(s->pc++);
6963 mod = (modrm >> 6) & 3;
6964 op = (modrm >> 3) & 7;
6965 switch(op) {
6966 case 0: /* sldt */
6967 if (!s->pe || s->vm86)
6968 goto illegal_op;
6969 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
6970 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
6971 ot = OT_WORD;
6972 if (mod == 3)
6973 ot += s->dflag;
6974 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6975 break;
6976 case 2: /* lldt */
6977 if (!s->pe || s->vm86)
6978 goto illegal_op;
6979 if (s->cpl != 0) {
6980 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6981 } else {
6982 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
6983 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6984 gen_jmp_im(pc_start - s->cs_base);
6985 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6986 gen_helper_lldt(cpu_tmp2_i32);
6987 }
6988 break;
6989 case 1: /* str */
6990 if (!s->pe || s->vm86)
6991 goto illegal_op;
6992 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
6993 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
6994 ot = OT_WORD;
6995 if (mod == 3)
6996 ot += s->dflag;
6997 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6998 break;
6999 case 3: /* ltr */
7000 if (!s->pe || s->vm86)
7001 goto illegal_op;
7002 if (s->cpl != 0) {
7003 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7004 } else {
7005 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
7006 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7007 gen_jmp_im(pc_start - s->cs_base);
7008 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7009 gen_helper_ltr(cpu_tmp2_i32);
7010 }
7011 break;
7012 case 4: /* verr */
7013 case 5: /* verw */
7014 if (!s->pe || s->vm86)
7015 goto illegal_op;
7016 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7017 if (s->cc_op != CC_OP_DYNAMIC)
7018 gen_op_set_cc_op(s->cc_op);
7019 if (op == 4)
7020 gen_helper_verr(cpu_T[0]);
7021 else
7022 gen_helper_verw(cpu_T[0]);
7023 s->cc_op = CC_OP_EFLAGS;
7024 break;
7025 default:
7026 goto illegal_op;
7027 }
7028 break;
7029 case 0x101:
7030 modrm = ldub_code(s->pc++);
7031 mod = (modrm >> 6) & 3;
7032 op = (modrm >> 3) & 7;
7033 rm = modrm & 7;
7034 switch(op) {
7035 case 0: /* sgdt */
7036 if (mod == 3)
7037 goto illegal_op;
7038 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
7039 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7040 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
7041 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7042 gen_add_A0_im(s, 2);
7043 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
7044 if (!s->dflag)
7045 gen_op_andl_T0_im(0xffffff);
7046 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7047 break;
7048 case 1:
7049 if (mod == 3) {
7050 switch (rm) {
7051 case 0: /* monitor */
7052 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7053 s->cpl != 0)
7054 goto illegal_op;
7055 if (s->cc_op != CC_OP_DYNAMIC)
7056 gen_op_set_cc_op(s->cc_op);
7057 gen_jmp_im(pc_start - s->cs_base);
7058 #ifdef TARGET_X86_64
7059 if (s->aflag == 2) {
7060 gen_op_movq_A0_reg(R_EAX);
7061 } else
7062 #endif
7063 {
7064 gen_op_movl_A0_reg(R_EAX);
7065 if (s->aflag == 0)
7066 gen_op_andl_A0_ffff();
7067 }
7068 gen_add_A0_ds_seg(s);
7069 gen_helper_monitor(cpu_A0);
7070 break;
7071 case 1: /* mwait */
7072 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7073 s->cpl != 0)
7074 goto illegal_op;
7075 if (s->cc_op != CC_OP_DYNAMIC) {
7076 gen_op_set_cc_op(s->cc_op);
7077 s->cc_op = CC_OP_DYNAMIC;
7078 }
7079 gen_jmp_im(pc_start - s->cs_base);
7080 gen_helper_mwait(tcg_const_i32(s->pc - pc_start));
7081 gen_eob(s);
7082 break;
7083 default:
7084 goto illegal_op;
7085 }
7086 } else { /* sidt */
7087 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
7088 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7089 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7090 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7091 gen_add_A0_im(s, 2);
7092 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7093 if (!s->dflag)
7094 gen_op_andl_T0_im(0xffffff);
7095 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7096 }
7097 break;
7098 case 2: /* lgdt */
7099 case 3: /* lidt */
7100 if (mod == 3) {
7101 if (s->cc_op != CC_OP_DYNAMIC)
7102 gen_op_set_cc_op(s->cc_op);
7103 gen_jmp_im(pc_start - s->cs_base);
7104 switch(rm) {
7105 case 0: /* VMRUN */
7106 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7107 goto illegal_op;
7108 if (s->cpl != 0) {
7109 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7110 break;
7111 } else {
7112 gen_helper_vmrun(tcg_const_i32(s->aflag),
7113 tcg_const_i32(s->pc - pc_start));
7114 tcg_gen_exit_tb(0);
7115 s->is_jmp = 3;
7116 }
7117 break;
7118 case 1: /* VMMCALL */
7119 if (!(s->flags & HF_SVME_MASK))
7120 goto illegal_op;
7121 gen_helper_vmmcall();
7122 break;
7123 case 2: /* VMLOAD */
7124 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7125 goto illegal_op;
7126 if (s->cpl != 0) {
7127 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7128 break;
7129 } else {
7130 gen_helper_vmload(tcg_const_i32(s->aflag));
7131 }
7132 break;
7133 case 3: /* VMSAVE */
7134 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7135 goto illegal_op;
7136 if (s->cpl != 0) {
7137 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7138 break;
7139 } else {
7140 gen_helper_vmsave(tcg_const_i32(s->aflag));
7141 }
7142 break;
7143 case 4: /* STGI */
7144 if ((!(s->flags & HF_SVME_MASK) &&
7145 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7146 !s->pe)
7147 goto illegal_op;
7148 if (s->cpl != 0) {
7149 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7150 break;
7151 } else {
7152 gen_helper_stgi();
7153 }
7154 break;
7155 case 5: /* CLGI */
7156 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7157 goto illegal_op;
7158 if (s->cpl != 0) {
7159 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7160 break;
7161 } else {
7162 gen_helper_clgi();
7163 }
7164 break;
7165 case 6: /* SKINIT */
7166 if ((!(s->flags & HF_SVME_MASK) &&
7167 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7168 !s->pe)
7169 goto illegal_op;
7170 gen_helper_skinit();
7171 break;
7172 case 7: /* INVLPGA */
7173 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7174 goto illegal_op;
7175 if (s->cpl != 0) {
7176 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7177 break;
7178 } else {
7179 gen_helper_invlpga(tcg_const_i32(s->aflag));
7180 }
7181 break;
7182 default:
7183 goto illegal_op;
7184 }
7185 } else if (s->cpl != 0) {
7186 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7187 } else {
7188 gen_svm_check_intercept(s, pc_start,
7189 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
7190 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7191 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
7192 gen_add_A0_im(s, 2);
7193 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7194 if (!s->dflag)
7195 gen_op_andl_T0_im(0xffffff);
7196 if (op == 2) {
7197 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7198 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7199 } else {
7200 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7201 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7202 }
7203 }
7204 break;
7205 case 4: /* smsw */
7206 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
7207 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7208 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7209 #else
7210 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7211 #endif
7212 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
7213 break;
7214 case 6: /* lmsw */
7215 if (s->cpl != 0) {
7216 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7217 } else {
7218 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7219 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7220 gen_helper_lmsw(cpu_T[0]);
7221 gen_jmp_im(s->pc - s->cs_base);
7222 gen_eob(s);
7223 }
7224 break;
7225 case 7:
7226 if (mod != 3) { /* invlpg */
7227 if (s->cpl != 0) {
7228 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7229 } else {
7230 if (s->cc_op != CC_OP_DYNAMIC)
7231 gen_op_set_cc_op(s->cc_op);
7232 gen_jmp_im(pc_start - s->cs_base);
7233 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7234 gen_helper_invlpg(cpu_A0);
7235 gen_jmp_im(s->pc - s->cs_base);
7236 gen_eob(s);
7237 }
7238 } else {
7239 switch (rm) {
7240 case 0: /* swapgs */
7241 #ifdef TARGET_X86_64
7242 if (CODE64(s)) {
7243 if (s->cpl != 0) {
7244 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7245 } else {
7246 tcg_gen_ld_tl(cpu_T[0], cpu_env,
7247 offsetof(CPUX86State,segs[R_GS].base));
7248 tcg_gen_ld_tl(cpu_T[1], cpu_env,
7249 offsetof(CPUX86State,kernelgsbase));
7250 tcg_gen_st_tl(cpu_T[1], cpu_env,
7251 offsetof(CPUX86State,segs[R_GS].base));
7252 tcg_gen_st_tl(cpu_T[0], cpu_env,
7253 offsetof(CPUX86State,kernelgsbase));
7254 }
7255 } else
7256 #endif
7257 {
7258 goto illegal_op;
7259 }
7260 break;
7261 case 1: /* rdtscp */
7262 if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP))
7263 goto illegal_op;
7264 if (s->cc_op != CC_OP_DYNAMIC)
7265 gen_op_set_cc_op(s->cc_op);
7266 gen_jmp_im(pc_start - s->cs_base);
7267 if (use_icount)
7268 gen_io_start();
7269 gen_helper_rdtscp();
7270 if (use_icount) {
7271 gen_io_end();
7272 gen_jmp(s, s->pc - s->cs_base);
7273 }
7274 break;
7275 default:
7276 goto illegal_op;
7277 }
7278 }
7279 break;
7280 default:
7281 goto illegal_op;
7282 }
7283 break;
7284 case 0x108: /* invd */
7285 case 0x109: /* wbinvd */
7286 if (s->cpl != 0) {
7287 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7288 } else {
7289 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
7290 /* nothing to do */
7291 }
7292 break;
7293 case 0x63: /* arpl or movslS (x86_64) */
7294 #ifdef TARGET_X86_64
7295 if (CODE64(s)) {
7296 int d_ot;
7297 /* d_ot is the size of destination */
7298 d_ot = dflag + OT_WORD;
7299
7300 modrm = ldub_code(s->pc++);
7301 reg = ((modrm >> 3) & 7) | rex_r;
7302 mod = (modrm >> 6) & 3;
7303 rm = (modrm & 7) | REX_B(s);
7304
7305 if (mod == 3) {
7306 gen_op_mov_TN_reg(OT_LONG, 0, rm);
7307 /* sign extend */
7308 if (d_ot == OT_QUAD)
7309 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7310 gen_op_mov_reg_T0(d_ot, reg);
7311 } else {
7312 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7313 if (d_ot == OT_QUAD) {
7314 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
7315 } else {
7316 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7317 }
7318 gen_op_mov_reg_T0(d_ot, reg);
7319 }
7320 } else
7321 #endif
7322 {
7323 int label1;
7324 TCGv t0, t1, t2, a0;
7325
7326 if (!s->pe || s->vm86)
7327 goto illegal_op;
7328 t0 = tcg_temp_local_new();
7329 t1 = tcg_temp_local_new();
7330 t2 = tcg_temp_local_new();
7331 ot = OT_WORD;
7332 modrm = ldub_code(s->pc++);
7333 reg = (modrm >> 3) & 7;
7334 mod = (modrm >> 6) & 3;
7335 rm = modrm & 7;
7336 if (mod != 3) {
7337 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7338 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
7339 a0 = tcg_temp_local_new();
7340 tcg_gen_mov_tl(a0, cpu_A0);
7341 } else {
7342 gen_op_mov_v_reg(ot, t0, rm);
7343 TCGV_UNUSED(a0);
7344 }
7345 gen_op_mov_v_reg(ot, t1, reg);
7346 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7347 tcg_gen_andi_tl(t1, t1, 3);
7348 tcg_gen_movi_tl(t2, 0);
7349 label1 = gen_new_label();
7350 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7351 tcg_gen_andi_tl(t0, t0, ~3);
7352 tcg_gen_or_tl(t0, t0, t1);
7353 tcg_gen_movi_tl(t2, CC_Z);
7354 gen_set_label(label1);
7355 if (mod != 3) {
7356 gen_op_st_v(ot + s->mem_index, t0, a0);
7357 tcg_temp_free(a0);
7358 } else {
7359 gen_op_mov_reg_v(ot, rm, t0);
7360 }
7361 if (s->cc_op != CC_OP_DYNAMIC)
7362 gen_op_set_cc_op(s->cc_op);
7363 gen_compute_eflags(cpu_cc_src);
7364 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7365 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
7366 s->cc_op = CC_OP_EFLAGS;
7367 tcg_temp_free(t0);
7368 tcg_temp_free(t1);
7369 tcg_temp_free(t2);
7370 }
7371 break;
7372 case 0x102: /* lar */
7373 case 0x103: /* lsl */
7374 {
7375 int label1;
7376 TCGv t0;
7377 if (!s->pe || s->vm86)
7378 goto illegal_op;
7379 ot = dflag ? OT_LONG : OT_WORD;
7380 modrm = ldub_code(s->pc++);
7381 reg = ((modrm >> 3) & 7) | rex_r;
7382 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7383 t0 = tcg_temp_local_new();
7384 if (s->cc_op != CC_OP_DYNAMIC)
7385 gen_op_set_cc_op(s->cc_op);
7386 if (b == 0x102)
7387 gen_helper_lar(t0, cpu_T[0]);
7388 else
7389 gen_helper_lsl(t0, cpu_T[0]);
7390 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7391 label1 = gen_new_label();
7392 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7393 gen_op_mov_reg_v(ot, reg, t0);
7394 gen_set_label(label1);
7395 s->cc_op = CC_OP_EFLAGS;
7396 tcg_temp_free(t0);
7397 }
7398 break;
7399 case 0x118:
7400 modrm = ldub_code(s->pc++);
7401 mod = (modrm >> 6) & 3;
7402 op = (modrm >> 3) & 7;
7403 switch(op) {
7404 case 0: /* prefetchnta */
7405 case 1: /* prefetchnt0 */
7406 case 2: /* prefetchnt0 */
7407 case 3: /* prefetchnt0 */
7408 if (mod == 3)
7409 goto illegal_op;
7410 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7411 /* nothing more to do */
7412 break;
7413 default: /* nop (multi byte) */
7414 gen_nop_modrm(s, modrm);
7415 break;
7416 }
7417 break;
7418 case 0x119 ... 0x11f: /* nop (multi byte) */
7419 modrm = ldub_code(s->pc++);
7420 gen_nop_modrm(s, modrm);
7421 break;
7422 case 0x120: /* mov reg, crN */
7423 case 0x122: /* mov crN, reg */
7424 if (s->cpl != 0) {
7425 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7426 } else {
7427 modrm = ldub_code(s->pc++);
7428 if ((modrm & 0xc0) != 0xc0)
7429 goto illegal_op;
7430 rm = (modrm & 7) | REX_B(s);
7431 reg = ((modrm >> 3) & 7) | rex_r;
7432 if (CODE64(s))
7433 ot = OT_QUAD;
7434 else
7435 ot = OT_LONG;
7436 if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
7437 (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
7438 reg = 8;
7439 }
7440 switch(reg) {
7441 case 0:
7442 case 2:
7443 case 3:
7444 case 4:
7445 case 8:
7446 if (s->cc_op != CC_OP_DYNAMIC)
7447 gen_op_set_cc_op(s->cc_op);
7448 gen_jmp_im(pc_start - s->cs_base);
7449 if (b & 2) {
7450 gen_op_mov_TN_reg(ot, 0, rm);
7451 gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
7452 gen_jmp_im(s->pc - s->cs_base);
7453 gen_eob(s);
7454 } else {
7455 gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
7456 gen_op_mov_reg_T0(ot, rm);
7457 }
7458 break;
7459 default:
7460 goto illegal_op;
7461 }
7462 }
7463 break;
7464 case 0x121: /* mov reg, drN */
7465 case 0x123: /* mov drN, reg */
7466 if (s->cpl != 0) {
7467 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7468 } else {
7469 modrm = ldub_code(s->pc++);
7470 if ((modrm & 0xc0) != 0xc0)
7471 goto illegal_op;
7472 rm = (modrm & 7) | REX_B(s);
7473 reg = ((modrm >> 3) & 7) | rex_r;
7474 if (CODE64(s))
7475 ot = OT_QUAD;
7476 else
7477 ot = OT_LONG;
7478 /* XXX: do it dynamically with CR4.DE bit */
7479 if (reg == 4 || reg == 5 || reg >= 8)
7480 goto illegal_op;
7481 if (b & 2) {
7482 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7483 gen_op_mov_TN_reg(ot, 0, rm);
7484 gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
7485 gen_jmp_im(s->pc - s->cs_base);
7486 gen_eob(s);
7487 } else {
7488 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7489 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7490 gen_op_mov_reg_T0(ot, rm);
7491 }
7492 }
7493 break;
7494 case 0x106: /* clts */
7495 if (s->cpl != 0) {
7496 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7497 } else {
7498 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7499 gen_helper_clts();
7500 /* abort block because static cpu state changed */
7501 gen_jmp_im(s->pc - s->cs_base);
7502 gen_eob(s);
7503 }
7504 break;
7505 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7506 case 0x1c3: /* MOVNTI reg, mem */
7507 if (!(s->cpuid_features & CPUID_SSE2))
7508 goto illegal_op;
7509 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7510 modrm = ldub_code(s->pc++);
7511 mod = (modrm >> 6) & 3;
7512 if (mod == 3)
7513 goto illegal_op;
7514 reg = ((modrm >> 3) & 7) | rex_r;
7515 /* generate a generic store */
7516 gen_ldst_modrm(s, modrm, ot, reg, 1);
7517 break;
7518 case 0x1ae:
7519 modrm = ldub_code(s->pc++);
7520 mod = (modrm >> 6) & 3;
7521 op = (modrm >> 3) & 7;
7522 switch(op) {
7523 case 0: /* fxsave */
7524 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7525 (s->prefix & PREFIX_LOCK))
7526 goto illegal_op;
7527 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7528 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7529 break;
7530 }
7531 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7532 if (s->cc_op != CC_OP_DYNAMIC)
7533 gen_op_set_cc_op(s->cc_op);
7534 gen_jmp_im(pc_start - s->cs_base);
7535 gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2)));
7536 break;
7537 case 1: /* fxrstor */
7538 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7539 (s->prefix & PREFIX_LOCK))
7540 goto illegal_op;
7541 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7542 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7543 break;
7544 }
7545 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7546 if (s->cc_op != CC_OP_DYNAMIC)
7547 gen_op_set_cc_op(s->cc_op);
7548 gen_jmp_im(pc_start - s->cs_base);
7549 gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2)));
7550 break;
7551 case 2: /* ldmxcsr */
7552 case 3: /* stmxcsr */
7553 if (s->flags & HF_TS_MASK) {
7554 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7555 break;
7556 }
7557 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7558 mod == 3)
7559 goto illegal_op;
7560 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7561 if (op == 2) {
7562 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7563 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7564 } else {
7565 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7566 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7567 }
7568 break;
7569 case 5: /* lfence */
7570 case 6: /* mfence */
7571 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
7572 goto illegal_op;
7573 break;
7574 case 7: /* sfence / clflush */
7575 if ((modrm & 0xc7) == 0xc0) {
7576 /* sfence */
7577 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7578 if (!(s->cpuid_features & CPUID_SSE))
7579 goto illegal_op;
7580 } else {
7581 /* clflush */
7582 if (!(s->cpuid_features & CPUID_CLFLUSH))
7583 goto illegal_op;
7584 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7585 }
7586 break;
7587 default:
7588 goto illegal_op;
7589 }
7590 break;
7591 case 0x10d: /* 3DNow! prefetch(w) */
7592 modrm = ldub_code(s->pc++);
7593 mod = (modrm >> 6) & 3;
7594 if (mod == 3)
7595 goto illegal_op;
7596 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7597 /* ignore for now */
7598 break;
7599 case 0x1aa: /* rsm */
7600 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7601 if (!(s->flags & HF_SMM_MASK))
7602 goto illegal_op;
7603 if (s->cc_op != CC_OP_DYNAMIC) {
7604 gen_op_set_cc_op(s->cc_op);
7605 s->cc_op = CC_OP_DYNAMIC;
7606 }
7607 gen_jmp_im(s->pc - s->cs_base);
7608 gen_helper_rsm();
7609 gen_eob(s);
7610 break;
7611 case 0x1b8: /* SSE4.2 popcnt */
7612 if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7613 PREFIX_REPZ)
7614 goto illegal_op;
7615 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7616 goto illegal_op;
7617
7618 modrm = ldub_code(s->pc++);
7619 reg = ((modrm >> 3) & 7);
7620
7621 if (s->prefix & PREFIX_DATA)
7622 ot = OT_WORD;
7623 else if (s->dflag != 2)
7624 ot = OT_LONG;
7625 else
7626 ot = OT_QUAD;
7627
7628 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
7629 gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot));
7630 gen_op_mov_reg_T0(ot, reg);
7631
7632 s->cc_op = CC_OP_EFLAGS;
7633 break;
7634 case 0x10e ... 0x10f:
7635 /* 3DNow! instructions, ignore prefixes */
7636 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7637 case 0x110 ... 0x117:
7638 case 0x128 ... 0x12f:
7639 case 0x138 ... 0x13a:
7640 case 0x150 ... 0x179:
7641 case 0x17c ... 0x17f:
7642 case 0x1c2:
7643 case 0x1c4 ... 0x1c6:
7644 case 0x1d0 ... 0x1fe:
7645 gen_sse(s, b, pc_start, rex_r);
7646 break;
7647 default:
7648 goto illegal_op;
7649 }
7650 /* lock generation */
7651 if (s->prefix & PREFIX_LOCK)
7652 gen_helper_unlock();
7653 return s->pc;
7654 illegal_op:
7655 if (s->prefix & PREFIX_LOCK)
7656 gen_helper_unlock();
7657 /* XXX: ensure that no lock was generated */
7658 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7659 return s->pc;
7660 }
7661
7662 void optimize_flags_init(void)
7663 {
7664 #if TCG_TARGET_REG_BITS == 32
7665 assert(sizeof(CCTable) == (1 << 3));
7666 #else
7667 assert(sizeof(CCTable) == (1 << 4));
7668 #endif
7669 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7670 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7671 offsetof(CPUState, cc_op), "cc_op");
7672 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
7673 "cc_src");
7674 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
7675 "cc_dst");
7676 cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp),
7677 "cc_tmp");
7678
7679 #ifdef TARGET_X86_64
7680 cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
7681 offsetof(CPUState, regs[R_EAX]), "rax");
7682 cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
7683 offsetof(CPUState, regs[R_ECX]), "rcx");
7684 cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
7685 offsetof(CPUState, regs[R_EDX]), "rdx");
7686 cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
7687 offsetof(CPUState, regs[R_EBX]), "rbx");
7688 cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
7689 offsetof(CPUState, regs[R_ESP]), "rsp");
7690 cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
7691 offsetof(CPUState, regs[R_EBP]), "rbp");
7692 cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
7693 offsetof(CPUState, regs[R_ESI]), "rsi");
7694 cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
7695 offsetof(CPUState, regs[R_EDI]), "rdi");
7696 cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
7697 offsetof(CPUState, regs[8]), "r8");
7698 cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
7699 offsetof(CPUState, regs[9]), "r9");
7700 cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
7701 offsetof(CPUState, regs[10]), "r10");
7702 cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
7703 offsetof(CPUState, regs[11]), "r11");
7704 cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
7705 offsetof(CPUState, regs[12]), "r12");
7706 cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
7707 offsetof(CPUState, regs[13]), "r13");
7708 cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
7709 offsetof(CPUState, regs[14]), "r14");
7710 cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
7711 offsetof(CPUState, regs[15]), "r15");
7712 #else
7713 cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
7714 offsetof(CPUState, regs[R_EAX]), "eax");
7715 cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
7716 offsetof(CPUState, regs[R_ECX]), "ecx");
7717 cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
7718 offsetof(CPUState, regs[R_EDX]), "edx");
7719 cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
7720 offsetof(CPUState, regs[R_EBX]), "ebx");
7721 cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
7722 offsetof(CPUState, regs[R_ESP]), "esp");
7723 cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
7724 offsetof(CPUState, regs[R_EBP]), "ebp");
7725 cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
7726 offsetof(CPUState, regs[R_ESI]), "esi");
7727 cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
7728 offsetof(CPUState, regs[R_EDI]), "edi");
7729 #endif
7730
7731 /* register helpers */
7732 #define GEN_HELPER 2
7733 #include "helper.h"
7734 }
7735
7736 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7737 basic block 'tb'. If search_pc is TRUE, also generate PC
7738 information for each intermediate instruction. */
7739 static inline void gen_intermediate_code_internal(CPUState *env,
7740 TranslationBlock *tb,
7741 int search_pc)
7742 {
7743 DisasContext dc1, *dc = &dc1;
7744 target_ulong pc_ptr;
7745 uint16_t *gen_opc_end;
7746 CPUBreakpoint *bp;
7747 int j, lj, cflags;
7748 uint64_t flags;
7749 target_ulong pc_start;
7750 target_ulong cs_base;
7751 int num_insns;
7752 int max_insns;
7753
7754 /* generate intermediate code */
7755 pc_start = tb->pc;
7756 cs_base = tb->cs_base;
7757 flags = tb->flags;
7758 cflags = tb->cflags;
7759
7760 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7761 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7762 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7763 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7764 dc->f_st = 0;
7765 dc->vm86 = (flags >> VM_SHIFT) & 1;
7766 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7767 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7768 dc->tf = (flags >> TF_SHIFT) & 1;
7769 dc->singlestep_enabled = env->singlestep_enabled;
7770 dc->cc_op = CC_OP_DYNAMIC;
7771 dc->cs_base = cs_base;
7772 dc->tb = tb;
7773 dc->popl_esp_hack = 0;
7774 /* select memory access functions */
7775 dc->mem_index = 0;
7776 if (flags & HF_SOFTMMU_MASK) {
7777 if (dc->cpl == 3)
7778 dc->mem_index = 2 * 4;
7779 else
7780 dc->mem_index = 1 * 4;
7781 }
7782 dc->cpuid_features = env->cpuid_features;
7783 dc->cpuid_ext_features = env->cpuid_ext_features;
7784 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7785 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7786 #ifdef TARGET_X86_64
7787 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7788 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7789 #endif
7790 dc->flags = flags;
7791 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7792 (flags & HF_INHIBIT_IRQ_MASK)
7793 #ifndef CONFIG_SOFTMMU
7794 || (flags & HF_SOFTMMU_MASK)
7795 #endif
7796 );
7797 #if 0
7798 /* check addseg logic */
7799 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7800 printf("ERROR addseg\n");
7801 #endif
7802
7803 cpu_T[0] = tcg_temp_new();
7804 cpu_T[1] = tcg_temp_new();
7805 cpu_A0 = tcg_temp_new();
7806 cpu_T3 = tcg_temp_new();
7807
7808 cpu_tmp0 = tcg_temp_new();
7809 cpu_tmp1_i64 = tcg_temp_new_i64();
7810 cpu_tmp2_i32 = tcg_temp_new_i32();
7811 cpu_tmp3_i32 = tcg_temp_new_i32();
7812 cpu_tmp4 = tcg_temp_new();
7813 cpu_tmp5 = tcg_temp_new();
7814 cpu_ptr0 = tcg_temp_new_ptr();
7815 cpu_ptr1 = tcg_temp_new_ptr();
7816
7817 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7818
7819 dc->is_jmp = DISAS_NEXT;
7820 pc_ptr = pc_start;
7821 lj = -1;
7822 num_insns = 0;
7823 max_insns = tb->cflags & CF_COUNT_MASK;
7824 if (max_insns == 0)
7825 max_insns = CF_COUNT_MASK;
7826
7827 gen_icount_start();
7828 for(;;) {
7829 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
7830 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
7831 if (bp->pc == pc_ptr &&
7832 !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
7833 gen_debug(dc, pc_ptr - dc->cs_base);
7834 break;
7835 }
7836 }
7837 }
7838 if (search_pc) {
7839 j = gen_opc_ptr - gen_opc_buf;
7840 if (lj < j) {
7841 lj++;
7842 while (lj < j)
7843 gen_opc_instr_start[lj++] = 0;
7844 }
7845 gen_opc_pc[lj] = pc_ptr;
7846 gen_opc_cc_op[lj] = dc->cc_op;
7847 gen_opc_instr_start[lj] = 1;
7848 gen_opc_icount[lj] = num_insns;
7849 }
7850 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7851 gen_io_start();
7852
7853 pc_ptr = disas_insn(dc, pc_ptr);
7854 num_insns++;
7855 /* stop translation if indicated */
7856 if (dc->is_jmp)
7857 break;
7858 /* if single step mode, we generate only one instruction and
7859 generate an exception */
7860 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7861 the flag and abort the translation to give the irqs a
7862 change to be happen */
7863 if (dc->tf || dc->singlestep_enabled ||
7864 (flags & HF_INHIBIT_IRQ_MASK)) {
7865 gen_jmp_im(pc_ptr - dc->cs_base);
7866 gen_eob(dc);
7867 break;
7868 }
7869 /* if too long translation, stop generation too */
7870 if (gen_opc_ptr >= gen_opc_end ||
7871 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7872 num_insns >= max_insns) {
7873 gen_jmp_im(pc_ptr - dc->cs_base);
7874 gen_eob(dc);
7875 break;
7876 }
7877 if (singlestep) {
7878 gen_jmp_im(pc_ptr - dc->cs_base);
7879 gen_eob(dc);
7880 break;
7881 }
7882 }
7883 if (tb->cflags & CF_LAST_IO)
7884 gen_io_end();
7885 gen_icount_end(tb, num_insns);
7886 *gen_opc_ptr = INDEX_op_end;
7887 /* we don't forget to fill the last values */
7888 if (search_pc) {
7889 j = gen_opc_ptr - gen_opc_buf;
7890 lj++;
7891 while (lj <= j)
7892 gen_opc_instr_start[lj++] = 0;
7893 }
7894
7895 #ifdef DEBUG_DISAS
7896 log_cpu_state_mask(CPU_LOG_TB_CPU, env, X86_DUMP_CCOP);
7897 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
7898 int disas_flags;
7899 qemu_log("----------------\n");
7900 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7901 #ifdef TARGET_X86_64
7902 if (dc->code64)
7903 disas_flags = 2;
7904 else
7905 #endif
7906 disas_flags = !dc->code32;
7907 log_target_disas(pc_start, pc_ptr - pc_start, disas_flags);
7908 qemu_log("\n");
7909 }
7910 #endif
7911
7912 if (!search_pc) {
7913 tb->size = pc_ptr - pc_start;
7914 tb->icount = num_insns;
7915 }
7916 }
7917
7918 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
7919 {
7920 gen_intermediate_code_internal(env, tb, 0);
7921 }
7922
7923 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
7924 {
7925 gen_intermediate_code_internal(env, tb, 1);
7926 }
7927
7928 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7929 unsigned long searched_pc, int pc_pos, void *puc)
7930 {
7931 int cc_op;
7932 #ifdef DEBUG_DISAS
7933 if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
7934 int i;
7935 qemu_log("RESTORE:\n");
7936 for(i = 0;i <= pc_pos; i++) {
7937 if (gen_opc_instr_start[i]) {
7938 qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7939 }
7940 }
7941 qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7942 searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7943 (uint32_t)tb->cs_base);
7944 }
7945 #endif
7946 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7947 cc_op = gen_opc_cc_op[pc_pos];
7948 if (cc_op != CC_OP_DYNAMIC)
7949 env->cc_op = cc_op;
7950 }
QEmu