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target-ppc: Add helpers for updating a CPU's SDR1 and external HPT
[qemu.git] / hw / ppc / spapr.c
blobeb66a87136622d95f963f5075dd5c61d477407d1
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "sysemu/sysemu.h"
29 #include "sysemu/numa.h"
30 #include "hw/hw.h"
31 #include "hw/fw-path-provider.h"
32 #include "elf.h"
33 #include "net/net.h"
34 #include "sysemu/device_tree.h"
35 #include "sysemu/block-backend.h"
36 #include "sysemu/cpus.h"
37 #include "sysemu/kvm.h"
38 #include "sysemu/device_tree.h"
39 #include "kvm_ppc.h"
40 #include "migration/migration.h"
41 #include "mmu-hash64.h"
42 #include "qom/cpu.h"
43
44 #include "hw/boards.h"
45 #include "hw/ppc/ppc.h"
46 #include "hw/loader.h"
47
48 #include "hw/ppc/spapr.h"
49 #include "hw/ppc/spapr_vio.h"
50 #include "hw/pci-host/spapr.h"
51 #include "hw/ppc/xics.h"
52 #include "hw/pci/msi.h"
53
54 #include "hw/pci/pci.h"
55 #include "hw/scsi/scsi.h"
56 #include "hw/virtio/virtio-scsi.h"
57
58 #include "exec/address-spaces.h"
59 #include "hw/usb.h"
60 #include "qemu/config-file.h"
61 #include "qemu/error-report.h"
62 #include "trace.h"
63 #include "hw/nmi.h"
64
65 #include "hw/compat.h"
66 #include "qemu-common.h"
67
68 #include <libfdt.h>
69
70 /* SLOF memory layout:
71 *
72 * SLOF raw image loaded at 0, copies its romfs right below the flat
73 * device-tree, then position SLOF itself 31M below that
74 *
75 * So we set FW_OVERHEAD to 40MB which should account for all of that
76 * and more
77 *
78 * We load our kernel at 4M, leaving space for SLOF initial image
79 */
80 #define FDT_MAX_SIZE 0x100000
81 #define RTAS_MAX_SIZE 0x10000
82 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
83 #define FW_MAX_SIZE 0x400000
84 #define FW_FILE_NAME "slof.bin"
85 #define FW_OVERHEAD 0x2800000
86 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
87
88 #define MIN_RMA_SLOF 128UL
89
90 #define TIMEBASE_FREQ 512000000ULL
91
92 #define PHANDLE_XICP 0x00001111
93
94 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
95
96 static XICSState *try_create_xics(const char *type, int nr_servers,
97 int nr_irqs, Error **errp)
98 {
99 Error *err = NULL;
100 DeviceState *dev;
101
102 dev = qdev_create(NULL, type);
103 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
104 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
105 object_property_set_bool(OBJECT(dev), true, "realized", &err);
106 if (err) {
107 error_propagate(errp, err);
108 object_unparent(OBJECT(dev));
109 return NULL;
110 }
111 return XICS_COMMON(dev);
112 }
113
114 static XICSState *xics_system_init(MachineState *machine,
115 int nr_servers, int nr_irqs, Error **errp)
116 {
117 XICSState *icp = NULL;
118
119 if (kvm_enabled()) {
120 Error *err = NULL;
121
122 if (machine_kernel_irqchip_allowed(machine)) {
123 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err);
124 }
125 if (machine_kernel_irqchip_required(machine) && !icp) {
126 error_reportf_err(err,
127 "kernel_irqchip requested but unavailable: ");
128 } else {
129 error_free(err);
130 }
131 }
132
133 if (!icp) {
134 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp);
135 }
136
137 return icp;
138 }
139
140 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
141 int smt_threads)
142 {
143 int i, ret = 0;
144 uint32_t servers_prop[smt_threads];
145 uint32_t gservers_prop[smt_threads * 2];
146 int index = ppc_get_vcpu_dt_id(cpu);
147
148 if (cpu->cpu_version) {
149 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
150 if (ret < 0) {
151 return ret;
152 }
153 }
154
155 /* Build interrupt servers and gservers properties */
156 for (i = 0; i < smt_threads; i++) {
157 servers_prop[i] = cpu_to_be32(index + i);
158 /* Hack, direct the group queues back to cpu 0 */
159 gservers_prop[i*2] = cpu_to_be32(index + i);
160 gservers_prop[i*2 + 1] = 0;
161 }
162 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
163 servers_prop, sizeof(servers_prop));
164 if (ret < 0) {
165 return ret;
166 }
167 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
168 gservers_prop, sizeof(gservers_prop));
169
170 return ret;
171 }
172
173 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
174 {
175 int ret = 0;
176 PowerPCCPU *cpu = POWERPC_CPU(cs);
177 int index = ppc_get_vcpu_dt_id(cpu);
178 uint32_t associativity[] = {cpu_to_be32(0x5),
179 cpu_to_be32(0x0),
180 cpu_to_be32(0x0),
181 cpu_to_be32(0x0),
182 cpu_to_be32(cs->numa_node),
183 cpu_to_be32(index)};
184
185 /* Advertise NUMA via ibm,associativity */
186 if (nb_numa_nodes > 1) {
187 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
188 sizeof(associativity));
189 }
190
191 return ret;
192 }
193
194 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
195 {
196 int ret = 0, offset, cpus_offset;
197 CPUState *cs;
198 char cpu_model[32];
199 int smt = kvmppc_smt_threads();
200 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
201
202 CPU_FOREACH(cs) {
203 PowerPCCPU *cpu = POWERPC_CPU(cs);
204 DeviceClass *dc = DEVICE_GET_CLASS(cs);
205 int index = ppc_get_vcpu_dt_id(cpu);
206
207 if ((index % smt) != 0) {
208 continue;
209 }
210
211 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
212
213 cpus_offset = fdt_path_offset(fdt, "/cpus");
214 if (cpus_offset < 0) {
215 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
216 "cpus");
217 if (cpus_offset < 0) {
218 return cpus_offset;
219 }
220 }
221 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
222 if (offset < 0) {
223 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
224 if (offset < 0) {
225 return offset;
226 }
227 }
228
229 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
230 pft_size_prop, sizeof(pft_size_prop));
231 if (ret < 0) {
232 return ret;
233 }
234
235 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
236 if (ret < 0) {
237 return ret;
238 }
239
240 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
241 ppc_get_compat_smt_threads(cpu));
242 if (ret < 0) {
243 return ret;
244 }
245 }
246 return ret;
247 }
248
249
250 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
251 size_t maxsize)
252 {
253 size_t maxcells = maxsize / sizeof(uint32_t);
254 int i, j, count;
255 uint32_t *p = prop;
256
257 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
258 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
259
260 if (!sps->page_shift) {
261 break;
262 }
263 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
264 if (sps->enc[count].page_shift == 0) {
265 break;
266 }
267 }
268 if ((p - prop) >= (maxcells - 3 - count * 2)) {
269 break;
270 }
271 *(p++) = cpu_to_be32(sps->page_shift);
272 *(p++) = cpu_to_be32(sps->slb_enc);
273 *(p++) = cpu_to_be32(count);
274 for (j = 0; j < count; j++) {
275 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
276 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
277 }
278 }
279
280 return (p - prop) * sizeof(uint32_t);
281 }
282
283 static hwaddr spapr_node0_size(void)
284 {
285 MachineState *machine = MACHINE(qdev_get_machine());
286
287 if (nb_numa_nodes) {
288 int i;
289 for (i = 0; i < nb_numa_nodes; ++i) {
290 if (numa_info[i].node_mem) {
291 return MIN(pow2floor(numa_info[i].node_mem),
292 machine->ram_size);
293 }
294 }
295 }
296 return machine->ram_size;
297 }
298
299 #define _FDT(exp) \
300 do { \
301 int ret = (exp); \
302 if (ret < 0) { \
303 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
304 #exp, fdt_strerror(ret)); \
305 exit(1); \
306 } \
307 } while (0)
308
309 static void add_str(GString *s, const gchar *s1)
310 {
311 g_string_append_len(s, s1, strlen(s1) + 1);
312 }
313
314 static void *spapr_create_fdt_skel(hwaddr initrd_base,
315 hwaddr initrd_size,
316 hwaddr kernel_size,
317 bool little_endian,
318 const char *kernel_cmdline,
319 uint32_t epow_irq)
320 {
321 void *fdt;
322 uint32_t start_prop = cpu_to_be32(initrd_base);
323 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
324 GString *hypertas = g_string_sized_new(256);
325 GString *qemu_hypertas = g_string_sized_new(256);
326 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
327 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
328 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
329 char *buf;
330
331 add_str(hypertas, "hcall-pft");
332 add_str(hypertas, "hcall-term");
333 add_str(hypertas, "hcall-dabr");
334 add_str(hypertas, "hcall-interrupt");
335 add_str(hypertas, "hcall-tce");
336 add_str(hypertas, "hcall-vio");
337 add_str(hypertas, "hcall-splpar");
338 add_str(hypertas, "hcall-bulk");
339 add_str(hypertas, "hcall-set-mode");
340 add_str(qemu_hypertas, "hcall-memop1");
341
342 fdt = g_malloc0(FDT_MAX_SIZE);
343 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
344
345 if (kernel_size) {
346 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
347 }
348 if (initrd_size) {
349 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
350 }
351 _FDT((fdt_finish_reservemap(fdt)));
352
353 /* Root node */
354 _FDT((fdt_begin_node(fdt, "")));
355 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
356 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
357 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
358
359 /*
360 * Add info to guest to indentify which host is it being run on
361 * and what is the uuid of the guest
362 */
363 if (kvmppc_get_host_model(&buf)) {
364 _FDT((fdt_property_string(fdt, "host-model", buf)));
365 g_free(buf);
366 }
367 if (kvmppc_get_host_serial(&buf)) {
368 _FDT((fdt_property_string(fdt, "host-serial", buf)));
369 g_free(buf);
370 }
371
372 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
373 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
374 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
375 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
376 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
377 qemu_uuid[14], qemu_uuid[15]);
378
379 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
380 if (qemu_uuid_set) {
381 _FDT((fdt_property_string(fdt, "system-id", buf)));
382 }
383 g_free(buf);
384
385 if (qemu_get_vm_name()) {
386 _FDT((fdt_property_string(fdt, "ibm,partition-name",
387 qemu_get_vm_name())));
388 }
389
390 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
391 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
392
393 /* /chosen */
394 _FDT((fdt_begin_node(fdt, "chosen")));
395
396 /* Set Form1_affinity */
397 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
398
399 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
400 _FDT((fdt_property(fdt, "linux,initrd-start",
401 &start_prop, sizeof(start_prop))));
402 _FDT((fdt_property(fdt, "linux,initrd-end",
403 &end_prop, sizeof(end_prop))));
404 if (kernel_size) {
405 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
406 cpu_to_be64(kernel_size) };
407
408 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
409 if (little_endian) {
410 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
411 }
412 }
413 if (boot_menu) {
414 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
415 }
416 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
417 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
418 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
419
420 _FDT((fdt_end_node(fdt)));
421
422 /* RTAS */
423 _FDT((fdt_begin_node(fdt, "rtas")));
424
425 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
426 add_str(hypertas, "hcall-multi-tce");
427 }
428 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
429 hypertas->len)));
430 g_string_free(hypertas, TRUE);
431 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
432 qemu_hypertas->len)));
433 g_string_free(qemu_hypertas, TRUE);
434
435 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
436 refpoints, sizeof(refpoints))));
437
438 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
439 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
440 RTAS_EVENT_SCAN_RATE)));
441
442 if (msi_nonbroken) {
443 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
444 }
445
446 /*
447 * According to PAPR, rtas ibm,os-term does not guarantee a return
448 * back to the guest cpu.
449 *
450 * While an additional ibm,extended-os-term property indicates that
451 * rtas call return will always occur. Set this property.
452 */
453 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
454
455 _FDT((fdt_end_node(fdt)));
456
457 /* interrupt controller */
458 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
459
460 _FDT((fdt_property_string(fdt, "device_type",
461 "PowerPC-External-Interrupt-Presentation")));
462 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
463 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
464 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
465 interrupt_server_ranges_prop,
466 sizeof(interrupt_server_ranges_prop))));
467 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
468 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
469 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
470
471 _FDT((fdt_end_node(fdt)));
472
473 /* vdevice */
474 _FDT((fdt_begin_node(fdt, "vdevice")));
475
476 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
477 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
478 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
479 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
480 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
481 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
482
483 _FDT((fdt_end_node(fdt)));
484
485 /* event-sources */
486 spapr_events_fdt_skel(fdt, epow_irq);
487
488 /* /hypervisor node */
489 if (kvm_enabled()) {
490 uint8_t hypercall[16];
491
492 /* indicate KVM hypercall interface */
493 _FDT((fdt_begin_node(fdt, "hypervisor")));
494 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
495 if (kvmppc_has_cap_fixup_hcalls()) {
496 /*
497 * Older KVM versions with older guest kernels were broken with the
498 * magic page, don't allow the guest to map it.
499 */
500 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
501 sizeof(hypercall));
502 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
503 sizeof(hypercall))));
504 }
505 _FDT((fdt_end_node(fdt)));
506 }
507
508 _FDT((fdt_end_node(fdt))); /* close root node */
509 _FDT((fdt_finish(fdt)));
510
511 return fdt;
512 }
513
514 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
515 hwaddr size)
516 {
517 uint32_t associativity[] = {
518 cpu_to_be32(0x4), /* length */
519 cpu_to_be32(0x0), cpu_to_be32(0x0),
520 cpu_to_be32(0x0), cpu_to_be32(nodeid)
521 };
522 char mem_name[32];
523 uint64_t mem_reg_property[2];
524 int off;
525
526 mem_reg_property[0] = cpu_to_be64(start);
527 mem_reg_property[1] = cpu_to_be64(size);
528
529 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
530 off = fdt_add_subnode(fdt, 0, mem_name);
531 _FDT(off);
532 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
533 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
534 sizeof(mem_reg_property))));
535 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
536 sizeof(associativity))));
537 return off;
538 }
539
540 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
541 {
542 MachineState *machine = MACHINE(spapr);
543 hwaddr mem_start, node_size;
544 int i, nb_nodes = nb_numa_nodes;
545 NodeInfo *nodes = numa_info;
546 NodeInfo ramnode;
547
548 /* No NUMA nodes, assume there is just one node with whole RAM */
549 if (!nb_numa_nodes) {
550 nb_nodes = 1;
551 ramnode.node_mem = machine->ram_size;
552 nodes = &ramnode;
553 }
554
555 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
556 if (!nodes[i].node_mem) {
557 continue;
558 }
559 if (mem_start >= machine->ram_size) {
560 node_size = 0;
561 } else {
562 node_size = nodes[i].node_mem;
563 if (node_size > machine->ram_size - mem_start) {
564 node_size = machine->ram_size - mem_start;
565 }
566 }
567 if (!mem_start) {
568 /* ppc_spapr_init() checks for rma_size <= node0_size already */
569 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
570 mem_start += spapr->rma_size;
571 node_size -= spapr->rma_size;
572 }
573 for ( ; node_size; ) {
574 hwaddr sizetmp = pow2floor(node_size);
575
576 /* mem_start != 0 here */
577 if (ctzl(mem_start) < ctzl(sizetmp)) {
578 sizetmp = 1ULL << ctzl(mem_start);
579 }
580
581 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
582 node_size -= sizetmp;
583 mem_start += sizetmp;
584 }
585 }
586
587 return 0;
588 }
589
590 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
591 sPAPRMachineState *spapr)
592 {
593 PowerPCCPU *cpu = POWERPC_CPU(cs);
594 CPUPPCState *env = &cpu->env;
595 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
596 int index = ppc_get_vcpu_dt_id(cpu);
597 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
598 0xffffffff, 0xffffffff};
599 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
600 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
601 uint32_t page_sizes_prop[64];
602 size_t page_sizes_prop_size;
603 uint32_t vcpus_per_socket = smp_threads * smp_cores;
604 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
605
606 /* Note: we keep CI large pages off for now because a 64K capable guest
607 * provisioned with large pages might otherwise try to map a qemu
608 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
609 * even if that qemu runs on a 4k host.
610 *
611 * We can later add this bit back when we are confident this is not
612 * an issue (!HV KVM or 64K host)
613 */
614 uint8_t pa_features_206[] = { 6, 0,
615 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
616 uint8_t pa_features_207[] = { 24, 0,
617 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
618 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
619 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
620 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
621 uint8_t *pa_features;
622 size_t pa_size;
623
624 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
625 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
626
627 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
628 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
629 env->dcache_line_size)));
630 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
631 env->dcache_line_size)));
632 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
633 env->icache_line_size)));
634 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
635 env->icache_line_size)));
636
637 if (pcc->l1_dcache_size) {
638 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
639 pcc->l1_dcache_size)));
640 } else {
641 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
642 }
643 if (pcc->l1_icache_size) {
644 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
645 pcc->l1_icache_size)));
646 } else {
647 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
648 }
649
650 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
651 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
652 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
653 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
654 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
655 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
656
657 if (env->spr_cb[SPR_PURR].oea_read) {
658 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
659 }
660
661 if (env->mmu_model & POWERPC_MMU_1TSEG) {
662 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
663 segs, sizeof(segs))));
664 }
665
666 /* Advertise VMX/VSX (vector extensions) if available
667 * 0 / no property == no vector extensions
668 * 1 == VMX / Altivec available
669 * 2 == VSX available */
670 if (env->insns_flags & PPC_ALTIVEC) {
671 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
672
673 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
674 }
675
676 /* Advertise DFP (Decimal Floating Point) if available
677 * 0 / no property == no DFP
678 * 1 == DFP available */
679 if (env->insns_flags2 & PPC2_DFP) {
680 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
681 }
682
683 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
684 sizeof(page_sizes_prop));
685 if (page_sizes_prop_size) {
686 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
687 page_sizes_prop, page_sizes_prop_size)));
688 }
689
690 /* Do the ibm,pa-features property, adjust it for ci-large-pages */
691 if (env->mmu_model == POWERPC_MMU_2_06) {
692 pa_features = pa_features_206;
693 pa_size = sizeof(pa_features_206);
694 } else /* env->mmu_model == POWERPC_MMU_2_07 */ {
695 pa_features = pa_features_207;
696 pa_size = sizeof(pa_features_207);
697 }
698 if (env->ci_large_pages) {
699 pa_features[3] |= 0x20;
700 }
701 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
702
703 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
704 cs->cpu_index / vcpus_per_socket)));
705
706 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
707 pft_size_prop, sizeof(pft_size_prop))));
708
709 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
710
711 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
712 ppc_get_compat_smt_threads(cpu)));
713 }
714
715 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
716 {
717 CPUState *cs;
718 int cpus_offset;
719 char *nodename;
720 int smt = kvmppc_smt_threads();
721
722 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
723 _FDT(cpus_offset);
724 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
725 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
726
727 /*
728 * We walk the CPUs in reverse order to ensure that CPU DT nodes
729 * created by fdt_add_subnode() end up in the right order in FDT
730 * for the guest kernel the enumerate the CPUs correctly.
731 */
732 CPU_FOREACH_REVERSE(cs) {
733 PowerPCCPU *cpu = POWERPC_CPU(cs);
734 int index = ppc_get_vcpu_dt_id(cpu);
735 DeviceClass *dc = DEVICE_GET_CLASS(cs);
736 int offset;
737
738 if ((index % smt) != 0) {
739 continue;
740 }
741
742 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
743 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
744 g_free(nodename);
745 _FDT(offset);
746 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
747 }
748
749 }
750
751 /*
752 * Adds ibm,dynamic-reconfiguration-memory node.
753 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
754 * of this device tree node.
755 */
756 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
757 {
758 MachineState *machine = MACHINE(spapr);
759 int ret, i, offset;
760 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
761 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
762 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
763 uint32_t *int_buf, *cur_index, buf_len;
764 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
765
766 /*
767 * Don't create the node if there are no DR LMBs.
768 */
769 if (!nr_lmbs) {
770 return 0;
771 }
772
773 /*
774 * Allocate enough buffer size to fit in ibm,dynamic-memory
775 * or ibm,associativity-lookup-arrays
776 */
777 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
778 * sizeof(uint32_t);
779 cur_index = int_buf = g_malloc0(buf_len);
780
781 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
782
783 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
784 sizeof(prop_lmb_size));
785 if (ret < 0) {
786 goto out;
787 }
788
789 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
790 if (ret < 0) {
791 goto out;
792 }
793
794 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
795 if (ret < 0) {
796 goto out;
797 }
798
799 /* ibm,dynamic-memory */
800 int_buf[0] = cpu_to_be32(nr_lmbs);
801 cur_index++;
802 for (i = 0; i < nr_lmbs; i++) {
803 sPAPRDRConnector *drc;
804 sPAPRDRConnectorClass *drck;
805 uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;;
806 uint32_t *dynamic_memory = cur_index;
807
808 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
809 addr/lmb_size);
810 g_assert(drc);
811 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
812
813 dynamic_memory[0] = cpu_to_be32(addr >> 32);
814 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
815 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
816 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
817 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
818 if (addr < machine->ram_size ||
819 memory_region_present(get_system_memory(), addr)) {
820 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
821 } else {
822 dynamic_memory[5] = cpu_to_be32(0);
823 }
824
825 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
826 }
827 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
828 if (ret < 0) {
829 goto out;
830 }
831
832 /* ibm,associativity-lookup-arrays */
833 cur_index = int_buf;
834 int_buf[0] = cpu_to_be32(nr_nodes);
835 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
836 cur_index += 2;
837 for (i = 0; i < nr_nodes; i++) {
838 uint32_t associativity[] = {
839 cpu_to_be32(0x0),
840 cpu_to_be32(0x0),
841 cpu_to_be32(0x0),
842 cpu_to_be32(i)
843 };
844 memcpy(cur_index, associativity, sizeof(associativity));
845 cur_index += 4;
846 }
847 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
848 (cur_index - int_buf) * sizeof(uint32_t));
849 out:
850 g_free(int_buf);
851 return ret;
852 }
853
854 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
855 target_ulong addr, target_ulong size,
856 bool cpu_update, bool memory_update)
857 {
858 void *fdt, *fdt_skel;
859 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
860 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
861
862 size -= sizeof(hdr);
863
864 /* Create sceleton */
865 fdt_skel = g_malloc0(size);
866 _FDT((fdt_create(fdt_skel, size)));
867 _FDT((fdt_begin_node(fdt_skel, "")));
868 _FDT((fdt_end_node(fdt_skel)));
869 _FDT((fdt_finish(fdt_skel)));
870 fdt = g_malloc0(size);
871 _FDT((fdt_open_into(fdt_skel, fdt, size)));
872 g_free(fdt_skel);
873
874 /* Fixup cpu nodes */
875 if (cpu_update) {
876 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
877 }
878
879 /* Generate ibm,dynamic-reconfiguration-memory node if required */
880 if (memory_update && smc->dr_lmb_enabled) {
881 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
882 }
883
884 /* Pack resulting tree */
885 _FDT((fdt_pack(fdt)));
886
887 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
888 trace_spapr_cas_failed(size);
889 return -1;
890 }
891
892 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
893 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
894 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
895 g_free(fdt);
896
897 return 0;
898 }
899
900 static void spapr_finalize_fdt(sPAPRMachineState *spapr,
901 hwaddr fdt_addr,
902 hwaddr rtas_addr,
903 hwaddr rtas_size)
904 {
905 MachineState *machine = MACHINE(qdev_get_machine());
906 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
907 const char *boot_device = machine->boot_order;
908 int ret, i;
909 size_t cb = 0;
910 char *bootlist;
911 void *fdt;
912 sPAPRPHBState *phb;
913
914 fdt = g_malloc(FDT_MAX_SIZE);
915
916 /* open out the base tree into a temp buffer for the final tweaks */
917 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
918
919 ret = spapr_populate_memory(spapr, fdt);
920 if (ret < 0) {
921 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
922 exit(1);
923 }
924
925 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
926 if (ret < 0) {
927 fprintf(stderr, "couldn't setup vio devices in fdt\n");
928 exit(1);
929 }
930
931 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
932 ret = spapr_rng_populate_dt(fdt);
933 if (ret < 0) {
934 fprintf(stderr, "could not set up rng device in the fdt\n");
935 exit(1);
936 }
937 }
938
939 QLIST_FOREACH(phb, &spapr->phbs, list) {
940 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
941 }
942
943 if (ret < 0) {
944 fprintf(stderr, "couldn't setup PCI devices in fdt\n");
945 exit(1);
946 }
947
948 /* RTAS */
949 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
950 if (ret < 0) {
951 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
952 }
953
954 /* cpus */
955 spapr_populate_cpus_dt_node(fdt, spapr);
956
957 bootlist = get_boot_devices_list(&cb, true);
958 if (cb && bootlist) {
959 int offset = fdt_path_offset(fdt, "/chosen");
960 if (offset < 0) {
961 exit(1);
962 }
963 for (i = 0; i < cb; i++) {
964 if (bootlist[i] == '\n') {
965 bootlist[i] = ' ';
966 }
967
968 }
969 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
970 }
971
972 if (boot_device && strlen(boot_device)) {
973 int offset = fdt_path_offset(fdt, "/chosen");
974
975 if (offset < 0) {
976 exit(1);
977 }
978 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
979 }
980
981 if (!spapr->has_graphics) {
982 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
983 }
984
985 if (smc->dr_lmb_enabled) {
986 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
987 }
988
989 _FDT((fdt_pack(fdt)));
990
991 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
992 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
993 fdt_totalsize(fdt), FDT_MAX_SIZE);
994 exit(1);
995 }
996
997 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
998 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
999
1000 g_free(bootlist);
1001 g_free(fdt);
1002 }
1003
1004 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1005 {
1006 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1007 }
1008
1009 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
1010 {
1011 CPUPPCState *env = &cpu->env;
1012
1013 if (msr_pr) {
1014 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1015 env->gpr[3] = H_PRIVILEGE;
1016 } else {
1017 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1018 }
1019 }
1020
1021 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1022 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1023 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1024 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1025 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1026
1027 /*
1028 * Get the fd to access the kernel htab, re-opening it if necessary
1029 */
1030 static int get_htab_fd(sPAPRMachineState *spapr)
1031 {
1032 if (spapr->htab_fd >= 0) {
1033 return spapr->htab_fd;
1034 }
1035
1036 spapr->htab_fd = kvmppc_get_htab_fd(false);
1037 if (spapr->htab_fd < 0) {
1038 error_report("Unable to open fd for reading hash table from KVM: %s",
1039 strerror(errno));
1040 }
1041
1042 return spapr->htab_fd;
1043 }
1044
1045 static void close_htab_fd(sPAPRMachineState *spapr)
1046 {
1047 if (spapr->htab_fd >= 0) {
1048 close(spapr->htab_fd);
1049 }
1050 spapr->htab_fd = -1;
1051 }
1052
1053 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1054 {
1055 int shift;
1056
1057 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1058 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1059 * that's much more than is needed for Linux guests */
1060 shift = ctz64(pow2ceil(ramsize)) - 7;
1061 shift = MAX(shift, 18); /* Minimum architected size */
1062 shift = MIN(shift, 46); /* Maximum architected size */
1063 return shift;
1064 }
1065
1066 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1067 Error **errp)
1068 {
1069 long rc;
1070
1071 /* Clean up any HPT info from a previous boot */
1072 g_free(spapr->htab);
1073 spapr->htab = NULL;
1074 spapr->htab_shift = 0;
1075 close_htab_fd(spapr);
1076
1077 rc = kvmppc_reset_htab(shift);
1078 if (rc < 0) {
1079 /* kernel-side HPT needed, but couldn't allocate one */
1080 error_setg_errno(errp, errno,
1081 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1082 shift);
1083 /* This is almost certainly fatal, but if the caller really
1084 * wants to carry on with shift == 0, it's welcome to try */
1085 } else if (rc > 0) {
1086 /* kernel-side HPT allocated */
1087 if (rc != shift) {
1088 error_setg(errp,
1089 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1090 shift, rc);
1091 }
1092
1093 spapr->htab_shift = shift;
1094 kvmppc_kern_htab = true;
1095 } else {
1096 /* kernel-side HPT not needed, allocate in userspace instead */
1097 size_t size = 1ULL << shift;
1098 int i;
1099
1100 spapr->htab = qemu_memalign(size, size);
1101 if (!spapr->htab) {
1102 error_setg_errno(errp, errno,
1103 "Could not allocate HPT of order %d", shift);
1104 return;
1105 }
1106
1107 memset(spapr->htab, 0, size);
1108 spapr->htab_shift = shift;
1109 kvmppc_kern_htab = false;
1110
1111 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1112 DIRTY_HPTE(HPTE(spapr->htab, i));
1113 }
1114 }
1115 }
1116
1117 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1118 {
1119 bool matched = false;
1120
1121 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1122 matched = true;
1123 }
1124
1125 if (!matched) {
1126 error_report("Device %s is not supported by this machine yet.",
1127 qdev_fw_name(DEVICE(sbdev)));
1128 exit(1);
1129 }
1130
1131 return 0;
1132 }
1133
1134 static void ppc_spapr_reset(void)
1135 {
1136 MachineState *machine = MACHINE(qdev_get_machine());
1137 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1138 PowerPCCPU *first_ppc_cpu;
1139 uint32_t rtas_limit;
1140
1141 /* Check for unknown sysbus devices */
1142 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1143
1144 /* Allocate and/or reset the hash page table */
1145 spapr_reallocate_hpt(spapr,
1146 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1147 &error_fatal);
1148
1149 /* Update the RMA size if necessary */
1150 if (spapr->vrma_adjust) {
1151 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1152 spapr->htab_shift);
1153 }
1154
1155 qemu_devices_reset();
1156
1157 /*
1158 * We place the device tree and RTAS just below either the top of the RMA,
1159 * or just below 2GB, whichever is lowere, so that it can be
1160 * processed with 32-bit real mode code if necessary
1161 */
1162 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1163 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1164 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1165
1166 /* Load the fdt */
1167 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1168 spapr->rtas_size);
1169
1170 /* Copy RTAS over */
1171 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1172 spapr->rtas_size);
1173
1174 /* Set up the entry state */
1175 first_ppc_cpu = POWERPC_CPU(first_cpu);
1176 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1177 first_ppc_cpu->env.gpr[5] = 0;
1178 first_cpu->halted = 0;
1179 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1180
1181 }
1182
1183 static void spapr_cpu_reset(void *opaque)
1184 {
1185 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1186 PowerPCCPU *cpu = opaque;
1187 CPUState *cs = CPU(cpu);
1188 CPUPPCState *env = &cpu->env;
1189
1190 cpu_reset(cs);
1191
1192 /* All CPUs start halted. CPU0 is unhalted from the machine level
1193 * reset code and the rest are explicitly started up by the guest
1194 * using an RTAS call */
1195 cs->halted = 1;
1196
1197 env->spr[SPR_HIOR] = 0;
1198
1199 ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
1200 &error_fatal);
1201 }
1202
1203 static void spapr_create_nvram(sPAPRMachineState *spapr)
1204 {
1205 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1206 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1207
1208 if (dinfo) {
1209 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1210 &error_fatal);
1211 }
1212
1213 qdev_init_nofail(dev);
1214
1215 spapr->nvram = (struct sPAPRNVRAM *)dev;
1216 }
1217
1218 static void spapr_rtc_create(sPAPRMachineState *spapr)
1219 {
1220 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1221
1222 qdev_init_nofail(dev);
1223 spapr->rtc = dev;
1224
1225 object_property_add_alias(qdev_get_machine(), "rtc-time",
1226 OBJECT(spapr->rtc), "date", NULL);
1227 }
1228
1229 /* Returns whether we want to use VGA or not */
1230 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1231 {
1232 switch (vga_interface_type) {
1233 case VGA_NONE:
1234 return false;
1235 case VGA_DEVICE:
1236 return true;
1237 case VGA_STD:
1238 case VGA_VIRTIO:
1239 return pci_vga_init(pci_bus) != NULL;
1240 default:
1241 error_setg(errp,
1242 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1243 return false;
1244 }
1245 }
1246
1247 static int spapr_post_load(void *opaque, int version_id)
1248 {
1249 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1250 int err = 0;
1251
1252 /* In earlier versions, there was no separate qdev for the PAPR
1253 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1254 * So when migrating from those versions, poke the incoming offset
1255 * value into the RTC device */
1256 if (version_id < 3) {
1257 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1258 }
1259
1260 return err;
1261 }
1262
1263 static bool version_before_3(void *opaque, int version_id)
1264 {
1265 return version_id < 3;
1266 }
1267
1268 static const VMStateDescription vmstate_spapr = {
1269 .name = "spapr",
1270 .version_id = 3,
1271 .minimum_version_id = 1,
1272 .post_load = spapr_post_load,
1273 .fields = (VMStateField[]) {
1274 /* used to be @next_irq */
1275 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1276
1277 /* RTC offset */
1278 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1279
1280 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1281 VMSTATE_END_OF_LIST()
1282 },
1283 };
1284
1285 static int htab_save_setup(QEMUFile *f, void *opaque)
1286 {
1287 sPAPRMachineState *spapr = opaque;
1288
1289 /* "Iteration" header */
1290 qemu_put_be32(f, spapr->htab_shift);
1291
1292 if (spapr->htab) {
1293 spapr->htab_save_index = 0;
1294 spapr->htab_first_pass = true;
1295 } else {
1296 assert(kvm_enabled());
1297 }
1298
1299
1300 return 0;
1301 }
1302
1303 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1304 int64_t max_ns)
1305 {
1306 bool has_timeout = max_ns != -1;
1307 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1308 int index = spapr->htab_save_index;
1309 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1310
1311 assert(spapr->htab_first_pass);
1312
1313 do {
1314 int chunkstart;
1315
1316 /* Consume invalid HPTEs */
1317 while ((index < htabslots)
1318 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1319 index++;
1320 CLEAN_HPTE(HPTE(spapr->htab, index));
1321 }
1322
1323 /* Consume valid HPTEs */
1324 chunkstart = index;
1325 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1326 && HPTE_VALID(HPTE(spapr->htab, index))) {
1327 index++;
1328 CLEAN_HPTE(HPTE(spapr->htab, index));
1329 }
1330
1331 if (index > chunkstart) {
1332 int n_valid = index - chunkstart;
1333
1334 qemu_put_be32(f, chunkstart);
1335 qemu_put_be16(f, n_valid);
1336 qemu_put_be16(f, 0);
1337 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1338 HASH_PTE_SIZE_64 * n_valid);
1339
1340 if (has_timeout &&
1341 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1342 break;
1343 }
1344 }
1345 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1346
1347 if (index >= htabslots) {
1348 assert(index == htabslots);
1349 index = 0;
1350 spapr->htab_first_pass = false;
1351 }
1352 spapr->htab_save_index = index;
1353 }
1354
1355 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1356 int64_t max_ns)
1357 {
1358 bool final = max_ns < 0;
1359 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1360 int examined = 0, sent = 0;
1361 int index = spapr->htab_save_index;
1362 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1363
1364 assert(!spapr->htab_first_pass);
1365
1366 do {
1367 int chunkstart, invalidstart;
1368
1369 /* Consume non-dirty HPTEs */
1370 while ((index < htabslots)
1371 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1372 index++;
1373 examined++;
1374 }
1375
1376 chunkstart = index;
1377 /* Consume valid dirty HPTEs */
1378 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1379 && HPTE_DIRTY(HPTE(spapr->htab, index))
1380 && HPTE_VALID(HPTE(spapr->htab, index))) {
1381 CLEAN_HPTE(HPTE(spapr->htab, index));
1382 index++;
1383 examined++;
1384 }
1385
1386 invalidstart = index;
1387 /* Consume invalid dirty HPTEs */
1388 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1389 && HPTE_DIRTY(HPTE(spapr->htab, index))
1390 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1391 CLEAN_HPTE(HPTE(spapr->htab, index));
1392 index++;
1393 examined++;
1394 }
1395
1396 if (index > chunkstart) {
1397 int n_valid = invalidstart - chunkstart;
1398 int n_invalid = index - invalidstart;
1399
1400 qemu_put_be32(f, chunkstart);
1401 qemu_put_be16(f, n_valid);
1402 qemu_put_be16(f, n_invalid);
1403 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1404 HASH_PTE_SIZE_64 * n_valid);
1405 sent += index - chunkstart;
1406
1407 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1408 break;
1409 }
1410 }
1411
1412 if (examined >= htabslots) {
1413 break;
1414 }
1415
1416 if (index >= htabslots) {
1417 assert(index == htabslots);
1418 index = 0;
1419 }
1420 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1421
1422 if (index >= htabslots) {
1423 assert(index == htabslots);
1424 index = 0;
1425 }
1426
1427 spapr->htab_save_index = index;
1428
1429 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1430 }
1431
1432 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1433 #define MAX_KVM_BUF_SIZE 2048
1434
1435 static int htab_save_iterate(QEMUFile *f, void *opaque)
1436 {
1437 sPAPRMachineState *spapr = opaque;
1438 int fd;
1439 int rc = 0;
1440
1441 /* Iteration header */
1442 qemu_put_be32(f, 0);
1443
1444 if (!spapr->htab) {
1445 assert(kvm_enabled());
1446
1447 fd = get_htab_fd(spapr);
1448 if (fd < 0) {
1449 return fd;
1450 }
1451
1452 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1453 if (rc < 0) {
1454 return rc;
1455 }
1456 } else if (spapr->htab_first_pass) {
1457 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1458 } else {
1459 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1460 }
1461
1462 /* End marker */
1463 qemu_put_be32(f, 0);
1464 qemu_put_be16(f, 0);
1465 qemu_put_be16(f, 0);
1466
1467 return rc;
1468 }
1469
1470 static int htab_save_complete(QEMUFile *f, void *opaque)
1471 {
1472 sPAPRMachineState *spapr = opaque;
1473 int fd;
1474
1475 /* Iteration header */
1476 qemu_put_be32(f, 0);
1477
1478 if (!spapr->htab) {
1479 int rc;
1480
1481 assert(kvm_enabled());
1482
1483 fd = get_htab_fd(spapr);
1484 if (fd < 0) {
1485 return fd;
1486 }
1487
1488 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1489 if (rc < 0) {
1490 return rc;
1491 }
1492 close_htab_fd(spapr);
1493 } else {
1494 if (spapr->htab_first_pass) {
1495 htab_save_first_pass(f, spapr, -1);
1496 }
1497 htab_save_later_pass(f, spapr, -1);
1498 }
1499
1500 /* End marker */
1501 qemu_put_be32(f, 0);
1502 qemu_put_be16(f, 0);
1503 qemu_put_be16(f, 0);
1504
1505 return 0;
1506 }
1507
1508 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1509 {
1510 sPAPRMachineState *spapr = opaque;
1511 uint32_t section_hdr;
1512 int fd = -1;
1513
1514 if (version_id < 1 || version_id > 1) {
1515 error_report("htab_load() bad version");
1516 return -EINVAL;
1517 }
1518
1519 section_hdr = qemu_get_be32(f);
1520
1521 if (section_hdr) {
1522 Error *local_err = NULL;
1523
1524 /* First section gives the htab size */
1525 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1526 if (local_err) {
1527 error_report_err(local_err);
1528 return -EINVAL;
1529 }
1530 return 0;
1531 }
1532
1533 if (!spapr->htab) {
1534 assert(kvm_enabled());
1535
1536 fd = kvmppc_get_htab_fd(true);
1537 if (fd < 0) {
1538 error_report("Unable to open fd to restore KVM hash table: %s",
1539 strerror(errno));
1540 }
1541 }
1542
1543 while (true) {
1544 uint32_t index;
1545 uint16_t n_valid, n_invalid;
1546
1547 index = qemu_get_be32(f);
1548 n_valid = qemu_get_be16(f);
1549 n_invalid = qemu_get_be16(f);
1550
1551 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1552 /* End of Stream */
1553 break;
1554 }
1555
1556 if ((index + n_valid + n_invalid) >
1557 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1558 /* Bad index in stream */
1559 error_report(
1560 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1561 index, n_valid, n_invalid, spapr->htab_shift);
1562 return -EINVAL;
1563 }
1564
1565 if (spapr->htab) {
1566 if (n_valid) {
1567 qemu_get_buffer(f, HPTE(spapr->htab, index),
1568 HASH_PTE_SIZE_64 * n_valid);
1569 }
1570 if (n_invalid) {
1571 memset(HPTE(spapr->htab, index + n_valid), 0,
1572 HASH_PTE_SIZE_64 * n_invalid);
1573 }
1574 } else {
1575 int rc;
1576
1577 assert(fd >= 0);
1578
1579 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1580 if (rc < 0) {
1581 return rc;
1582 }
1583 }
1584 }
1585
1586 if (!spapr->htab) {
1587 assert(fd >= 0);
1588 close(fd);
1589 }
1590
1591 return 0;
1592 }
1593
1594 static SaveVMHandlers savevm_htab_handlers = {
1595 .save_live_setup = htab_save_setup,
1596 .save_live_iterate = htab_save_iterate,
1597 .save_live_complete_precopy = htab_save_complete,
1598 .load_state = htab_load,
1599 };
1600
1601 static void spapr_boot_set(void *opaque, const char *boot_device,
1602 Error **errp)
1603 {
1604 MachineState *machine = MACHINE(qdev_get_machine());
1605 machine->boot_order = g_strdup(boot_device);
1606 }
1607
1608 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
1609 Error **errp)
1610 {
1611 CPUPPCState *env = &cpu->env;
1612
1613 /* Set time-base frequency to 512 MHz */
1614 cpu_ppc_tb_init(env, TIMEBASE_FREQ);
1615
1616 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1617 * MSR[IP] should never be set.
1618 */
1619 env->msr_mask &= ~(1 << 6);
1620
1621 /* Tell KVM that we're in PAPR mode */
1622 if (kvm_enabled()) {
1623 kvmppc_set_papr(cpu);
1624 }
1625
1626 if (cpu->max_compat) {
1627 Error *local_err = NULL;
1628
1629 ppc_set_compat(cpu, cpu->max_compat, &local_err);
1630 if (local_err) {
1631 error_propagate(errp, local_err);
1632 return;
1633 }
1634 }
1635
1636 xics_cpu_setup(spapr->icp, cpu);
1637
1638 qemu_register_reset(spapr_cpu_reset, cpu);
1639 }
1640
1641 /*
1642 * Reset routine for LMB DR devices.
1643 *
1644 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1645 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1646 * when it walks all its children devices. LMB devices reset occurs
1647 * as part of spapr_ppc_reset().
1648 */
1649 static void spapr_drc_reset(void *opaque)
1650 {
1651 sPAPRDRConnector *drc = opaque;
1652 DeviceState *d = DEVICE(drc);
1653
1654 if (d) {
1655 device_reset(d);
1656 }
1657 }
1658
1659 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1660 {
1661 MachineState *machine = MACHINE(spapr);
1662 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1663 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1664 int i;
1665
1666 for (i = 0; i < nr_lmbs; i++) {
1667 sPAPRDRConnector *drc;
1668 uint64_t addr;
1669
1670 addr = i * lmb_size + spapr->hotplug_memory.base;
1671 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1672 addr/lmb_size);
1673 qemu_register_reset(spapr_drc_reset, drc);
1674 }
1675 }
1676
1677 /*
1678 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1679 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1680 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1681 */
1682 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1683 {
1684 int i;
1685
1686 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1687 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1688 " is not aligned to %llu MiB",
1689 machine->ram_size,
1690 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1691 return;
1692 }
1693
1694 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1695 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1696 " is not aligned to %llu MiB",
1697 machine->ram_size,
1698 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1699 return;
1700 }
1701
1702 for (i = 0; i < nb_numa_nodes; i++) {
1703 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1704 error_setg(errp,
1705 "Node %d memory size 0x%" PRIx64
1706 " is not aligned to %llu MiB",
1707 i, numa_info[i].node_mem,
1708 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1709 return;
1710 }
1711 }
1712 }
1713
1714 /* pSeries LPAR / sPAPR hardware init */
1715 static void ppc_spapr_init(MachineState *machine)
1716 {
1717 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1718 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1719 const char *kernel_filename = machine->kernel_filename;
1720 const char *kernel_cmdline = machine->kernel_cmdline;
1721 const char *initrd_filename = machine->initrd_filename;
1722 PowerPCCPU *cpu;
1723 PCIHostState *phb;
1724 int i;
1725 MemoryRegion *sysmem = get_system_memory();
1726 MemoryRegion *ram = g_new(MemoryRegion, 1);
1727 MemoryRegion *rma_region;
1728 void *rma = NULL;
1729 hwaddr rma_alloc_size;
1730 hwaddr node0_size = spapr_node0_size();
1731 uint32_t initrd_base = 0;
1732 long kernel_size = 0, initrd_size = 0;
1733 long load_limit, fw_size;
1734 bool kernel_le = false;
1735 char *filename;
1736
1737 msi_nonbroken = true;
1738
1739 QLIST_INIT(&spapr->phbs);
1740
1741 cpu_ppc_hypercall = emulate_spapr_hypercall;
1742
1743 /* Allocate RMA if necessary */
1744 rma_alloc_size = kvmppc_alloc_rma(&rma);
1745
1746 if (rma_alloc_size == -1) {
1747 error_report("Unable to create RMA");
1748 exit(1);
1749 }
1750
1751 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1752 spapr->rma_size = rma_alloc_size;
1753 } else {
1754 spapr->rma_size = node0_size;
1755
1756 /* With KVM, we don't actually know whether KVM supports an
1757 * unbounded RMA (PR KVM) or is limited by the hash table size
1758 * (HV KVM using VRMA), so we always assume the latter
1759 *
1760 * In that case, we also limit the initial allocations for RTAS
1761 * etc... to 256M since we have no way to know what the VRMA size
1762 * is going to be as it depends on the size of the hash table
1763 * isn't determined yet.
1764 */
1765 if (kvm_enabled()) {
1766 spapr->vrma_adjust = 1;
1767 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1768 }
1769 }
1770
1771 if (spapr->rma_size > node0_size) {
1772 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1773 spapr->rma_size);
1774 exit(1);
1775 }
1776
1777 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1778 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1779
1780 /* Set up Interrupt Controller before we create the VCPUs */
1781 spapr->icp = xics_system_init(machine,
1782 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
1783 smp_threads),
1784 XICS_IRQS, &error_fatal);
1785
1786 if (smc->dr_lmb_enabled) {
1787 spapr_validate_node_memory(machine, &error_fatal);
1788 }
1789
1790 /* init CPUs */
1791 if (machine->cpu_model == NULL) {
1792 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
1793 }
1794 for (i = 0; i < smp_cpus; i++) {
1795 cpu = cpu_ppc_init(machine->cpu_model);
1796 if (cpu == NULL) {
1797 error_report("Unable to find PowerPC CPU definition");
1798 exit(1);
1799 }
1800 spapr_cpu_init(spapr, cpu, &error_fatal);
1801 }
1802
1803 if (kvm_enabled()) {
1804 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1805 kvmppc_enable_logical_ci_hcalls();
1806 kvmppc_enable_set_mode_hcall();
1807 }
1808
1809 /* allocate RAM */
1810 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1811 machine->ram_size);
1812 memory_region_add_subregion(sysmem, 0, ram);
1813
1814 if (rma_alloc_size && rma) {
1815 rma_region = g_new(MemoryRegion, 1);
1816 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1817 rma_alloc_size, rma);
1818 vmstate_register_ram_global(rma_region);
1819 memory_region_add_subregion(sysmem, 0, rma_region);
1820 }
1821
1822 /* initialize hotplug memory address space */
1823 if (machine->ram_size < machine->maxram_size) {
1824 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1825
1826 if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) {
1827 error_report("Specified number of memory slots %"
1828 PRIu64" exceeds max supported %d",
1829 machine->ram_slots, SPAPR_MAX_RAM_SLOTS);
1830 exit(1);
1831 }
1832
1833 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1834 SPAPR_HOTPLUG_MEM_ALIGN);
1835 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1836 "hotplug-memory", hotplug_mem_size);
1837 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1838 &spapr->hotplug_memory.mr);
1839 }
1840
1841 if (smc->dr_lmb_enabled) {
1842 spapr_create_lmb_dr_connectors(spapr);
1843 }
1844
1845 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1846 if (!filename) {
1847 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1848 exit(1);
1849 }
1850 spapr->rtas_size = get_image_size(filename);
1851 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1852 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1853 error_report("Could not load LPAR rtas '%s'", filename);
1854 exit(1);
1855 }
1856 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1857 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1858 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1859 exit(1);
1860 }
1861 g_free(filename);
1862
1863 /* Set up EPOW events infrastructure */
1864 spapr_events_init(spapr);
1865
1866 /* Set up the RTC RTAS interfaces */
1867 spapr_rtc_create(spapr);
1868
1869 /* Set up VIO bus */
1870 spapr->vio_bus = spapr_vio_bus_init();
1871
1872 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1873 if (serial_hds[i]) {
1874 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1875 }
1876 }
1877
1878 /* We always have at least the nvram device on VIO */
1879 spapr_create_nvram(spapr);
1880
1881 /* Set up PCI */
1882 spapr_pci_rtas_init();
1883
1884 phb = spapr_create_phb(spapr, 0);
1885
1886 for (i = 0; i < nb_nics; i++) {
1887 NICInfo *nd = &nd_table[i];
1888
1889 if (!nd->model) {
1890 nd->model = g_strdup("ibmveth");
1891 }
1892
1893 if (strcmp(nd->model, "ibmveth") == 0) {
1894 spapr_vlan_create(spapr->vio_bus, nd);
1895 } else {
1896 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1897 }
1898 }
1899
1900 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1901 spapr_vscsi_create(spapr->vio_bus);
1902 }
1903
1904 /* Graphics */
1905 if (spapr_vga_init(phb->bus, &error_fatal)) {
1906 spapr->has_graphics = true;
1907 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1908 }
1909
1910 if (machine->usb) {
1911 if (smc->use_ohci_by_default) {
1912 pci_create_simple(phb->bus, -1, "pci-ohci");
1913 } else {
1914 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1915 }
1916
1917 if (spapr->has_graphics) {
1918 USBBus *usb_bus = usb_bus_find(-1);
1919
1920 usb_create_simple(usb_bus, "usb-kbd");
1921 usb_create_simple(usb_bus, "usb-mouse");
1922 }
1923 }
1924
1925 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1926 error_report(
1927 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1928 MIN_RMA_SLOF);
1929 exit(1);
1930 }
1931
1932 if (kernel_filename) {
1933 uint64_t lowaddr = 0;
1934
1935 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
1936 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
1937 0, 0);
1938 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1939 kernel_size = load_elf(kernel_filename,
1940 translate_kernel_address, NULL,
1941 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1942 0, 0);
1943 kernel_le = kernel_size > 0;
1944 }
1945 if (kernel_size < 0) {
1946 error_report("error loading %s: %s",
1947 kernel_filename, load_elf_strerror(kernel_size));
1948 exit(1);
1949 }
1950
1951 /* load initrd */
1952 if (initrd_filename) {
1953 /* Try to locate the initrd in the gap between the kernel
1954 * and the firmware. Add a bit of space just in case
1955 */
1956 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
1957 initrd_size = load_image_targphys(initrd_filename, initrd_base,
1958 load_limit - initrd_base);
1959 if (initrd_size < 0) {
1960 error_report("could not load initial ram disk '%s'",
1961 initrd_filename);
1962 exit(1);
1963 }
1964 } else {
1965 initrd_base = 0;
1966 initrd_size = 0;
1967 }
1968 }
1969
1970 if (bios_name == NULL) {
1971 bios_name = FW_FILE_NAME;
1972 }
1973 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1974 if (!filename) {
1975 error_report("Could not find LPAR firmware '%s'", bios_name);
1976 exit(1);
1977 }
1978 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
1979 if (fw_size <= 0) {
1980 error_report("Could not load LPAR firmware '%s'", filename);
1981 exit(1);
1982 }
1983 g_free(filename);
1984
1985 /* FIXME: Should register things through the MachineState's qdev
1986 * interface, this is a legacy from the sPAPREnvironment structure
1987 * which predated MachineState but had a similar function */
1988 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
1989 register_savevm_live(NULL, "spapr/htab", -1, 1,
1990 &savevm_htab_handlers, spapr);
1991
1992 /* Prepare the device tree */
1993 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
1994 kernel_size, kernel_le,
1995 kernel_cmdline,
1996 spapr->check_exception_irq);
1997 assert(spapr->fdt_skel != NULL);
1998
1999 /* used by RTAS */
2000 QTAILQ_INIT(&spapr->ccs_list);
2001 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2002
2003 qemu_register_boot_set(spapr_boot_set, spapr);
2004 }
2005
2006 static int spapr_kvm_type(const char *vm_type)
2007 {
2008 if (!vm_type) {
2009 return 0;
2010 }
2011
2012 if (!strcmp(vm_type, "HV")) {
2013 return 1;
2014 }
2015
2016 if (!strcmp(vm_type, "PR")) {
2017 return 2;
2018 }
2019
2020 error_report("Unknown kvm-type specified '%s'", vm_type);
2021 exit(1);
2022 }
2023
2024 /*
2025 * Implementation of an interface to adjust firmware path
2026 * for the bootindex property handling.
2027 */
2028 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2029 DeviceState *dev)
2030 {
2031 #define CAST(type, obj, name) \
2032 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2033 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2034 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2035
2036 if (d) {
2037 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2038 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2039 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2040
2041 if (spapr) {
2042 /*
2043 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2044 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2045 * in the top 16 bits of the 64-bit LUN
2046 */
2047 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2048 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2049 (uint64_t)id << 48);
2050 } else if (virtio) {
2051 /*
2052 * We use SRP luns of the form 01000000 | (target << 8) | lun
2053 * in the top 32 bits of the 64-bit LUN
2054 * Note: the quote above is from SLOF and it is wrong,
2055 * the actual binding is:
2056 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2057 */
2058 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2059 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2060 (uint64_t)id << 32);
2061 } else if (usb) {
2062 /*
2063 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2064 * in the top 32 bits of the 64-bit LUN
2065 */
2066 unsigned usb_port = atoi(usb->port->path);
2067 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2068 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2069 (uint64_t)id << 32);
2070 }
2071 }
2072
2073 if (phb) {
2074 /* Replace "pci" with "pci@800000020000000" */
2075 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2076 }
2077
2078 return NULL;
2079 }
2080
2081 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2082 {
2083 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2084
2085 return g_strdup(spapr->kvm_type);
2086 }
2087
2088 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2089 {
2090 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2091
2092 g_free(spapr->kvm_type);
2093 spapr->kvm_type = g_strdup(value);
2094 }
2095
2096 static void spapr_machine_initfn(Object *obj)
2097 {
2098 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2099
2100 spapr->htab_fd = -1;
2101 object_property_add_str(obj, "kvm-type",
2102 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2103 object_property_set_description(obj, "kvm-type",
2104 "Specifies the KVM virtualization mode (HV, PR)",
2105 NULL);
2106 }
2107
2108 static void spapr_machine_finalizefn(Object *obj)
2109 {
2110 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2111
2112 g_free(spapr->kvm_type);
2113 }
2114
2115 static void ppc_cpu_do_nmi_on_cpu(void *arg)
2116 {
2117 CPUState *cs = arg;
2118
2119 cpu_synchronize_state(cs);
2120 ppc_cpu_do_system_reset(cs);
2121 }
2122
2123 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2124 {
2125 CPUState *cs;
2126
2127 CPU_FOREACH(cs) {
2128 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2129 }
2130 }
2131
2132 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2133 uint32_t node, Error **errp)
2134 {
2135 sPAPRDRConnector *drc;
2136 sPAPRDRConnectorClass *drck;
2137 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2138 int i, fdt_offset, fdt_size;
2139 void *fdt;
2140
2141 /*
2142 * Check for DRC connectors and send hotplug notification to the
2143 * guest only in case of hotplugged memory. This allows cold plugged
2144 * memory to be specified at boot time.
2145 */
2146 if (!dev->hotplugged) {
2147 return;
2148 }
2149
2150 for (i = 0; i < nr_lmbs; i++) {
2151 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2152 addr/SPAPR_MEMORY_BLOCK_SIZE);
2153 g_assert(drc);
2154
2155 fdt = create_device_tree(&fdt_size);
2156 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2157 SPAPR_MEMORY_BLOCK_SIZE);
2158
2159 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2160 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2161 addr += SPAPR_MEMORY_BLOCK_SIZE;
2162 }
2163 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2164 }
2165
2166 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2167 uint32_t node, Error **errp)
2168 {
2169 Error *local_err = NULL;
2170 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2171 PCDIMMDevice *dimm = PC_DIMM(dev);
2172 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2173 MemoryRegion *mr = ddc->get_memory_region(dimm);
2174 uint64_t align = memory_region_get_alignment(mr);
2175 uint64_t size = memory_region_size(mr);
2176 uint64_t addr;
2177
2178 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2179 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2180 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2181 goto out;
2182 }
2183
2184 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2185 if (local_err) {
2186 goto out;
2187 }
2188
2189 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2190 if (local_err) {
2191 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2192 goto out;
2193 }
2194
2195 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2196
2197 out:
2198 error_propagate(errp, local_err);
2199 }
2200
2201 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2202 DeviceState *dev, Error **errp)
2203 {
2204 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2205
2206 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2207 int node;
2208
2209 if (!smc->dr_lmb_enabled) {
2210 error_setg(errp, "Memory hotplug not supported for this machine");
2211 return;
2212 }
2213 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2214 if (*errp) {
2215 return;
2216 }
2217
2218 /*
2219 * Currently PowerPC kernel doesn't allow hot-adding memory to
2220 * memory-less node, but instead will silently add the memory
2221 * to the first node that has some memory. This causes two
2222 * unexpected behaviours for the user.
2223 *
2224 * - Memory gets hotplugged to a different node than what the user
2225 * specified.
2226 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2227 * to memory-less node, a reboot will set things accordingly
2228 * and the previously hotplugged memory now ends in the right node.
2229 * This appears as if some memory moved from one node to another.
2230 *
2231 * So until kernel starts supporting memory hotplug to memory-less
2232 * nodes, just prevent such attempts upfront in QEMU.
2233 */
2234 if (nb_numa_nodes && !numa_info[node].node_mem) {
2235 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2236 node);
2237 return;
2238 }
2239
2240 spapr_memory_plug(hotplug_dev, dev, node, errp);
2241 }
2242 }
2243
2244 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2245 DeviceState *dev, Error **errp)
2246 {
2247 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2248 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2249 }
2250 }
2251
2252 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2253 DeviceState *dev)
2254 {
2255 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2256 return HOTPLUG_HANDLER(machine);
2257 }
2258 return NULL;
2259 }
2260
2261 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2262 {
2263 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2264 * socket means much for the paravirtualized PAPR platform) */
2265 return cpu_index / smp_threads / smp_cores;
2266 }
2267
2268 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2269 {
2270 MachineClass *mc = MACHINE_CLASS(oc);
2271 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2272 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2273 NMIClass *nc = NMI_CLASS(oc);
2274 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2275
2276 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2277
2278 /*
2279 * We set up the default / latest behaviour here. The class_init
2280 * functions for the specific versioned machine types can override
2281 * these details for backwards compatibility
2282 */
2283 mc->init = ppc_spapr_init;
2284 mc->reset = ppc_spapr_reset;
2285 mc->block_default_type = IF_SCSI;
2286 mc->max_cpus = MAX_CPUMASK_BITS;
2287 mc->no_parallel = 1;
2288 mc->default_boot_order = "";
2289 mc->default_ram_size = 512 * M_BYTE;
2290 mc->kvm_type = spapr_kvm_type;
2291 mc->has_dynamic_sysbus = true;
2292 mc->pci_allow_0_address = true;
2293 mc->get_hotplug_handler = spapr_get_hotpug_handler;
2294 hc->plug = spapr_machine_device_plug;
2295 hc->unplug = spapr_machine_device_unplug;
2296 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2297
2298 smc->dr_lmb_enabled = true;
2299 fwc->get_dev_path = spapr_get_fw_dev_path;
2300 nc->nmi_monitor_handler = spapr_nmi;
2301 }
2302
2303 static const TypeInfo spapr_machine_info = {
2304 .name = TYPE_SPAPR_MACHINE,
2305 .parent = TYPE_MACHINE,
2306 .abstract = true,
2307 .instance_size = sizeof(sPAPRMachineState),
2308 .instance_init = spapr_machine_initfn,
2309 .instance_finalize = spapr_machine_finalizefn,
2310 .class_size = sizeof(sPAPRMachineClass),
2311 .class_init = spapr_machine_class_init,
2312 .interfaces = (InterfaceInfo[]) {
2313 { TYPE_FW_PATH_PROVIDER },
2314 { TYPE_NMI },
2315 { TYPE_HOTPLUG_HANDLER },
2316 { }
2317 },
2318 };
2319
2320 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2321 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2322 void *data) \
2323 { \
2324 MachineClass *mc = MACHINE_CLASS(oc); \
2325 spapr_machine_##suffix##_class_options(mc); \
2326 if (latest) { \
2327 mc->alias = "pseries"; \
2328 mc->is_default = 1; \
2329 } \
2330 } \
2331 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2332 { \
2333 MachineState *machine = MACHINE(obj); \
2334 spapr_machine_##suffix##_instance_options(machine); \
2335 } \
2336 static const TypeInfo spapr_machine_##suffix##_info = { \
2337 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2338 .parent = TYPE_SPAPR_MACHINE, \
2339 .class_init = spapr_machine_##suffix##_class_init, \
2340 .instance_init = spapr_machine_##suffix##_instance_init, \
2341 }; \
2342 static void spapr_machine_register_##suffix(void) \
2343 { \
2344 type_register(&spapr_machine_##suffix##_info); \
2345 } \
2346 machine_init(spapr_machine_register_##suffix)
2347
2348 /*
2349 * pseries-2.6
2350 */
2351 static void spapr_machine_2_6_instance_options(MachineState *machine)
2352 {
2353 }
2354
2355 static void spapr_machine_2_6_class_options(MachineClass *mc)
2356 {
2357 /* Defaults for the latest behaviour inherited from the base class */
2358 }
2359
2360 DEFINE_SPAPR_MACHINE(2_6, "2.6", true);
2361
2362 /*
2363 * pseries-2.5
2364 */
2365 #define SPAPR_COMPAT_2_5 \
2366 HW_COMPAT_2_5
2367
2368 static void spapr_machine_2_5_instance_options(MachineState *machine)
2369 {
2370 }
2371
2372 static void spapr_machine_2_5_class_options(MachineClass *mc)
2373 {
2374 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2375
2376 spapr_machine_2_6_class_options(mc);
2377 smc->use_ohci_by_default = true;
2378 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
2379 }
2380
2381 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
2382
2383 /*
2384 * pseries-2.4
2385 */
2386 #define SPAPR_COMPAT_2_4 \
2387 SPAPR_COMPAT_2_5 \
2388 HW_COMPAT_2_4
2389
2390 static void spapr_machine_2_4_instance_options(MachineState *machine)
2391 {
2392 spapr_machine_2_5_instance_options(machine);
2393 }
2394
2395 static void spapr_machine_2_4_class_options(MachineClass *mc)
2396 {
2397 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2398
2399 spapr_machine_2_5_class_options(mc);
2400 smc->dr_lmb_enabled = false;
2401 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
2402 }
2403
2404 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
2405
2406 /*
2407 * pseries-2.3
2408 */
2409 #define SPAPR_COMPAT_2_3 \
2410 SPAPR_COMPAT_2_4 \
2411 HW_COMPAT_2_3 \
2412 {\
2413 .driver = "spapr-pci-host-bridge",\
2414 .property = "dynamic-reconfiguration",\
2415 .value = "off",\
2416 },
2417
2418 static void spapr_machine_2_3_instance_options(MachineState *machine)
2419 {
2420 spapr_machine_2_4_instance_options(machine);
2421 savevm_skip_section_footers();
2422 global_state_set_optional();
2423 savevm_skip_configuration();
2424 }
2425
2426 static void spapr_machine_2_3_class_options(MachineClass *mc)
2427 {
2428 spapr_machine_2_4_class_options(mc);
2429 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
2430 }
2431 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
2432
2433 /*
2434 * pseries-2.2
2435 */
2436
2437 #define SPAPR_COMPAT_2_2 \
2438 SPAPR_COMPAT_2_3 \
2439 HW_COMPAT_2_2 \
2440 {\
2441 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2442 .property = "mem_win_size",\
2443 .value = "0x20000000",\
2444 },
2445
2446 static void spapr_machine_2_2_instance_options(MachineState *machine)
2447 {
2448 spapr_machine_2_3_instance_options(machine);
2449 machine->suppress_vmdesc = true;
2450 }
2451
2452 static void spapr_machine_2_2_class_options(MachineClass *mc)
2453 {
2454 spapr_machine_2_3_class_options(mc);
2455 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
2456 }
2457 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
2458
2459 /*
2460 * pseries-2.1
2461 */
2462 #define SPAPR_COMPAT_2_1 \
2463 SPAPR_COMPAT_2_2 \
2464 HW_COMPAT_2_1
2465
2466 static void spapr_machine_2_1_instance_options(MachineState *machine)
2467 {
2468 spapr_machine_2_2_instance_options(machine);
2469 }
2470
2471 static void spapr_machine_2_1_class_options(MachineClass *mc)
2472 {
2473 spapr_machine_2_2_class_options(mc);
2474 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
2475 }
2476 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
2477
2478 static void spapr_machine_register_types(void)
2479 {
2480 type_register_static(&spapr_machine_info);
2481 }
2482
2483 type_init(spapr_machine_register_types)
QEmu