2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #define TARGET_LONG_BITS 32
34 #define CPUArchState struct CPUXtensaState
36 #include "qemu-common.h"
38 #include "exec/cpu-defs.h"
39 #include "fpu/softfloat.h"
41 #define NB_MMU_MODES 4
43 #define TARGET_PHYS_ADDR_SPACE_BITS 32
44 #define TARGET_VIRT_ADDR_SPACE_BITS 32
45 #define TARGET_PAGE_BITS 12
48 /* Additional instructions */
49 XTENSA_OPTION_CODE_DENSITY
,
51 XTENSA_OPTION_EXTENDED_L32R
,
52 XTENSA_OPTION_16_BIT_IMUL
,
53 XTENSA_OPTION_32_BIT_IMUL
,
54 XTENSA_OPTION_32_BIT_IMUL_HIGH
,
55 XTENSA_OPTION_32_BIT_IDIV
,
57 XTENSA_OPTION_MISC_OP_NSA
,
58 XTENSA_OPTION_MISC_OP_MINMAX
,
59 XTENSA_OPTION_MISC_OP_SEXT
,
60 XTENSA_OPTION_MISC_OP_CLAMPS
,
61 XTENSA_OPTION_COPROCESSOR
,
62 XTENSA_OPTION_BOOLEAN
,
63 XTENSA_OPTION_FP_COPROCESSOR
,
64 XTENSA_OPTION_MP_SYNCHRO
,
65 XTENSA_OPTION_CONDITIONAL_STORE
,
66 XTENSA_OPTION_ATOMCTL
,
67 XTENSA_OPTION_DEPBITS
,
69 /* Interrupts and exceptions */
70 XTENSA_OPTION_EXCEPTION
,
71 XTENSA_OPTION_RELOCATABLE_VECTOR
,
72 XTENSA_OPTION_UNALIGNED_EXCEPTION
,
73 XTENSA_OPTION_INTERRUPT
,
74 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
75 XTENSA_OPTION_TIMER_INTERRUPT
,
79 XTENSA_OPTION_ICACHE_TEST
,
80 XTENSA_OPTION_ICACHE_INDEX_LOCK
,
82 XTENSA_OPTION_DCACHE_TEST
,
83 XTENSA_OPTION_DCACHE_INDEX_LOCK
,
89 XTENSA_OPTION_HW_ALIGNMENT
,
90 XTENSA_OPTION_MEMORY_ECC_PARITY
,
92 /* Memory protection and translation */
93 XTENSA_OPTION_REGION_PROTECTION
,
94 XTENSA_OPTION_REGION_TRANSLATION
,
96 XTENSA_OPTION_CACHEATTR
,
99 XTENSA_OPTION_WINDOWED_REGISTER
,
100 XTENSA_OPTION_PROCESSOR_INTERFACE
,
101 XTENSA_OPTION_MISC_SR
,
102 XTENSA_OPTION_THREAD_POINTER
,
103 XTENSA_OPTION_PROCESSOR_ID
,
105 XTENSA_OPTION_TRACE_PORT
,
160 #define PS_INTLEVEL 0xf
161 #define PS_INTLEVEL_SHIFT 0
167 #define PS_RING_SHIFT 6
170 #define PS_OWB_SHIFT 8
172 #define PS_CALLINC 0x30000
173 #define PS_CALLINC_SHIFT 16
174 #define PS_CALLINC_LEN 2
176 #define PS_WOE 0x40000
178 #define DEBUGCAUSE_IC 0x1
179 #define DEBUGCAUSE_IB 0x2
180 #define DEBUGCAUSE_DB 0x4
181 #define DEBUGCAUSE_BI 0x8
182 #define DEBUGCAUSE_BN 0x10
183 #define DEBUGCAUSE_DI 0x20
184 #define DEBUGCAUSE_DBNUM 0xf00
185 #define DEBUGCAUSE_DBNUM_SHIFT 8
187 #define DBREAKC_SB 0x80000000
188 #define DBREAKC_LB 0x40000000
189 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
190 #define DBREAKC_MASK 0x3f
193 #define MAX_NINTERRUPT 32
196 #define MAX_NCCOMPARE 3
197 #define MAX_TLB_WAY_SIZE 8
198 #define MAX_NDBREAK 2
200 #define REGION_PAGE_MASK 0xe0000000
202 #define PAGE_CACHE_MASK 0x700
203 #define PAGE_CACHE_SHIFT 8
204 #define PAGE_CACHE_INVALID 0x000
205 #define PAGE_CACHE_BYPASS 0x100
206 #define PAGE_CACHE_WT 0x200
207 #define PAGE_CACHE_WB 0x400
208 #define PAGE_CACHE_ISOLATE 0x600
215 /* Dynamic vectors */
216 EXC_WINDOW_OVERFLOW4
,
217 EXC_WINDOW_UNDERFLOW4
,
218 EXC_WINDOW_OVERFLOW8
,
219 EXC_WINDOW_UNDERFLOW8
,
220 EXC_WINDOW_OVERFLOW12
,
221 EXC_WINDOW_UNDERFLOW12
,
231 ILLEGAL_INSTRUCTION_CAUSE
= 0,
233 INSTRUCTION_FETCH_ERROR_CAUSE
,
234 LOAD_STORE_ERROR_CAUSE
,
235 LEVEL1_INTERRUPT_CAUSE
,
237 INTEGER_DIVIDE_BY_ZERO_CAUSE
,
238 PRIVILEGED_CAUSE
= 8,
239 LOAD_STORE_ALIGNMENT_CAUSE
,
241 INSTR_PIF_DATA_ERROR_CAUSE
= 12,
242 LOAD_STORE_PIF_DATA_ERROR_CAUSE
,
243 INSTR_PIF_ADDR_ERROR_CAUSE
,
244 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
247 INST_TLB_MULTI_HIT_CAUSE
,
248 INST_FETCH_PRIVILEGE_CAUSE
,
249 INST_FETCH_PROHIBITED_CAUSE
= 20,
250 LOAD_STORE_TLB_MISS_CAUSE
= 24,
251 LOAD_STORE_TLB_MULTI_HIT_CAUSE
,
252 LOAD_STORE_PRIVILEGE_CAUSE
,
253 LOAD_PROHIBITED_CAUSE
= 28,
254 STORE_PROHIBITED_CAUSE
,
256 COPROCESSOR0_DISABLED
= 32,
271 typedef struct xtensa_tlb_entry
{
279 typedef struct xtensa_tlb
{
281 const unsigned way_size
[10];
283 unsigned nrefillentries
;
286 typedef struct XtensaGdbReg
{
293 typedef struct XtensaGdbRegmap
{
296 /* PC + a + ar + sr + ur */
297 XtensaGdbReg reg
[1 + 16 + 64 + 256 + 256];
300 struct XtensaConfig
{
303 XtensaGdbRegmap gdb_regmap
;
308 uint32_t exception_vector
[EXC_MAX
];
311 uint32_t interrupt_vector
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
312 uint32_t level_mask
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
313 uint32_t inttype_mask
[INTTYPE_MAX
];
316 interrupt_type inttype
;
317 } interrupt
[MAX_NINTERRUPT
];
319 uint32_t timerint
[MAX_NCCOMPARE
];
321 unsigned extint
[MAX_NINTERRUPT
];
323 unsigned debug_level
;
327 uint32_t configid
[2];
329 uint32_t clock_freq_khz
;
335 typedef struct XtensaConfigList
{
336 const XtensaConfig
*config
;
337 struct XtensaConfigList
*next
;
340 #ifdef HOST_WORDS_BIGENDIAN
352 typedef struct CPUXtensaState
{
353 const XtensaConfig
*config
;
358 uint32_t phys_regs
[MAX_NAREG
];
363 float_status fp_status
;
365 xtensa_tlb_entry itlb
[7][MAX_TLB_WAY_SIZE
];
366 xtensa_tlb_entry dtlb
[10][MAX_TLB_WAY_SIZE
];
367 unsigned autorefill_idx
;
369 int pending_irq_level
; /* level of last raised IRQ */
371 QEMUTimer
*ccompare_timer
;
372 uint32_t wake_ccount
;
377 /* Watchpoints for DBREAK registers */
378 struct CPUWatchpoint
*cpu_watchpoint
[MAX_NDBREAK
];
385 * @env: #CPUXtensaState
397 static inline XtensaCPU
*xtensa_env_get_cpu(const CPUXtensaState
*env
)
399 return container_of(env
, XtensaCPU
, env
);
402 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
404 #define ENV_OFFSET offsetof(XtensaCPU, env)
406 void xtensa_cpu_do_interrupt(CPUState
*cpu
);
407 bool xtensa_cpu_exec_interrupt(CPUState
*cpu
, int interrupt_request
);
408 void xtensa_cpu_do_unassigned_access(CPUState
*cpu
, hwaddr addr
,
409 bool is_write
, bool is_exec
, int opaque
,
411 void xtensa_cpu_dump_state(CPUState
*cpu
, FILE *f
,
412 fprintf_function cpu_fprintf
, int flags
);
413 hwaddr
xtensa_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
414 int xtensa_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
415 int xtensa_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
416 void xtensa_cpu_do_unaligned_access(CPUState
*cpu
, vaddr addr
,
417 int is_write
, int is_user
, uintptr_t retaddr
);
419 #define cpu_exec cpu_xtensa_exec
420 #define cpu_signal_handler cpu_xtensa_signal_handler
421 #define cpu_list xtensa_cpu_list
423 #ifdef TARGET_WORDS_BIGENDIAN
424 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
426 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
429 XtensaCPU
*cpu_xtensa_init(const char *cpu_model
);
431 #define cpu_init(cpu_model) CPU(cpu_xtensa_init(cpu_model))
433 void xtensa_translate_init(void);
434 void xtensa_breakpoint_handler(CPUState
*cs
);
435 int cpu_xtensa_exec(CPUState
*cpu
);
436 void xtensa_finalize_config(XtensaConfig
*config
);
437 void xtensa_register_core(XtensaConfigList
*node
);
438 void check_interrupts(CPUXtensaState
*s
);
439 void xtensa_irq_init(CPUXtensaState
*env
);
440 void *xtensa_get_extint(CPUXtensaState
*env
, unsigned extint
);
441 void xtensa_advance_ccount(CPUXtensaState
*env
, uint32_t d
);
442 void xtensa_timer_irq(CPUXtensaState
*env
, uint32_t id
, uint32_t active
);
443 void xtensa_rearm_ccompare_timer(CPUXtensaState
*env
);
444 int cpu_xtensa_signal_handler(int host_signum
, void *pinfo
, void *puc
);
445 void xtensa_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
446 void xtensa_sync_window_from_phys(CPUXtensaState
*env
);
447 void xtensa_sync_phys_from_window(CPUXtensaState
*env
);
448 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState
*env
, bool dtlb
, uint32_t way
);
449 void split_tlb_entry_spec_way(const CPUXtensaState
*env
, uint32_t v
, bool dtlb
,
450 uint32_t *vpn
, uint32_t wi
, uint32_t *ei
);
451 int xtensa_tlb_lookup(const CPUXtensaState
*env
, uint32_t addr
, bool dtlb
,
452 uint32_t *pwi
, uint32_t *pei
, uint8_t *pring
);
453 void xtensa_tlb_set_entry_mmu(const CPUXtensaState
*env
,
454 xtensa_tlb_entry
*entry
, bool dtlb
,
455 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
);
456 void xtensa_tlb_set_entry(CPUXtensaState
*env
, bool dtlb
,
457 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
);
458 int xtensa_get_physical_addr(CPUXtensaState
*env
, bool update_tlb
,
459 uint32_t vaddr
, int is_write
, int mmu_idx
,
460 uint32_t *paddr
, uint32_t *page_size
, unsigned *access
);
461 void reset_mmu(CPUXtensaState
*env
);
462 void dump_mmu(FILE *f
, fprintf_function cpu_fprintf
, CPUXtensaState
*env
);
463 void debug_exception_env(CPUXtensaState
*new_env
, uint32_t cause
);
466 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
467 #define XTENSA_OPTION_ALL (~(uint64_t)0)
469 static inline bool xtensa_option_bits_enabled(const XtensaConfig
*config
,
472 return (config
->options
& opt
) != 0;
475 static inline bool xtensa_option_enabled(const XtensaConfig
*config
, int opt
)
477 return xtensa_option_bits_enabled(config
, XTENSA_OPTION_BIT(opt
));
480 static inline int xtensa_get_cintlevel(const CPUXtensaState
*env
)
482 int level
= (env
->sregs
[PS
] & PS_INTLEVEL
) >> PS_INTLEVEL_SHIFT
;
483 if ((env
->sregs
[PS
] & PS_EXCM
) && env
->config
->excm_level
> level
) {
484 level
= env
->config
->excm_level
;
489 static inline int xtensa_get_ring(const CPUXtensaState
*env
)
491 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
492 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
498 static inline int xtensa_get_cring(const CPUXtensaState
*env
)
500 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
) &&
501 (env
->sregs
[PS
] & PS_EXCM
) == 0) {
502 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
508 static inline xtensa_tlb_entry
*xtensa_tlb_get_entry(CPUXtensaState
*env
,
509 bool dtlb
, unsigned wi
, unsigned ei
)
516 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState
*env
)
518 return env
->sregs
[WINDOW_START
] |
519 (env
->sregs
[WINDOW_START
] << env
->config
->nareg
/ 4);
522 /* MMU modes definitions */
523 #define MMU_MODE0_SUFFIX _ring0
524 #define MMU_MODE1_SUFFIX _ring1
525 #define MMU_MODE2_SUFFIX _ring2
526 #define MMU_MODE3_SUFFIX _ring3
528 static inline int cpu_mmu_index(CPUXtensaState
*env
, bool ifetch
)
530 return xtensa_get_cring(env
);
533 #define XTENSA_TBFLAG_RING_MASK 0x3
534 #define XTENSA_TBFLAG_EXCM 0x4
535 #define XTENSA_TBFLAG_LITBASE 0x8
536 #define XTENSA_TBFLAG_DEBUG 0x10
537 #define XTENSA_TBFLAG_ICOUNT 0x20
538 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
539 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
540 #define XTENSA_TBFLAG_EXCEPTION 0x4000
541 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
542 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
544 static inline void cpu_get_tb_cpu_state(CPUXtensaState
*env
, target_ulong
*pc
,
545 target_ulong
*cs_base
, uint32_t *flags
)
547 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
552 *flags
|= xtensa_get_ring(env
);
553 if (env
->sregs
[PS
] & PS_EXCM
) {
554 *flags
|= XTENSA_TBFLAG_EXCM
;
556 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_EXTENDED_L32R
) &&
557 (env
->sregs
[LITBASE
] & 1)) {
558 *flags
|= XTENSA_TBFLAG_LITBASE
;
560 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_DEBUG
)) {
561 if (xtensa_get_cintlevel(env
) < env
->config
->debug_level
) {
562 *flags
|= XTENSA_TBFLAG_DEBUG
;
564 if (xtensa_get_cintlevel(env
) < env
->sregs
[ICOUNTLEVEL
]) {
565 *flags
|= XTENSA_TBFLAG_ICOUNT
;
568 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_COPROCESSOR
)) {
569 *flags
|= env
->sregs
[CPENABLE
] << XTENSA_TBFLAG_CPENABLE_SHIFT
;
571 if (cs
->singlestep_enabled
&& env
->exception_taken
) {
572 *flags
|= XTENSA_TBFLAG_EXCEPTION
;
574 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
575 (env
->sregs
[PS
] & (PS_WOE
| PS_EXCM
)) == PS_WOE
) {
576 uint32_t windowstart
= xtensa_replicate_windowstart(env
) >>
577 (env
->sregs
[WINDOW_BASE
] + 1);
578 uint32_t w
= ctz32(windowstart
| 0x8);
580 *flags
|= w
<< XTENSA_TBFLAG_WINDOW_SHIFT
;
582 *flags
|= 3 << XTENSA_TBFLAG_WINDOW_SHIFT
;
586 #include "exec/cpu-all.h"