host-utils: Prefer 'false' for bool type
[qemu.git] / target-arm / helper.c
blob862e7808a2ddc3fd3c3b66abc4626b94dc4ec179
1 #include "qemu/osdep.h"
2 #include "cpu.h"
3 #include "internals.h"
4 #include "exec/gdbstub.h"
5 #include "exec/helper-proto.h"
6 #include "qemu/host-utils.h"
7 #include "sysemu/arch_init.h"
8 #include "sysemu/sysemu.h"
9 #include "qemu/bitops.h"
10 #include "qemu/crc32c.h"
11 #include "exec/exec-all.h"
12 #include "exec/cpu_ldst.h"
13 #include "arm_ldst.h"
14 #include <zlib.h> /* For crc32 */
15 #include "exec/semihost.h"
16 #include "sysemu/kvm.h"
18 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
20 #ifndef CONFIG_USER_ONLY
21 static bool get_phys_addr(CPUARMState *env, target_ulong address,
22 int access_type, ARMMMUIdx mmu_idx,
23 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
24 target_ulong *page_size, uint32_t *fsr,
25 ARMMMUFaultInfo *fi);
27 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
28 int access_type, ARMMMUIdx mmu_idx,
29 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
30 target_ulong *page_size_ptr, uint32_t *fsr,
31 ARMMMUFaultInfo *fi);
33 /* Definitions for the PMCCNTR and PMCR registers */
34 #define PMCRD 0x8
35 #define PMCRC 0x4
36 #define PMCRE 0x1
37 #endif
39 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
41 int nregs;
43 /* VFP data registers are always little-endian. */
44 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
45 if (reg < nregs) {
46 stfq_le_p(buf, env->vfp.regs[reg]);
47 return 8;
49 if (arm_feature(env, ARM_FEATURE_NEON)) {
50 /* Aliases for Q regs. */
51 nregs += 16;
52 if (reg < nregs) {
53 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
54 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
55 return 16;
58 switch (reg - nregs) {
59 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
60 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
61 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
63 return 0;
66 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
68 int nregs;
70 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
71 if (reg < nregs) {
72 env->vfp.regs[reg] = ldfq_le_p(buf);
73 return 8;
75 if (arm_feature(env, ARM_FEATURE_NEON)) {
76 nregs += 16;
77 if (reg < nregs) {
78 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
79 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
80 return 16;
83 switch (reg - nregs) {
84 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
85 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
86 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
88 return 0;
91 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
93 switch (reg) {
94 case 0 ... 31:
95 /* 128 bit FP register */
96 stfq_le_p(buf, env->vfp.regs[reg * 2]);
97 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
98 return 16;
99 case 32:
100 /* FPSR */
101 stl_p(buf, vfp_get_fpsr(env));
102 return 4;
103 case 33:
104 /* FPCR */
105 stl_p(buf, vfp_get_fpcr(env));
106 return 4;
107 default:
108 return 0;
112 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
114 switch (reg) {
115 case 0 ... 31:
116 /* 128 bit FP register */
117 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
118 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
119 return 16;
120 case 32:
121 /* FPSR */
122 vfp_set_fpsr(env, ldl_p(buf));
123 return 4;
124 case 33:
125 /* FPCR */
126 vfp_set_fpcr(env, ldl_p(buf));
127 return 4;
128 default:
129 return 0;
133 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
135 assert(ri->fieldoffset);
136 if (cpreg_field_is_64bit(ri)) {
137 return CPREG_FIELD64(env, ri);
138 } else {
139 return CPREG_FIELD32(env, ri);
143 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
144 uint64_t value)
146 assert(ri->fieldoffset);
147 if (cpreg_field_is_64bit(ri)) {
148 CPREG_FIELD64(env, ri) = value;
149 } else {
150 CPREG_FIELD32(env, ri) = value;
154 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
156 return (char *)env + ri->fieldoffset;
159 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
161 /* Raw read of a coprocessor register (as needed for migration, etc). */
162 if (ri->type & ARM_CP_CONST) {
163 return ri->resetvalue;
164 } else if (ri->raw_readfn) {
165 return ri->raw_readfn(env, ri);
166 } else if (ri->readfn) {
167 return ri->readfn(env, ri);
168 } else {
169 return raw_read(env, ri);
173 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
174 uint64_t v)
176 /* Raw write of a coprocessor register (as needed for migration, etc).
177 * Note that constant registers are treated as write-ignored; the
178 * caller should check for success by whether a readback gives the
179 * value written.
181 if (ri->type & ARM_CP_CONST) {
182 return;
183 } else if (ri->raw_writefn) {
184 ri->raw_writefn(env, ri, v);
185 } else if (ri->writefn) {
186 ri->writefn(env, ri, v);
187 } else {
188 raw_write(env, ri, v);
192 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
194 /* Return true if the regdef would cause an assertion if you called
195 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
196 * program bug for it not to have the NO_RAW flag).
197 * NB that returning false here doesn't necessarily mean that calling
198 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
199 * read/write access functions which are safe for raw use" from "has
200 * read/write access functions which have side effects but has forgotten
201 * to provide raw access functions".
202 * The tests here line up with the conditions in read/write_raw_cp_reg()
203 * and assertions in raw_read()/raw_write().
205 if ((ri->type & ARM_CP_CONST) ||
206 ri->fieldoffset ||
207 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
208 return false;
210 return true;
213 bool write_cpustate_to_list(ARMCPU *cpu)
215 /* Write the coprocessor state from cpu->env to the (index,value) list. */
216 int i;
217 bool ok = true;
219 for (i = 0; i < cpu->cpreg_array_len; i++) {
220 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
221 const ARMCPRegInfo *ri;
223 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
224 if (!ri) {
225 ok = false;
226 continue;
228 if (ri->type & ARM_CP_NO_RAW) {
229 continue;
231 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
233 return ok;
236 bool write_list_to_cpustate(ARMCPU *cpu)
238 int i;
239 bool ok = true;
241 for (i = 0; i < cpu->cpreg_array_len; i++) {
242 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
243 uint64_t v = cpu->cpreg_values[i];
244 const ARMCPRegInfo *ri;
246 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
247 if (!ri) {
248 ok = false;
249 continue;
251 if (ri->type & ARM_CP_NO_RAW) {
252 continue;
254 /* Write value and confirm it reads back as written
255 * (to catch read-only registers and partially read-only
256 * registers where the incoming migration value doesn't match)
258 write_raw_cp_reg(&cpu->env, ri, v);
259 if (read_raw_cp_reg(&cpu->env, ri) != v) {
260 ok = false;
263 return ok;
266 static void add_cpreg_to_list(gpointer key, gpointer opaque)
268 ARMCPU *cpu = opaque;
269 uint64_t regidx;
270 const ARMCPRegInfo *ri;
272 regidx = *(uint32_t *)key;
273 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
275 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
276 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
277 /* The value array need not be initialized at this point */
278 cpu->cpreg_array_len++;
282 static void count_cpreg(gpointer key, gpointer opaque)
284 ARMCPU *cpu = opaque;
285 uint64_t regidx;
286 const ARMCPRegInfo *ri;
288 regidx = *(uint32_t *)key;
289 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
291 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
292 cpu->cpreg_array_len++;
296 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
298 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
299 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
301 if (aidx > bidx) {
302 return 1;
304 if (aidx < bidx) {
305 return -1;
307 return 0;
310 void init_cpreg_list(ARMCPU *cpu)
312 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
313 * Note that we require cpreg_tuples[] to be sorted by key ID.
315 GList *keys;
316 int arraylen;
318 keys = g_hash_table_get_keys(cpu->cp_regs);
319 keys = g_list_sort(keys, cpreg_key_compare);
321 cpu->cpreg_array_len = 0;
323 g_list_foreach(keys, count_cpreg, cpu);
325 arraylen = cpu->cpreg_array_len;
326 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
327 cpu->cpreg_values = g_new(uint64_t, arraylen);
328 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
329 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
330 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
331 cpu->cpreg_array_len = 0;
333 g_list_foreach(keys, add_cpreg_to_list, cpu);
335 assert(cpu->cpreg_array_len == arraylen);
337 g_list_free(keys);
341 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
342 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
344 * access_el3_aa32ns: Used to check AArch32 register views.
345 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
347 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
348 const ARMCPRegInfo *ri,
349 bool isread)
351 bool secure = arm_is_secure_below_el3(env);
353 assert(!arm_el_is_aa64(env, 3));
354 if (secure) {
355 return CP_ACCESS_TRAP_UNCATEGORIZED;
357 return CP_ACCESS_OK;
360 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
361 const ARMCPRegInfo *ri,
362 bool isread)
364 if (!arm_el_is_aa64(env, 3)) {
365 return access_el3_aa32ns(env, ri, isread);
367 return CP_ACCESS_OK;
370 /* Some secure-only AArch32 registers trap to EL3 if used from
371 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
372 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
373 * We assume that the .access field is set to PL1_RW.
375 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
376 const ARMCPRegInfo *ri,
377 bool isread)
379 if (arm_current_el(env) == 3) {
380 return CP_ACCESS_OK;
382 if (arm_is_secure_below_el3(env)) {
383 return CP_ACCESS_TRAP_EL3;
385 /* This will be EL1 NS and EL2 NS, which just UNDEF */
386 return CP_ACCESS_TRAP_UNCATEGORIZED;
389 /* Check for traps to "powerdown debug" registers, which are controlled
390 * by MDCR.TDOSA
392 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
393 bool isread)
395 int el = arm_current_el(env);
397 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA)
398 && !arm_is_secure_below_el3(env)) {
399 return CP_ACCESS_TRAP_EL2;
401 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
402 return CP_ACCESS_TRAP_EL3;
404 return CP_ACCESS_OK;
407 /* Check for traps to "debug ROM" registers, which are controlled
408 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
410 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
411 bool isread)
413 int el = arm_current_el(env);
415 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA)
416 && !arm_is_secure_below_el3(env)) {
417 return CP_ACCESS_TRAP_EL2;
419 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
420 return CP_ACCESS_TRAP_EL3;
422 return CP_ACCESS_OK;
425 /* Check for traps to general debug registers, which are controlled
426 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
428 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
429 bool isread)
431 int el = arm_current_el(env);
433 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA)
434 && !arm_is_secure_below_el3(env)) {
435 return CP_ACCESS_TRAP_EL2;
437 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
438 return CP_ACCESS_TRAP_EL3;
440 return CP_ACCESS_OK;
443 /* Check for traps to performance monitor registers, which are controlled
444 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
446 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
447 bool isread)
449 int el = arm_current_el(env);
451 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
452 && !arm_is_secure_below_el3(env)) {
453 return CP_ACCESS_TRAP_EL2;
455 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
456 return CP_ACCESS_TRAP_EL3;
458 return CP_ACCESS_OK;
461 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
463 ARMCPU *cpu = arm_env_get_cpu(env);
465 raw_write(env, ri, value);
466 tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
469 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
471 ARMCPU *cpu = arm_env_get_cpu(env);
473 if (raw_read(env, ri) != value) {
474 /* Unlike real hardware the qemu TLB uses virtual addresses,
475 * not modified virtual addresses, so this causes a TLB flush.
477 tlb_flush(CPU(cpu), 1);
478 raw_write(env, ri, value);
482 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
483 uint64_t value)
485 ARMCPU *cpu = arm_env_get_cpu(env);
487 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
488 && !extended_addresses_enabled(env)) {
489 /* For VMSA (when not using the LPAE long descriptor page table
490 * format) this register includes the ASID, so do a TLB flush.
491 * For PMSA it is purely a process ID and no action is needed.
493 tlb_flush(CPU(cpu), 1);
495 raw_write(env, ri, value);
498 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
499 uint64_t value)
501 /* Invalidate all (TLBIALL) */
502 ARMCPU *cpu = arm_env_get_cpu(env);
504 tlb_flush(CPU(cpu), 1);
507 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
508 uint64_t value)
510 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
511 ARMCPU *cpu = arm_env_get_cpu(env);
513 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
516 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
517 uint64_t value)
519 /* Invalidate by ASID (TLBIASID) */
520 ARMCPU *cpu = arm_env_get_cpu(env);
522 tlb_flush(CPU(cpu), value == 0);
525 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
526 uint64_t value)
528 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
529 ARMCPU *cpu = arm_env_get_cpu(env);
531 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
534 /* IS variants of TLB operations must affect all cores */
535 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
536 uint64_t value)
538 CPUState *other_cs;
540 CPU_FOREACH(other_cs) {
541 tlb_flush(other_cs, 1);
545 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
546 uint64_t value)
548 CPUState *other_cs;
550 CPU_FOREACH(other_cs) {
551 tlb_flush(other_cs, value == 0);
555 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
556 uint64_t value)
558 CPUState *other_cs;
560 CPU_FOREACH(other_cs) {
561 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
565 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
566 uint64_t value)
568 CPUState *other_cs;
570 CPU_FOREACH(other_cs) {
571 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
575 static const ARMCPRegInfo cp_reginfo[] = {
576 /* Define the secure and non-secure FCSE identifier CP registers
577 * separately because there is no secure bank in V8 (no _EL3). This allows
578 * the secure register to be properly reset and migrated. There is also no
579 * v8 EL1 version of the register so the non-secure instance stands alone.
581 { .name = "FCSEIDR(NS)",
582 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
583 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
584 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
585 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
586 { .name = "FCSEIDR(S)",
587 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
588 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
589 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
590 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
591 /* Define the secure and non-secure context identifier CP registers
592 * separately because there is no secure bank in V8 (no _EL3). This allows
593 * the secure register to be properly reset and migrated. In the
594 * non-secure case, the 32-bit register will have reset and migration
595 * disabled during registration as it is handled by the 64-bit instance.
597 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
598 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
599 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
600 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
601 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
602 { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
603 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
604 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
605 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
606 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
607 REGINFO_SENTINEL
610 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
611 /* NB: Some of these registers exist in v8 but with more precise
612 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
614 /* MMU Domain access control / MPU write buffer control */
615 { .name = "DACR",
616 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
617 .access = PL1_RW, .resetvalue = 0,
618 .writefn = dacr_write, .raw_writefn = raw_write,
619 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
620 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
621 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
622 * For v6 and v5, these mappings are overly broad.
624 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
625 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
626 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
627 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
628 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
629 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
630 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
631 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
632 /* Cache maintenance ops; some of this space may be overridden later. */
633 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
634 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
635 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
636 REGINFO_SENTINEL
639 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
640 /* Not all pre-v6 cores implemented this WFI, so this is slightly
641 * over-broad.
643 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
644 .access = PL1_W, .type = ARM_CP_WFI },
645 REGINFO_SENTINEL
648 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
649 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
650 * is UNPREDICTABLE; we choose to NOP as most implementations do).
652 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
653 .access = PL1_W, .type = ARM_CP_WFI },
654 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
655 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
656 * OMAPCP will override this space.
658 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
659 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
660 .resetvalue = 0 },
661 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
662 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
663 .resetvalue = 0 },
664 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
665 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
666 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
667 .resetvalue = 0 },
668 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
669 * implementing it as RAZ means the "debug architecture version" bits
670 * will read as a reserved value, which should cause Linux to not try
671 * to use the debug hardware.
673 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
674 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
675 /* MMU TLB control. Note that the wildcarding means we cover not just
676 * the unified TLB ops but also the dside/iside/inner-shareable variants.
678 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
679 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
680 .type = ARM_CP_NO_RAW },
681 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
682 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
683 .type = ARM_CP_NO_RAW },
684 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
685 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
686 .type = ARM_CP_NO_RAW },
687 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
688 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
689 .type = ARM_CP_NO_RAW },
690 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
691 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
692 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
693 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
694 REGINFO_SENTINEL
697 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
698 uint64_t value)
700 uint32_t mask = 0;
702 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
703 if (!arm_feature(env, ARM_FEATURE_V8)) {
704 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
705 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
706 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
708 if (arm_feature(env, ARM_FEATURE_VFP)) {
709 /* VFP coprocessor: cp10 & cp11 [23:20] */
710 mask |= (1 << 31) | (1 << 30) | (0xf << 20);
712 if (!arm_feature(env, ARM_FEATURE_NEON)) {
713 /* ASEDIS [31] bit is RAO/WI */
714 value |= (1 << 31);
717 /* VFPv3 and upwards with NEON implement 32 double precision
718 * registers (D0-D31).
720 if (!arm_feature(env, ARM_FEATURE_NEON) ||
721 !arm_feature(env, ARM_FEATURE_VFP3)) {
722 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
723 value |= (1 << 30);
726 value &= mask;
728 env->cp15.cpacr_el1 = value;
731 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
732 bool isread)
734 if (arm_feature(env, ARM_FEATURE_V8)) {
735 /* Check if CPACR accesses are to be trapped to EL2 */
736 if (arm_current_el(env) == 1 &&
737 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
738 return CP_ACCESS_TRAP_EL2;
739 /* Check if CPACR accesses are to be trapped to EL3 */
740 } else if (arm_current_el(env) < 3 &&
741 (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
742 return CP_ACCESS_TRAP_EL3;
746 return CP_ACCESS_OK;
749 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
750 bool isread)
752 /* Check if CPTR accesses are set to trap to EL3 */
753 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
754 return CP_ACCESS_TRAP_EL3;
757 return CP_ACCESS_OK;
760 static const ARMCPRegInfo v6_cp_reginfo[] = {
761 /* prefetch by MVA in v6, NOP in v7 */
762 { .name = "MVA_prefetch",
763 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
764 .access = PL1_W, .type = ARM_CP_NOP },
765 /* We need to break the TB after ISB to execute self-modifying code
766 * correctly and also to take any pending interrupts immediately.
767 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
769 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
770 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
771 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
772 .access = PL0_W, .type = ARM_CP_NOP },
773 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
774 .access = PL0_W, .type = ARM_CP_NOP },
775 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
776 .access = PL1_RW,
777 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
778 offsetof(CPUARMState, cp15.ifar_ns) },
779 .resetvalue = 0, },
780 /* Watchpoint Fault Address Register : should actually only be present
781 * for 1136, 1176, 11MPCore.
783 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
784 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
785 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
786 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
787 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
788 .resetvalue = 0, .writefn = cpacr_write },
789 REGINFO_SENTINEL
792 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
793 bool isread)
795 /* Performance monitor registers user accessibility is controlled
796 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
797 * trapping to EL2 or EL3 for other accesses.
799 int el = arm_current_el(env);
801 if (el == 0 && !env->cp15.c9_pmuserenr) {
802 return CP_ACCESS_TRAP;
804 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
805 && !arm_is_secure_below_el3(env)) {
806 return CP_ACCESS_TRAP_EL2;
808 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
809 return CP_ACCESS_TRAP_EL3;
812 return CP_ACCESS_OK;
815 #ifndef CONFIG_USER_ONLY
817 static inline bool arm_ccnt_enabled(CPUARMState *env)
819 /* This does not support checking PMCCFILTR_EL0 register */
821 if (!(env->cp15.c9_pmcr & PMCRE)) {
822 return false;
825 return true;
828 void pmccntr_sync(CPUARMState *env)
830 uint64_t temp_ticks;
832 temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
833 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
835 if (env->cp15.c9_pmcr & PMCRD) {
836 /* Increment once every 64 processor clock cycles */
837 temp_ticks /= 64;
840 if (arm_ccnt_enabled(env)) {
841 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
845 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
846 uint64_t value)
848 pmccntr_sync(env);
850 if (value & PMCRC) {
851 /* The counter has been reset */
852 env->cp15.c15_ccnt = 0;
855 /* only the DP, X, D and E bits are writable */
856 env->cp15.c9_pmcr &= ~0x39;
857 env->cp15.c9_pmcr |= (value & 0x39);
859 pmccntr_sync(env);
862 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
864 uint64_t total_ticks;
866 if (!arm_ccnt_enabled(env)) {
867 /* Counter is disabled, do not change value */
868 return env->cp15.c15_ccnt;
871 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
872 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
874 if (env->cp15.c9_pmcr & PMCRD) {
875 /* Increment once every 64 processor clock cycles */
876 total_ticks /= 64;
878 return total_ticks - env->cp15.c15_ccnt;
881 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
882 uint64_t value)
884 uint64_t total_ticks;
886 if (!arm_ccnt_enabled(env)) {
887 /* Counter is disabled, set the absolute value */
888 env->cp15.c15_ccnt = value;
889 return;
892 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
893 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
895 if (env->cp15.c9_pmcr & PMCRD) {
896 /* Increment once every 64 processor clock cycles */
897 total_ticks /= 64;
899 env->cp15.c15_ccnt = total_ticks - value;
902 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
903 uint64_t value)
905 uint64_t cur_val = pmccntr_read(env, NULL);
907 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
910 #else /* CONFIG_USER_ONLY */
912 void pmccntr_sync(CPUARMState *env)
916 #endif
918 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
919 uint64_t value)
921 pmccntr_sync(env);
922 env->cp15.pmccfiltr_el0 = value & 0x7E000000;
923 pmccntr_sync(env);
926 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
927 uint64_t value)
929 value &= (1 << 31);
930 env->cp15.c9_pmcnten |= value;
933 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
934 uint64_t value)
936 value &= (1 << 31);
937 env->cp15.c9_pmcnten &= ~value;
940 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
941 uint64_t value)
943 env->cp15.c9_pmovsr &= ~value;
946 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
947 uint64_t value)
949 env->cp15.c9_pmxevtyper = value & 0xff;
952 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
953 uint64_t value)
955 env->cp15.c9_pmuserenr = value & 1;
958 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
959 uint64_t value)
961 /* We have no event counters so only the C bit can be changed */
962 value &= (1 << 31);
963 env->cp15.c9_pminten |= value;
966 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
967 uint64_t value)
969 value &= (1 << 31);
970 env->cp15.c9_pminten &= ~value;
973 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
974 uint64_t value)
976 /* Note that even though the AArch64 view of this register has bits
977 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
978 * architectural requirements for bits which are RES0 only in some
979 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
980 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
982 raw_write(env, ri, value & ~0x1FULL);
985 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
987 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
988 * For bits that vary between AArch32/64, code needs to check the
989 * current execution mode before directly using the feature bit.
991 uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
993 if (!arm_feature(env, ARM_FEATURE_EL2)) {
994 valid_mask &= ~SCR_HCE;
996 /* On ARMv7, SMD (or SCD as it is called in v7) is only
997 * supported if EL2 exists. The bit is UNK/SBZP when
998 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
999 * when EL2 is unavailable.
1000 * On ARMv8, this bit is always available.
1002 if (arm_feature(env, ARM_FEATURE_V7) &&
1003 !arm_feature(env, ARM_FEATURE_V8)) {
1004 valid_mask &= ~SCR_SMD;
1008 /* Clear all-context RES0 bits. */
1009 value &= valid_mask;
1010 raw_write(env, ri, value);
1013 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1015 ARMCPU *cpu = arm_env_get_cpu(env);
1017 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1018 * bank
1020 uint32_t index = A32_BANKED_REG_GET(env, csselr,
1021 ri->secure & ARM_CP_SECSTATE_S);
1023 return cpu->ccsidr[index];
1026 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1027 uint64_t value)
1029 raw_write(env, ri, value & 0xf);
1032 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1034 CPUState *cs = ENV_GET_CPU(env);
1035 uint64_t ret = 0;
1037 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
1038 ret |= CPSR_I;
1040 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
1041 ret |= CPSR_F;
1043 /* External aborts are not possible in QEMU so A bit is always clear */
1044 return ret;
1047 static const ARMCPRegInfo v7_cp_reginfo[] = {
1048 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1049 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
1050 .access = PL1_W, .type = ARM_CP_NOP },
1051 /* Performance monitors are implementation defined in v7,
1052 * but with an ARM recommended set of registers, which we
1053 * follow (although we don't actually implement any counters)
1055 * Performance registers fall into three categories:
1056 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1057 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1058 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1059 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1060 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1062 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
1063 .access = PL0_RW, .type = ARM_CP_ALIAS,
1064 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1065 .writefn = pmcntenset_write,
1066 .accessfn = pmreg_access,
1067 .raw_writefn = raw_write },
1068 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
1069 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
1070 .access = PL0_RW, .accessfn = pmreg_access,
1071 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
1072 .writefn = pmcntenset_write, .raw_writefn = raw_write },
1073 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
1074 .access = PL0_RW,
1075 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1076 .accessfn = pmreg_access,
1077 .writefn = pmcntenclr_write,
1078 .type = ARM_CP_ALIAS },
1079 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
1080 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
1081 .access = PL0_RW, .accessfn = pmreg_access,
1082 .type = ARM_CP_ALIAS,
1083 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
1084 .writefn = pmcntenclr_write },
1085 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
1086 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1087 .accessfn = pmreg_access,
1088 .writefn = pmovsr_write,
1089 .raw_writefn = raw_write },
1090 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
1091 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
1092 .access = PL0_RW, .accessfn = pmreg_access,
1093 .type = ARM_CP_ALIAS,
1094 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1095 .writefn = pmovsr_write,
1096 .raw_writefn = raw_write },
1097 /* Unimplemented so WI. */
1098 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
1099 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
1100 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
1101 * We choose to RAZ/WI.
1103 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
1104 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1105 .accessfn = pmreg_access },
1106 #ifndef CONFIG_USER_ONLY
1107 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
1108 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
1109 .readfn = pmccntr_read, .writefn = pmccntr_write32,
1110 .accessfn = pmreg_access },
1111 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
1112 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
1113 .access = PL0_RW, .accessfn = pmreg_access,
1114 .type = ARM_CP_IO,
1115 .readfn = pmccntr_read, .writefn = pmccntr_write, },
1116 #endif
1117 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1118 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1119 .writefn = pmccfiltr_write,
1120 .access = PL0_RW, .accessfn = pmreg_access,
1121 .type = ARM_CP_IO,
1122 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1123 .resetvalue = 0, },
1124 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1125 .access = PL0_RW,
1126 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
1127 .accessfn = pmreg_access, .writefn = pmxevtyper_write,
1128 .raw_writefn = raw_write },
1129 /* Unimplemented, RAZ/WI. */
1130 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1131 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1132 .accessfn = pmreg_access },
1133 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1134 .access = PL0_R | PL1_RW, .accessfn = access_tpm,
1135 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1136 .resetvalue = 0,
1137 .writefn = pmuserenr_write, .raw_writefn = raw_write },
1138 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
1139 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
1140 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1141 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1142 .resetvalue = 0,
1143 .writefn = pmuserenr_write, .raw_writefn = raw_write },
1144 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1145 .access = PL1_RW, .accessfn = access_tpm,
1146 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1147 .resetvalue = 0,
1148 .writefn = pmintenset_write, .raw_writefn = raw_write },
1149 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1150 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1151 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1152 .writefn = pmintenclr_write, },
1153 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
1154 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
1155 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1156 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1157 .writefn = pmintenclr_write },
1158 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
1159 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1160 .access = PL1_RW, .writefn = vbar_write,
1161 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
1162 offsetof(CPUARMState, cp15.vbar_ns) },
1163 .resetvalue = 0 },
1164 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1165 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1166 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1167 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1168 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1169 .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1170 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1171 offsetof(CPUARMState, cp15.csselr_ns) } },
1172 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1173 * just RAZ for all cores:
1175 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1176 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1177 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1178 /* Auxiliary fault status registers: these also are IMPDEF, and we
1179 * choose to RAZ/WI for all cores.
1181 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1182 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1183 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1184 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1185 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1186 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1187 /* MAIR can just read-as-written because we don't implement caches
1188 * and so don't need to care about memory attributes.
1190 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1191 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1192 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1193 .resetvalue = 0 },
1194 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1195 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1196 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1197 .resetvalue = 0 },
1198 /* For non-long-descriptor page tables these are PRRR and NMRR;
1199 * regardless they still act as reads-as-written for QEMU.
1201 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1202 * allows them to assign the correct fieldoffset based on the endianness
1203 * handled in the field definitions.
1205 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1206 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1207 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1208 offsetof(CPUARMState, cp15.mair0_ns) },
1209 .resetfn = arm_cp_reset_ignore },
1210 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1211 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1212 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1213 offsetof(CPUARMState, cp15.mair1_ns) },
1214 .resetfn = arm_cp_reset_ignore },
1215 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1216 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1217 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1218 /* 32 bit ITLB invalidates */
1219 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1220 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1221 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1222 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1223 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1224 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1225 /* 32 bit DTLB invalidates */
1226 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1227 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1228 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1229 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1230 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1231 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1232 /* 32 bit TLB invalidates */
1233 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1234 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1235 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1236 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1237 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1238 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1239 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1240 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1241 REGINFO_SENTINEL
1244 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1245 /* 32 bit TLB invalidates, Inner Shareable */
1246 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1247 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1248 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1249 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1250 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1251 .type = ARM_CP_NO_RAW, .access = PL1_W,
1252 .writefn = tlbiasid_is_write },
1253 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1254 .type = ARM_CP_NO_RAW, .access = PL1_W,
1255 .writefn = tlbimvaa_is_write },
1256 REGINFO_SENTINEL
1259 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1260 uint64_t value)
1262 value &= 1;
1263 env->teecr = value;
1266 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1267 bool isread)
1269 if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1270 return CP_ACCESS_TRAP;
1272 return CP_ACCESS_OK;
1275 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1276 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1277 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1278 .resetvalue = 0,
1279 .writefn = teecr_write },
1280 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1281 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1282 .accessfn = teehbr_access, .resetvalue = 0 },
1283 REGINFO_SENTINEL
1286 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1287 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1288 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1289 .access = PL0_RW,
1290 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1291 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1292 .access = PL0_RW,
1293 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1294 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1295 .resetfn = arm_cp_reset_ignore },
1296 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1297 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1298 .access = PL0_R|PL1_W,
1299 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1300 .resetvalue = 0},
1301 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1302 .access = PL0_R|PL1_W,
1303 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1304 offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1305 .resetfn = arm_cp_reset_ignore },
1306 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1307 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1308 .access = PL1_RW,
1309 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1310 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1311 .access = PL1_RW,
1312 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1313 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1314 .resetvalue = 0 },
1315 REGINFO_SENTINEL
1318 #ifndef CONFIG_USER_ONLY
1320 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
1321 bool isread)
1323 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1324 * Writable only at the highest implemented exception level.
1326 int el = arm_current_el(env);
1328 switch (el) {
1329 case 0:
1330 if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
1331 return CP_ACCESS_TRAP;
1333 break;
1334 case 1:
1335 if (!isread && ri->state == ARM_CP_STATE_AA32 &&
1336 arm_is_secure_below_el3(env)) {
1337 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1338 return CP_ACCESS_TRAP_UNCATEGORIZED;
1340 break;
1341 case 2:
1342 case 3:
1343 break;
1346 if (!isread && el < arm_highest_el(env)) {
1347 return CP_ACCESS_TRAP_UNCATEGORIZED;
1350 return CP_ACCESS_OK;
1353 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
1354 bool isread)
1356 unsigned int cur_el = arm_current_el(env);
1357 bool secure = arm_is_secure(env);
1359 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1360 if (cur_el == 0 &&
1361 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1362 return CP_ACCESS_TRAP;
1365 if (arm_feature(env, ARM_FEATURE_EL2) &&
1366 timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1367 !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1368 return CP_ACCESS_TRAP_EL2;
1370 return CP_ACCESS_OK;
1373 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
1374 bool isread)
1376 unsigned int cur_el = arm_current_el(env);
1377 bool secure = arm_is_secure(env);
1379 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1380 * EL0[PV]TEN is zero.
1382 if (cur_el == 0 &&
1383 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1384 return CP_ACCESS_TRAP;
1387 if (arm_feature(env, ARM_FEATURE_EL2) &&
1388 timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1389 !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1390 return CP_ACCESS_TRAP_EL2;
1392 return CP_ACCESS_OK;
1395 static CPAccessResult gt_pct_access(CPUARMState *env,
1396 const ARMCPRegInfo *ri,
1397 bool isread)
1399 return gt_counter_access(env, GTIMER_PHYS, isread);
1402 static CPAccessResult gt_vct_access(CPUARMState *env,
1403 const ARMCPRegInfo *ri,
1404 bool isread)
1406 return gt_counter_access(env, GTIMER_VIRT, isread);
1409 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1410 bool isread)
1412 return gt_timer_access(env, GTIMER_PHYS, isread);
1415 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1416 bool isread)
1418 return gt_timer_access(env, GTIMER_VIRT, isread);
1421 static CPAccessResult gt_stimer_access(CPUARMState *env,
1422 const ARMCPRegInfo *ri,
1423 bool isread)
1425 /* The AArch64 register view of the secure physical timer is
1426 * always accessible from EL3, and configurably accessible from
1427 * Secure EL1.
1429 switch (arm_current_el(env)) {
1430 case 1:
1431 if (!arm_is_secure(env)) {
1432 return CP_ACCESS_TRAP;
1434 if (!(env->cp15.scr_el3 & SCR_ST)) {
1435 return CP_ACCESS_TRAP_EL3;
1437 return CP_ACCESS_OK;
1438 case 0:
1439 case 2:
1440 return CP_ACCESS_TRAP;
1441 case 3:
1442 return CP_ACCESS_OK;
1443 default:
1444 g_assert_not_reached();
1448 static uint64_t gt_get_countervalue(CPUARMState *env)
1450 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1453 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1455 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1457 if (gt->ctl & 1) {
1458 /* Timer enabled: calculate and set current ISTATUS, irq, and
1459 * reset timer to when ISTATUS next has to change
1461 uint64_t offset = timeridx == GTIMER_VIRT ?
1462 cpu->env.cp15.cntvoff_el2 : 0;
1463 uint64_t count = gt_get_countervalue(&cpu->env);
1464 /* Note that this must be unsigned 64 bit arithmetic: */
1465 int istatus = count - offset >= gt->cval;
1466 uint64_t nexttick;
1468 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1469 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1470 (istatus && !(gt->ctl & 2)));
1471 if (istatus) {
1472 /* Next transition is when count rolls back over to zero */
1473 nexttick = UINT64_MAX;
1474 } else {
1475 /* Next transition is when we hit cval */
1476 nexttick = gt->cval + offset;
1478 /* Note that the desired next expiry time might be beyond the
1479 * signed-64-bit range of a QEMUTimer -- in this case we just
1480 * set the timer for as far in the future as possible. When the
1481 * timer expires we will reset the timer for any remaining period.
1483 if (nexttick > INT64_MAX / GTIMER_SCALE) {
1484 nexttick = INT64_MAX / GTIMER_SCALE;
1486 timer_mod(cpu->gt_timer[timeridx], nexttick);
1487 } else {
1488 /* Timer disabled: ISTATUS and timer output always clear */
1489 gt->ctl &= ~4;
1490 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1491 timer_del(cpu->gt_timer[timeridx]);
1495 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1496 int timeridx)
1498 ARMCPU *cpu = arm_env_get_cpu(env);
1500 timer_del(cpu->gt_timer[timeridx]);
1503 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1505 return gt_get_countervalue(env);
1508 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1510 return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1513 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1514 int timeridx,
1515 uint64_t value)
1517 env->cp15.c14_timer[timeridx].cval = value;
1518 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1521 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1522 int timeridx)
1524 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1526 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1527 (gt_get_countervalue(env) - offset));
1530 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1531 int timeridx,
1532 uint64_t value)
1534 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1536 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1537 sextract64(value, 0, 32);
1538 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1541 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1542 int timeridx,
1543 uint64_t value)
1545 ARMCPU *cpu = arm_env_get_cpu(env);
1546 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1548 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1549 if ((oldval ^ value) & 1) {
1550 /* Enable toggled */
1551 gt_recalc_timer(cpu, timeridx);
1552 } else if ((oldval ^ value) & 2) {
1553 /* IMASK toggled: don't need to recalculate,
1554 * just set the interrupt line based on ISTATUS
1556 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1557 (oldval & 4) && !(value & 2));
1561 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1563 gt_timer_reset(env, ri, GTIMER_PHYS);
1566 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1567 uint64_t value)
1569 gt_cval_write(env, ri, GTIMER_PHYS, value);
1572 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1574 return gt_tval_read(env, ri, GTIMER_PHYS);
1577 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1578 uint64_t value)
1580 gt_tval_write(env, ri, GTIMER_PHYS, value);
1583 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1584 uint64_t value)
1586 gt_ctl_write(env, ri, GTIMER_PHYS, value);
1589 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1591 gt_timer_reset(env, ri, GTIMER_VIRT);
1594 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1595 uint64_t value)
1597 gt_cval_write(env, ri, GTIMER_VIRT, value);
1600 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1602 return gt_tval_read(env, ri, GTIMER_VIRT);
1605 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1606 uint64_t value)
1608 gt_tval_write(env, ri, GTIMER_VIRT, value);
1611 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1612 uint64_t value)
1614 gt_ctl_write(env, ri, GTIMER_VIRT, value);
1617 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1618 uint64_t value)
1620 ARMCPU *cpu = arm_env_get_cpu(env);
1622 raw_write(env, ri, value);
1623 gt_recalc_timer(cpu, GTIMER_VIRT);
1626 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1628 gt_timer_reset(env, ri, GTIMER_HYP);
1631 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1632 uint64_t value)
1634 gt_cval_write(env, ri, GTIMER_HYP, value);
1637 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1639 return gt_tval_read(env, ri, GTIMER_HYP);
1642 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1643 uint64_t value)
1645 gt_tval_write(env, ri, GTIMER_HYP, value);
1648 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1649 uint64_t value)
1651 gt_ctl_write(env, ri, GTIMER_HYP, value);
1654 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1656 gt_timer_reset(env, ri, GTIMER_SEC);
1659 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1660 uint64_t value)
1662 gt_cval_write(env, ri, GTIMER_SEC, value);
1665 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1667 return gt_tval_read(env, ri, GTIMER_SEC);
1670 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1671 uint64_t value)
1673 gt_tval_write(env, ri, GTIMER_SEC, value);
1676 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1677 uint64_t value)
1679 gt_ctl_write(env, ri, GTIMER_SEC, value);
1682 void arm_gt_ptimer_cb(void *opaque)
1684 ARMCPU *cpu = opaque;
1686 gt_recalc_timer(cpu, GTIMER_PHYS);
1689 void arm_gt_vtimer_cb(void *opaque)
1691 ARMCPU *cpu = opaque;
1693 gt_recalc_timer(cpu, GTIMER_VIRT);
1696 void arm_gt_htimer_cb(void *opaque)
1698 ARMCPU *cpu = opaque;
1700 gt_recalc_timer(cpu, GTIMER_HYP);
1703 void arm_gt_stimer_cb(void *opaque)
1705 ARMCPU *cpu = opaque;
1707 gt_recalc_timer(cpu, GTIMER_SEC);
1710 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1711 /* Note that CNTFRQ is purely reads-as-written for the benefit
1712 * of software; writing it doesn't actually change the timer frequency.
1713 * Our reset value matches the fixed frequency we implement the timer at.
1715 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1716 .type = ARM_CP_ALIAS,
1717 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1718 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1720 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1721 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1722 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1723 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1724 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1726 /* overall control: mostly access permissions */
1727 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1728 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1729 .access = PL1_RW,
1730 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1731 .resetvalue = 0,
1733 /* per-timer control */
1734 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1735 .secure = ARM_CP_SECSTATE_NS,
1736 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1737 .accessfn = gt_ptimer_access,
1738 .fieldoffset = offsetoflow32(CPUARMState,
1739 cp15.c14_timer[GTIMER_PHYS].ctl),
1740 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1742 { .name = "CNTP_CTL(S)",
1743 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1744 .secure = ARM_CP_SECSTATE_S,
1745 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1746 .accessfn = gt_ptimer_access,
1747 .fieldoffset = offsetoflow32(CPUARMState,
1748 cp15.c14_timer[GTIMER_SEC].ctl),
1749 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1751 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1752 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1753 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1754 .accessfn = gt_ptimer_access,
1755 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1756 .resetvalue = 0,
1757 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1759 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1760 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1761 .accessfn = gt_vtimer_access,
1762 .fieldoffset = offsetoflow32(CPUARMState,
1763 cp15.c14_timer[GTIMER_VIRT].ctl),
1764 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1766 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1767 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1768 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1769 .accessfn = gt_vtimer_access,
1770 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1771 .resetvalue = 0,
1772 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1774 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1775 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1776 .secure = ARM_CP_SECSTATE_NS,
1777 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1778 .accessfn = gt_ptimer_access,
1779 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1781 { .name = "CNTP_TVAL(S)",
1782 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1783 .secure = ARM_CP_SECSTATE_S,
1784 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1785 .accessfn = gt_ptimer_access,
1786 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1788 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1789 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1790 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1791 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1792 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1794 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1795 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1796 .accessfn = gt_vtimer_access,
1797 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1799 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1800 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1801 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1802 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1803 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1805 /* The counter itself */
1806 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1807 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1808 .accessfn = gt_pct_access,
1809 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1811 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1812 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1813 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1814 .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1816 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1817 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1818 .accessfn = gt_vct_access,
1819 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1821 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1822 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1823 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1824 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1826 /* Comparison value, indicating when the timer goes off */
1827 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1828 .secure = ARM_CP_SECSTATE_NS,
1829 .access = PL1_RW | PL0_R,
1830 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1831 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1832 .accessfn = gt_ptimer_access,
1833 .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1835 { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1836 .secure = ARM_CP_SECSTATE_S,
1837 .access = PL1_RW | PL0_R,
1838 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1839 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1840 .accessfn = gt_ptimer_access,
1841 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1843 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1844 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1845 .access = PL1_RW | PL0_R,
1846 .type = ARM_CP_IO,
1847 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1848 .resetvalue = 0, .accessfn = gt_ptimer_access,
1849 .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1851 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1852 .access = PL1_RW | PL0_R,
1853 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1854 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1855 .accessfn = gt_vtimer_access,
1856 .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1858 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1859 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1860 .access = PL1_RW | PL0_R,
1861 .type = ARM_CP_IO,
1862 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1863 .resetvalue = 0, .accessfn = gt_vtimer_access,
1864 .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1866 /* Secure timer -- this is actually restricted to only EL3
1867 * and configurably Secure-EL1 via the accessfn.
1869 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1870 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1871 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1872 .accessfn = gt_stimer_access,
1873 .readfn = gt_sec_tval_read,
1874 .writefn = gt_sec_tval_write,
1875 .resetfn = gt_sec_timer_reset,
1877 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1878 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1879 .type = ARM_CP_IO, .access = PL1_RW,
1880 .accessfn = gt_stimer_access,
1881 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1882 .resetvalue = 0,
1883 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1885 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1886 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1887 .type = ARM_CP_IO, .access = PL1_RW,
1888 .accessfn = gt_stimer_access,
1889 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1890 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1892 REGINFO_SENTINEL
1895 #else
1896 /* In user-mode none of the generic timer registers are accessible,
1897 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1898 * so instead just don't register any of them.
1900 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1901 REGINFO_SENTINEL
1904 #endif
1906 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1908 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1909 raw_write(env, ri, value);
1910 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1911 raw_write(env, ri, value & 0xfffff6ff);
1912 } else {
1913 raw_write(env, ri, value & 0xfffff1ff);
1917 #ifndef CONFIG_USER_ONLY
1918 /* get_phys_addr() isn't present for user-mode-only targets */
1920 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
1921 bool isread)
1923 if (ri->opc2 & 4) {
1924 /* The ATS12NSO* operations must trap to EL3 if executed in
1925 * Secure EL1 (which can only happen if EL3 is AArch64).
1926 * They are simply UNDEF if executed from NS EL1.
1927 * They function normally from EL2 or EL3.
1929 if (arm_current_el(env) == 1) {
1930 if (arm_is_secure_below_el3(env)) {
1931 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1933 return CP_ACCESS_TRAP_UNCATEGORIZED;
1936 return CP_ACCESS_OK;
1939 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1940 int access_type, ARMMMUIdx mmu_idx)
1942 hwaddr phys_addr;
1943 target_ulong page_size;
1944 int prot;
1945 uint32_t fsr;
1946 bool ret;
1947 uint64_t par64;
1948 MemTxAttrs attrs = {};
1949 ARMMMUFaultInfo fi = {};
1951 ret = get_phys_addr(env, value, access_type, mmu_idx,
1952 &phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
1953 if (extended_addresses_enabled(env)) {
1954 /* fsr is a DFSR/IFSR value for the long descriptor
1955 * translation table format, but with WnR always clear.
1956 * Convert it to a 64-bit PAR.
1958 par64 = (1 << 11); /* LPAE bit always set */
1959 if (!ret) {
1960 par64 |= phys_addr & ~0xfffULL;
1961 if (!attrs.secure) {
1962 par64 |= (1 << 9); /* NS */
1964 /* We don't set the ATTR or SH fields in the PAR. */
1965 } else {
1966 par64 |= 1; /* F */
1967 par64 |= (fsr & 0x3f) << 1; /* FS */
1968 /* Note that S2WLK and FSTAGE are always zero, because we don't
1969 * implement virtualization and therefore there can't be a stage 2
1970 * fault.
1973 } else {
1974 /* fsr is a DFSR/IFSR value for the short descriptor
1975 * translation table format (with WnR always clear).
1976 * Convert it to a 32-bit PAR.
1978 if (!ret) {
1979 /* We do not set any attribute bits in the PAR */
1980 if (page_size == (1 << 24)
1981 && arm_feature(env, ARM_FEATURE_V7)) {
1982 par64 = (phys_addr & 0xff000000) | (1 << 1);
1983 } else {
1984 par64 = phys_addr & 0xfffff000;
1986 if (!attrs.secure) {
1987 par64 |= (1 << 9); /* NS */
1989 } else {
1990 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1991 ((fsr & 0xf) << 1) | 1;
1994 return par64;
1997 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1999 int access_type = ri->opc2 & 1;
2000 uint64_t par64;
2001 ARMMMUIdx mmu_idx;
2002 int el = arm_current_el(env);
2003 bool secure = arm_is_secure_below_el3(env);
2005 switch (ri->opc2 & 6) {
2006 case 0:
2007 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2008 switch (el) {
2009 case 3:
2010 mmu_idx = ARMMMUIdx_S1E3;
2011 break;
2012 case 2:
2013 mmu_idx = ARMMMUIdx_S1NSE1;
2014 break;
2015 case 1:
2016 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2017 break;
2018 default:
2019 g_assert_not_reached();
2021 break;
2022 case 2:
2023 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2024 switch (el) {
2025 case 3:
2026 mmu_idx = ARMMMUIdx_S1SE0;
2027 break;
2028 case 2:
2029 mmu_idx = ARMMMUIdx_S1NSE0;
2030 break;
2031 case 1:
2032 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2033 break;
2034 default:
2035 g_assert_not_reached();
2037 break;
2038 case 4:
2039 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2040 mmu_idx = ARMMMUIdx_S12NSE1;
2041 break;
2042 case 6:
2043 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2044 mmu_idx = ARMMMUIdx_S12NSE0;
2045 break;
2046 default:
2047 g_assert_not_reached();
2050 par64 = do_ats_write(env, value, access_type, mmu_idx);
2052 A32_BANKED_CURRENT_REG_SET(env, par, par64);
2055 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
2056 uint64_t value)
2058 int access_type = ri->opc2 & 1;
2059 uint64_t par64;
2061 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
2063 A32_BANKED_CURRENT_REG_SET(env, par, par64);
2066 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
2067 bool isread)
2069 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
2070 return CP_ACCESS_TRAP;
2072 return CP_ACCESS_OK;
2075 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
2076 uint64_t value)
2078 int access_type = ri->opc2 & 1;
2079 ARMMMUIdx mmu_idx;
2080 int secure = arm_is_secure_below_el3(env);
2082 switch (ri->opc2 & 6) {
2083 case 0:
2084 switch (ri->opc1) {
2085 case 0: /* AT S1E1R, AT S1E1W */
2086 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2087 break;
2088 case 4: /* AT S1E2R, AT S1E2W */
2089 mmu_idx = ARMMMUIdx_S1E2;
2090 break;
2091 case 6: /* AT S1E3R, AT S1E3W */
2092 mmu_idx = ARMMMUIdx_S1E3;
2093 break;
2094 default:
2095 g_assert_not_reached();
2097 break;
2098 case 2: /* AT S1E0R, AT S1E0W */
2099 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2100 break;
2101 case 4: /* AT S12E1R, AT S12E1W */
2102 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
2103 break;
2104 case 6: /* AT S12E0R, AT S12E0W */
2105 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
2106 break;
2107 default:
2108 g_assert_not_reached();
2111 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
2113 #endif
2115 static const ARMCPRegInfo vapa_cp_reginfo[] = {
2116 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
2117 .access = PL1_RW, .resetvalue = 0,
2118 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
2119 offsetoflow32(CPUARMState, cp15.par_ns) },
2120 .writefn = par_write },
2121 #ifndef CONFIG_USER_ONLY
2122 /* This underdecoding is safe because the reginfo is NO_RAW. */
2123 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
2124 .access = PL1_W, .accessfn = ats_access,
2125 .writefn = ats_write, .type = ARM_CP_NO_RAW },
2126 #endif
2127 REGINFO_SENTINEL
2130 /* Return basic MPU access permission bits. */
2131 static uint32_t simple_mpu_ap_bits(uint32_t val)
2133 uint32_t ret;
2134 uint32_t mask;
2135 int i;
2136 ret = 0;
2137 mask = 3;
2138 for (i = 0; i < 16; i += 2) {
2139 ret |= (val >> i) & mask;
2140 mask <<= 2;
2142 return ret;
2145 /* Pad basic MPU access permission bits to extended format. */
2146 static uint32_t extended_mpu_ap_bits(uint32_t val)
2148 uint32_t ret;
2149 uint32_t mask;
2150 int i;
2151 ret = 0;
2152 mask = 3;
2153 for (i = 0; i < 16; i += 2) {
2154 ret |= (val & mask) << i;
2155 mask <<= 2;
2157 return ret;
2160 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2161 uint64_t value)
2163 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2166 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2168 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2171 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2172 uint64_t value)
2174 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2177 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2179 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2182 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2184 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2186 if (!u32p) {
2187 return 0;
2190 u32p += env->cp15.c6_rgnr;
2191 return *u32p;
2194 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2195 uint64_t value)
2197 ARMCPU *cpu = arm_env_get_cpu(env);
2198 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2200 if (!u32p) {
2201 return;
2204 u32p += env->cp15.c6_rgnr;
2205 tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2206 *u32p = value;
2209 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2211 ARMCPU *cpu = arm_env_get_cpu(env);
2212 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2214 if (!u32p) {
2215 return;
2218 memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2221 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2222 uint64_t value)
2224 ARMCPU *cpu = arm_env_get_cpu(env);
2225 uint32_t nrgs = cpu->pmsav7_dregion;
2227 if (value >= nrgs) {
2228 qemu_log_mask(LOG_GUEST_ERROR,
2229 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2230 " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2231 return;
2234 raw_write(env, ri, value);
2237 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2238 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2239 .access = PL1_RW, .type = ARM_CP_NO_RAW,
2240 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2241 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2242 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2243 .access = PL1_RW, .type = ARM_CP_NO_RAW,
2244 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2245 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2246 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2247 .access = PL1_RW, .type = ARM_CP_NO_RAW,
2248 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2249 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2250 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2251 .access = PL1_RW,
2252 .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2253 .writefn = pmsav7_rgnr_write },
2254 REGINFO_SENTINEL
2257 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2258 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2259 .access = PL1_RW, .type = ARM_CP_ALIAS,
2260 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2261 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2262 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2263 .access = PL1_RW, .type = ARM_CP_ALIAS,
2264 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2265 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2266 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2267 .access = PL1_RW,
2268 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2269 .resetvalue = 0, },
2270 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2271 .access = PL1_RW,
2272 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2273 .resetvalue = 0, },
2274 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2275 .access = PL1_RW,
2276 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2277 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2278 .access = PL1_RW,
2279 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2280 /* Protection region base and size registers */
2281 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2282 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2283 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2284 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2285 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2286 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2287 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2288 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2289 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2290 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2291 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2292 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2293 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2294 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2295 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2296 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2297 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2298 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2299 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2300 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2301 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2302 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2303 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2304 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2305 REGINFO_SENTINEL
2308 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2309 uint64_t value)
2311 TCR *tcr = raw_ptr(env, ri);
2312 int maskshift = extract32(value, 0, 3);
2314 if (!arm_feature(env, ARM_FEATURE_V8)) {
2315 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2316 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2317 * using Long-desciptor translation table format */
2318 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2319 } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2320 /* In an implementation that includes the Security Extensions
2321 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2322 * Short-descriptor translation table format.
2324 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2325 } else {
2326 value &= TTBCR_N;
2330 /* Update the masks corresponding to the TCR bank being written
2331 * Note that we always calculate mask and base_mask, but
2332 * they are only used for short-descriptor tables (ie if EAE is 0);
2333 * for long-descriptor tables the TCR fields are used differently
2334 * and the mask and base_mask values are meaningless.
2336 tcr->raw_tcr = value;
2337 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2338 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2341 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2342 uint64_t value)
2344 ARMCPU *cpu = arm_env_get_cpu(env);
2346 if (arm_feature(env, ARM_FEATURE_LPAE)) {
2347 /* With LPAE the TTBCR could result in a change of ASID
2348 * via the TTBCR.A1 bit, so do a TLB flush.
2350 tlb_flush(CPU(cpu), 1);
2352 vmsa_ttbcr_raw_write(env, ri, value);
2355 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2357 TCR *tcr = raw_ptr(env, ri);
2359 /* Reset both the TCR as well as the masks corresponding to the bank of
2360 * the TCR being reset.
2362 tcr->raw_tcr = 0;
2363 tcr->mask = 0;
2364 tcr->base_mask = 0xffffc000u;
2367 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2368 uint64_t value)
2370 ARMCPU *cpu = arm_env_get_cpu(env);
2371 TCR *tcr = raw_ptr(env, ri);
2373 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2374 tlb_flush(CPU(cpu), 1);
2375 tcr->raw_tcr = value;
2378 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2379 uint64_t value)
2381 /* 64 bit accesses to the TTBRs can change the ASID and so we
2382 * must flush the TLB.
2384 if (cpreg_field_is_64bit(ri)) {
2385 ARMCPU *cpu = arm_env_get_cpu(env);
2387 tlb_flush(CPU(cpu), 1);
2389 raw_write(env, ri, value);
2392 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2393 uint64_t value)
2395 ARMCPU *cpu = arm_env_get_cpu(env);
2396 CPUState *cs = CPU(cpu);
2398 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2399 if (raw_read(env, ri) != value) {
2400 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2401 ARMMMUIdx_S2NS, -1);
2402 raw_write(env, ri, value);
2406 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2407 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2408 .access = PL1_RW, .type = ARM_CP_ALIAS,
2409 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2410 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2411 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2412 .access = PL1_RW, .resetvalue = 0,
2413 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2414 offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2415 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2416 .access = PL1_RW, .resetvalue = 0,
2417 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2418 offsetof(CPUARMState, cp15.dfar_ns) } },
2419 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2420 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2421 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2422 .resetvalue = 0, },
2423 REGINFO_SENTINEL
2426 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2427 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2428 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2429 .access = PL1_RW,
2430 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2431 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2432 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2433 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2434 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2435 offsetof(CPUARMState, cp15.ttbr0_ns) } },
2436 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2437 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2438 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2439 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2440 offsetof(CPUARMState, cp15.ttbr1_ns) } },
2441 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2442 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2443 .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2444 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2445 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2446 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2447 .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2448 .raw_writefn = vmsa_ttbcr_raw_write,
2449 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2450 offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2451 REGINFO_SENTINEL
2454 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2455 uint64_t value)
2457 env->cp15.c15_ticonfig = value & 0xe7;
2458 /* The OS_TYPE bit in this register changes the reported CPUID! */
2459 env->cp15.c0_cpuid = (value & (1 << 5)) ?
2460 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2463 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2464 uint64_t value)
2466 env->cp15.c15_threadid = value & 0xffff;
2469 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2470 uint64_t value)
2472 /* Wait-for-interrupt (deprecated) */
2473 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2476 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2477 uint64_t value)
2479 /* On OMAP there are registers indicating the max/min index of dcache lines
2480 * containing a dirty line; cache flush operations have to reset these.
2482 env->cp15.c15_i_max = 0x000;
2483 env->cp15.c15_i_min = 0xff0;
2486 static const ARMCPRegInfo omap_cp_reginfo[] = {
2487 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2488 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2489 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2490 .resetvalue = 0, },
2491 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2492 .access = PL1_RW, .type = ARM_CP_NOP },
2493 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2494 .access = PL1_RW,
2495 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2496 .writefn = omap_ticonfig_write },
2497 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2498 .access = PL1_RW,
2499 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2500 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2501 .access = PL1_RW, .resetvalue = 0xff0,
2502 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2503 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2504 .access = PL1_RW,
2505 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2506 .writefn = omap_threadid_write },
2507 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2508 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2509 .type = ARM_CP_NO_RAW,
2510 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2511 /* TODO: Peripheral port remap register:
2512 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2513 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2514 * when MMU is off.
2516 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2517 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2518 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2519 .writefn = omap_cachemaint_write },
2520 { .name = "C9", .cp = 15, .crn = 9,
2521 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2522 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2523 REGINFO_SENTINEL
2526 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2527 uint64_t value)
2529 env->cp15.c15_cpar = value & 0x3fff;
2532 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2533 { .name = "XSCALE_CPAR",
2534 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2535 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2536 .writefn = xscale_cpar_write, },
2537 { .name = "XSCALE_AUXCR",
2538 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2539 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2540 .resetvalue = 0, },
2541 /* XScale specific cache-lockdown: since we have no cache we NOP these
2542 * and hope the guest does not really rely on cache behaviour.
2544 { .name = "XSCALE_LOCK_ICACHE_LINE",
2545 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2546 .access = PL1_W, .type = ARM_CP_NOP },
2547 { .name = "XSCALE_UNLOCK_ICACHE",
2548 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2549 .access = PL1_W, .type = ARM_CP_NOP },
2550 { .name = "XSCALE_DCACHE_LOCK",
2551 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2552 .access = PL1_RW, .type = ARM_CP_NOP },
2553 { .name = "XSCALE_UNLOCK_DCACHE",
2554 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2555 .access = PL1_W, .type = ARM_CP_NOP },
2556 REGINFO_SENTINEL
2559 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2560 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2561 * implementation of this implementation-defined space.
2562 * Ideally this should eventually disappear in favour of actually
2563 * implementing the correct behaviour for all cores.
2565 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2566 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2567 .access = PL1_RW,
2568 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2569 .resetvalue = 0 },
2570 REGINFO_SENTINEL
2573 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2574 /* Cache status: RAZ because we have no cache so it's always clean */
2575 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2576 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2577 .resetvalue = 0 },
2578 REGINFO_SENTINEL
2581 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2582 /* We never have a a block transfer operation in progress */
2583 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2584 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2585 .resetvalue = 0 },
2586 /* The cache ops themselves: these all NOP for QEMU */
2587 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2588 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2589 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2590 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2591 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2592 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2593 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2594 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2595 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2596 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2597 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2598 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2599 REGINFO_SENTINEL
2602 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2603 /* The cache test-and-clean instructions always return (1 << 30)
2604 * to indicate that there are no dirty cache lines.
2606 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2607 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2608 .resetvalue = (1 << 30) },
2609 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2610 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2611 .resetvalue = (1 << 30) },
2612 REGINFO_SENTINEL
2615 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2616 /* Ignore ReadBuffer accesses */
2617 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2618 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2619 .access = PL1_RW, .resetvalue = 0,
2620 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2621 REGINFO_SENTINEL
2624 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2626 ARMCPU *cpu = arm_env_get_cpu(env);
2627 unsigned int cur_el = arm_current_el(env);
2628 bool secure = arm_is_secure(env);
2630 if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2631 return env->cp15.vpidr_el2;
2633 return raw_read(env, ri);
2636 static uint64_t mpidr_read_val(CPUARMState *env)
2638 ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2639 uint64_t mpidr = cpu->mp_affinity;
2641 if (arm_feature(env, ARM_FEATURE_V7MP)) {
2642 mpidr |= (1U << 31);
2643 /* Cores which are uniprocessor (non-coherent)
2644 * but still implement the MP extensions set
2645 * bit 30. (For instance, Cortex-R5).
2647 if (cpu->mp_is_up) {
2648 mpidr |= (1u << 30);
2651 return mpidr;
2654 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2656 unsigned int cur_el = arm_current_el(env);
2657 bool secure = arm_is_secure(env);
2659 if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2660 return env->cp15.vmpidr_el2;
2662 return mpidr_read_val(env);
2665 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2666 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2667 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2668 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2669 REGINFO_SENTINEL
2672 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2673 /* NOP AMAIR0/1 */
2674 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2675 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2676 .access = PL1_RW, .type = ARM_CP_CONST,
2677 .resetvalue = 0 },
2678 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2679 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2680 .access = PL1_RW, .type = ARM_CP_CONST,
2681 .resetvalue = 0 },
2682 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2683 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2684 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2685 offsetof(CPUARMState, cp15.par_ns)} },
2686 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2687 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2688 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2689 offsetof(CPUARMState, cp15.ttbr0_ns) },
2690 .writefn = vmsa_ttbr_write, },
2691 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2692 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2693 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2694 offsetof(CPUARMState, cp15.ttbr1_ns) },
2695 .writefn = vmsa_ttbr_write, },
2696 REGINFO_SENTINEL
2699 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2701 return vfp_get_fpcr(env);
2704 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2705 uint64_t value)
2707 vfp_set_fpcr(env, value);
2710 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2712 return vfp_get_fpsr(env);
2715 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2716 uint64_t value)
2718 vfp_set_fpsr(env, value);
2721 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
2722 bool isread)
2724 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2725 return CP_ACCESS_TRAP;
2727 return CP_ACCESS_OK;
2730 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2731 uint64_t value)
2733 env->daif = value & PSTATE_DAIF;
2736 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2737 const ARMCPRegInfo *ri,
2738 bool isread)
2740 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2741 * SCTLR_EL1.UCI is set.
2743 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2744 return CP_ACCESS_TRAP;
2746 return CP_ACCESS_OK;
2749 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2750 * Page D4-1736 (DDI0487A.b)
2753 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2754 uint64_t value)
2756 ARMCPU *cpu = arm_env_get_cpu(env);
2757 CPUState *cs = CPU(cpu);
2759 if (arm_is_secure_below_el3(env)) {
2760 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2761 } else {
2762 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2766 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2767 uint64_t value)
2769 bool sec = arm_is_secure_below_el3(env);
2770 CPUState *other_cs;
2772 CPU_FOREACH(other_cs) {
2773 if (sec) {
2774 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2775 } else {
2776 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2777 ARMMMUIdx_S12NSE0, -1);
2782 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2783 uint64_t value)
2785 /* Note that the 'ALL' scope must invalidate both stage 1 and
2786 * stage 2 translations, whereas most other scopes only invalidate
2787 * stage 1 translations.
2789 ARMCPU *cpu = arm_env_get_cpu(env);
2790 CPUState *cs = CPU(cpu);
2792 if (arm_is_secure_below_el3(env)) {
2793 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2794 } else {
2795 if (arm_feature(env, ARM_FEATURE_EL2)) {
2796 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2797 ARMMMUIdx_S2NS, -1);
2798 } else {
2799 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2804 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2805 uint64_t value)
2807 ARMCPU *cpu = arm_env_get_cpu(env);
2808 CPUState *cs = CPU(cpu);
2810 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2813 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2814 uint64_t value)
2816 ARMCPU *cpu = arm_env_get_cpu(env);
2817 CPUState *cs = CPU(cpu);
2819 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2822 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2823 uint64_t value)
2825 /* Note that the 'ALL' scope must invalidate both stage 1 and
2826 * stage 2 translations, whereas most other scopes only invalidate
2827 * stage 1 translations.
2829 bool sec = arm_is_secure_below_el3(env);
2830 bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2831 CPUState *other_cs;
2833 CPU_FOREACH(other_cs) {
2834 if (sec) {
2835 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2836 } else if (has_el2) {
2837 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2838 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2839 } else {
2840 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2841 ARMMMUIdx_S12NSE0, -1);
2846 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2847 uint64_t value)
2849 CPUState *other_cs;
2851 CPU_FOREACH(other_cs) {
2852 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2856 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2857 uint64_t value)
2859 CPUState *other_cs;
2861 CPU_FOREACH(other_cs) {
2862 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2866 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2867 uint64_t value)
2869 /* Invalidate by VA, EL1&0 (AArch64 version).
2870 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2871 * since we don't support flush-for-specific-ASID-only or
2872 * flush-last-level-only.
2874 ARMCPU *cpu = arm_env_get_cpu(env);
2875 CPUState *cs = CPU(cpu);
2876 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2878 if (arm_is_secure_below_el3(env)) {
2879 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2880 ARMMMUIdx_S1SE0, -1);
2881 } else {
2882 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2883 ARMMMUIdx_S12NSE0, -1);
2887 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2888 uint64_t value)
2890 /* Invalidate by VA, EL2
2891 * Currently handles both VAE2 and VALE2, since we don't support
2892 * flush-last-level-only.
2894 ARMCPU *cpu = arm_env_get_cpu(env);
2895 CPUState *cs = CPU(cpu);
2896 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2898 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2901 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2902 uint64_t value)
2904 /* Invalidate by VA, EL3
2905 * Currently handles both VAE3 and VALE3, since we don't support
2906 * flush-last-level-only.
2908 ARMCPU *cpu = arm_env_get_cpu(env);
2909 CPUState *cs = CPU(cpu);
2910 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2912 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2915 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2916 uint64_t value)
2918 bool sec = arm_is_secure_below_el3(env);
2919 CPUState *other_cs;
2920 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2922 CPU_FOREACH(other_cs) {
2923 if (sec) {
2924 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2925 ARMMMUIdx_S1SE0, -1);
2926 } else {
2927 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2928 ARMMMUIdx_S12NSE0, -1);
2933 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2934 uint64_t value)
2936 CPUState *other_cs;
2937 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2939 CPU_FOREACH(other_cs) {
2940 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2944 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2945 uint64_t value)
2947 CPUState *other_cs;
2948 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2950 CPU_FOREACH(other_cs) {
2951 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2955 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2956 uint64_t value)
2958 /* Invalidate by IPA. This has to invalidate any structures that
2959 * contain only stage 2 translation information, but does not need
2960 * to apply to structures that contain combined stage 1 and stage 2
2961 * translation information.
2962 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2964 ARMCPU *cpu = arm_env_get_cpu(env);
2965 CPUState *cs = CPU(cpu);
2966 uint64_t pageaddr;
2968 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2969 return;
2972 pageaddr = sextract64(value << 12, 0, 48);
2974 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2977 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2978 uint64_t value)
2980 CPUState *other_cs;
2981 uint64_t pageaddr;
2983 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2984 return;
2987 pageaddr = sextract64(value << 12, 0, 48);
2989 CPU_FOREACH(other_cs) {
2990 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2994 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
2995 bool isread)
2997 /* We don't implement EL2, so the only control on DC ZVA is the
2998 * bit in the SCTLR which can prohibit access for EL0.
3000 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
3001 return CP_ACCESS_TRAP;
3003 return CP_ACCESS_OK;
3006 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
3008 ARMCPU *cpu = arm_env_get_cpu(env);
3009 int dzp_bit = 1 << 4;
3011 /* DZP indicates whether DC ZVA access is allowed */
3012 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
3013 dzp_bit = 0;
3015 return cpu->dcz_blocksize | dzp_bit;
3018 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3019 bool isread)
3021 if (!(env->pstate & PSTATE_SP)) {
3022 /* Access to SP_EL0 is undefined if it's being used as
3023 * the stack pointer.
3025 return CP_ACCESS_TRAP_UNCATEGORIZED;
3027 return CP_ACCESS_OK;
3030 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
3032 return env->pstate & PSTATE_SP;
3035 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
3037 update_spsel(env, val);
3040 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3041 uint64_t value)
3043 ARMCPU *cpu = arm_env_get_cpu(env);
3045 if (raw_read(env, ri) == value) {
3046 /* Skip the TLB flush if nothing actually changed; Linux likes
3047 * to do a lot of pointless SCTLR writes.
3049 return;
3052 raw_write(env, ri, value);
3053 /* ??? Lots of these bits are not implemented. */
3054 /* This may enable/disable the MMU, so do a TLB flush. */
3055 tlb_flush(CPU(cpu), 1);
3058 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
3059 bool isread)
3061 if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
3062 return CP_ACCESS_TRAP_FP_EL2;
3064 if (env->cp15.cptr_el[3] & CPTR_TFP) {
3065 return CP_ACCESS_TRAP_FP_EL3;
3067 return CP_ACCESS_OK;
3070 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3071 uint64_t value)
3073 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
3076 static const ARMCPRegInfo v8_cp_reginfo[] = {
3077 /* Minimal set of EL0-visible registers. This will need to be expanded
3078 * significantly for system emulation of AArch64 CPUs.
3080 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
3081 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
3082 .access = PL0_RW, .type = ARM_CP_NZCV },
3083 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
3084 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
3085 .type = ARM_CP_NO_RAW,
3086 .access = PL0_RW, .accessfn = aa64_daif_access,
3087 .fieldoffset = offsetof(CPUARMState, daif),
3088 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
3089 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
3090 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
3091 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
3092 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
3093 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
3094 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
3095 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
3096 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
3097 .access = PL0_R, .type = ARM_CP_NO_RAW,
3098 .readfn = aa64_dczid_read },
3099 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
3100 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
3101 .access = PL0_W, .type = ARM_CP_DC_ZVA,
3102 #ifndef CONFIG_USER_ONLY
3103 /* Avoid overhead of an access check that always passes in user-mode */
3104 .accessfn = aa64_zva_access,
3105 #endif
3107 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
3108 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
3109 .access = PL1_R, .type = ARM_CP_CURRENTEL },
3110 /* Cache ops: all NOPs since we don't emulate caches */
3111 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
3112 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3113 .access = PL1_W, .type = ARM_CP_NOP },
3114 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
3115 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3116 .access = PL1_W, .type = ARM_CP_NOP },
3117 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
3118 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
3119 .access = PL0_W, .type = ARM_CP_NOP,
3120 .accessfn = aa64_cacheop_access },
3121 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
3122 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3123 .access = PL1_W, .type = ARM_CP_NOP },
3124 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
3125 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3126 .access = PL1_W, .type = ARM_CP_NOP },
3127 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
3128 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
3129 .access = PL0_W, .type = ARM_CP_NOP,
3130 .accessfn = aa64_cacheop_access },
3131 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
3132 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3133 .access = PL1_W, .type = ARM_CP_NOP },
3134 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
3135 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
3136 .access = PL0_W, .type = ARM_CP_NOP,
3137 .accessfn = aa64_cacheop_access },
3138 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
3139 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
3140 .access = PL0_W, .type = ARM_CP_NOP,
3141 .accessfn = aa64_cacheop_access },
3142 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
3143 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3144 .access = PL1_W, .type = ARM_CP_NOP },
3145 /* TLBI operations */
3146 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
3147 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
3148 .access = PL1_W, .type = ARM_CP_NO_RAW,
3149 .writefn = tlbi_aa64_vmalle1is_write },
3150 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
3151 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
3152 .access = PL1_W, .type = ARM_CP_NO_RAW,
3153 .writefn = tlbi_aa64_vae1is_write },
3154 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
3155 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
3156 .access = PL1_W, .type = ARM_CP_NO_RAW,
3157 .writefn = tlbi_aa64_vmalle1is_write },
3158 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
3159 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
3160 .access = PL1_W, .type = ARM_CP_NO_RAW,
3161 .writefn = tlbi_aa64_vae1is_write },
3162 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
3163 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3164 .access = PL1_W, .type = ARM_CP_NO_RAW,
3165 .writefn = tlbi_aa64_vae1is_write },
3166 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
3167 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3168 .access = PL1_W, .type = ARM_CP_NO_RAW,
3169 .writefn = tlbi_aa64_vae1is_write },
3170 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
3171 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
3172 .access = PL1_W, .type = ARM_CP_NO_RAW,
3173 .writefn = tlbi_aa64_vmalle1_write },
3174 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
3175 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
3176 .access = PL1_W, .type = ARM_CP_NO_RAW,
3177 .writefn = tlbi_aa64_vae1_write },
3178 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
3179 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
3180 .access = PL1_W, .type = ARM_CP_NO_RAW,
3181 .writefn = tlbi_aa64_vmalle1_write },
3182 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
3183 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3184 .access = PL1_W, .type = ARM_CP_NO_RAW,
3185 .writefn = tlbi_aa64_vae1_write },
3186 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3187 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3188 .access = PL1_W, .type = ARM_CP_NO_RAW,
3189 .writefn = tlbi_aa64_vae1_write },
3190 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3191 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3192 .access = PL1_W, .type = ARM_CP_NO_RAW,
3193 .writefn = tlbi_aa64_vae1_write },
3194 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3195 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3196 .access = PL2_W, .type = ARM_CP_NO_RAW,
3197 .writefn = tlbi_aa64_ipas2e1is_write },
3198 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3199 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3200 .access = PL2_W, .type = ARM_CP_NO_RAW,
3201 .writefn = tlbi_aa64_ipas2e1is_write },
3202 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3203 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3204 .access = PL2_W, .type = ARM_CP_NO_RAW,
3205 .writefn = tlbi_aa64_alle1is_write },
3206 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3207 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3208 .access = PL2_W, .type = ARM_CP_NO_RAW,
3209 .writefn = tlbi_aa64_alle1is_write },
3210 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3211 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3212 .access = PL2_W, .type = ARM_CP_NO_RAW,
3213 .writefn = tlbi_aa64_ipas2e1_write },
3214 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3215 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3216 .access = PL2_W, .type = ARM_CP_NO_RAW,
3217 .writefn = tlbi_aa64_ipas2e1_write },
3218 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3219 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3220 .access = PL2_W, .type = ARM_CP_NO_RAW,
3221 .writefn = tlbi_aa64_alle1_write },
3222 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3223 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3224 .access = PL2_W, .type = ARM_CP_NO_RAW,
3225 .writefn = tlbi_aa64_alle1is_write },
3226 #ifndef CONFIG_USER_ONLY
3227 /* 64 bit address translation operations */
3228 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3229 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3230 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3231 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3232 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3233 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3234 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3235 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3236 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3237 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3238 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3239 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3240 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3241 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3242 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3243 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3244 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3245 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3246 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3247 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3248 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3249 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3250 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3251 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3252 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3253 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3254 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3255 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3256 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3257 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3258 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3259 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3260 .type = ARM_CP_ALIAS,
3261 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3262 .access = PL1_RW, .resetvalue = 0,
3263 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3264 .writefn = par_write },
3265 #endif
3266 /* TLB invalidate last level of translation table walk */
3267 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3268 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3269 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3270 .type = ARM_CP_NO_RAW, .access = PL1_W,
3271 .writefn = tlbimvaa_is_write },
3272 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3273 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3274 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3275 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3276 /* 32 bit cache operations */
3277 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3278 .type = ARM_CP_NOP, .access = PL1_W },
3279 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3280 .type = ARM_CP_NOP, .access = PL1_W },
3281 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3282 .type = ARM_CP_NOP, .access = PL1_W },
3283 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3284 .type = ARM_CP_NOP, .access = PL1_W },
3285 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3286 .type = ARM_CP_NOP, .access = PL1_W },
3287 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3288 .type = ARM_CP_NOP, .access = PL1_W },
3289 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3290 .type = ARM_CP_NOP, .access = PL1_W },
3291 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3292 .type = ARM_CP_NOP, .access = PL1_W },
3293 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3294 .type = ARM_CP_NOP, .access = PL1_W },
3295 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3296 .type = ARM_CP_NOP, .access = PL1_W },
3297 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3298 .type = ARM_CP_NOP, .access = PL1_W },
3299 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3300 .type = ARM_CP_NOP, .access = PL1_W },
3301 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3302 .type = ARM_CP_NOP, .access = PL1_W },
3303 /* MMU Domain access control / MPU write buffer control */
3304 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3305 .access = PL1_RW, .resetvalue = 0,
3306 .writefn = dacr_write, .raw_writefn = raw_write,
3307 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3308 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3309 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3310 .type = ARM_CP_ALIAS,
3311 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3312 .access = PL1_RW,
3313 .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3314 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3315 .type = ARM_CP_ALIAS,
3316 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3317 .access = PL1_RW,
3318 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
3319 /* We rely on the access checks not allowing the guest to write to the
3320 * state field when SPSel indicates that it's being used as the stack
3321 * pointer.
3323 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3324 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3325 .access = PL1_RW, .accessfn = sp_el0_access,
3326 .type = ARM_CP_ALIAS,
3327 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3328 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3329 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3330 .access = PL2_RW, .type = ARM_CP_ALIAS,
3331 .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3332 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3333 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3334 .type = ARM_CP_NO_RAW,
3335 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3336 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
3337 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
3338 .type = ARM_CP_ALIAS,
3339 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
3340 .access = PL2_RW, .accessfn = fpexc32_access },
3341 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3342 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3343 .access = PL2_RW, .resetvalue = 0,
3344 .writefn = dacr_write, .raw_writefn = raw_write,
3345 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3346 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3347 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3348 .access = PL2_RW, .resetvalue = 0,
3349 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3350 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3351 .type = ARM_CP_ALIAS,
3352 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3353 .access = PL2_RW,
3354 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
3355 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3356 .type = ARM_CP_ALIAS,
3357 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3358 .access = PL2_RW,
3359 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
3360 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3361 .type = ARM_CP_ALIAS,
3362 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3363 .access = PL2_RW,
3364 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
3365 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3366 .type = ARM_CP_ALIAS,
3367 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3368 .access = PL2_RW,
3369 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
3370 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
3371 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
3372 .resetvalue = 0,
3373 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
3374 { .name = "SDCR", .type = ARM_CP_ALIAS,
3375 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
3376 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3377 .writefn = sdcr_write,
3378 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
3379 REGINFO_SENTINEL
3382 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3383 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3384 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3385 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3386 .access = PL2_RW,
3387 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3388 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3389 .type = ARM_CP_NO_RAW,
3390 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3391 .access = PL2_RW,
3392 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3393 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3394 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3395 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3396 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3397 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3398 .access = PL2_RW, .type = ARM_CP_CONST,
3399 .resetvalue = 0 },
3400 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3401 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3402 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3403 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3404 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3405 .access = PL2_RW, .type = ARM_CP_CONST,
3406 .resetvalue = 0 },
3407 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3408 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3409 .access = PL2_RW, .type = ARM_CP_CONST,
3410 .resetvalue = 0 },
3411 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3412 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3413 .access = PL2_RW, .type = ARM_CP_CONST,
3414 .resetvalue = 0 },
3415 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3416 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3417 .access = PL2_RW, .type = ARM_CP_CONST,
3418 .resetvalue = 0 },
3419 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3420 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3421 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3422 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3423 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3424 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3425 .type = ARM_CP_CONST, .resetvalue = 0 },
3426 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3427 .cp = 15, .opc1 = 6, .crm = 2,
3428 .access = PL2_RW, .accessfn = access_el3_aa32ns,
3429 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3430 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3431 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3432 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3433 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3434 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3435 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3436 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3437 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3438 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3439 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3440 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3441 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3442 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3443 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3444 .resetvalue = 0 },
3445 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3446 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3447 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3448 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3449 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3450 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3451 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3452 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3453 .resetvalue = 0 },
3454 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3455 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3456 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3457 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3458 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3459 .resetvalue = 0 },
3460 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3461 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3462 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3463 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3464 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3465 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3466 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3467 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3468 .access = PL2_RW, .accessfn = access_tda,
3469 .type = ARM_CP_CONST, .resetvalue = 0 },
3470 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3471 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3472 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3473 .type = ARM_CP_CONST, .resetvalue = 0 },
3474 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
3475 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
3476 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3477 REGINFO_SENTINEL
3480 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3482 ARMCPU *cpu = arm_env_get_cpu(env);
3483 uint64_t valid_mask = HCR_MASK;
3485 if (arm_feature(env, ARM_FEATURE_EL3)) {
3486 valid_mask &= ~HCR_HCD;
3487 } else {
3488 valid_mask &= ~HCR_TSC;
3491 /* Clear RES0 bits. */
3492 value &= valid_mask;
3494 /* These bits change the MMU setup:
3495 * HCR_VM enables stage 2 translation
3496 * HCR_PTW forbids certain page-table setups
3497 * HCR_DC Disables stage1 and enables stage2 translation
3499 if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3500 tlb_flush(CPU(cpu), 1);
3502 raw_write(env, ri, value);
3505 static const ARMCPRegInfo el2_cp_reginfo[] = {
3506 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3507 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3508 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3509 .writefn = hcr_write },
3510 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3511 .type = ARM_CP_ALIAS,
3512 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3513 .access = PL2_RW,
3514 .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3515 { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3516 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3517 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3518 { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3519 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3520 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3521 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3522 .type = ARM_CP_ALIAS,
3523 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3524 .access = PL2_RW,
3525 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
3526 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3527 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3528 .access = PL2_RW, .writefn = vbar_write,
3529 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3530 .resetvalue = 0 },
3531 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3532 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3533 .access = PL3_RW, .type = ARM_CP_ALIAS,
3534 .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3535 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3536 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3537 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3538 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3539 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3540 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3541 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3542 .resetvalue = 0 },
3543 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3544 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3545 .access = PL2_RW, .type = ARM_CP_ALIAS,
3546 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3547 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3548 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3549 .access = PL2_RW, .type = ARM_CP_CONST,
3550 .resetvalue = 0 },
3551 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3552 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3553 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3554 .access = PL2_RW, .type = ARM_CP_CONST,
3555 .resetvalue = 0 },
3556 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3557 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3558 .access = PL2_RW, .type = ARM_CP_CONST,
3559 .resetvalue = 0 },
3560 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3561 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3562 .access = PL2_RW, .type = ARM_CP_CONST,
3563 .resetvalue = 0 },
3564 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3565 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3566 .access = PL2_RW,
3567 /* no .writefn needed as this can't cause an ASID change;
3568 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3570 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3571 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3572 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3573 .type = ARM_CP_ALIAS,
3574 .access = PL2_RW, .accessfn = access_el3_aa32ns,
3575 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3576 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
3577 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3578 .access = PL2_RW,
3579 /* no .writefn needed as this can't cause an ASID change;
3580 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3582 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3583 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3584 .cp = 15, .opc1 = 6, .crm = 2,
3585 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3586 .access = PL2_RW, .accessfn = access_el3_aa32ns,
3587 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
3588 .writefn = vttbr_write },
3589 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3590 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3591 .access = PL2_RW, .writefn = vttbr_write,
3592 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
3593 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3594 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3595 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3596 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3597 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3598 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3599 .access = PL2_RW, .resetvalue = 0,
3600 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3601 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3602 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3603 .access = PL2_RW, .resetvalue = 0,
3604 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3605 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3606 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3607 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3608 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3609 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3610 .type = ARM_CP_NO_RAW, .access = PL2_W,
3611 .writefn = tlbi_aa64_alle2_write },
3612 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3613 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3614 .type = ARM_CP_NO_RAW, .access = PL2_W,
3615 .writefn = tlbi_aa64_vae2_write },
3616 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3617 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3618 .access = PL2_W, .type = ARM_CP_NO_RAW,
3619 .writefn = tlbi_aa64_vae2_write },
3620 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3621 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3622 .access = PL2_W, .type = ARM_CP_NO_RAW,
3623 .writefn = tlbi_aa64_alle2is_write },
3624 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3625 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3626 .type = ARM_CP_NO_RAW, .access = PL2_W,
3627 .writefn = tlbi_aa64_vae2is_write },
3628 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3629 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3630 .access = PL2_W, .type = ARM_CP_NO_RAW,
3631 .writefn = tlbi_aa64_vae2is_write },
3632 #ifndef CONFIG_USER_ONLY
3633 /* Unlike the other EL2-related AT operations, these must
3634 * UNDEF from EL3 if EL2 is not implemented, which is why we
3635 * define them here rather than with the rest of the AT ops.
3637 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3638 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3639 .access = PL2_W, .accessfn = at_s1e2_access,
3640 .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3641 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3642 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3643 .access = PL2_W, .accessfn = at_s1e2_access,
3644 .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3645 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3646 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3647 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3648 * to behave as if SCR.NS was 1.
3650 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3651 .access = PL2_W,
3652 .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3653 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3654 .access = PL2_W,
3655 .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3656 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3657 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3658 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3659 * reset values as IMPDEF. We choose to reset to 3 to comply with
3660 * both ARMv7 and ARMv8.
3662 .access = PL2_RW, .resetvalue = 3,
3663 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3664 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3665 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3666 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3667 .writefn = gt_cntvoff_write,
3668 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3669 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3670 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3671 .writefn = gt_cntvoff_write,
3672 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3673 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3674 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3675 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3676 .type = ARM_CP_IO, .access = PL2_RW,
3677 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3678 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3679 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3680 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3681 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3682 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3683 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3684 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
3685 .resetfn = gt_hyp_timer_reset,
3686 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3687 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3688 .type = ARM_CP_IO,
3689 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3690 .access = PL2_RW,
3691 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3692 .resetvalue = 0,
3693 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3694 #endif
3695 /* The only field of MDCR_EL2 that has a defined architectural reset value
3696 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3697 * don't impelment any PMU event counters, so using zero as a reset
3698 * value for MDCR_EL2 is okay
3700 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3701 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3702 .access = PL2_RW, .resetvalue = 0,
3703 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
3704 { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
3705 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3706 .access = PL2_RW, .accessfn = access_el3_aa32ns,
3707 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3708 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
3709 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3710 .access = PL2_RW,
3711 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3712 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
3713 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
3714 .access = PL2_RW,
3715 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
3716 REGINFO_SENTINEL
3719 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
3720 bool isread)
3722 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
3723 * At Secure EL1 it traps to EL3.
3725 if (arm_current_el(env) == 3) {
3726 return CP_ACCESS_OK;
3728 if (arm_is_secure_below_el3(env)) {
3729 return CP_ACCESS_TRAP_EL3;
3731 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
3732 if (isread) {
3733 return CP_ACCESS_OK;
3735 return CP_ACCESS_TRAP_UNCATEGORIZED;
3738 static const ARMCPRegInfo el3_cp_reginfo[] = {
3739 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3740 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3741 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3742 .resetvalue = 0, .writefn = scr_write },
3743 { .name = "SCR", .type = ARM_CP_ALIAS,
3744 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3745 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3746 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3747 .writefn = scr_write },
3748 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3749 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3750 .access = PL3_RW, .resetvalue = 0,
3751 .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3752 { .name = "SDER",
3753 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3754 .access = PL3_RW, .resetvalue = 0,
3755 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3756 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3757 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3758 .writefn = vbar_write, .resetvalue = 0,
3759 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3760 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3761 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3762 .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3763 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3764 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3765 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3766 .access = PL3_RW,
3767 /* no .writefn needed as this can't cause an ASID change;
3768 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3770 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3771 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3772 .type = ARM_CP_ALIAS,
3773 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3774 .access = PL3_RW,
3775 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3776 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3777 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3778 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3779 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3780 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3781 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3782 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3783 .type = ARM_CP_ALIAS,
3784 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3785 .access = PL3_RW,
3786 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
3787 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3788 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3789 .access = PL3_RW, .writefn = vbar_write,
3790 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3791 .resetvalue = 0 },
3792 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3793 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3794 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3795 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3796 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3797 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3798 .access = PL3_RW, .resetvalue = 0,
3799 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3800 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3801 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3802 .access = PL3_RW, .type = ARM_CP_CONST,
3803 .resetvalue = 0 },
3804 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3805 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3806 .access = PL3_RW, .type = ARM_CP_CONST,
3807 .resetvalue = 0 },
3808 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3809 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3810 .access = PL3_RW, .type = ARM_CP_CONST,
3811 .resetvalue = 0 },
3812 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3813 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3814 .access = PL3_W, .type = ARM_CP_NO_RAW,
3815 .writefn = tlbi_aa64_alle3is_write },
3816 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3817 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3818 .access = PL3_W, .type = ARM_CP_NO_RAW,
3819 .writefn = tlbi_aa64_vae3is_write },
3820 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3821 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3822 .access = PL3_W, .type = ARM_CP_NO_RAW,
3823 .writefn = tlbi_aa64_vae3is_write },
3824 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3825 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3826 .access = PL3_W, .type = ARM_CP_NO_RAW,
3827 .writefn = tlbi_aa64_alle3_write },
3828 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3829 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3830 .access = PL3_W, .type = ARM_CP_NO_RAW,
3831 .writefn = tlbi_aa64_vae3_write },
3832 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3833 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3834 .access = PL3_W, .type = ARM_CP_NO_RAW,
3835 .writefn = tlbi_aa64_vae3_write },
3836 REGINFO_SENTINEL
3839 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3840 bool isread)
3842 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3843 * but the AArch32 CTR has its own reginfo struct)
3845 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3846 return CP_ACCESS_TRAP;
3848 return CP_ACCESS_OK;
3851 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
3852 uint64_t value)
3854 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
3855 * read via a bit in OSLSR_EL1.
3857 int oslock;
3859 if (ri->state == ARM_CP_STATE_AA32) {
3860 oslock = (value == 0xC5ACCE55);
3861 } else {
3862 oslock = value & 1;
3865 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
3868 static const ARMCPRegInfo debug_cp_reginfo[] = {
3869 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3870 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3871 * unlike DBGDRAR it is never accessible from EL0.
3872 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3873 * accessor.
3875 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3876 .access = PL0_R, .accessfn = access_tdra,
3877 .type = ARM_CP_CONST, .resetvalue = 0 },
3878 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3879 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3880 .access = PL1_R, .accessfn = access_tdra,
3881 .type = ARM_CP_CONST, .resetvalue = 0 },
3882 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3883 .access = PL0_R, .accessfn = access_tdra,
3884 .type = ARM_CP_CONST, .resetvalue = 0 },
3885 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3886 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3887 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3888 .access = PL1_RW, .accessfn = access_tda,
3889 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3890 .resetvalue = 0 },
3891 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3892 * We don't implement the configurable EL0 access.
3894 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3895 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3896 .type = ARM_CP_ALIAS,
3897 .access = PL1_R, .accessfn = access_tda,
3898 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3899 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3900 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3901 .access = PL1_W, .type = ARM_CP_NO_RAW,
3902 .accessfn = access_tdosa,
3903 .writefn = oslar_write },
3904 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
3905 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
3906 .access = PL1_R, .resetvalue = 10,
3907 .accessfn = access_tdosa,
3908 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
3909 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3910 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3911 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3912 .access = PL1_RW, .accessfn = access_tdosa,
3913 .type = ARM_CP_NOP },
3914 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3915 * implement vector catch debug events yet.
3917 { .name = "DBGVCR",
3918 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3919 .access = PL1_RW, .accessfn = access_tda,
3920 .type = ARM_CP_NOP },
3921 REGINFO_SENTINEL
3924 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3925 /* 64 bit access versions of the (dummy) debug registers */
3926 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3927 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3928 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3929 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3930 REGINFO_SENTINEL
3933 void hw_watchpoint_update(ARMCPU *cpu, int n)
3935 CPUARMState *env = &cpu->env;
3936 vaddr len = 0;
3937 vaddr wvr = env->cp15.dbgwvr[n];
3938 uint64_t wcr = env->cp15.dbgwcr[n];
3939 int mask;
3940 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3942 if (env->cpu_watchpoint[n]) {
3943 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3944 env->cpu_watchpoint[n] = NULL;
3947 if (!extract64(wcr, 0, 1)) {
3948 /* E bit clear : watchpoint disabled */
3949 return;
3952 switch (extract64(wcr, 3, 2)) {
3953 case 0:
3954 /* LSC 00 is reserved and must behave as if the wp is disabled */
3955 return;
3956 case 1:
3957 flags |= BP_MEM_READ;
3958 break;
3959 case 2:
3960 flags |= BP_MEM_WRITE;
3961 break;
3962 case 3:
3963 flags |= BP_MEM_ACCESS;
3964 break;
3967 /* Attempts to use both MASK and BAS fields simultaneously are
3968 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3969 * thus generating a watchpoint for every byte in the masked region.
3971 mask = extract64(wcr, 24, 4);
3972 if (mask == 1 || mask == 2) {
3973 /* Reserved values of MASK; we must act as if the mask value was
3974 * some non-reserved value, or as if the watchpoint were disabled.
3975 * We choose the latter.
3977 return;
3978 } else if (mask) {
3979 /* Watchpoint covers an aligned area up to 2GB in size */
3980 len = 1ULL << mask;
3981 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3982 * whether the watchpoint fires when the unmasked bits match; we opt
3983 * to generate the exceptions.
3985 wvr &= ~(len - 1);
3986 } else {
3987 /* Watchpoint covers bytes defined by the byte address select bits */
3988 int bas = extract64(wcr, 5, 8);
3989 int basstart;
3991 if (bas == 0) {
3992 /* This must act as if the watchpoint is disabled */
3993 return;
3996 if (extract64(wvr, 2, 1)) {
3997 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3998 * ignored, and BAS[3:0] define which bytes to watch.
4000 bas &= 0xf;
4002 /* The BAS bits are supposed to be programmed to indicate a contiguous
4003 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
4004 * we fire for each byte in the word/doubleword addressed by the WVR.
4005 * We choose to ignore any non-zero bits after the first range of 1s.
4007 basstart = ctz32(bas);
4008 len = cto32(bas >> basstart);
4009 wvr += basstart;
4012 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
4013 &env->cpu_watchpoint[n]);
4016 void hw_watchpoint_update_all(ARMCPU *cpu)
4018 int i;
4019 CPUARMState *env = &cpu->env;
4021 /* Completely clear out existing QEMU watchpoints and our array, to
4022 * avoid possible stale entries following migration load.
4024 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
4025 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
4027 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
4028 hw_watchpoint_update(cpu, i);
4032 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4033 uint64_t value)
4035 ARMCPU *cpu = arm_env_get_cpu(env);
4036 int i = ri->crm;
4038 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4039 * register reads and behaves as if values written are sign extended.
4040 * Bits [1:0] are RES0.
4042 value = sextract64(value, 0, 49) & ~3ULL;
4044 raw_write(env, ri, value);
4045 hw_watchpoint_update(cpu, i);
4048 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4049 uint64_t value)
4051 ARMCPU *cpu = arm_env_get_cpu(env);
4052 int i = ri->crm;
4054 raw_write(env, ri, value);
4055 hw_watchpoint_update(cpu, i);
4058 void hw_breakpoint_update(ARMCPU *cpu, int n)
4060 CPUARMState *env = &cpu->env;
4061 uint64_t bvr = env->cp15.dbgbvr[n];
4062 uint64_t bcr = env->cp15.dbgbcr[n];
4063 vaddr addr;
4064 int bt;
4065 int flags = BP_CPU;
4067 if (env->cpu_breakpoint[n]) {
4068 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
4069 env->cpu_breakpoint[n] = NULL;
4072 if (!extract64(bcr, 0, 1)) {
4073 /* E bit clear : watchpoint disabled */
4074 return;
4077 bt = extract64(bcr, 20, 4);
4079 switch (bt) {
4080 case 4: /* unlinked address mismatch (reserved if AArch64) */
4081 case 5: /* linked address mismatch (reserved if AArch64) */
4082 qemu_log_mask(LOG_UNIMP,
4083 "arm: address mismatch breakpoint types not implemented");
4084 return;
4085 case 0: /* unlinked address match */
4086 case 1: /* linked address match */
4088 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4089 * we behave as if the register was sign extended. Bits [1:0] are
4090 * RES0. The BAS field is used to allow setting breakpoints on 16
4091 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4092 * a bp will fire if the addresses covered by the bp and the addresses
4093 * covered by the insn overlap but the insn doesn't start at the
4094 * start of the bp address range. We choose to require the insn and
4095 * the bp to have the same address. The constraints on writing to
4096 * BAS enforced in dbgbcr_write mean we have only four cases:
4097 * 0b0000 => no breakpoint
4098 * 0b0011 => breakpoint on addr
4099 * 0b1100 => breakpoint on addr + 2
4100 * 0b1111 => breakpoint on addr
4101 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4103 int bas = extract64(bcr, 5, 4);
4104 addr = sextract64(bvr, 0, 49) & ~3ULL;
4105 if (bas == 0) {
4106 return;
4108 if (bas == 0xc) {
4109 addr += 2;
4111 break;
4113 case 2: /* unlinked context ID match */
4114 case 8: /* unlinked VMID match (reserved if no EL2) */
4115 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4116 qemu_log_mask(LOG_UNIMP,
4117 "arm: unlinked context breakpoint types not implemented");
4118 return;
4119 case 9: /* linked VMID match (reserved if no EL2) */
4120 case 11: /* linked context ID and VMID match (reserved if no EL2) */
4121 case 3: /* linked context ID match */
4122 default:
4123 /* We must generate no events for Linked context matches (unless
4124 * they are linked to by some other bp/wp, which is handled in
4125 * updates for the linking bp/wp). We choose to also generate no events
4126 * for reserved values.
4128 return;
4131 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
4134 void hw_breakpoint_update_all(ARMCPU *cpu)
4136 int i;
4137 CPUARMState *env = &cpu->env;
4139 /* Completely clear out existing QEMU breakpoints and our array, to
4140 * avoid possible stale entries following migration load.
4142 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
4143 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
4145 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
4146 hw_breakpoint_update(cpu, i);
4150 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4151 uint64_t value)
4153 ARMCPU *cpu = arm_env_get_cpu(env);
4154 int i = ri->crm;
4156 raw_write(env, ri, value);
4157 hw_breakpoint_update(cpu, i);
4160 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4161 uint64_t value)
4163 ARMCPU *cpu = arm_env_get_cpu(env);
4164 int i = ri->crm;
4166 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4167 * copy of BAS[0].
4169 value = deposit64(value, 6, 1, extract64(value, 5, 1));
4170 value = deposit64(value, 8, 1, extract64(value, 7, 1));
4172 raw_write(env, ri, value);
4173 hw_breakpoint_update(cpu, i);
4176 static void define_debug_regs(ARMCPU *cpu)
4178 /* Define v7 and v8 architectural debug registers.
4179 * These are just dummy implementations for now.
4181 int i;
4182 int wrps, brps, ctx_cmps;
4183 ARMCPRegInfo dbgdidr = {
4184 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
4185 .access = PL0_R, .accessfn = access_tda,
4186 .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
4189 /* Note that all these register fields hold "number of Xs minus 1". */
4190 brps = extract32(cpu->dbgdidr, 24, 4);
4191 wrps = extract32(cpu->dbgdidr, 28, 4);
4192 ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
4194 assert(ctx_cmps <= brps);
4196 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4197 * of the debug registers such as number of breakpoints;
4198 * check that if they both exist then they agree.
4200 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
4201 assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
4202 assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
4203 assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
4206 define_one_arm_cp_reg(cpu, &dbgdidr);
4207 define_arm_cp_regs(cpu, debug_cp_reginfo);
4209 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
4210 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
4213 for (i = 0; i < brps + 1; i++) {
4214 ARMCPRegInfo dbgregs[] = {
4215 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
4216 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
4217 .access = PL1_RW, .accessfn = access_tda,
4218 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
4219 .writefn = dbgbvr_write, .raw_writefn = raw_write
4221 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
4222 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
4223 .access = PL1_RW, .accessfn = access_tda,
4224 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
4225 .writefn = dbgbcr_write, .raw_writefn = raw_write
4227 REGINFO_SENTINEL
4229 define_arm_cp_regs(cpu, dbgregs);
4232 for (i = 0; i < wrps + 1; i++) {
4233 ARMCPRegInfo dbgregs[] = {
4234 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
4235 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
4236 .access = PL1_RW, .accessfn = access_tda,
4237 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
4238 .writefn = dbgwvr_write, .raw_writefn = raw_write
4240 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4241 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4242 .access = PL1_RW, .accessfn = access_tda,
4243 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4244 .writefn = dbgwcr_write, .raw_writefn = raw_write
4246 REGINFO_SENTINEL
4248 define_arm_cp_regs(cpu, dbgregs);
4252 void register_cp_regs_for_features(ARMCPU *cpu)
4254 /* Register all the coprocessor registers based on feature bits */
4255 CPUARMState *env = &cpu->env;
4256 if (arm_feature(env, ARM_FEATURE_M)) {
4257 /* M profile has no coprocessor registers */
4258 return;
4261 define_arm_cp_regs(cpu, cp_reginfo);
4262 if (!arm_feature(env, ARM_FEATURE_V8)) {
4263 /* Must go early as it is full of wildcards that may be
4264 * overridden by later definitions.
4266 define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4269 if (arm_feature(env, ARM_FEATURE_V6)) {
4270 /* The ID registers all have impdef reset values */
4271 ARMCPRegInfo v6_idregs[] = {
4272 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4273 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4274 .access = PL1_R, .type = ARM_CP_CONST,
4275 .resetvalue = cpu->id_pfr0 },
4276 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4277 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4278 .access = PL1_R, .type = ARM_CP_CONST,
4279 .resetvalue = cpu->id_pfr1 },
4280 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4281 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4282 .access = PL1_R, .type = ARM_CP_CONST,
4283 .resetvalue = cpu->id_dfr0 },
4284 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4285 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4286 .access = PL1_R, .type = ARM_CP_CONST,
4287 .resetvalue = cpu->id_afr0 },
4288 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4289 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4290 .access = PL1_R, .type = ARM_CP_CONST,
4291 .resetvalue = cpu->id_mmfr0 },
4292 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4293 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4294 .access = PL1_R, .type = ARM_CP_CONST,
4295 .resetvalue = cpu->id_mmfr1 },
4296 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4297 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4298 .access = PL1_R, .type = ARM_CP_CONST,
4299 .resetvalue = cpu->id_mmfr2 },
4300 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4301 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4302 .access = PL1_R, .type = ARM_CP_CONST,
4303 .resetvalue = cpu->id_mmfr3 },
4304 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4305 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4306 .access = PL1_R, .type = ARM_CP_CONST,
4307 .resetvalue = cpu->id_isar0 },
4308 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4309 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4310 .access = PL1_R, .type = ARM_CP_CONST,
4311 .resetvalue = cpu->id_isar1 },
4312 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4313 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4314 .access = PL1_R, .type = ARM_CP_CONST,
4315 .resetvalue = cpu->id_isar2 },
4316 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4317 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4318 .access = PL1_R, .type = ARM_CP_CONST,
4319 .resetvalue = cpu->id_isar3 },
4320 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4321 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4322 .access = PL1_R, .type = ARM_CP_CONST,
4323 .resetvalue = cpu->id_isar4 },
4324 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4325 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4326 .access = PL1_R, .type = ARM_CP_CONST,
4327 .resetvalue = cpu->id_isar5 },
4328 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
4329 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
4330 .access = PL1_R, .type = ARM_CP_CONST,
4331 .resetvalue = cpu->id_mmfr4 },
4332 /* 7 is as yet unallocated and must RAZ */
4333 { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH,
4334 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
4335 .access = PL1_R, .type = ARM_CP_CONST,
4336 .resetvalue = 0 },
4337 REGINFO_SENTINEL
4339 define_arm_cp_regs(cpu, v6_idregs);
4340 define_arm_cp_regs(cpu, v6_cp_reginfo);
4341 } else {
4342 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4344 if (arm_feature(env, ARM_FEATURE_V6K)) {
4345 define_arm_cp_regs(cpu, v6k_cp_reginfo);
4347 if (arm_feature(env, ARM_FEATURE_V7MP) &&
4348 !arm_feature(env, ARM_FEATURE_MPU)) {
4349 define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4351 if (arm_feature(env, ARM_FEATURE_V7)) {
4352 /* v7 performance monitor control register: same implementor
4353 * field as main ID register, and we implement only the cycle
4354 * count register.
4356 #ifndef CONFIG_USER_ONLY
4357 ARMCPRegInfo pmcr = {
4358 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4359 .access = PL0_RW,
4360 .type = ARM_CP_IO | ARM_CP_ALIAS,
4361 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4362 .accessfn = pmreg_access, .writefn = pmcr_write,
4363 .raw_writefn = raw_write,
4365 ARMCPRegInfo pmcr64 = {
4366 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
4367 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
4368 .access = PL0_RW, .accessfn = pmreg_access,
4369 .type = ARM_CP_IO,
4370 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
4371 .resetvalue = cpu->midr & 0xff000000,
4372 .writefn = pmcr_write, .raw_writefn = raw_write,
4374 define_one_arm_cp_reg(cpu, &pmcr);
4375 define_one_arm_cp_reg(cpu, &pmcr64);
4376 #endif
4377 ARMCPRegInfo clidr = {
4378 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
4379 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
4380 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
4382 define_one_arm_cp_reg(cpu, &clidr);
4383 define_arm_cp_regs(cpu, v7_cp_reginfo);
4384 define_debug_regs(cpu);
4385 } else {
4386 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
4388 if (arm_feature(env, ARM_FEATURE_V8)) {
4389 /* AArch64 ID registers, which all have impdef reset values.
4390 * Note that within the ID register ranges the unused slots
4391 * must all RAZ, not UNDEF; future architecture versions may
4392 * define new registers here.
4394 ARMCPRegInfo v8_idregs[] = {
4395 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
4396 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
4397 .access = PL1_R, .type = ARM_CP_CONST,
4398 .resetvalue = cpu->id_aa64pfr0 },
4399 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
4400 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
4401 .access = PL1_R, .type = ARM_CP_CONST,
4402 .resetvalue = cpu->id_aa64pfr1},
4403 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4404 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
4405 .access = PL1_R, .type = ARM_CP_CONST,
4406 .resetvalue = 0 },
4407 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4408 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
4409 .access = PL1_R, .type = ARM_CP_CONST,
4410 .resetvalue = 0 },
4411 { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4412 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
4413 .access = PL1_R, .type = ARM_CP_CONST,
4414 .resetvalue = 0 },
4415 { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4416 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
4417 .access = PL1_R, .type = ARM_CP_CONST,
4418 .resetvalue = 0 },
4419 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4420 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
4421 .access = PL1_R, .type = ARM_CP_CONST,
4422 .resetvalue = 0 },
4423 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4424 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
4425 .access = PL1_R, .type = ARM_CP_CONST,
4426 .resetvalue = 0 },
4427 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
4428 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
4429 .access = PL1_R, .type = ARM_CP_CONST,
4430 /* We mask out the PMUVer field, because we don't currently
4431 * implement the PMU. Not advertising it prevents the guest
4432 * from trying to use it and getting UNDEFs on registers we
4433 * don't implement.
4435 .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
4436 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
4437 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
4438 .access = PL1_R, .type = ARM_CP_CONST,
4439 .resetvalue = cpu->id_aa64dfr1 },
4440 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4441 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
4442 .access = PL1_R, .type = ARM_CP_CONST,
4443 .resetvalue = 0 },
4444 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4445 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
4446 .access = PL1_R, .type = ARM_CP_CONST,
4447 .resetvalue = 0 },
4448 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4449 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4450 .access = PL1_R, .type = ARM_CP_CONST,
4451 .resetvalue = cpu->id_aa64afr0 },
4452 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4453 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4454 .access = PL1_R, .type = ARM_CP_CONST,
4455 .resetvalue = cpu->id_aa64afr1 },
4456 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4457 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
4458 .access = PL1_R, .type = ARM_CP_CONST,
4459 .resetvalue = 0 },
4460 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4461 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
4462 .access = PL1_R, .type = ARM_CP_CONST,
4463 .resetvalue = 0 },
4464 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4465 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4466 .access = PL1_R, .type = ARM_CP_CONST,
4467 .resetvalue = cpu->id_aa64isar0 },
4468 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4469 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4470 .access = PL1_R, .type = ARM_CP_CONST,
4471 .resetvalue = cpu->id_aa64isar1 },
4472 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4473 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
4474 .access = PL1_R, .type = ARM_CP_CONST,
4475 .resetvalue = 0 },
4476 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4477 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
4478 .access = PL1_R, .type = ARM_CP_CONST,
4479 .resetvalue = 0 },
4480 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4481 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
4482 .access = PL1_R, .type = ARM_CP_CONST,
4483 .resetvalue = 0 },
4484 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4485 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
4486 .access = PL1_R, .type = ARM_CP_CONST,
4487 .resetvalue = 0 },
4488 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4489 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
4490 .access = PL1_R, .type = ARM_CP_CONST,
4491 .resetvalue = 0 },
4492 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4493 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
4494 .access = PL1_R, .type = ARM_CP_CONST,
4495 .resetvalue = 0 },
4496 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4497 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4498 .access = PL1_R, .type = ARM_CP_CONST,
4499 .resetvalue = cpu->id_aa64mmfr0 },
4500 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4501 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4502 .access = PL1_R, .type = ARM_CP_CONST,
4503 .resetvalue = cpu->id_aa64mmfr1 },
4504 { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4505 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
4506 .access = PL1_R, .type = ARM_CP_CONST,
4507 .resetvalue = 0 },
4508 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4509 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
4510 .access = PL1_R, .type = ARM_CP_CONST,
4511 .resetvalue = 0 },
4512 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4513 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
4514 .access = PL1_R, .type = ARM_CP_CONST,
4515 .resetvalue = 0 },
4516 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4517 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
4518 .access = PL1_R, .type = ARM_CP_CONST,
4519 .resetvalue = 0 },
4520 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4521 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
4522 .access = PL1_R, .type = ARM_CP_CONST,
4523 .resetvalue = 0 },
4524 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4525 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
4526 .access = PL1_R, .type = ARM_CP_CONST,
4527 .resetvalue = 0 },
4528 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4529 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4530 .access = PL1_R, .type = ARM_CP_CONST,
4531 .resetvalue = cpu->mvfr0 },
4532 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4533 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4534 .access = PL1_R, .type = ARM_CP_CONST,
4535 .resetvalue = cpu->mvfr1 },
4536 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4537 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4538 .access = PL1_R, .type = ARM_CP_CONST,
4539 .resetvalue = cpu->mvfr2 },
4540 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4541 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
4542 .access = PL1_R, .type = ARM_CP_CONST,
4543 .resetvalue = 0 },
4544 { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4545 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
4546 .access = PL1_R, .type = ARM_CP_CONST,
4547 .resetvalue = 0 },
4548 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4549 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
4550 .access = PL1_R, .type = ARM_CP_CONST,
4551 .resetvalue = 0 },
4552 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4553 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
4554 .access = PL1_R, .type = ARM_CP_CONST,
4555 .resetvalue = 0 },
4556 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4557 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
4558 .access = PL1_R, .type = ARM_CP_CONST,
4559 .resetvalue = 0 },
4560 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
4561 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
4562 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4563 .resetvalue = cpu->pmceid0 },
4564 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
4565 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
4566 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4567 .resetvalue = cpu->pmceid0 },
4568 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
4569 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
4570 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4571 .resetvalue = cpu->pmceid1 },
4572 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
4573 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
4574 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4575 .resetvalue = cpu->pmceid1 },
4576 REGINFO_SENTINEL
4578 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4579 if (!arm_feature(env, ARM_FEATURE_EL3) &&
4580 !arm_feature(env, ARM_FEATURE_EL2)) {
4581 ARMCPRegInfo rvbar = {
4582 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4583 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4584 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4586 define_one_arm_cp_reg(cpu, &rvbar);
4588 define_arm_cp_regs(cpu, v8_idregs);
4589 define_arm_cp_regs(cpu, v8_cp_reginfo);
4591 if (arm_feature(env, ARM_FEATURE_EL2)) {
4592 uint64_t vmpidr_def = mpidr_read_val(env);
4593 ARMCPRegInfo vpidr_regs[] = {
4594 { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
4595 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4596 .access = PL2_RW, .accessfn = access_el3_aa32ns,
4597 .resetvalue = cpu->midr,
4598 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4599 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
4600 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4601 .access = PL2_RW, .resetvalue = cpu->midr,
4602 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4603 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
4604 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4605 .access = PL2_RW, .accessfn = access_el3_aa32ns,
4606 .resetvalue = vmpidr_def,
4607 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4608 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
4609 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4610 .access = PL2_RW,
4611 .resetvalue = vmpidr_def,
4612 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4613 REGINFO_SENTINEL
4615 define_arm_cp_regs(cpu, vpidr_regs);
4616 define_arm_cp_regs(cpu, el2_cp_reginfo);
4617 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4618 if (!arm_feature(env, ARM_FEATURE_EL3)) {
4619 ARMCPRegInfo rvbar = {
4620 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4621 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4622 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4624 define_one_arm_cp_reg(cpu, &rvbar);
4626 } else {
4627 /* If EL2 is missing but higher ELs are enabled, we need to
4628 * register the no_el2 reginfos.
4630 if (arm_feature(env, ARM_FEATURE_EL3)) {
4631 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4632 * of MIDR_EL1 and MPIDR_EL1.
4634 ARMCPRegInfo vpidr_regs[] = {
4635 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4636 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4637 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4638 .type = ARM_CP_CONST, .resetvalue = cpu->midr,
4639 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4640 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4641 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4642 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4643 .type = ARM_CP_NO_RAW,
4644 .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
4645 REGINFO_SENTINEL
4647 define_arm_cp_regs(cpu, vpidr_regs);
4648 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4651 if (arm_feature(env, ARM_FEATURE_EL3)) {
4652 define_arm_cp_regs(cpu, el3_cp_reginfo);
4653 ARMCPRegInfo el3_regs[] = {
4654 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4655 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4656 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
4657 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
4658 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
4659 .access = PL3_RW,
4660 .raw_writefn = raw_write, .writefn = sctlr_write,
4661 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
4662 .resetvalue = cpu->reset_sctlr },
4663 REGINFO_SENTINEL
4666 define_arm_cp_regs(cpu, el3_regs);
4668 /* The behaviour of NSACR is sufficiently various that we don't
4669 * try to describe it in a single reginfo:
4670 * if EL3 is 64 bit, then trap to EL3 from S EL1,
4671 * reads as constant 0xc00 from NS EL1 and NS EL2
4672 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
4673 * if v7 without EL3, register doesn't exist
4674 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
4676 if (arm_feature(env, ARM_FEATURE_EL3)) {
4677 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4678 ARMCPRegInfo nsacr = {
4679 .name = "NSACR", .type = ARM_CP_CONST,
4680 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4681 .access = PL1_RW, .accessfn = nsacr_access,
4682 .resetvalue = 0xc00
4684 define_one_arm_cp_reg(cpu, &nsacr);
4685 } else {
4686 ARMCPRegInfo nsacr = {
4687 .name = "NSACR",
4688 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4689 .access = PL3_RW | PL1_R,
4690 .resetvalue = 0,
4691 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
4693 define_one_arm_cp_reg(cpu, &nsacr);
4695 } else {
4696 if (arm_feature(env, ARM_FEATURE_V8)) {
4697 ARMCPRegInfo nsacr = {
4698 .name = "NSACR", .type = ARM_CP_CONST,
4699 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4700 .access = PL1_R,
4701 .resetvalue = 0xc00
4703 define_one_arm_cp_reg(cpu, &nsacr);
4707 if (arm_feature(env, ARM_FEATURE_MPU)) {
4708 if (arm_feature(env, ARM_FEATURE_V6)) {
4709 /* PMSAv6 not implemented */
4710 assert(arm_feature(env, ARM_FEATURE_V7));
4711 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4712 define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4713 } else {
4714 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4716 } else {
4717 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4718 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4720 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4721 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4723 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4724 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4726 if (arm_feature(env, ARM_FEATURE_VAPA)) {
4727 define_arm_cp_regs(cpu, vapa_cp_reginfo);
4729 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4730 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4732 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4733 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4735 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4736 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4738 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4739 define_arm_cp_regs(cpu, omap_cp_reginfo);
4741 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4742 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4744 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4745 define_arm_cp_regs(cpu, xscale_cp_reginfo);
4747 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4748 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4750 if (arm_feature(env, ARM_FEATURE_LPAE)) {
4751 define_arm_cp_regs(cpu, lpae_cp_reginfo);
4753 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4754 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4755 * be read-only (ie write causes UNDEF exception).
4758 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4759 /* Pre-v8 MIDR space.
4760 * Note that the MIDR isn't a simple constant register because
4761 * of the TI925 behaviour where writes to another register can
4762 * cause the MIDR value to change.
4764 * Unimplemented registers in the c15 0 0 0 space default to
4765 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4766 * and friends override accordingly.
4768 { .name = "MIDR",
4769 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4770 .access = PL1_R, .resetvalue = cpu->midr,
4771 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4772 .readfn = midr_read,
4773 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4774 .type = ARM_CP_OVERRIDE },
4775 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4776 { .name = "DUMMY",
4777 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4778 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4779 { .name = "DUMMY",
4780 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4781 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4782 { .name = "DUMMY",
4783 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4784 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4785 { .name = "DUMMY",
4786 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4787 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4788 { .name = "DUMMY",
4789 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4790 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4791 REGINFO_SENTINEL
4793 ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4794 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4795 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4796 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
4797 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4798 .readfn = midr_read },
4799 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4800 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4801 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4802 .access = PL1_R, .resetvalue = cpu->midr },
4803 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4804 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4805 .access = PL1_R, .resetvalue = cpu->midr },
4806 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4807 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4808 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4809 REGINFO_SENTINEL
4811 ARMCPRegInfo id_cp_reginfo[] = {
4812 /* These are common to v8 and pre-v8 */
4813 { .name = "CTR",
4814 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4815 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4816 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4817 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4818 .access = PL0_R, .accessfn = ctr_el0_access,
4819 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4820 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4821 { .name = "TCMTR",
4822 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4823 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4824 REGINFO_SENTINEL
4826 /* TLBTR is specific to VMSA */
4827 ARMCPRegInfo id_tlbtr_reginfo = {
4828 .name = "TLBTR",
4829 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4830 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4832 /* MPUIR is specific to PMSA V6+ */
4833 ARMCPRegInfo id_mpuir_reginfo = {
4834 .name = "MPUIR",
4835 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4836 .access = PL1_R, .type = ARM_CP_CONST,
4837 .resetvalue = cpu->pmsav7_dregion << 8
4839 ARMCPRegInfo crn0_wi_reginfo = {
4840 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4841 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4842 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4844 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4845 arm_feature(env, ARM_FEATURE_STRONGARM)) {
4846 ARMCPRegInfo *r;
4847 /* Register the blanket "writes ignored" value first to cover the
4848 * whole space. Then update the specific ID registers to allow write
4849 * access, so that they ignore writes rather than causing them to
4850 * UNDEF.
4852 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4853 for (r = id_pre_v8_midr_cp_reginfo;
4854 r->type != ARM_CP_SENTINEL; r++) {
4855 r->access = PL1_RW;
4857 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4858 r->access = PL1_RW;
4860 id_tlbtr_reginfo.access = PL1_RW;
4861 id_tlbtr_reginfo.access = PL1_RW;
4863 if (arm_feature(env, ARM_FEATURE_V8)) {
4864 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4865 } else {
4866 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4868 define_arm_cp_regs(cpu, id_cp_reginfo);
4869 if (!arm_feature(env, ARM_FEATURE_MPU)) {
4870 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4871 } else if (arm_feature(env, ARM_FEATURE_V7)) {
4872 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4876 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4877 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4880 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4881 ARMCPRegInfo auxcr_reginfo[] = {
4882 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4883 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4884 .access = PL1_RW, .type = ARM_CP_CONST,
4885 .resetvalue = cpu->reset_auxcr },
4886 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4887 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4888 .access = PL2_RW, .type = ARM_CP_CONST,
4889 .resetvalue = 0 },
4890 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4891 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4892 .access = PL3_RW, .type = ARM_CP_CONST,
4893 .resetvalue = 0 },
4894 REGINFO_SENTINEL
4896 define_arm_cp_regs(cpu, auxcr_reginfo);
4899 if (arm_feature(env, ARM_FEATURE_CBAR)) {
4900 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4901 /* 32 bit view is [31:18] 0...0 [43:32]. */
4902 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4903 | extract64(cpu->reset_cbar, 32, 12);
4904 ARMCPRegInfo cbar_reginfo[] = {
4905 { .name = "CBAR",
4906 .type = ARM_CP_CONST,
4907 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4908 .access = PL1_R, .resetvalue = cpu->reset_cbar },
4909 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4910 .type = ARM_CP_CONST,
4911 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4912 .access = PL1_R, .resetvalue = cbar32 },
4913 REGINFO_SENTINEL
4915 /* We don't implement a r/w 64 bit CBAR currently */
4916 assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4917 define_arm_cp_regs(cpu, cbar_reginfo);
4918 } else {
4919 ARMCPRegInfo cbar = {
4920 .name = "CBAR",
4921 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4922 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4923 .fieldoffset = offsetof(CPUARMState,
4924 cp15.c15_config_base_address)
4926 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4927 cbar.access = PL1_R;
4928 cbar.fieldoffset = 0;
4929 cbar.type = ARM_CP_CONST;
4931 define_one_arm_cp_reg(cpu, &cbar);
4935 /* Generic registers whose values depend on the implementation */
4937 ARMCPRegInfo sctlr = {
4938 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4939 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4940 .access = PL1_RW,
4941 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4942 offsetof(CPUARMState, cp15.sctlr_ns) },
4943 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4944 .raw_writefn = raw_write,
4946 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4947 /* Normally we would always end the TB on an SCTLR write, but Linux
4948 * arch/arm/mach-pxa/sleep.S expects two instructions following
4949 * an MMU enable to execute from cache. Imitate this behaviour.
4951 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4953 define_one_arm_cp_reg(cpu, &sctlr);
4957 ARMCPU *cpu_arm_init(const char *cpu_model)
4959 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4962 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4964 CPUState *cs = CPU(cpu);
4965 CPUARMState *env = &cpu->env;
4967 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4968 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4969 aarch64_fpu_gdb_set_reg,
4970 34, "aarch64-fpu.xml", 0);
4971 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4972 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4973 51, "arm-neon.xml", 0);
4974 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4975 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4976 35, "arm-vfp3.xml", 0);
4977 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4978 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4979 19, "arm-vfp.xml", 0);
4983 /* Sort alphabetically by type name, except for "any". */
4984 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4986 ObjectClass *class_a = (ObjectClass *)a;
4987 ObjectClass *class_b = (ObjectClass *)b;
4988 const char *name_a, *name_b;
4990 name_a = object_class_get_name(class_a);
4991 name_b = object_class_get_name(class_b);
4992 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4993 return 1;
4994 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4995 return -1;
4996 } else {
4997 return strcmp(name_a, name_b);
5001 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
5003 ObjectClass *oc = data;
5004 CPUListState *s = user_data;
5005 const char *typename;
5006 char *name;
5008 typename = object_class_get_name(oc);
5009 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
5010 (*s->cpu_fprintf)(s->file, " %s\n",
5011 name);
5012 g_free(name);
5015 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5017 CPUListState s = {
5018 .file = f,
5019 .cpu_fprintf = cpu_fprintf,
5021 GSList *list;
5023 list = object_class_get_list(TYPE_ARM_CPU, false);
5024 list = g_slist_sort(list, arm_cpu_list_compare);
5025 (*cpu_fprintf)(f, "Available CPUs:\n");
5026 g_slist_foreach(list, arm_cpu_list_entry, &s);
5027 g_slist_free(list);
5028 #ifdef CONFIG_KVM
5029 /* The 'host' CPU type is dynamically registered only if KVM is
5030 * enabled, so we have to special-case it here:
5032 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
5033 #endif
5036 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
5038 ObjectClass *oc = data;
5039 CpuDefinitionInfoList **cpu_list = user_data;
5040 CpuDefinitionInfoList *entry;
5041 CpuDefinitionInfo *info;
5042 const char *typename;
5044 typename = object_class_get_name(oc);
5045 info = g_malloc0(sizeof(*info));
5046 info->name = g_strndup(typename,
5047 strlen(typename) - strlen("-" TYPE_ARM_CPU));
5049 entry = g_malloc0(sizeof(*entry));
5050 entry->value = info;
5051 entry->next = *cpu_list;
5052 *cpu_list = entry;
5055 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
5057 CpuDefinitionInfoList *cpu_list = NULL;
5058 GSList *list;
5060 list = object_class_get_list(TYPE_ARM_CPU, false);
5061 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
5062 g_slist_free(list);
5064 return cpu_list;
5067 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
5068 void *opaque, int state, int secstate,
5069 int crm, int opc1, int opc2)
5071 /* Private utility function for define_one_arm_cp_reg_with_opaque():
5072 * add a single reginfo struct to the hash table.
5074 uint32_t *key = g_new(uint32_t, 1);
5075 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
5076 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
5077 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
5079 /* Reset the secure state to the specific incoming state. This is
5080 * necessary as the register may have been defined with both states.
5082 r2->secure = secstate;
5084 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5085 /* Register is banked (using both entries in array).
5086 * Overwriting fieldoffset as the array is only used to define
5087 * banked registers but later only fieldoffset is used.
5089 r2->fieldoffset = r->bank_fieldoffsets[ns];
5092 if (state == ARM_CP_STATE_AA32) {
5093 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5094 /* If the register is banked then we don't need to migrate or
5095 * reset the 32-bit instance in certain cases:
5097 * 1) If the register has both 32-bit and 64-bit instances then we
5098 * can count on the 64-bit instance taking care of the
5099 * non-secure bank.
5100 * 2) If ARMv8 is enabled then we can count on a 64-bit version
5101 * taking care of the secure bank. This requires that separate
5102 * 32 and 64-bit definitions are provided.
5104 if ((r->state == ARM_CP_STATE_BOTH && ns) ||
5105 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
5106 r2->type |= ARM_CP_ALIAS;
5108 } else if ((secstate != r->secure) && !ns) {
5109 /* The register is not banked so we only want to allow migration of
5110 * the non-secure instance.
5112 r2->type |= ARM_CP_ALIAS;
5115 if (r->state == ARM_CP_STATE_BOTH) {
5116 /* We assume it is a cp15 register if the .cp field is left unset.
5118 if (r2->cp == 0) {
5119 r2->cp = 15;
5122 #ifdef HOST_WORDS_BIGENDIAN
5123 if (r2->fieldoffset) {
5124 r2->fieldoffset += sizeof(uint32_t);
5126 #endif
5129 if (state == ARM_CP_STATE_AA64) {
5130 /* To allow abbreviation of ARMCPRegInfo
5131 * definitions, we treat cp == 0 as equivalent to
5132 * the value for "standard guest-visible sysreg".
5133 * STATE_BOTH definitions are also always "standard
5134 * sysreg" in their AArch64 view (the .cp value may
5135 * be non-zero for the benefit of the AArch32 view).
5137 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
5138 r2->cp = CP_REG_ARM64_SYSREG_CP;
5140 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
5141 r2->opc0, opc1, opc2);
5142 } else {
5143 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
5145 if (opaque) {
5146 r2->opaque = opaque;
5148 /* reginfo passed to helpers is correct for the actual access,
5149 * and is never ARM_CP_STATE_BOTH:
5151 r2->state = state;
5152 /* Make sure reginfo passed to helpers for wildcarded regs
5153 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5155 r2->crm = crm;
5156 r2->opc1 = opc1;
5157 r2->opc2 = opc2;
5158 /* By convention, for wildcarded registers only the first
5159 * entry is used for migration; the others are marked as
5160 * ALIAS so we don't try to transfer the register
5161 * multiple times. Special registers (ie NOP/WFI) are
5162 * never migratable and not even raw-accessible.
5164 if ((r->type & ARM_CP_SPECIAL)) {
5165 r2->type |= ARM_CP_NO_RAW;
5167 if (((r->crm == CP_ANY) && crm != 0) ||
5168 ((r->opc1 == CP_ANY) && opc1 != 0) ||
5169 ((r->opc2 == CP_ANY) && opc2 != 0)) {
5170 r2->type |= ARM_CP_ALIAS;
5173 /* Check that raw accesses are either forbidden or handled. Note that
5174 * we can't assert this earlier because the setup of fieldoffset for
5175 * banked registers has to be done first.
5177 if (!(r2->type & ARM_CP_NO_RAW)) {
5178 assert(!raw_accessors_invalid(r2));
5181 /* Overriding of an existing definition must be explicitly
5182 * requested.
5184 if (!(r->type & ARM_CP_OVERRIDE)) {
5185 ARMCPRegInfo *oldreg;
5186 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
5187 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
5188 fprintf(stderr, "Register redefined: cp=%d %d bit "
5189 "crn=%d crm=%d opc1=%d opc2=%d, "
5190 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
5191 r2->crn, r2->crm, r2->opc1, r2->opc2,
5192 oldreg->name, r2->name);
5193 g_assert_not_reached();
5196 g_hash_table_insert(cpu->cp_regs, key, r2);
5200 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
5201 const ARMCPRegInfo *r, void *opaque)
5203 /* Define implementations of coprocessor registers.
5204 * We store these in a hashtable because typically
5205 * there are less than 150 registers in a space which
5206 * is 16*16*16*8*8 = 262144 in size.
5207 * Wildcarding is supported for the crm, opc1 and opc2 fields.
5208 * If a register is defined twice then the second definition is
5209 * used, so this can be used to define some generic registers and
5210 * then override them with implementation specific variations.
5211 * At least one of the original and the second definition should
5212 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5213 * against accidental use.
5215 * The state field defines whether the register is to be
5216 * visible in the AArch32 or AArch64 execution state. If the
5217 * state is set to ARM_CP_STATE_BOTH then we synthesise a
5218 * reginfo structure for the AArch32 view, which sees the lower
5219 * 32 bits of the 64 bit register.
5221 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5222 * be wildcarded. AArch64 registers are always considered to be 64
5223 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5224 * the register, if any.
5226 int crm, opc1, opc2, state;
5227 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
5228 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
5229 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
5230 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
5231 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
5232 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
5233 /* 64 bit registers have only CRm and Opc1 fields */
5234 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
5235 /* op0 only exists in the AArch64 encodings */
5236 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
5237 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5238 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
5239 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5240 * encodes a minimum access level for the register. We roll this
5241 * runtime check into our general permission check code, so check
5242 * here that the reginfo's specified permissions are strict enough
5243 * to encompass the generic architectural permission check.
5245 if (r->state != ARM_CP_STATE_AA32) {
5246 int mask = 0;
5247 switch (r->opc1) {
5248 case 0: case 1: case 2:
5249 /* min_EL EL1 */
5250 mask = PL1_RW;
5251 break;
5252 case 3:
5253 /* min_EL EL0 */
5254 mask = PL0_RW;
5255 break;
5256 case 4:
5257 /* min_EL EL2 */
5258 mask = PL2_RW;
5259 break;
5260 case 5:
5261 /* unallocated encoding, so not possible */
5262 assert(false);
5263 break;
5264 case 6:
5265 /* min_EL EL3 */
5266 mask = PL3_RW;
5267 break;
5268 case 7:
5269 /* min_EL EL1, secure mode only (we don't check the latter) */
5270 mask = PL1_RW;
5271 break;
5272 default:
5273 /* broken reginfo with out-of-range opc1 */
5274 assert(false);
5275 break;
5277 /* assert our permissions are not too lax (stricter is fine) */
5278 assert((r->access & ~mask) == 0);
5281 /* Check that the register definition has enough info to handle
5282 * reads and writes if they are permitted.
5284 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
5285 if (r->access & PL3_R) {
5286 assert((r->fieldoffset ||
5287 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5288 r->readfn);
5290 if (r->access & PL3_W) {
5291 assert((r->fieldoffset ||
5292 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5293 r->writefn);
5296 /* Bad type field probably means missing sentinel at end of reg list */
5297 assert(cptype_valid(r->type));
5298 for (crm = crmmin; crm <= crmmax; crm++) {
5299 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
5300 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
5301 for (state = ARM_CP_STATE_AA32;
5302 state <= ARM_CP_STATE_AA64; state++) {
5303 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
5304 continue;
5306 if (state == ARM_CP_STATE_AA32) {
5307 /* Under AArch32 CP registers can be common
5308 * (same for secure and non-secure world) or banked.
5310 switch (r->secure) {
5311 case ARM_CP_SECSTATE_S:
5312 case ARM_CP_SECSTATE_NS:
5313 add_cpreg_to_hashtable(cpu, r, opaque, state,
5314 r->secure, crm, opc1, opc2);
5315 break;
5316 default:
5317 add_cpreg_to_hashtable(cpu, r, opaque, state,
5318 ARM_CP_SECSTATE_S,
5319 crm, opc1, opc2);
5320 add_cpreg_to_hashtable(cpu, r, opaque, state,
5321 ARM_CP_SECSTATE_NS,
5322 crm, opc1, opc2);
5323 break;
5325 } else {
5326 /* AArch64 registers get mapped to non-secure instance
5327 * of AArch32 */
5328 add_cpreg_to_hashtable(cpu, r, opaque, state,
5329 ARM_CP_SECSTATE_NS,
5330 crm, opc1, opc2);
5338 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
5339 const ARMCPRegInfo *regs, void *opaque)
5341 /* Define a whole list of registers */
5342 const ARMCPRegInfo *r;
5343 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
5344 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
5348 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
5350 return g_hash_table_lookup(cpregs, &encoded_cp);
5353 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
5354 uint64_t value)
5356 /* Helper coprocessor write function for write-ignore registers */
5359 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
5361 /* Helper coprocessor write function for read-as-zero registers */
5362 return 0;
5365 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
5367 /* Helper coprocessor reset function for do-nothing-on-reset registers */
5370 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
5372 /* Return true if it is not valid for us to switch to
5373 * this CPU mode (ie all the UNPREDICTABLE cases in
5374 * the ARM ARM CPSRWriteByInstr pseudocode).
5377 /* Changes to or from Hyp via MSR and CPS are illegal. */
5378 if (write_type == CPSRWriteByInstr &&
5379 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
5380 mode == ARM_CPU_MODE_HYP)) {
5381 return 1;
5384 switch (mode) {
5385 case ARM_CPU_MODE_USR:
5386 return 0;
5387 case ARM_CPU_MODE_SYS:
5388 case ARM_CPU_MODE_SVC:
5389 case ARM_CPU_MODE_ABT:
5390 case ARM_CPU_MODE_UND:
5391 case ARM_CPU_MODE_IRQ:
5392 case ARM_CPU_MODE_FIQ:
5393 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5394 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5396 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5397 * and CPS are treated as illegal mode changes.
5399 if (write_type == CPSRWriteByInstr &&
5400 (env->cp15.hcr_el2 & HCR_TGE) &&
5401 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
5402 !arm_is_secure_below_el3(env)) {
5403 return 1;
5405 return 0;
5406 case ARM_CPU_MODE_HYP:
5407 return !arm_feature(env, ARM_FEATURE_EL2)
5408 || arm_current_el(env) < 2 || arm_is_secure(env);
5409 case ARM_CPU_MODE_MON:
5410 return arm_current_el(env) < 3;
5411 default:
5412 return 1;
5416 uint32_t cpsr_read(CPUARMState *env)
5418 int ZF;
5419 ZF = (env->ZF == 0);
5420 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
5421 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
5422 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
5423 | ((env->condexec_bits & 0xfc) << 8)
5424 | (env->GE << 16) | (env->daif & CPSR_AIF);
5427 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
5428 CPSRWriteType write_type)
5430 uint32_t changed_daif;
5432 if (mask & CPSR_NZCV) {
5433 env->ZF = (~val) & CPSR_Z;
5434 env->NF = val;
5435 env->CF = (val >> 29) & 1;
5436 env->VF = (val << 3) & 0x80000000;
5438 if (mask & CPSR_Q)
5439 env->QF = ((val & CPSR_Q) != 0);
5440 if (mask & CPSR_T)
5441 env->thumb = ((val & CPSR_T) != 0);
5442 if (mask & CPSR_IT_0_1) {
5443 env->condexec_bits &= ~3;
5444 env->condexec_bits |= (val >> 25) & 3;
5446 if (mask & CPSR_IT_2_7) {
5447 env->condexec_bits &= 3;
5448 env->condexec_bits |= (val >> 8) & 0xfc;
5450 if (mask & CPSR_GE) {
5451 env->GE = (val >> 16) & 0xf;
5454 /* In a V7 implementation that includes the security extensions but does
5455 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5456 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5457 * bits respectively.
5459 * In a V8 implementation, it is permitted for privileged software to
5460 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5462 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) &&
5463 arm_feature(env, ARM_FEATURE_EL3) &&
5464 !arm_feature(env, ARM_FEATURE_EL2) &&
5465 !arm_is_secure(env)) {
5467 changed_daif = (env->daif ^ val) & mask;
5469 if (changed_daif & CPSR_A) {
5470 /* Check to see if we are allowed to change the masking of async
5471 * abort exceptions from a non-secure state.
5473 if (!(env->cp15.scr_el3 & SCR_AW)) {
5474 qemu_log_mask(LOG_GUEST_ERROR,
5475 "Ignoring attempt to switch CPSR_A flag from "
5476 "non-secure world with SCR.AW bit clear\n");
5477 mask &= ~CPSR_A;
5481 if (changed_daif & CPSR_F) {
5482 /* Check to see if we are allowed to change the masking of FIQ
5483 * exceptions from a non-secure state.
5485 if (!(env->cp15.scr_el3 & SCR_FW)) {
5486 qemu_log_mask(LOG_GUEST_ERROR,
5487 "Ignoring attempt to switch CPSR_F flag from "
5488 "non-secure world with SCR.FW bit clear\n");
5489 mask &= ~CPSR_F;
5492 /* Check whether non-maskable FIQ (NMFI) support is enabled.
5493 * If this bit is set software is not allowed to mask
5494 * FIQs, but is allowed to set CPSR_F to 0.
5496 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
5497 (val & CPSR_F)) {
5498 qemu_log_mask(LOG_GUEST_ERROR,
5499 "Ignoring attempt to enable CPSR_F flag "
5500 "(non-maskable FIQ [NMFI] support enabled)\n");
5501 mask &= ~CPSR_F;
5506 env->daif &= ~(CPSR_AIF & mask);
5507 env->daif |= val & CPSR_AIF & mask;
5509 if (write_type != CPSRWriteRaw &&
5510 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
5511 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
5512 /* Note that we can only get here in USR mode if this is a
5513 * gdb stub write; for this case we follow the architectural
5514 * behaviour for guest writes in USR mode of ignoring an attempt
5515 * to switch mode. (Those are caught by translate.c for writes
5516 * triggered by guest instructions.)
5518 mask &= ~CPSR_M;
5519 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
5520 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
5521 * v7, and has defined behaviour in v8:
5522 * + leave CPSR.M untouched
5523 * + allow changes to the other CPSR fields
5524 * + set PSTATE.IL
5525 * For user changes via the GDB stub, we don't set PSTATE.IL,
5526 * as this would be unnecessarily harsh for a user error.
5528 mask &= ~CPSR_M;
5529 if (write_type != CPSRWriteByGDBStub &&
5530 arm_feature(env, ARM_FEATURE_V8)) {
5531 mask |= CPSR_IL;
5532 val |= CPSR_IL;
5534 } else {
5535 switch_mode(env, val & CPSR_M);
5538 mask &= ~CACHED_CPSR_BITS;
5539 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
5542 /* Sign/zero extend */
5543 uint32_t HELPER(sxtb16)(uint32_t x)
5545 uint32_t res;
5546 res = (uint16_t)(int8_t)x;
5547 res |= (uint32_t)(int8_t)(x >> 16) << 16;
5548 return res;
5551 uint32_t HELPER(uxtb16)(uint32_t x)
5553 uint32_t res;
5554 res = (uint16_t)(uint8_t)x;
5555 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
5556 return res;
5559 uint32_t HELPER(clz)(uint32_t x)
5561 return clz32(x);
5564 int32_t HELPER(sdiv)(int32_t num, int32_t den)
5566 if (den == 0)
5567 return 0;
5568 if (num == INT_MIN && den == -1)
5569 return INT_MIN;
5570 return num / den;
5573 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
5575 if (den == 0)
5576 return 0;
5577 return num / den;
5580 uint32_t HELPER(rbit)(uint32_t x)
5582 return revbit32(x);
5585 #if defined(CONFIG_USER_ONLY)
5587 /* These should probably raise undefined insn exceptions. */
5588 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5590 ARMCPU *cpu = arm_env_get_cpu(env);
5592 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
5595 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5597 ARMCPU *cpu = arm_env_get_cpu(env);
5599 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
5600 return 0;
5603 void switch_mode(CPUARMState *env, int mode)
5605 ARMCPU *cpu = arm_env_get_cpu(env);
5607 if (mode != ARM_CPU_MODE_USR) {
5608 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
5612 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5613 uint32_t cur_el, bool secure)
5615 return 1;
5618 void aarch64_sync_64_to_32(CPUARMState *env)
5620 g_assert_not_reached();
5623 #else
5625 void switch_mode(CPUARMState *env, int mode)
5627 int old_mode;
5628 int i;
5630 old_mode = env->uncached_cpsr & CPSR_M;
5631 if (mode == old_mode)
5632 return;
5634 if (old_mode == ARM_CPU_MODE_FIQ) {
5635 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5636 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5637 } else if (mode == ARM_CPU_MODE_FIQ) {
5638 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5639 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5642 i = bank_number(old_mode);
5643 env->banked_r13[i] = env->regs[13];
5644 env->banked_r14[i] = env->regs[14];
5645 env->banked_spsr[i] = env->spsr;
5647 i = bank_number(mode);
5648 env->regs[13] = env->banked_r13[i];
5649 env->regs[14] = env->banked_r14[i];
5650 env->spsr = env->banked_spsr[i];
5653 /* Physical Interrupt Target EL Lookup Table
5655 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5657 * The below multi-dimensional table is used for looking up the target
5658 * exception level given numerous condition criteria. Specifically, the
5659 * target EL is based on SCR and HCR routing controls as well as the
5660 * currently executing EL and secure state.
5662 * Dimensions:
5663 * target_el_table[2][2][2][2][2][4]
5664 * | | | | | +--- Current EL
5665 * | | | | +------ Non-secure(0)/Secure(1)
5666 * | | | +--------- HCR mask override
5667 * | | +------------ SCR exec state control
5668 * | +--------------- SCR mask override
5669 * +------------------ 32-bit(0)/64-bit(1) EL3
5671 * The table values are as such:
5672 * 0-3 = EL0-EL3
5673 * -1 = Cannot occur
5675 * The ARM ARM target EL table includes entries indicating that an "exception
5676 * is not taken". The two cases where this is applicable are:
5677 * 1) An exception is taken from EL3 but the SCR does not have the exception
5678 * routed to EL3.
5679 * 2) An exception is taken from EL2 but the HCR does not have the exception
5680 * routed to EL2.
5681 * In these two cases, the below table contain a target of EL1. This value is
5682 * returned as it is expected that the consumer of the table data will check
5683 * for "target EL >= current EL" to ensure the exception is not taken.
5685 * SCR HCR
5686 * 64 EA AMO From
5687 * BIT IRQ IMO Non-secure Secure
5688 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
5690 static const int8_t target_el_table[2][2][2][2][2][4] = {
5691 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5692 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
5693 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5694 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
5695 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5696 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
5697 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5698 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
5699 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
5700 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
5701 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
5702 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
5703 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5704 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
5705 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5706 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
5710 * Determine the target EL for physical exceptions
5712 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5713 uint32_t cur_el, bool secure)
5715 CPUARMState *env = cs->env_ptr;
5716 int rw;
5717 int scr;
5718 int hcr;
5719 int target_el;
5720 /* Is the highest EL AArch64? */
5721 int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
5723 if (arm_feature(env, ARM_FEATURE_EL3)) {
5724 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5725 } else {
5726 /* Either EL2 is the highest EL (and so the EL2 register width
5727 * is given by is64); or there is no EL2 or EL3, in which case
5728 * the value of 'rw' does not affect the table lookup anyway.
5730 rw = is64;
5733 switch (excp_idx) {
5734 case EXCP_IRQ:
5735 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5736 hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5737 break;
5738 case EXCP_FIQ:
5739 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5740 hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5741 break;
5742 default:
5743 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5744 hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5745 break;
5748 /* If HCR.TGE is set then HCR is treated as being 1 */
5749 hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5751 /* Perform a table-lookup for the target EL given the current state */
5752 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5754 assert(target_el > 0);
5756 return target_el;
5759 static void v7m_push(CPUARMState *env, uint32_t val)
5761 CPUState *cs = CPU(arm_env_get_cpu(env));
5763 env->regs[13] -= 4;
5764 stl_phys(cs->as, env->regs[13], val);
5767 static uint32_t v7m_pop(CPUARMState *env)
5769 CPUState *cs = CPU(arm_env_get_cpu(env));
5770 uint32_t val;
5772 val = ldl_phys(cs->as, env->regs[13]);
5773 env->regs[13] += 4;
5774 return val;
5777 /* Switch to V7M main or process stack pointer. */
5778 static void switch_v7m_sp(CPUARMState *env, int process)
5780 uint32_t tmp;
5781 if (env->v7m.current_sp != process) {
5782 tmp = env->v7m.other_sp;
5783 env->v7m.other_sp = env->regs[13];
5784 env->regs[13] = tmp;
5785 env->v7m.current_sp = process;
5789 static void do_v7m_exception_exit(CPUARMState *env)
5791 uint32_t type;
5792 uint32_t xpsr;
5794 type = env->regs[15];
5795 if (env->v7m.exception != 0)
5796 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5798 /* Switch to the target stack. */
5799 switch_v7m_sp(env, (type & 4) != 0);
5800 /* Pop registers. */
5801 env->regs[0] = v7m_pop(env);
5802 env->regs[1] = v7m_pop(env);
5803 env->regs[2] = v7m_pop(env);
5804 env->regs[3] = v7m_pop(env);
5805 env->regs[12] = v7m_pop(env);
5806 env->regs[14] = v7m_pop(env);
5807 env->regs[15] = v7m_pop(env);
5808 if (env->regs[15] & 1) {
5809 qemu_log_mask(LOG_GUEST_ERROR,
5810 "M profile return from interrupt with misaligned "
5811 "PC is UNPREDICTABLE\n");
5812 /* Actual hardware seems to ignore the lsbit, and there are several
5813 * RTOSes out there which incorrectly assume the r15 in the stack
5814 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5816 env->regs[15] &= ~1U;
5818 xpsr = v7m_pop(env);
5819 xpsr_write(env, xpsr, 0xfffffdff);
5820 /* Undo stack alignment. */
5821 if (xpsr & 0x200)
5822 env->regs[13] |= 4;
5823 /* ??? The exception return type specifies Thread/Handler mode. However
5824 this is also implied by the xPSR value. Not sure what to do
5825 if there is a mismatch. */
5826 /* ??? Likewise for mismatches between the CONTROL register and the stack
5827 pointer. */
5830 static void arm_log_exception(int idx)
5832 if (qemu_loglevel_mask(CPU_LOG_INT)) {
5833 const char *exc = NULL;
5835 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
5836 exc = excnames[idx];
5838 if (!exc) {
5839 exc = "unknown";
5841 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
5845 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5847 ARMCPU *cpu = ARM_CPU(cs);
5848 CPUARMState *env = &cpu->env;
5849 uint32_t xpsr = xpsr_read(env);
5850 uint32_t lr;
5851 uint32_t addr;
5853 arm_log_exception(cs->exception_index);
5855 lr = 0xfffffff1;
5856 if (env->v7m.current_sp)
5857 lr |= 4;
5858 if (env->v7m.exception == 0)
5859 lr |= 8;
5861 /* For exceptions we just mark as pending on the NVIC, and let that
5862 handle it. */
5863 /* TODO: Need to escalate if the current priority is higher than the
5864 one we're raising. */
5865 switch (cs->exception_index) {
5866 case EXCP_UDEF:
5867 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5868 return;
5869 case EXCP_SWI:
5870 /* The PC already points to the next instruction. */
5871 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5872 return;
5873 case EXCP_PREFETCH_ABORT:
5874 case EXCP_DATA_ABORT:
5875 /* TODO: if we implemented the MPU registers, this is where we
5876 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5878 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5879 return;
5880 case EXCP_BKPT:
5881 if (semihosting_enabled()) {
5882 int nr;
5883 nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff;
5884 if (nr == 0xab) {
5885 env->regs[15] += 2;
5886 qemu_log_mask(CPU_LOG_INT,
5887 "...handling as semihosting call 0x%x\n",
5888 env->regs[0]);
5889 env->regs[0] = do_arm_semihosting(env);
5890 return;
5893 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5894 return;
5895 case EXCP_IRQ:
5896 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5897 break;
5898 case EXCP_EXCEPTION_EXIT:
5899 do_v7m_exception_exit(env);
5900 return;
5901 default:
5902 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5903 return; /* Never happens. Keep compiler happy. */
5906 /* Align stack pointer. */
5907 /* ??? Should only do this if Configuration Control Register
5908 STACKALIGN bit is set. */
5909 if (env->regs[13] & 4) {
5910 env->regs[13] -= 4;
5911 xpsr |= 0x200;
5913 /* Switch to the handler mode. */
5914 v7m_push(env, xpsr);
5915 v7m_push(env, env->regs[15]);
5916 v7m_push(env, env->regs[14]);
5917 v7m_push(env, env->regs[12]);
5918 v7m_push(env, env->regs[3]);
5919 v7m_push(env, env->regs[2]);
5920 v7m_push(env, env->regs[1]);
5921 v7m_push(env, env->regs[0]);
5922 switch_v7m_sp(env, 0);
5923 /* Clear IT bits */
5924 env->condexec_bits = 0;
5925 env->regs[14] = lr;
5926 addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5927 env->regs[15] = addr & 0xfffffffe;
5928 env->thumb = addr & 1;
5931 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5932 * register set. This is necessary when switching between AArch32 and AArch64
5933 * execution state.
5935 void aarch64_sync_32_to_64(CPUARMState *env)
5937 int i;
5938 uint32_t mode = env->uncached_cpsr & CPSR_M;
5940 /* We can blanket copy R[0:7] to X[0:7] */
5941 for (i = 0; i < 8; i++) {
5942 env->xregs[i] = env->regs[i];
5945 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5946 * Otherwise, they come from the banked user regs.
5948 if (mode == ARM_CPU_MODE_FIQ) {
5949 for (i = 8; i < 13; i++) {
5950 env->xregs[i] = env->usr_regs[i - 8];
5952 } else {
5953 for (i = 8; i < 13; i++) {
5954 env->xregs[i] = env->regs[i];
5958 /* Registers x13-x23 are the various mode SP and FP registers. Registers
5959 * r13 and r14 are only copied if we are in that mode, otherwise we copy
5960 * from the mode banked register.
5962 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5963 env->xregs[13] = env->regs[13];
5964 env->xregs[14] = env->regs[14];
5965 } else {
5966 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5967 /* HYP is an exception in that it is copied from r14 */
5968 if (mode == ARM_CPU_MODE_HYP) {
5969 env->xregs[14] = env->regs[14];
5970 } else {
5971 env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5975 if (mode == ARM_CPU_MODE_HYP) {
5976 env->xregs[15] = env->regs[13];
5977 } else {
5978 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5981 if (mode == ARM_CPU_MODE_IRQ) {
5982 env->xregs[16] = env->regs[14];
5983 env->xregs[17] = env->regs[13];
5984 } else {
5985 env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5986 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5989 if (mode == ARM_CPU_MODE_SVC) {
5990 env->xregs[18] = env->regs[14];
5991 env->xregs[19] = env->regs[13];
5992 } else {
5993 env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5994 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5997 if (mode == ARM_CPU_MODE_ABT) {
5998 env->xregs[20] = env->regs[14];
5999 env->xregs[21] = env->regs[13];
6000 } else {
6001 env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
6002 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
6005 if (mode == ARM_CPU_MODE_UND) {
6006 env->xregs[22] = env->regs[14];
6007 env->xregs[23] = env->regs[13];
6008 } else {
6009 env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
6010 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
6013 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
6014 * mode, then we can copy from r8-r14. Otherwise, we copy from the
6015 * FIQ bank for r8-r14.
6017 if (mode == ARM_CPU_MODE_FIQ) {
6018 for (i = 24; i < 31; i++) {
6019 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */
6021 } else {
6022 for (i = 24; i < 29; i++) {
6023 env->xregs[i] = env->fiq_regs[i - 24];
6025 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
6026 env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
6029 env->pc = env->regs[15];
6032 /* Function used to synchronize QEMU's AArch32 register set with AArch64
6033 * register set. This is necessary when switching between AArch32 and AArch64
6034 * execution state.
6036 void aarch64_sync_64_to_32(CPUARMState *env)
6038 int i;
6039 uint32_t mode = env->uncached_cpsr & CPSR_M;
6041 /* We can blanket copy X[0:7] to R[0:7] */
6042 for (i = 0; i < 8; i++) {
6043 env->regs[i] = env->xregs[i];
6046 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
6047 * Otherwise, we copy x8-x12 into the banked user regs.
6049 if (mode == ARM_CPU_MODE_FIQ) {
6050 for (i = 8; i < 13; i++) {
6051 env->usr_regs[i - 8] = env->xregs[i];
6053 } else {
6054 for (i = 8; i < 13; i++) {
6055 env->regs[i] = env->xregs[i];
6059 /* Registers r13 & r14 depend on the current mode.
6060 * If we are in a given mode, we copy the corresponding x registers to r13
6061 * and r14. Otherwise, we copy the x register to the banked r13 and r14
6062 * for the mode.
6064 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
6065 env->regs[13] = env->xregs[13];
6066 env->regs[14] = env->xregs[14];
6067 } else {
6068 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
6070 /* HYP is an exception in that it does not have its own banked r14 but
6071 * shares the USR r14
6073 if (mode == ARM_CPU_MODE_HYP) {
6074 env->regs[14] = env->xregs[14];
6075 } else {
6076 env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
6080 if (mode == ARM_CPU_MODE_HYP) {
6081 env->regs[13] = env->xregs[15];
6082 } else {
6083 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
6086 if (mode == ARM_CPU_MODE_IRQ) {
6087 env->regs[14] = env->xregs[16];
6088 env->regs[13] = env->xregs[17];
6089 } else {
6090 env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
6091 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
6094 if (mode == ARM_CPU_MODE_SVC) {
6095 env->regs[14] = env->xregs[18];
6096 env->regs[13] = env->xregs[19];
6097 } else {
6098 env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
6099 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
6102 if (mode == ARM_CPU_MODE_ABT) {
6103 env->regs[14] = env->xregs[20];
6104 env->regs[13] = env->xregs[21];
6105 } else {
6106 env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
6107 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
6110 if (mode == ARM_CPU_MODE_UND) {
6111 env->regs[14] = env->xregs[22];
6112 env->regs[13] = env->xregs[23];
6113 } else {
6114 env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
6115 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
6118 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
6119 * mode, then we can copy to r8-r14. Otherwise, we copy to the
6120 * FIQ bank for r8-r14.
6122 if (mode == ARM_CPU_MODE_FIQ) {
6123 for (i = 24; i < 31; i++) {
6124 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */
6126 } else {
6127 for (i = 24; i < 29; i++) {
6128 env->fiq_regs[i - 24] = env->xregs[i];
6130 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
6131 env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
6134 env->regs[15] = env->pc;
6137 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
6139 ARMCPU *cpu = ARM_CPU(cs);
6140 CPUARMState *env = &cpu->env;
6141 uint32_t addr;
6142 uint32_t mask;
6143 int new_mode;
6144 uint32_t offset;
6145 uint32_t moe;
6147 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
6148 switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
6149 case EC_BREAKPOINT:
6150 case EC_BREAKPOINT_SAME_EL:
6151 moe = 1;
6152 break;
6153 case EC_WATCHPOINT:
6154 case EC_WATCHPOINT_SAME_EL:
6155 moe = 10;
6156 break;
6157 case EC_AA32_BKPT:
6158 moe = 3;
6159 break;
6160 case EC_VECTORCATCH:
6161 moe = 5;
6162 break;
6163 default:
6164 moe = 0;
6165 break;
6168 if (moe) {
6169 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
6172 /* TODO: Vectored interrupt controller. */
6173 switch (cs->exception_index) {
6174 case EXCP_UDEF:
6175 new_mode = ARM_CPU_MODE_UND;
6176 addr = 0x04;
6177 mask = CPSR_I;
6178 if (env->thumb)
6179 offset = 2;
6180 else
6181 offset = 4;
6182 break;
6183 case EXCP_SWI:
6184 new_mode = ARM_CPU_MODE_SVC;
6185 addr = 0x08;
6186 mask = CPSR_I;
6187 /* The PC already points to the next instruction. */
6188 offset = 0;
6189 break;
6190 case EXCP_BKPT:
6191 env->exception.fsr = 2;
6192 /* Fall through to prefetch abort. */
6193 case EXCP_PREFETCH_ABORT:
6194 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
6195 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
6196 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
6197 env->exception.fsr, (uint32_t)env->exception.vaddress);
6198 new_mode = ARM_CPU_MODE_ABT;
6199 addr = 0x0c;
6200 mask = CPSR_A | CPSR_I;
6201 offset = 4;
6202 break;
6203 case EXCP_DATA_ABORT:
6204 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
6205 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
6206 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
6207 env->exception.fsr,
6208 (uint32_t)env->exception.vaddress);
6209 new_mode = ARM_CPU_MODE_ABT;
6210 addr = 0x10;
6211 mask = CPSR_A | CPSR_I;
6212 offset = 8;
6213 break;
6214 case EXCP_IRQ:
6215 new_mode = ARM_CPU_MODE_IRQ;
6216 addr = 0x18;
6217 /* Disable IRQ and imprecise data aborts. */
6218 mask = CPSR_A | CPSR_I;
6219 offset = 4;
6220 if (env->cp15.scr_el3 & SCR_IRQ) {
6221 /* IRQ routed to monitor mode */
6222 new_mode = ARM_CPU_MODE_MON;
6223 mask |= CPSR_F;
6225 break;
6226 case EXCP_FIQ:
6227 new_mode = ARM_CPU_MODE_FIQ;
6228 addr = 0x1c;
6229 /* Disable FIQ, IRQ and imprecise data aborts. */
6230 mask = CPSR_A | CPSR_I | CPSR_F;
6231 if (env->cp15.scr_el3 & SCR_FIQ) {
6232 /* FIQ routed to monitor mode */
6233 new_mode = ARM_CPU_MODE_MON;
6235 offset = 4;
6236 break;
6237 case EXCP_SMC:
6238 new_mode = ARM_CPU_MODE_MON;
6239 addr = 0x08;
6240 mask = CPSR_A | CPSR_I | CPSR_F;
6241 offset = 0;
6242 break;
6243 default:
6244 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6245 return; /* Never happens. Keep compiler happy. */
6248 if (new_mode == ARM_CPU_MODE_MON) {
6249 addr += env->cp15.mvbar;
6250 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
6251 /* High vectors. When enabled, base address cannot be remapped. */
6252 addr += 0xffff0000;
6253 } else {
6254 /* ARM v7 architectures provide a vector base address register to remap
6255 * the interrupt vector table.
6256 * This register is only followed in non-monitor mode, and is banked.
6257 * Note: only bits 31:5 are valid.
6259 addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
6262 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
6263 env->cp15.scr_el3 &= ~SCR_NS;
6266 switch_mode (env, new_mode);
6267 /* For exceptions taken to AArch32 we must clear the SS bit in both
6268 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
6270 env->uncached_cpsr &= ~PSTATE_SS;
6271 env->spsr = cpsr_read(env);
6272 /* Clear IT bits. */
6273 env->condexec_bits = 0;
6274 /* Switch to the new mode, and to the correct instruction set. */
6275 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
6276 /* Set new mode endianness */
6277 env->uncached_cpsr &= ~CPSR_E;
6278 if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
6279 env->uncached_cpsr |= ~CPSR_E;
6281 env->daif |= mask;
6282 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
6283 * and we should just guard the thumb mode on V4 */
6284 if (arm_feature(env, ARM_FEATURE_V4T)) {
6285 env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
6287 env->regs[14] = env->regs[15] + offset;
6288 env->regs[15] = addr;
6291 /* Handle exception entry to a target EL which is using AArch64 */
6292 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
6294 ARMCPU *cpu = ARM_CPU(cs);
6295 CPUARMState *env = &cpu->env;
6296 unsigned int new_el = env->exception.target_el;
6297 target_ulong addr = env->cp15.vbar_el[new_el];
6298 unsigned int new_mode = aarch64_pstate_mode(new_el, true);
6300 if (arm_current_el(env) < new_el) {
6301 /* Entry vector offset depends on whether the implemented EL
6302 * immediately lower than the target level is using AArch32 or AArch64
6304 bool is_aa64;
6306 switch (new_el) {
6307 case 3:
6308 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
6309 break;
6310 case 2:
6311 is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
6312 break;
6313 case 1:
6314 is_aa64 = is_a64(env);
6315 break;
6316 default:
6317 g_assert_not_reached();
6320 if (is_aa64) {
6321 addr += 0x400;
6322 } else {
6323 addr += 0x600;
6325 } else if (pstate_read(env) & PSTATE_SP) {
6326 addr += 0x200;
6329 switch (cs->exception_index) {
6330 case EXCP_PREFETCH_ABORT:
6331 case EXCP_DATA_ABORT:
6332 env->cp15.far_el[new_el] = env->exception.vaddress;
6333 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
6334 env->cp15.far_el[new_el]);
6335 /* fall through */
6336 case EXCP_BKPT:
6337 case EXCP_UDEF:
6338 case EXCP_SWI:
6339 case EXCP_HVC:
6340 case EXCP_HYP_TRAP:
6341 case EXCP_SMC:
6342 env->cp15.esr_el[new_el] = env->exception.syndrome;
6343 break;
6344 case EXCP_IRQ:
6345 case EXCP_VIRQ:
6346 addr += 0x80;
6347 break;
6348 case EXCP_FIQ:
6349 case EXCP_VFIQ:
6350 addr += 0x100;
6351 break;
6352 case EXCP_SEMIHOST:
6353 qemu_log_mask(CPU_LOG_INT,
6354 "...handling as semihosting call 0x%" PRIx64 "\n",
6355 env->xregs[0]);
6356 env->xregs[0] = do_arm_semihosting(env);
6357 return;
6358 default:
6359 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6362 if (is_a64(env)) {
6363 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
6364 aarch64_save_sp(env, arm_current_el(env));
6365 env->elr_el[new_el] = env->pc;
6366 } else {
6367 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
6368 env->elr_el[new_el] = env->regs[15];
6370 aarch64_sync_32_to_64(env);
6372 env->condexec_bits = 0;
6374 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
6375 env->elr_el[new_el]);
6377 pstate_write(env, PSTATE_DAIF | new_mode);
6378 env->aarch64 = 1;
6379 aarch64_restore_sp(env, new_el);
6381 env->pc = addr;
6383 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
6384 new_el, env->pc, pstate_read(env));
6387 static inline bool check_for_semihosting(CPUState *cs)
6389 /* Check whether this exception is a semihosting call; if so
6390 * then handle it and return true; otherwise return false.
6392 ARMCPU *cpu = ARM_CPU(cs);
6393 CPUARMState *env = &cpu->env;
6395 if (is_a64(env)) {
6396 if (cs->exception_index == EXCP_SEMIHOST) {
6397 /* This is always the 64-bit semihosting exception.
6398 * The "is this usermode" and "is semihosting enabled"
6399 * checks have been done at translate time.
6401 qemu_log_mask(CPU_LOG_INT,
6402 "...handling as semihosting call 0x%" PRIx64 "\n",
6403 env->xregs[0]);
6404 env->xregs[0] = do_arm_semihosting(env);
6405 return true;
6407 return false;
6408 } else {
6409 uint32_t imm;
6411 /* Only intercept calls from privileged modes, to provide some
6412 * semblance of security.
6414 if (!semihosting_enabled() ||
6415 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)) {
6416 return false;
6419 switch (cs->exception_index) {
6420 case EXCP_SWI:
6421 /* Check for semihosting interrupt. */
6422 if (env->thumb) {
6423 imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
6424 & 0xff;
6425 if (imm == 0xab) {
6426 break;
6428 } else {
6429 imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env))
6430 & 0xffffff;
6431 if (imm == 0x123456) {
6432 break;
6435 return false;
6436 case EXCP_BKPT:
6437 /* See if this is a semihosting syscall. */
6438 if (env->thumb) {
6439 imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
6440 & 0xff;
6441 if (imm == 0xab) {
6442 env->regs[15] += 2;
6443 break;
6446 return false;
6447 default:
6448 return false;
6451 qemu_log_mask(CPU_LOG_INT,
6452 "...handling as semihosting call 0x%x\n",
6453 env->regs[0]);
6454 env->regs[0] = do_arm_semihosting(env);
6455 return true;
6459 /* Handle a CPU exception for A and R profile CPUs.
6460 * Do any appropriate logging, handle PSCI calls, and then hand off
6461 * to the AArch64-entry or AArch32-entry function depending on the
6462 * target exception level's register width.
6464 void arm_cpu_do_interrupt(CPUState *cs)
6466 ARMCPU *cpu = ARM_CPU(cs);
6467 CPUARMState *env = &cpu->env;
6468 unsigned int new_el = env->exception.target_el;
6470 assert(!IS_M(env));
6472 arm_log_exception(cs->exception_index);
6473 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
6474 new_el);
6475 if (qemu_loglevel_mask(CPU_LOG_INT)
6476 && !excp_is_internal(cs->exception_index)) {
6477 qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n",
6478 env->exception.syndrome >> ARM_EL_EC_SHIFT,
6479 env->exception.syndrome);
6482 if (arm_is_psci_call(cpu, cs->exception_index)) {
6483 arm_handle_psci_call(cpu);
6484 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
6485 return;
6488 /* Semihosting semantics depend on the register width of the
6489 * code that caused the exception, not the target exception level,
6490 * so must be handled here.
6492 if (check_for_semihosting(cs)) {
6493 return;
6496 assert(!excp_is_internal(cs->exception_index));
6497 if (arm_el_is_aa64(env, new_el)) {
6498 arm_cpu_do_interrupt_aarch64(cs);
6499 } else {
6500 arm_cpu_do_interrupt_aarch32(cs);
6503 if (!kvm_enabled()) {
6504 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
6508 /* Return the exception level which controls this address translation regime */
6509 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
6511 switch (mmu_idx) {
6512 case ARMMMUIdx_S2NS:
6513 case ARMMMUIdx_S1E2:
6514 return 2;
6515 case ARMMMUIdx_S1E3:
6516 return 3;
6517 case ARMMMUIdx_S1SE0:
6518 return arm_el_is_aa64(env, 3) ? 1 : 3;
6519 case ARMMMUIdx_S1SE1:
6520 case ARMMMUIdx_S1NSE0:
6521 case ARMMMUIdx_S1NSE1:
6522 return 1;
6523 default:
6524 g_assert_not_reached();
6528 /* Return true if this address translation regime is secure */
6529 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
6531 switch (mmu_idx) {
6532 case ARMMMUIdx_S12NSE0:
6533 case ARMMMUIdx_S12NSE1:
6534 case ARMMMUIdx_S1NSE0:
6535 case ARMMMUIdx_S1NSE1:
6536 case ARMMMUIdx_S1E2:
6537 case ARMMMUIdx_S2NS:
6538 return false;
6539 case ARMMMUIdx_S1E3:
6540 case ARMMMUIdx_S1SE0:
6541 case ARMMMUIdx_S1SE1:
6542 return true;
6543 default:
6544 g_assert_not_reached();
6548 /* Return the SCTLR value which controls this address translation regime */
6549 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
6551 return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
6554 /* Return true if the specified stage of address translation is disabled */
6555 static inline bool regime_translation_disabled(CPUARMState *env,
6556 ARMMMUIdx mmu_idx)
6558 if (mmu_idx == ARMMMUIdx_S2NS) {
6559 return (env->cp15.hcr_el2 & HCR_VM) == 0;
6561 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
6564 static inline bool regime_translation_big_endian(CPUARMState *env,
6565 ARMMMUIdx mmu_idx)
6567 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
6570 /* Return the TCR controlling this translation regime */
6571 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
6573 if (mmu_idx == ARMMMUIdx_S2NS) {
6574 return &env->cp15.vtcr_el2;
6576 return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
6579 /* Return the TTBR associated with this translation regime */
6580 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
6581 int ttbrn)
6583 if (mmu_idx == ARMMMUIdx_S2NS) {
6584 return env->cp15.vttbr_el2;
6586 if (ttbrn == 0) {
6587 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
6588 } else {
6589 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
6593 /* Return true if the translation regime is using LPAE format page tables */
6594 static inline bool regime_using_lpae_format(CPUARMState *env,
6595 ARMMMUIdx mmu_idx)
6597 int el = regime_el(env, mmu_idx);
6598 if (el == 2 || arm_el_is_aa64(env, el)) {
6599 return true;
6601 if (arm_feature(env, ARM_FEATURE_LPAE)
6602 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
6603 return true;
6605 return false;
6608 /* Returns true if the stage 1 translation regime is using LPAE format page
6609 * tables. Used when raising alignment exceptions, whose FSR changes depending
6610 * on whether the long or short descriptor format is in use. */
6611 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
6613 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
6614 mmu_idx += ARMMMUIdx_S1NSE0;
6617 return regime_using_lpae_format(env, mmu_idx);
6620 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
6622 switch (mmu_idx) {
6623 case ARMMMUIdx_S1SE0:
6624 case ARMMMUIdx_S1NSE0:
6625 return true;
6626 default:
6627 return false;
6628 case ARMMMUIdx_S12NSE0:
6629 case ARMMMUIdx_S12NSE1:
6630 g_assert_not_reached();
6634 /* Translate section/page access permissions to page
6635 * R/W protection flags
6637 * @env: CPUARMState
6638 * @mmu_idx: MMU index indicating required translation regime
6639 * @ap: The 3-bit access permissions (AP[2:0])
6640 * @domain_prot: The 2-bit domain access permissions
6642 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
6643 int ap, int domain_prot)
6645 bool is_user = regime_is_user(env, mmu_idx);
6647 if (domain_prot == 3) {
6648 return PAGE_READ | PAGE_WRITE;
6651 switch (ap) {
6652 case 0:
6653 if (arm_feature(env, ARM_FEATURE_V7)) {
6654 return 0;
6656 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
6657 case SCTLR_S:
6658 return is_user ? 0 : PAGE_READ;
6659 case SCTLR_R:
6660 return PAGE_READ;
6661 default:
6662 return 0;
6664 case 1:
6665 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6666 case 2:
6667 if (is_user) {
6668 return PAGE_READ;
6669 } else {
6670 return PAGE_READ | PAGE_WRITE;
6672 case 3:
6673 return PAGE_READ | PAGE_WRITE;
6674 case 4: /* Reserved. */
6675 return 0;
6676 case 5:
6677 return is_user ? 0 : PAGE_READ;
6678 case 6:
6679 return PAGE_READ;
6680 case 7:
6681 if (!arm_feature(env, ARM_FEATURE_V6K)) {
6682 return 0;
6684 return PAGE_READ;
6685 default:
6686 g_assert_not_reached();
6690 /* Translate section/page access permissions to page
6691 * R/W protection flags.
6693 * @ap: The 2-bit simple AP (AP[2:1])
6694 * @is_user: TRUE if accessing from PL0
6696 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
6698 switch (ap) {
6699 case 0:
6700 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6701 case 1:
6702 return PAGE_READ | PAGE_WRITE;
6703 case 2:
6704 return is_user ? 0 : PAGE_READ;
6705 case 3:
6706 return PAGE_READ;
6707 default:
6708 g_assert_not_reached();
6712 static inline int
6713 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
6715 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
6718 /* Translate S2 section/page access permissions to protection flags
6720 * @env: CPUARMState
6721 * @s2ap: The 2-bit stage2 access permissions (S2AP)
6722 * @xn: XN (execute-never) bit
6724 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
6726 int prot = 0;
6728 if (s2ap & 1) {
6729 prot |= PAGE_READ;
6731 if (s2ap & 2) {
6732 prot |= PAGE_WRITE;
6734 if (!xn) {
6735 if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
6736 prot |= PAGE_EXEC;
6739 return prot;
6742 /* Translate section/page access permissions to protection flags
6744 * @env: CPUARMState
6745 * @mmu_idx: MMU index indicating required translation regime
6746 * @is_aa64: TRUE if AArch64
6747 * @ap: The 2-bit simple AP (AP[2:1])
6748 * @ns: NS (non-secure) bit
6749 * @xn: XN (execute-never) bit
6750 * @pxn: PXN (privileged execute-never) bit
6752 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
6753 int ap, int ns, int xn, int pxn)
6755 bool is_user = regime_is_user(env, mmu_idx);
6756 int prot_rw, user_rw;
6757 bool have_wxn;
6758 int wxn = 0;
6760 assert(mmu_idx != ARMMMUIdx_S2NS);
6762 user_rw = simple_ap_to_rw_prot_is_user(ap, true);
6763 if (is_user) {
6764 prot_rw = user_rw;
6765 } else {
6766 prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
6769 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
6770 return prot_rw;
6773 /* TODO have_wxn should be replaced with
6774 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6775 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6776 * compatible processors have EL2, which is required for [U]WXN.
6778 have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
6780 if (have_wxn) {
6781 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
6784 if (is_aa64) {
6785 switch (regime_el(env, mmu_idx)) {
6786 case 1:
6787 if (!is_user) {
6788 xn = pxn || (user_rw & PAGE_WRITE);
6790 break;
6791 case 2:
6792 case 3:
6793 break;
6795 } else if (arm_feature(env, ARM_FEATURE_V7)) {
6796 switch (regime_el(env, mmu_idx)) {
6797 case 1:
6798 case 3:
6799 if (is_user) {
6800 xn = xn || !(user_rw & PAGE_READ);
6801 } else {
6802 int uwxn = 0;
6803 if (have_wxn) {
6804 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
6806 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
6807 (uwxn && (user_rw & PAGE_WRITE));
6809 break;
6810 case 2:
6811 break;
6813 } else {
6814 xn = wxn = 0;
6817 if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
6818 return prot_rw;
6820 return prot_rw | PAGE_EXEC;
6823 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
6824 uint32_t *table, uint32_t address)
6826 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6827 TCR *tcr = regime_tcr(env, mmu_idx);
6829 if (address & tcr->mask) {
6830 if (tcr->raw_tcr & TTBCR_PD1) {
6831 /* Translation table walk disabled for TTBR1 */
6832 return false;
6834 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
6835 } else {
6836 if (tcr->raw_tcr & TTBCR_PD0) {
6837 /* Translation table walk disabled for TTBR0 */
6838 return false;
6840 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
6842 *table |= (address >> 18) & 0x3ffc;
6843 return true;
6846 /* Translate a S1 pagetable walk through S2 if needed. */
6847 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
6848 hwaddr addr, MemTxAttrs txattrs,
6849 uint32_t *fsr,
6850 ARMMMUFaultInfo *fi)
6852 if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
6853 !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
6854 target_ulong s2size;
6855 hwaddr s2pa;
6856 int s2prot;
6857 int ret;
6859 ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
6860 &txattrs, &s2prot, &s2size, fsr, fi);
6861 if (ret) {
6862 fi->s2addr = addr;
6863 fi->stage2 = true;
6864 fi->s1ptw = true;
6865 return ~0;
6867 addr = s2pa;
6869 return addr;
6872 /* All loads done in the course of a page table walk go through here.
6873 * TODO: rather than ignoring errors from physical memory reads (which
6874 * are external aborts in ARM terminology) we should propagate this
6875 * error out so that we can turn it into a Data Abort if this walk
6876 * was being done for a CPU load/store or an address translation instruction
6877 * (but not if it was for a debug access).
6879 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6880 ARMMMUIdx mmu_idx, uint32_t *fsr,
6881 ARMMMUFaultInfo *fi)
6883 ARMCPU *cpu = ARM_CPU(cs);
6884 CPUARMState *env = &cpu->env;
6885 MemTxAttrs attrs = {};
6886 AddressSpace *as;
6888 attrs.secure = is_secure;
6889 as = arm_addressspace(cs, attrs);
6890 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6891 if (fi->s1ptw) {
6892 return 0;
6894 if (regime_translation_big_endian(env, mmu_idx)) {
6895 return address_space_ldl_be(as, addr, attrs, NULL);
6896 } else {
6897 return address_space_ldl_le(as, addr, attrs, NULL);
6901 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6902 ARMMMUIdx mmu_idx, uint32_t *fsr,
6903 ARMMMUFaultInfo *fi)
6905 ARMCPU *cpu = ARM_CPU(cs);
6906 CPUARMState *env = &cpu->env;
6907 MemTxAttrs attrs = {};
6908 AddressSpace *as;
6910 attrs.secure = is_secure;
6911 as = arm_addressspace(cs, attrs);
6912 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6913 if (fi->s1ptw) {
6914 return 0;
6916 if (regime_translation_big_endian(env, mmu_idx)) {
6917 return address_space_ldq_be(as, addr, attrs, NULL);
6918 } else {
6919 return address_space_ldq_le(as, addr, attrs, NULL);
6923 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
6924 int access_type, ARMMMUIdx mmu_idx,
6925 hwaddr *phys_ptr, int *prot,
6926 target_ulong *page_size, uint32_t *fsr,
6927 ARMMMUFaultInfo *fi)
6929 CPUState *cs = CPU(arm_env_get_cpu(env));
6930 int code;
6931 uint32_t table;
6932 uint32_t desc;
6933 int type;
6934 int ap;
6935 int domain = 0;
6936 int domain_prot;
6937 hwaddr phys_addr;
6938 uint32_t dacr;
6940 /* Pagetable walk. */
6941 /* Lookup l1 descriptor. */
6942 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6943 /* Section translation fault if page walk is disabled by PD0 or PD1 */
6944 code = 5;
6945 goto do_fault;
6947 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6948 mmu_idx, fsr, fi);
6949 type = (desc & 3);
6950 domain = (desc >> 5) & 0x0f;
6951 if (regime_el(env, mmu_idx) == 1) {
6952 dacr = env->cp15.dacr_ns;
6953 } else {
6954 dacr = env->cp15.dacr_s;
6956 domain_prot = (dacr >> (domain * 2)) & 3;
6957 if (type == 0) {
6958 /* Section translation fault. */
6959 code = 5;
6960 goto do_fault;
6962 if (domain_prot == 0 || domain_prot == 2) {
6963 if (type == 2)
6964 code = 9; /* Section domain fault. */
6965 else
6966 code = 11; /* Page domain fault. */
6967 goto do_fault;
6969 if (type == 2) {
6970 /* 1Mb section. */
6971 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6972 ap = (desc >> 10) & 3;
6973 code = 13;
6974 *page_size = 1024 * 1024;
6975 } else {
6976 /* Lookup l2 entry. */
6977 if (type == 1) {
6978 /* Coarse pagetable. */
6979 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6980 } else {
6981 /* Fine pagetable. */
6982 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6984 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6985 mmu_idx, fsr, fi);
6986 switch (desc & 3) {
6987 case 0: /* Page translation fault. */
6988 code = 7;
6989 goto do_fault;
6990 case 1: /* 64k page. */
6991 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6992 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6993 *page_size = 0x10000;
6994 break;
6995 case 2: /* 4k page. */
6996 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6997 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6998 *page_size = 0x1000;
6999 break;
7000 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
7001 if (type == 1) {
7002 /* ARMv6/XScale extended small page format */
7003 if (arm_feature(env, ARM_FEATURE_XSCALE)
7004 || arm_feature(env, ARM_FEATURE_V6)) {
7005 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
7006 *page_size = 0x1000;
7007 } else {
7008 /* UNPREDICTABLE in ARMv5; we choose to take a
7009 * page translation fault.
7011 code = 7;
7012 goto do_fault;
7014 } else {
7015 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
7016 *page_size = 0x400;
7018 ap = (desc >> 4) & 3;
7019 break;
7020 default:
7021 /* Never happens, but compiler isn't smart enough to tell. */
7022 abort();
7024 code = 15;
7026 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
7027 *prot |= *prot ? PAGE_EXEC : 0;
7028 if (!(*prot & (1 << access_type))) {
7029 /* Access permission fault. */
7030 goto do_fault;
7032 *phys_ptr = phys_addr;
7033 return false;
7034 do_fault:
7035 *fsr = code | (domain << 4);
7036 return true;
7039 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
7040 int access_type, ARMMMUIdx mmu_idx,
7041 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7042 target_ulong *page_size, uint32_t *fsr,
7043 ARMMMUFaultInfo *fi)
7045 CPUState *cs = CPU(arm_env_get_cpu(env));
7046 int code;
7047 uint32_t table;
7048 uint32_t desc;
7049 uint32_t xn;
7050 uint32_t pxn = 0;
7051 int type;
7052 int ap;
7053 int domain = 0;
7054 int domain_prot;
7055 hwaddr phys_addr;
7056 uint32_t dacr;
7057 bool ns;
7059 /* Pagetable walk. */
7060 /* Lookup l1 descriptor. */
7061 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
7062 /* Section translation fault if page walk is disabled by PD0 or PD1 */
7063 code = 5;
7064 goto do_fault;
7066 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7067 mmu_idx, fsr, fi);
7068 type = (desc & 3);
7069 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
7070 /* Section translation fault, or attempt to use the encoding
7071 * which is Reserved on implementations without PXN.
7073 code = 5;
7074 goto do_fault;
7076 if ((type == 1) || !(desc & (1 << 18))) {
7077 /* Page or Section. */
7078 domain = (desc >> 5) & 0x0f;
7080 if (regime_el(env, mmu_idx) == 1) {
7081 dacr = env->cp15.dacr_ns;
7082 } else {
7083 dacr = env->cp15.dacr_s;
7085 domain_prot = (dacr >> (domain * 2)) & 3;
7086 if (domain_prot == 0 || domain_prot == 2) {
7087 if (type != 1) {
7088 code = 9; /* Section domain fault. */
7089 } else {
7090 code = 11; /* Page domain fault. */
7092 goto do_fault;
7094 if (type != 1) {
7095 if (desc & (1 << 18)) {
7096 /* Supersection. */
7097 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
7098 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
7099 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
7100 *page_size = 0x1000000;
7101 } else {
7102 /* Section. */
7103 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
7104 *page_size = 0x100000;
7106 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
7107 xn = desc & (1 << 4);
7108 pxn = desc & 1;
7109 code = 13;
7110 ns = extract32(desc, 19, 1);
7111 } else {
7112 if (arm_feature(env, ARM_FEATURE_PXN)) {
7113 pxn = (desc >> 2) & 1;
7115 ns = extract32(desc, 3, 1);
7116 /* Lookup l2 entry. */
7117 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
7118 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7119 mmu_idx, fsr, fi);
7120 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
7121 switch (desc & 3) {
7122 case 0: /* Page translation fault. */
7123 code = 7;
7124 goto do_fault;
7125 case 1: /* 64k page. */
7126 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
7127 xn = desc & (1 << 15);
7128 *page_size = 0x10000;
7129 break;
7130 case 2: case 3: /* 4k page. */
7131 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
7132 xn = desc & 1;
7133 *page_size = 0x1000;
7134 break;
7135 default:
7136 /* Never happens, but compiler isn't smart enough to tell. */
7137 abort();
7139 code = 15;
7141 if (domain_prot == 3) {
7142 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7143 } else {
7144 if (pxn && !regime_is_user(env, mmu_idx)) {
7145 xn = 1;
7147 if (xn && access_type == 2)
7148 goto do_fault;
7150 if (arm_feature(env, ARM_FEATURE_V6K) &&
7151 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
7152 /* The simplified model uses AP[0] as an access control bit. */
7153 if ((ap & 1) == 0) {
7154 /* Access flag fault. */
7155 code = (code == 15) ? 6 : 3;
7156 goto do_fault;
7158 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
7159 } else {
7160 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
7162 if (*prot && !xn) {
7163 *prot |= PAGE_EXEC;
7165 if (!(*prot & (1 << access_type))) {
7166 /* Access permission fault. */
7167 goto do_fault;
7170 if (ns) {
7171 /* The NS bit will (as required by the architecture) have no effect if
7172 * the CPU doesn't support TZ or this is a non-secure translation
7173 * regime, because the attribute will already be non-secure.
7175 attrs->secure = false;
7177 *phys_ptr = phys_addr;
7178 return false;
7179 do_fault:
7180 *fsr = code | (domain << 4);
7181 return true;
7184 /* Fault type for long-descriptor MMU fault reporting; this corresponds
7185 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
7187 typedef enum {
7188 translation_fault = 1,
7189 access_fault = 2,
7190 permission_fault = 3,
7191 } MMUFaultType;
7194 * check_s2_mmu_setup
7195 * @cpu: ARMCPU
7196 * @is_aa64: True if the translation regime is in AArch64 state
7197 * @startlevel: Suggested starting level
7198 * @inputsize: Bitsize of IPAs
7199 * @stride: Page-table stride (See the ARM ARM)
7201 * Returns true if the suggested S2 translation parameters are OK and
7202 * false otherwise.
7204 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
7205 int inputsize, int stride)
7207 const int grainsize = stride + 3;
7208 int startsizecheck;
7210 /* Negative levels are never allowed. */
7211 if (level < 0) {
7212 return false;
7215 startsizecheck = inputsize - ((3 - level) * stride + grainsize);
7216 if (startsizecheck < 1 || startsizecheck > stride + 4) {
7217 return false;
7220 if (is_aa64) {
7221 CPUARMState *env = &cpu->env;
7222 unsigned int pamax = arm_pamax(cpu);
7224 switch (stride) {
7225 case 13: /* 64KB Pages. */
7226 if (level == 0 || (level == 1 && pamax <= 42)) {
7227 return false;
7229 break;
7230 case 11: /* 16KB Pages. */
7231 if (level == 0 || (level == 1 && pamax <= 40)) {
7232 return false;
7234 break;
7235 case 9: /* 4KB Pages. */
7236 if (level == 0 && pamax <= 42) {
7237 return false;
7239 break;
7240 default:
7241 g_assert_not_reached();
7244 /* Inputsize checks. */
7245 if (inputsize > pamax &&
7246 (arm_el_is_aa64(env, 1) || inputsize > 40)) {
7247 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
7248 return false;
7250 } else {
7251 /* AArch32 only supports 4KB pages. Assert on that. */
7252 assert(stride == 9);
7254 if (level == 0) {
7255 return false;
7258 return true;
7261 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
7262 int access_type, ARMMMUIdx mmu_idx,
7263 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
7264 target_ulong *page_size_ptr, uint32_t *fsr,
7265 ARMMMUFaultInfo *fi)
7267 ARMCPU *cpu = arm_env_get_cpu(env);
7268 CPUState *cs = CPU(cpu);
7269 /* Read an LPAE long-descriptor translation table. */
7270 MMUFaultType fault_type = translation_fault;
7271 uint32_t level;
7272 uint32_t epd = 0;
7273 int32_t t0sz, t1sz;
7274 uint32_t tg;
7275 uint64_t ttbr;
7276 int ttbr_select;
7277 hwaddr descaddr, indexmask, indexmask_grainsize;
7278 uint32_t tableattrs;
7279 target_ulong page_size;
7280 uint32_t attrs;
7281 int32_t stride = 9;
7282 int32_t addrsize;
7283 int inputsize;
7284 int32_t tbi = 0;
7285 TCR *tcr = regime_tcr(env, mmu_idx);
7286 int ap, ns, xn, pxn;
7287 uint32_t el = regime_el(env, mmu_idx);
7288 bool ttbr1_valid = true;
7289 uint64_t descaddrmask;
7290 bool aarch64 = arm_el_is_aa64(env, el);
7292 /* TODO:
7293 * This code does not handle the different format TCR for VTCR_EL2.
7294 * This code also does not support shareability levels.
7295 * Attribute and permission bit handling should also be checked when adding
7296 * support for those page table walks.
7298 if (aarch64) {
7299 level = 0;
7300 addrsize = 64;
7301 if (el > 1) {
7302 if (mmu_idx != ARMMMUIdx_S2NS) {
7303 tbi = extract64(tcr->raw_tcr, 20, 1);
7305 } else {
7306 if (extract64(address, 55, 1)) {
7307 tbi = extract64(tcr->raw_tcr, 38, 1);
7308 } else {
7309 tbi = extract64(tcr->raw_tcr, 37, 1);
7312 tbi *= 8;
7314 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
7315 * invalid.
7317 if (el > 1) {
7318 ttbr1_valid = false;
7320 } else {
7321 level = 1;
7322 addrsize = 32;
7323 /* There is no TTBR1 for EL2 */
7324 if (el == 2) {
7325 ttbr1_valid = false;
7329 /* Determine whether this address is in the region controlled by
7330 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
7331 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
7332 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
7334 if (aarch64) {
7335 /* AArch64 translation. */
7336 t0sz = extract32(tcr->raw_tcr, 0, 6);
7337 t0sz = MIN(t0sz, 39);
7338 t0sz = MAX(t0sz, 16);
7339 } else if (mmu_idx != ARMMMUIdx_S2NS) {
7340 /* AArch32 stage 1 translation. */
7341 t0sz = extract32(tcr->raw_tcr, 0, 3);
7342 } else {
7343 /* AArch32 stage 2 translation. */
7344 bool sext = extract32(tcr->raw_tcr, 4, 1);
7345 bool sign = extract32(tcr->raw_tcr, 3, 1);
7346 /* Address size is 40-bit for a stage 2 translation,
7347 * and t0sz can be negative (from -8 to 7),
7348 * so we need to adjust it to use the TTBR selecting logic below.
7350 addrsize = 40;
7351 t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8;
7353 /* If the sign-extend bit is not the same as t0sz[3], the result
7354 * is unpredictable. Flag this as a guest error. */
7355 if (sign != sext) {
7356 qemu_log_mask(LOG_GUEST_ERROR,
7357 "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
7360 t1sz = extract32(tcr->raw_tcr, 16, 6);
7361 if (aarch64) {
7362 t1sz = MIN(t1sz, 39);
7363 t1sz = MAX(t1sz, 16);
7365 if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) {
7366 /* there is a ttbr0 region and we are in it (high bits all zero) */
7367 ttbr_select = 0;
7368 } else if (ttbr1_valid && t1sz &&
7369 !extract64(~address, addrsize - t1sz, t1sz - tbi)) {
7370 /* there is a ttbr1 region and we are in it (high bits all one) */
7371 ttbr_select = 1;
7372 } else if (!t0sz) {
7373 /* ttbr0 region is "everything not in the ttbr1 region" */
7374 ttbr_select = 0;
7375 } else if (!t1sz && ttbr1_valid) {
7376 /* ttbr1 region is "everything not in the ttbr0 region" */
7377 ttbr_select = 1;
7378 } else {
7379 /* in the gap between the two regions, this is a Translation fault */
7380 fault_type = translation_fault;
7381 goto do_fault;
7384 /* Note that QEMU ignores shareability and cacheability attributes,
7385 * so we don't need to do anything with the SH, ORGN, IRGN fields
7386 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
7387 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
7388 * implement any ASID-like capability so we can ignore it (instead
7389 * we will always flush the TLB any time the ASID is changed).
7391 if (ttbr_select == 0) {
7392 ttbr = regime_ttbr(env, mmu_idx, 0);
7393 if (el < 2) {
7394 epd = extract32(tcr->raw_tcr, 7, 1);
7396 inputsize = addrsize - t0sz;
7398 tg = extract32(tcr->raw_tcr, 14, 2);
7399 if (tg == 1) { /* 64KB pages */
7400 stride = 13;
7402 if (tg == 2) { /* 16KB pages */
7403 stride = 11;
7405 } else {
7406 /* We should only be here if TTBR1 is valid */
7407 assert(ttbr1_valid);
7409 ttbr = regime_ttbr(env, mmu_idx, 1);
7410 epd = extract32(tcr->raw_tcr, 23, 1);
7411 inputsize = addrsize - t1sz;
7413 tg = extract32(tcr->raw_tcr, 30, 2);
7414 if (tg == 3) { /* 64KB pages */
7415 stride = 13;
7417 if (tg == 1) { /* 16KB pages */
7418 stride = 11;
7422 /* Here we should have set up all the parameters for the translation:
7423 * inputsize, ttbr, epd, stride, tbi
7426 if (epd) {
7427 /* Translation table walk disabled => Translation fault on TLB miss
7428 * Note: This is always 0 on 64-bit EL2 and EL3.
7430 goto do_fault;
7433 if (mmu_idx != ARMMMUIdx_S2NS) {
7434 /* The starting level depends on the virtual address size (which can
7435 * be up to 48 bits) and the translation granule size. It indicates
7436 * the number of strides (stride bits at a time) needed to
7437 * consume the bits of the input address. In the pseudocode this is:
7438 * level = 4 - RoundUp((inputsize - grainsize) / stride)
7439 * where their 'inputsize' is our 'inputsize', 'grainsize' is
7440 * our 'stride + 3' and 'stride' is our 'stride'.
7441 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
7442 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
7443 * = 4 - (inputsize - 4) / stride;
7445 level = 4 - (inputsize - 4) / stride;
7446 } else {
7447 /* For stage 2 translations the starting level is specified by the
7448 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
7450 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
7451 uint32_t startlevel;
7452 bool ok;
7454 if (!aarch64 || stride == 9) {
7455 /* AArch32 or 4KB pages */
7456 startlevel = 2 - sl0;
7457 } else {
7458 /* 16KB or 64KB pages */
7459 startlevel = 3 - sl0;
7462 /* Check that the starting level is valid. */
7463 ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
7464 inputsize, stride);
7465 if (!ok) {
7466 fault_type = translation_fault;
7467 goto do_fault;
7469 level = startlevel;
7472 indexmask_grainsize = (1ULL << (stride + 3)) - 1;
7473 indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
7475 /* Now we can extract the actual base address from the TTBR */
7476 descaddr = extract64(ttbr, 0, 48);
7477 descaddr &= ~indexmask;
7479 /* The address field in the descriptor goes up to bit 39 for ARMv7
7480 * but up to bit 47 for ARMv8, but we use the descaddrmask
7481 * up to bit 39 for AArch32, because we don't need other bits in that case
7482 * to construct next descriptor address (anyway they should be all zeroes).
7484 descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) &
7485 ~indexmask_grainsize;
7487 /* Secure accesses start with the page table in secure memory and
7488 * can be downgraded to non-secure at any step. Non-secure accesses
7489 * remain non-secure. We implement this by just ORing in the NSTable/NS
7490 * bits at each step.
7492 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
7493 for (;;) {
7494 uint64_t descriptor;
7495 bool nstable;
7497 descaddr |= (address >> (stride * (4 - level))) & indexmask;
7498 descaddr &= ~7ULL;
7499 nstable = extract32(tableattrs, 4, 1);
7500 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi);
7501 if (fi->s1ptw) {
7502 goto do_fault;
7505 if (!(descriptor & 1) ||
7506 (!(descriptor & 2) && (level == 3))) {
7507 /* Invalid, or the Reserved level 3 encoding */
7508 goto do_fault;
7510 descaddr = descriptor & descaddrmask;
7512 if ((descriptor & 2) && (level < 3)) {
7513 /* Table entry. The top five bits are attributes which may
7514 * propagate down through lower levels of the table (and
7515 * which are all arranged so that 0 means "no effect", so
7516 * we can gather them up by ORing in the bits at each level).
7518 tableattrs |= extract64(descriptor, 59, 5);
7519 level++;
7520 indexmask = indexmask_grainsize;
7521 continue;
7523 /* Block entry at level 1 or 2, or page entry at level 3.
7524 * These are basically the same thing, although the number
7525 * of bits we pull in from the vaddr varies.
7527 page_size = (1ULL << ((stride * (4 - level)) + 3));
7528 descaddr |= (address & (page_size - 1));
7529 /* Extract attributes from the descriptor */
7530 attrs = extract64(descriptor, 2, 10)
7531 | (extract64(descriptor, 52, 12) << 10);
7533 if (mmu_idx == ARMMMUIdx_S2NS) {
7534 /* Stage 2 table descriptors do not include any attribute fields */
7535 break;
7537 /* Merge in attributes from table descriptors */
7538 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
7539 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
7540 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
7541 * means "force PL1 access only", which means forcing AP[1] to 0.
7543 if (extract32(tableattrs, 2, 1)) {
7544 attrs &= ~(1 << 4);
7546 attrs |= nstable << 3; /* NS */
7547 break;
7549 /* Here descaddr is the final physical address, and attributes
7550 * are all in attrs.
7552 fault_type = access_fault;
7553 if ((attrs & (1 << 8)) == 0) {
7554 /* Access flag */
7555 goto do_fault;
7558 ap = extract32(attrs, 4, 2);
7559 xn = extract32(attrs, 12, 1);
7561 if (mmu_idx == ARMMMUIdx_S2NS) {
7562 ns = true;
7563 *prot = get_S2prot(env, ap, xn);
7564 } else {
7565 ns = extract32(attrs, 3, 1);
7566 pxn = extract32(attrs, 11, 1);
7567 *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
7570 fault_type = permission_fault;
7571 if (!(*prot & (1 << access_type))) {
7572 goto do_fault;
7575 if (ns) {
7576 /* The NS bit will (as required by the architecture) have no effect if
7577 * the CPU doesn't support TZ or this is a non-secure translation
7578 * regime, because the attribute will already be non-secure.
7580 txattrs->secure = false;
7582 *phys_ptr = descaddr;
7583 *page_size_ptr = page_size;
7584 return false;
7586 do_fault:
7587 /* Long-descriptor format IFSR/DFSR value */
7588 *fsr = (1 << 9) | (fault_type << 2) | level;
7589 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
7590 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
7591 return true;
7594 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
7595 ARMMMUIdx mmu_idx,
7596 int32_t address, int *prot)
7598 *prot = PAGE_READ | PAGE_WRITE;
7599 switch (address) {
7600 case 0xF0000000 ... 0xFFFFFFFF:
7601 if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
7602 *prot |= PAGE_EXEC;
7604 break;
7605 case 0x00000000 ... 0x7FFFFFFF:
7606 *prot |= PAGE_EXEC;
7607 break;
7612 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
7613 int access_type, ARMMMUIdx mmu_idx,
7614 hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7616 ARMCPU *cpu = arm_env_get_cpu(env);
7617 int n;
7618 bool is_user = regime_is_user(env, mmu_idx);
7620 *phys_ptr = address;
7621 *prot = 0;
7623 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
7624 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7625 } else { /* MPU enabled */
7626 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
7627 /* region search */
7628 uint32_t base = env->pmsav7.drbar[n];
7629 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
7630 uint32_t rmask;
7631 bool srdis = false;
7633 if (!(env->pmsav7.drsr[n] & 0x1)) {
7634 continue;
7637 if (!rsize) {
7638 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
7639 continue;
7641 rsize++;
7642 rmask = (1ull << rsize) - 1;
7644 if (base & rmask) {
7645 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
7646 "to DRSR region size, mask = %" PRIx32,
7647 base, rmask);
7648 continue;
7651 if (address < base || address > base + rmask) {
7652 continue;
7655 /* Region matched */
7657 if (rsize >= 8) { /* no subregions for regions < 256 bytes */
7658 int i, snd;
7659 uint32_t srdis_mask;
7661 rsize -= 3; /* sub region size (power of 2) */
7662 snd = ((address - base) >> rsize) & 0x7;
7663 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
7665 srdis_mask = srdis ? 0x3 : 0x0;
7666 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
7667 /* This will check in groups of 2, 4 and then 8, whether
7668 * the subregion bits are consistent. rsize is incremented
7669 * back up to give the region size, considering consistent
7670 * adjacent subregions as one region. Stop testing if rsize
7671 * is already big enough for an entire QEMU page.
7673 int snd_rounded = snd & ~(i - 1);
7674 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
7675 snd_rounded + 8, i);
7676 if (srdis_mask ^ srdis_multi) {
7677 break;
7679 srdis_mask = (srdis_mask << i) | srdis_mask;
7680 rsize++;
7683 if (rsize < TARGET_PAGE_BITS) {
7684 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
7685 "alignment of %" PRIu32 " bits. Minimum is %d\n",
7686 rsize, TARGET_PAGE_BITS);
7687 continue;
7689 if (srdis) {
7690 continue;
7692 break;
7695 if (n == -1) { /* no hits */
7696 if (cpu->pmsav7_dregion &&
7697 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
7698 /* background fault */
7699 *fsr = 0;
7700 return true;
7702 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7703 } else { /* a MPU hit! */
7704 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
7706 if (is_user) { /* User mode AP bit decoding */
7707 switch (ap) {
7708 case 0:
7709 case 1:
7710 case 5:
7711 break; /* no access */
7712 case 3:
7713 *prot |= PAGE_WRITE;
7714 /* fall through */
7715 case 2:
7716 case 6:
7717 *prot |= PAGE_READ | PAGE_EXEC;
7718 break;
7719 default:
7720 qemu_log_mask(LOG_GUEST_ERROR,
7721 "Bad value for AP bits in DRACR %"
7722 PRIx32 "\n", ap);
7724 } else { /* Priv. mode AP bits decoding */
7725 switch (ap) {
7726 case 0:
7727 break; /* no access */
7728 case 1:
7729 case 2:
7730 case 3:
7731 *prot |= PAGE_WRITE;
7732 /* fall through */
7733 case 5:
7734 case 6:
7735 *prot |= PAGE_READ | PAGE_EXEC;
7736 break;
7737 default:
7738 qemu_log_mask(LOG_GUEST_ERROR,
7739 "Bad value for AP bits in DRACR %"
7740 PRIx32 "\n", ap);
7744 /* execute never */
7745 if (env->pmsav7.dracr[n] & (1 << 12)) {
7746 *prot &= ~PAGE_EXEC;
7751 *fsr = 0x00d; /* Permission fault */
7752 return !(*prot & (1 << access_type));
7755 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
7756 int access_type, ARMMMUIdx mmu_idx,
7757 hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7759 int n;
7760 uint32_t mask;
7761 uint32_t base;
7762 bool is_user = regime_is_user(env, mmu_idx);
7764 *phys_ptr = address;
7765 for (n = 7; n >= 0; n--) {
7766 base = env->cp15.c6_region[n];
7767 if ((base & 1) == 0) {
7768 continue;
7770 mask = 1 << ((base >> 1) & 0x1f);
7771 /* Keep this shift separate from the above to avoid an
7772 (undefined) << 32. */
7773 mask = (mask << 1) - 1;
7774 if (((base ^ address) & ~mask) == 0) {
7775 break;
7778 if (n < 0) {
7779 *fsr = 2;
7780 return true;
7783 if (access_type == 2) {
7784 mask = env->cp15.pmsav5_insn_ap;
7785 } else {
7786 mask = env->cp15.pmsav5_data_ap;
7788 mask = (mask >> (n * 4)) & 0xf;
7789 switch (mask) {
7790 case 0:
7791 *fsr = 1;
7792 return true;
7793 case 1:
7794 if (is_user) {
7795 *fsr = 1;
7796 return true;
7798 *prot = PAGE_READ | PAGE_WRITE;
7799 break;
7800 case 2:
7801 *prot = PAGE_READ;
7802 if (!is_user) {
7803 *prot |= PAGE_WRITE;
7805 break;
7806 case 3:
7807 *prot = PAGE_READ | PAGE_WRITE;
7808 break;
7809 case 5:
7810 if (is_user) {
7811 *fsr = 1;
7812 return true;
7814 *prot = PAGE_READ;
7815 break;
7816 case 6:
7817 *prot = PAGE_READ;
7818 break;
7819 default:
7820 /* Bad permission. */
7821 *fsr = 1;
7822 return true;
7824 *prot |= PAGE_EXEC;
7825 return false;
7828 /* get_phys_addr - get the physical address for this virtual address
7830 * Find the physical address corresponding to the given virtual address,
7831 * by doing a translation table walk on MMU based systems or using the
7832 * MPU state on MPU based systems.
7834 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
7835 * prot and page_size may not be filled in, and the populated fsr value provides
7836 * information on why the translation aborted, in the format of a
7837 * DFSR/IFSR fault register, with the following caveats:
7838 * * we honour the short vs long DFSR format differences.
7839 * * the WnR bit is never set (the caller must do this).
7840 * * for PSMAv5 based systems we don't bother to return a full FSR format
7841 * value.
7843 * @env: CPUARMState
7844 * @address: virtual address to get physical address for
7845 * @access_type: 0 for read, 1 for write, 2 for execute
7846 * @mmu_idx: MMU index indicating required translation regime
7847 * @phys_ptr: set to the physical address corresponding to the virtual address
7848 * @attrs: set to the memory transaction attributes to use
7849 * @prot: set to the permissions for the page containing phys_ptr
7850 * @page_size: set to the size of the page containing phys_ptr
7851 * @fsr: set to the DFSR/IFSR value on failure
7853 static bool get_phys_addr(CPUARMState *env, target_ulong address,
7854 int access_type, ARMMMUIdx mmu_idx,
7855 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7856 target_ulong *page_size, uint32_t *fsr,
7857 ARMMMUFaultInfo *fi)
7859 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
7860 /* Call ourselves recursively to do the stage 1 and then stage 2
7861 * translations.
7863 if (arm_feature(env, ARM_FEATURE_EL2)) {
7864 hwaddr ipa;
7865 int s2_prot;
7866 int ret;
7868 ret = get_phys_addr(env, address, access_type,
7869 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
7870 prot, page_size, fsr, fi);
7872 /* If S1 fails or S2 is disabled, return early. */
7873 if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
7874 *phys_ptr = ipa;
7875 return ret;
7878 /* S1 is done. Now do S2 translation. */
7879 ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
7880 phys_ptr, attrs, &s2_prot,
7881 page_size, fsr, fi);
7882 fi->s2addr = ipa;
7883 /* Combine the S1 and S2 perms. */
7884 *prot &= s2_prot;
7885 return ret;
7886 } else {
7888 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
7890 mmu_idx += ARMMMUIdx_S1NSE0;
7894 /* The page table entries may downgrade secure to non-secure, but
7895 * cannot upgrade an non-secure translation regime's attributes
7896 * to secure.
7898 attrs->secure = regime_is_secure(env, mmu_idx);
7899 attrs->user = regime_is_user(env, mmu_idx);
7901 /* Fast Context Switch Extension. This doesn't exist at all in v8.
7902 * In v7 and earlier it affects all stage 1 translations.
7904 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
7905 && !arm_feature(env, ARM_FEATURE_V8)) {
7906 if (regime_el(env, mmu_idx) == 3) {
7907 address += env->cp15.fcseidr_s;
7908 } else {
7909 address += env->cp15.fcseidr_ns;
7913 /* pmsav7 has special handling for when MPU is disabled so call it before
7914 * the common MMU/MPU disabled check below.
7916 if (arm_feature(env, ARM_FEATURE_MPU) &&
7917 arm_feature(env, ARM_FEATURE_V7)) {
7918 *page_size = TARGET_PAGE_SIZE;
7919 return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
7920 phys_ptr, prot, fsr);
7923 if (regime_translation_disabled(env, mmu_idx)) {
7924 /* MMU/MPU disabled. */
7925 *phys_ptr = address;
7926 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7927 *page_size = TARGET_PAGE_SIZE;
7928 return 0;
7931 if (arm_feature(env, ARM_FEATURE_MPU)) {
7932 /* Pre-v7 MPU */
7933 *page_size = TARGET_PAGE_SIZE;
7934 return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
7935 phys_ptr, prot, fsr);
7938 if (regime_using_lpae_format(env, mmu_idx)) {
7939 return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
7940 attrs, prot, page_size, fsr, fi);
7941 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
7942 return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
7943 attrs, prot, page_size, fsr, fi);
7944 } else {
7945 return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
7946 prot, page_size, fsr, fi);
7950 /* Walk the page table and (if the mapping exists) add the page
7951 * to the TLB. Return false on success, or true on failure. Populate
7952 * fsr with ARM DFSR/IFSR fault register format value on failure.
7954 bool arm_tlb_fill(CPUState *cs, vaddr address,
7955 int access_type, int mmu_idx, uint32_t *fsr,
7956 ARMMMUFaultInfo *fi)
7958 ARMCPU *cpu = ARM_CPU(cs);
7959 CPUARMState *env = &cpu->env;
7960 hwaddr phys_addr;
7961 target_ulong page_size;
7962 int prot;
7963 int ret;
7964 MemTxAttrs attrs = {};
7966 ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
7967 &attrs, &prot, &page_size, fsr, fi);
7968 if (!ret) {
7969 /* Map a single [sub]page. */
7970 phys_addr &= TARGET_PAGE_MASK;
7971 address &= TARGET_PAGE_MASK;
7972 tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
7973 prot, mmu_idx, page_size);
7974 return 0;
7977 return ret;
7980 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
7981 MemTxAttrs *attrs)
7983 ARMCPU *cpu = ARM_CPU(cs);
7984 CPUARMState *env = &cpu->env;
7985 hwaddr phys_addr;
7986 target_ulong page_size;
7987 int prot;
7988 bool ret;
7989 uint32_t fsr;
7990 ARMMMUFaultInfo fi = {};
7992 *attrs = (MemTxAttrs) {};
7994 ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
7995 attrs, &prot, &page_size, &fsr, &fi);
7997 if (ret) {
7998 return -1;
8000 return phys_addr;
8003 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
8005 ARMCPU *cpu = arm_env_get_cpu(env);
8007 switch (reg) {
8008 case 0: /* APSR */
8009 return xpsr_read(env) & 0xf8000000;
8010 case 1: /* IAPSR */
8011 return xpsr_read(env) & 0xf80001ff;
8012 case 2: /* EAPSR */
8013 return xpsr_read(env) & 0xff00fc00;
8014 case 3: /* xPSR */
8015 return xpsr_read(env) & 0xff00fdff;
8016 case 5: /* IPSR */
8017 return xpsr_read(env) & 0x000001ff;
8018 case 6: /* EPSR */
8019 return xpsr_read(env) & 0x0700fc00;
8020 case 7: /* IEPSR */
8021 return xpsr_read(env) & 0x0700edff;
8022 case 8: /* MSP */
8023 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
8024 case 9: /* PSP */
8025 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
8026 case 16: /* PRIMASK */
8027 return (env->daif & PSTATE_I) != 0;
8028 case 17: /* BASEPRI */
8029 case 18: /* BASEPRI_MAX */
8030 return env->v7m.basepri;
8031 case 19: /* FAULTMASK */
8032 return (env->daif & PSTATE_F) != 0;
8033 case 20: /* CONTROL */
8034 return env->v7m.control;
8035 default:
8036 /* ??? For debugging only. */
8037 cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
8038 return 0;
8042 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
8044 ARMCPU *cpu = arm_env_get_cpu(env);
8046 switch (reg) {
8047 case 0: /* APSR */
8048 xpsr_write(env, val, 0xf8000000);
8049 break;
8050 case 1: /* IAPSR */
8051 xpsr_write(env, val, 0xf8000000);
8052 break;
8053 case 2: /* EAPSR */
8054 xpsr_write(env, val, 0xfe00fc00);
8055 break;
8056 case 3: /* xPSR */
8057 xpsr_write(env, val, 0xfe00fc00);
8058 break;
8059 case 5: /* IPSR */
8060 /* IPSR bits are readonly. */
8061 break;
8062 case 6: /* EPSR */
8063 xpsr_write(env, val, 0x0600fc00);
8064 break;
8065 case 7: /* IEPSR */
8066 xpsr_write(env, val, 0x0600fc00);
8067 break;
8068 case 8: /* MSP */
8069 if (env->v7m.current_sp)
8070 env->v7m.other_sp = val;
8071 else
8072 env->regs[13] = val;
8073 break;
8074 case 9: /* PSP */
8075 if (env->v7m.current_sp)
8076 env->regs[13] = val;
8077 else
8078 env->v7m.other_sp = val;
8079 break;
8080 case 16: /* PRIMASK */
8081 if (val & 1) {
8082 env->daif |= PSTATE_I;
8083 } else {
8084 env->daif &= ~PSTATE_I;
8086 break;
8087 case 17: /* BASEPRI */
8088 env->v7m.basepri = val & 0xff;
8089 break;
8090 case 18: /* BASEPRI_MAX */
8091 val &= 0xff;
8092 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
8093 env->v7m.basepri = val;
8094 break;
8095 case 19: /* FAULTMASK */
8096 if (val & 1) {
8097 env->daif |= PSTATE_F;
8098 } else {
8099 env->daif &= ~PSTATE_F;
8101 break;
8102 case 20: /* CONTROL */
8103 env->v7m.control = val & 3;
8104 switch_v7m_sp(env, (val & 2) != 0);
8105 break;
8106 default:
8107 /* ??? For debugging only. */
8108 cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
8109 return;
8113 #endif
8115 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
8117 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
8118 * Note that we do not implement the (architecturally mandated)
8119 * alignment fault for attempts to use this on Device memory
8120 * (which matches the usual QEMU behaviour of not implementing either
8121 * alignment faults or any memory attribute handling).
8124 ARMCPU *cpu = arm_env_get_cpu(env);
8125 uint64_t blocklen = 4 << cpu->dcz_blocksize;
8126 uint64_t vaddr = vaddr_in & ~(blocklen - 1);
8128 #ifndef CONFIG_USER_ONLY
8130 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
8131 * the block size so we might have to do more than one TLB lookup.
8132 * We know that in fact for any v8 CPU the page size is at least 4K
8133 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
8134 * 1K as an artefact of legacy v5 subpage support being present in the
8135 * same QEMU executable.
8137 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
8138 void *hostaddr[maxidx];
8139 int try, i;
8140 unsigned mmu_idx = cpu_mmu_index(env, false);
8141 TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
8143 for (try = 0; try < 2; try++) {
8145 for (i = 0; i < maxidx; i++) {
8146 hostaddr[i] = tlb_vaddr_to_host(env,
8147 vaddr + TARGET_PAGE_SIZE * i,
8148 1, mmu_idx);
8149 if (!hostaddr[i]) {
8150 break;
8153 if (i == maxidx) {
8154 /* If it's all in the TLB it's fair game for just writing to;
8155 * we know we don't need to update dirty status, etc.
8157 for (i = 0; i < maxidx - 1; i++) {
8158 memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
8160 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
8161 return;
8163 /* OK, try a store and see if we can populate the tlb. This
8164 * might cause an exception if the memory isn't writable,
8165 * in which case we will longjmp out of here. We must for
8166 * this purpose use the actual register value passed to us
8167 * so that we get the fault address right.
8169 helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
8170 /* Now we can populate the other TLB entries, if any */
8171 for (i = 0; i < maxidx; i++) {
8172 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
8173 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
8174 helper_ret_stb_mmu(env, va, 0, oi, GETRA());
8179 /* Slow path (probably attempt to do this to an I/O device or
8180 * similar, or clearing of a block of code we have translations
8181 * cached for). Just do a series of byte writes as the architecture
8182 * demands. It's not worth trying to use a cpu_physical_memory_map(),
8183 * memset(), unmap() sequence here because:
8184 * + we'd need to account for the blocksize being larger than a page
8185 * + the direct-RAM access case is almost always going to be dealt
8186 * with in the fastpath code above, so there's no speed benefit
8187 * + we would have to deal with the map returning NULL because the
8188 * bounce buffer was in use
8190 for (i = 0; i < blocklen; i++) {
8191 helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
8194 #else
8195 memset(g2h(vaddr), 0, blocklen);
8196 #endif
8199 /* Note that signed overflow is undefined in C. The following routines are
8200 careful to use unsigned types where modulo arithmetic is required.
8201 Failure to do so _will_ break on newer gcc. */
8203 /* Signed saturating arithmetic. */
8205 /* Perform 16-bit signed saturating addition. */
8206 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
8208 uint16_t res;
8210 res = a + b;
8211 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
8212 if (a & 0x8000)
8213 res = 0x8000;
8214 else
8215 res = 0x7fff;
8217 return res;
8220 /* Perform 8-bit signed saturating addition. */
8221 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
8223 uint8_t res;
8225 res = a + b;
8226 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
8227 if (a & 0x80)
8228 res = 0x80;
8229 else
8230 res = 0x7f;
8232 return res;
8235 /* Perform 16-bit signed saturating subtraction. */
8236 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
8238 uint16_t res;
8240 res = a - b;
8241 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
8242 if (a & 0x8000)
8243 res = 0x8000;
8244 else
8245 res = 0x7fff;
8247 return res;
8250 /* Perform 8-bit signed saturating subtraction. */
8251 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
8253 uint8_t res;
8255 res = a - b;
8256 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
8257 if (a & 0x80)
8258 res = 0x80;
8259 else
8260 res = 0x7f;
8262 return res;
8265 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
8266 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
8267 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
8268 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
8269 #define PFX q
8271 #include "op_addsub.h"
8273 /* Unsigned saturating arithmetic. */
8274 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
8276 uint16_t res;
8277 res = a + b;
8278 if (res < a)
8279 res = 0xffff;
8280 return res;
8283 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
8285 if (a > b)
8286 return a - b;
8287 else
8288 return 0;
8291 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
8293 uint8_t res;
8294 res = a + b;
8295 if (res < a)
8296 res = 0xff;
8297 return res;
8300 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
8302 if (a > b)
8303 return a - b;
8304 else
8305 return 0;
8308 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
8309 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
8310 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
8311 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
8312 #define PFX uq
8314 #include "op_addsub.h"
8316 /* Signed modulo arithmetic. */
8317 #define SARITH16(a, b, n, op) do { \
8318 int32_t sum; \
8319 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
8320 RESULT(sum, n, 16); \
8321 if (sum >= 0) \
8322 ge |= 3 << (n * 2); \
8323 } while(0)
8325 #define SARITH8(a, b, n, op) do { \
8326 int32_t sum; \
8327 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
8328 RESULT(sum, n, 8); \
8329 if (sum >= 0) \
8330 ge |= 1 << n; \
8331 } while(0)
8334 #define ADD16(a, b, n) SARITH16(a, b, n, +)
8335 #define SUB16(a, b, n) SARITH16(a, b, n, -)
8336 #define ADD8(a, b, n) SARITH8(a, b, n, +)
8337 #define SUB8(a, b, n) SARITH8(a, b, n, -)
8338 #define PFX s
8339 #define ARITH_GE
8341 #include "op_addsub.h"
8343 /* Unsigned modulo arithmetic. */
8344 #define ADD16(a, b, n) do { \
8345 uint32_t sum; \
8346 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
8347 RESULT(sum, n, 16); \
8348 if ((sum >> 16) == 1) \
8349 ge |= 3 << (n * 2); \
8350 } while(0)
8352 #define ADD8(a, b, n) do { \
8353 uint32_t sum; \
8354 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
8355 RESULT(sum, n, 8); \
8356 if ((sum >> 8) == 1) \
8357 ge |= 1 << n; \
8358 } while(0)
8360 #define SUB16(a, b, n) do { \
8361 uint32_t sum; \
8362 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
8363 RESULT(sum, n, 16); \
8364 if ((sum >> 16) == 0) \
8365 ge |= 3 << (n * 2); \
8366 } while(0)
8368 #define SUB8(a, b, n) do { \
8369 uint32_t sum; \
8370 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
8371 RESULT(sum, n, 8); \
8372 if ((sum >> 8) == 0) \
8373 ge |= 1 << n; \
8374 } while(0)
8376 #define PFX u
8377 #define ARITH_GE
8379 #include "op_addsub.h"
8381 /* Halved signed arithmetic. */
8382 #define ADD16(a, b, n) \
8383 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
8384 #define SUB16(a, b, n) \
8385 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
8386 #define ADD8(a, b, n) \
8387 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
8388 #define SUB8(a, b, n) \
8389 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
8390 #define PFX sh
8392 #include "op_addsub.h"
8394 /* Halved unsigned arithmetic. */
8395 #define ADD16(a, b, n) \
8396 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8397 #define SUB16(a, b, n) \
8398 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8399 #define ADD8(a, b, n) \
8400 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8401 #define SUB8(a, b, n) \
8402 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8403 #define PFX uh
8405 #include "op_addsub.h"
8407 static inline uint8_t do_usad(uint8_t a, uint8_t b)
8409 if (a > b)
8410 return a - b;
8411 else
8412 return b - a;
8415 /* Unsigned sum of absolute byte differences. */
8416 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
8418 uint32_t sum;
8419 sum = do_usad(a, b);
8420 sum += do_usad(a >> 8, b >> 8);
8421 sum += do_usad(a >> 16, b >>16);
8422 sum += do_usad(a >> 24, b >> 24);
8423 return sum;
8426 /* For ARMv6 SEL instruction. */
8427 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
8429 uint32_t mask;
8431 mask = 0;
8432 if (flags & 1)
8433 mask |= 0xff;
8434 if (flags & 2)
8435 mask |= 0xff00;
8436 if (flags & 4)
8437 mask |= 0xff0000;
8438 if (flags & 8)
8439 mask |= 0xff000000;
8440 return (a & mask) | (b & ~mask);
8443 /* VFP support. We follow the convention used for VFP instructions:
8444 Single precision routines have a "s" suffix, double precision a
8445 "d" suffix. */
8447 /* Convert host exception flags to vfp form. */
8448 static inline int vfp_exceptbits_from_host(int host_bits)
8450 int target_bits = 0;
8452 if (host_bits & float_flag_invalid)
8453 target_bits |= 1;
8454 if (host_bits & float_flag_divbyzero)
8455 target_bits |= 2;
8456 if (host_bits & float_flag_overflow)
8457 target_bits |= 4;
8458 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
8459 target_bits |= 8;
8460 if (host_bits & float_flag_inexact)
8461 target_bits |= 0x10;
8462 if (host_bits & float_flag_input_denormal)
8463 target_bits |= 0x80;
8464 return target_bits;
8467 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
8469 int i;
8470 uint32_t fpscr;
8472 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
8473 | (env->vfp.vec_len << 16)
8474 | (env->vfp.vec_stride << 20);
8475 i = get_float_exception_flags(&env->vfp.fp_status);
8476 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
8477 fpscr |= vfp_exceptbits_from_host(i);
8478 return fpscr;
8481 uint32_t vfp_get_fpscr(CPUARMState *env)
8483 return HELPER(vfp_get_fpscr)(env);
8486 /* Convert vfp exception flags to target form. */
8487 static inline int vfp_exceptbits_to_host(int target_bits)
8489 int host_bits = 0;
8491 if (target_bits & 1)
8492 host_bits |= float_flag_invalid;
8493 if (target_bits & 2)
8494 host_bits |= float_flag_divbyzero;
8495 if (target_bits & 4)
8496 host_bits |= float_flag_overflow;
8497 if (target_bits & 8)
8498 host_bits |= float_flag_underflow;
8499 if (target_bits & 0x10)
8500 host_bits |= float_flag_inexact;
8501 if (target_bits & 0x80)
8502 host_bits |= float_flag_input_denormal;
8503 return host_bits;
8506 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
8508 int i;
8509 uint32_t changed;
8511 changed = env->vfp.xregs[ARM_VFP_FPSCR];
8512 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
8513 env->vfp.vec_len = (val >> 16) & 7;
8514 env->vfp.vec_stride = (val >> 20) & 3;
8516 changed ^= val;
8517 if (changed & (3 << 22)) {
8518 i = (val >> 22) & 3;
8519 switch (i) {
8520 case FPROUNDING_TIEEVEN:
8521 i = float_round_nearest_even;
8522 break;
8523 case FPROUNDING_POSINF:
8524 i = float_round_up;
8525 break;
8526 case FPROUNDING_NEGINF:
8527 i = float_round_down;
8528 break;
8529 case FPROUNDING_ZERO:
8530 i = float_round_to_zero;
8531 break;
8533 set_float_rounding_mode(i, &env->vfp.fp_status);
8535 if (changed & (1 << 24)) {
8536 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8537 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8539 if (changed & (1 << 25))
8540 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
8542 i = vfp_exceptbits_to_host(val);
8543 set_float_exception_flags(i, &env->vfp.fp_status);
8544 set_float_exception_flags(0, &env->vfp.standard_fp_status);
8547 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
8549 HELPER(vfp_set_fpscr)(env, val);
8552 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
8554 #define VFP_BINOP(name) \
8555 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
8557 float_status *fpst = fpstp; \
8558 return float32_ ## name(a, b, fpst); \
8560 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
8562 float_status *fpst = fpstp; \
8563 return float64_ ## name(a, b, fpst); \
8565 VFP_BINOP(add)
8566 VFP_BINOP(sub)
8567 VFP_BINOP(mul)
8568 VFP_BINOP(div)
8569 VFP_BINOP(min)
8570 VFP_BINOP(max)
8571 VFP_BINOP(minnum)
8572 VFP_BINOP(maxnum)
8573 #undef VFP_BINOP
8575 float32 VFP_HELPER(neg, s)(float32 a)
8577 return float32_chs(a);
8580 float64 VFP_HELPER(neg, d)(float64 a)
8582 return float64_chs(a);
8585 float32 VFP_HELPER(abs, s)(float32 a)
8587 return float32_abs(a);
8590 float64 VFP_HELPER(abs, d)(float64 a)
8592 return float64_abs(a);
8595 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
8597 return float32_sqrt(a, &env->vfp.fp_status);
8600 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
8602 return float64_sqrt(a, &env->vfp.fp_status);
8605 /* XXX: check quiet/signaling case */
8606 #define DO_VFP_cmp(p, type) \
8607 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
8609 uint32_t flags; \
8610 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
8611 case 0: flags = 0x6; break; \
8612 case -1: flags = 0x8; break; \
8613 case 1: flags = 0x2; break; \
8614 default: case 2: flags = 0x3; break; \
8616 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8617 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8619 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
8621 uint32_t flags; \
8622 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
8623 case 0: flags = 0x6; break; \
8624 case -1: flags = 0x8; break; \
8625 case 1: flags = 0x2; break; \
8626 default: case 2: flags = 0x3; break; \
8628 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8629 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8631 DO_VFP_cmp(s, float32)
8632 DO_VFP_cmp(d, float64)
8633 #undef DO_VFP_cmp
8635 /* Integer to float and float to integer conversions */
8637 #define CONV_ITOF(name, fsz, sign) \
8638 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
8640 float_status *fpst = fpstp; \
8641 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
8644 #define CONV_FTOI(name, fsz, sign, round) \
8645 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8647 float_status *fpst = fpstp; \
8648 if (float##fsz##_is_any_nan(x)) { \
8649 float_raise(float_flag_invalid, fpst); \
8650 return 0; \
8652 return float##fsz##_to_##sign##int32##round(x, fpst); \
8655 #define FLOAT_CONVS(name, p, fsz, sign) \
8656 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
8657 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
8658 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
8660 FLOAT_CONVS(si, s, 32, )
8661 FLOAT_CONVS(si, d, 64, )
8662 FLOAT_CONVS(ui, s, 32, u)
8663 FLOAT_CONVS(ui, d, 64, u)
8665 #undef CONV_ITOF
8666 #undef CONV_FTOI
8667 #undef FLOAT_CONVS
8669 /* floating point conversion */
8670 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
8672 float64 r = float32_to_float64(x, &env->vfp.fp_status);
8673 /* ARM requires that S<->D conversion of any kind of NaN generates
8674 * a quiet NaN by forcing the most significant frac bit to 1.
8676 return float64_maybe_silence_nan(r);
8679 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
8681 float32 r = float64_to_float32(x, &env->vfp.fp_status);
8682 /* ARM requires that S<->D conversion of any kind of NaN generates
8683 * a quiet NaN by forcing the most significant frac bit to 1.
8685 return float32_maybe_silence_nan(r);
8688 /* VFP3 fixed point conversion. */
8689 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8690 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
8691 void *fpstp) \
8693 float_status *fpst = fpstp; \
8694 float##fsz tmp; \
8695 tmp = itype##_to_##float##fsz(x, fpst); \
8696 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
8699 /* Notice that we want only input-denormal exception flags from the
8700 * scalbn operation: the other possible flags (overflow+inexact if
8701 * we overflow to infinity, output-denormal) aren't correct for the
8702 * complete scale-and-convert operation.
8704 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
8705 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
8706 uint32_t shift, \
8707 void *fpstp) \
8709 float_status *fpst = fpstp; \
8710 int old_exc_flags = get_float_exception_flags(fpst); \
8711 float##fsz tmp; \
8712 if (float##fsz##_is_any_nan(x)) { \
8713 float_raise(float_flag_invalid, fpst); \
8714 return 0; \
8716 tmp = float##fsz##_scalbn(x, shift, fpst); \
8717 old_exc_flags |= get_float_exception_flags(fpst) \
8718 & float_flag_input_denormal; \
8719 set_float_exception_flags(old_exc_flags, fpst); \
8720 return float##fsz##_to_##itype##round(tmp, fpst); \
8723 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
8724 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8725 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
8726 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8728 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
8729 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8730 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8732 VFP_CONV_FIX(sh, d, 64, 64, int16)
8733 VFP_CONV_FIX(sl, d, 64, 64, int32)
8734 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
8735 VFP_CONV_FIX(uh, d, 64, 64, uint16)
8736 VFP_CONV_FIX(ul, d, 64, 64, uint32)
8737 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
8738 VFP_CONV_FIX(sh, s, 32, 32, int16)
8739 VFP_CONV_FIX(sl, s, 32, 32, int32)
8740 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
8741 VFP_CONV_FIX(uh, s, 32, 32, uint16)
8742 VFP_CONV_FIX(ul, s, 32, 32, uint32)
8743 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
8744 #undef VFP_CONV_FIX
8745 #undef VFP_CONV_FIX_FLOAT
8746 #undef VFP_CONV_FLOAT_FIX_ROUND
8748 /* Set the current fp rounding mode and return the old one.
8749 * The argument is a softfloat float_round_ value.
8751 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
8753 float_status *fp_status = &env->vfp.fp_status;
8755 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8756 set_float_rounding_mode(rmode, fp_status);
8758 return prev_rmode;
8761 /* Set the current fp rounding mode in the standard fp status and return
8762 * the old one. This is for NEON instructions that need to change the
8763 * rounding mode but wish to use the standard FPSCR values for everything
8764 * else. Always set the rounding mode back to the correct value after
8765 * modifying it.
8766 * The argument is a softfloat float_round_ value.
8768 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
8770 float_status *fp_status = &env->vfp.standard_fp_status;
8772 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8773 set_float_rounding_mode(rmode, fp_status);
8775 return prev_rmode;
8778 /* Half precision conversions. */
8779 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
8781 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8782 float32 r = float16_to_float32(make_float16(a), ieee, s);
8783 if (ieee) {
8784 return float32_maybe_silence_nan(r);
8786 return r;
8789 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
8791 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8792 float16 r = float32_to_float16(a, ieee, s);
8793 if (ieee) {
8794 r = float16_maybe_silence_nan(r);
8796 return float16_val(r);
8799 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8801 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
8804 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8806 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
8809 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8811 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
8814 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8816 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
8819 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
8821 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8822 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
8823 if (ieee) {
8824 return float64_maybe_silence_nan(r);
8826 return r;
8829 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
8831 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8832 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
8833 if (ieee) {
8834 r = float16_maybe_silence_nan(r);
8836 return float16_val(r);
8839 #define float32_two make_float32(0x40000000)
8840 #define float32_three make_float32(0x40400000)
8841 #define float32_one_point_five make_float32(0x3fc00000)
8843 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
8845 float_status *s = &env->vfp.standard_fp_status;
8846 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8847 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8848 if (!(float32_is_zero(a) || float32_is_zero(b))) {
8849 float_raise(float_flag_input_denormal, s);
8851 return float32_two;
8853 return float32_sub(float32_two, float32_mul(a, b, s), s);
8856 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
8858 float_status *s = &env->vfp.standard_fp_status;
8859 float32 product;
8860 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8861 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8862 if (!(float32_is_zero(a) || float32_is_zero(b))) {
8863 float_raise(float_flag_input_denormal, s);
8865 return float32_one_point_five;
8867 product = float32_mul(a, b, s);
8868 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
8871 /* NEON helpers. */
8873 /* Constants 256 and 512 are used in some helpers; we avoid relying on
8874 * int->float conversions at run-time. */
8875 #define float64_256 make_float64(0x4070000000000000LL)
8876 #define float64_512 make_float64(0x4080000000000000LL)
8877 #define float32_maxnorm make_float32(0x7f7fffff)
8878 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
8880 /* Reciprocal functions
8882 * The algorithm that must be used to calculate the estimate
8883 * is specified by the ARM ARM, see FPRecipEstimate()
8886 static float64 recip_estimate(float64 a, float_status *real_fp_status)
8888 /* These calculations mustn't set any fp exception flags,
8889 * so we use a local copy of the fp_status.
8891 float_status dummy_status = *real_fp_status;
8892 float_status *s = &dummy_status;
8893 /* q = (int)(a * 512.0) */
8894 float64 q = float64_mul(float64_512, a, s);
8895 int64_t q_int = float64_to_int64_round_to_zero(q, s);
8897 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
8898 q = int64_to_float64(q_int, s);
8899 q = float64_add(q, float64_half, s);
8900 q = float64_div(q, float64_512, s);
8901 q = float64_div(float64_one, q, s);
8903 /* s = (int)(256.0 * r + 0.5) */
8904 q = float64_mul(q, float64_256, s);
8905 q = float64_add(q, float64_half, s);
8906 q_int = float64_to_int64_round_to_zero(q, s);
8908 /* return (double)s / 256.0 */
8909 return float64_div(int64_to_float64(q_int, s), float64_256, s);
8912 /* Common wrapper to call recip_estimate */
8913 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
8915 uint64_t val64 = float64_val(num);
8916 uint64_t frac = extract64(val64, 0, 52);
8917 int64_t exp = extract64(val64, 52, 11);
8918 uint64_t sbit;
8919 float64 scaled, estimate;
8921 /* Generate the scaled number for the estimate function */
8922 if (exp == 0) {
8923 if (extract64(frac, 51, 1) == 0) {
8924 exp = -1;
8925 frac = extract64(frac, 0, 50) << 2;
8926 } else {
8927 frac = extract64(frac, 0, 51) << 1;
8931 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
8932 scaled = make_float64((0x3feULL << 52)
8933 | extract64(frac, 44, 8) << 44);
8935 estimate = recip_estimate(scaled, fpst);
8937 /* Build new result */
8938 val64 = float64_val(estimate);
8939 sbit = 0x8000000000000000ULL & val64;
8940 exp = off - exp;
8941 frac = extract64(val64, 0, 52);
8943 if (exp == 0) {
8944 frac = 1ULL << 51 | extract64(frac, 1, 51);
8945 } else if (exp == -1) {
8946 frac = 1ULL << 50 | extract64(frac, 2, 50);
8947 exp = 0;
8950 return make_float64(sbit | (exp << 52) | frac);
8953 static bool round_to_inf(float_status *fpst, bool sign_bit)
8955 switch (fpst->float_rounding_mode) {
8956 case float_round_nearest_even: /* Round to Nearest */
8957 return true;
8958 case float_round_up: /* Round to +Inf */
8959 return !sign_bit;
8960 case float_round_down: /* Round to -Inf */
8961 return sign_bit;
8962 case float_round_to_zero: /* Round to Zero */
8963 return false;
8966 g_assert_not_reached();
8969 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
8971 float_status *fpst = fpstp;
8972 float32 f32 = float32_squash_input_denormal(input, fpst);
8973 uint32_t f32_val = float32_val(f32);
8974 uint32_t f32_sbit = 0x80000000ULL & f32_val;
8975 int32_t f32_exp = extract32(f32_val, 23, 8);
8976 uint32_t f32_frac = extract32(f32_val, 0, 23);
8977 float64 f64, r64;
8978 uint64_t r64_val;
8979 int64_t r64_exp;
8980 uint64_t r64_frac;
8982 if (float32_is_any_nan(f32)) {
8983 float32 nan = f32;
8984 if (float32_is_signaling_nan(f32)) {
8985 float_raise(float_flag_invalid, fpst);
8986 nan = float32_maybe_silence_nan(f32);
8988 if (fpst->default_nan_mode) {
8989 nan = float32_default_nan;
8991 return nan;
8992 } else if (float32_is_infinity(f32)) {
8993 return float32_set_sign(float32_zero, float32_is_neg(f32));
8994 } else if (float32_is_zero(f32)) {
8995 float_raise(float_flag_divbyzero, fpst);
8996 return float32_set_sign(float32_infinity, float32_is_neg(f32));
8997 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
8998 /* Abs(value) < 2.0^-128 */
8999 float_raise(float_flag_overflow | float_flag_inexact, fpst);
9000 if (round_to_inf(fpst, f32_sbit)) {
9001 return float32_set_sign(float32_infinity, float32_is_neg(f32));
9002 } else {
9003 return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
9005 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
9006 float_raise(float_flag_underflow, fpst);
9007 return float32_set_sign(float32_zero, float32_is_neg(f32));
9011 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
9012 r64 = call_recip_estimate(f64, 253, fpst);
9013 r64_val = float64_val(r64);
9014 r64_exp = extract64(r64_val, 52, 11);
9015 r64_frac = extract64(r64_val, 0, 52);
9017 /* result = sign : result_exp<7:0> : fraction<51:29>; */
9018 return make_float32(f32_sbit |
9019 (r64_exp & 0xff) << 23 |
9020 extract64(r64_frac, 29, 24));
9023 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
9025 float_status *fpst = fpstp;
9026 float64 f64 = float64_squash_input_denormal(input, fpst);
9027 uint64_t f64_val = float64_val(f64);
9028 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
9029 int64_t f64_exp = extract64(f64_val, 52, 11);
9030 float64 r64;
9031 uint64_t r64_val;
9032 int64_t r64_exp;
9033 uint64_t r64_frac;
9035 /* Deal with any special cases */
9036 if (float64_is_any_nan(f64)) {
9037 float64 nan = f64;
9038 if (float64_is_signaling_nan(f64)) {
9039 float_raise(float_flag_invalid, fpst);
9040 nan = float64_maybe_silence_nan(f64);
9042 if (fpst->default_nan_mode) {
9043 nan = float64_default_nan;
9045 return nan;
9046 } else if (float64_is_infinity(f64)) {
9047 return float64_set_sign(float64_zero, float64_is_neg(f64));
9048 } else if (float64_is_zero(f64)) {
9049 float_raise(float_flag_divbyzero, fpst);
9050 return float64_set_sign(float64_infinity, float64_is_neg(f64));
9051 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
9052 /* Abs(value) < 2.0^-1024 */
9053 float_raise(float_flag_overflow | float_flag_inexact, fpst);
9054 if (round_to_inf(fpst, f64_sbit)) {
9055 return float64_set_sign(float64_infinity, float64_is_neg(f64));
9056 } else {
9057 return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
9059 } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
9060 float_raise(float_flag_underflow, fpst);
9061 return float64_set_sign(float64_zero, float64_is_neg(f64));
9064 r64 = call_recip_estimate(f64, 2045, fpst);
9065 r64_val = float64_val(r64);
9066 r64_exp = extract64(r64_val, 52, 11);
9067 r64_frac = extract64(r64_val, 0, 52);
9069 /* result = sign : result_exp<10:0> : fraction<51:0> */
9070 return make_float64(f64_sbit |
9071 ((r64_exp & 0x7ff) << 52) |
9072 r64_frac);
9075 /* The algorithm that must be used to calculate the estimate
9076 * is specified by the ARM ARM.
9078 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
9080 /* These calculations mustn't set any fp exception flags,
9081 * so we use a local copy of the fp_status.
9083 float_status dummy_status = *real_fp_status;
9084 float_status *s = &dummy_status;
9085 float64 q;
9086 int64_t q_int;
9088 if (float64_lt(a, float64_half, s)) {
9089 /* range 0.25 <= a < 0.5 */
9091 /* a in units of 1/512 rounded down */
9092 /* q0 = (int)(a * 512.0); */
9093 q = float64_mul(float64_512, a, s);
9094 q_int = float64_to_int64_round_to_zero(q, s);
9096 /* reciprocal root r */
9097 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
9098 q = int64_to_float64(q_int, s);
9099 q = float64_add(q, float64_half, s);
9100 q = float64_div(q, float64_512, s);
9101 q = float64_sqrt(q, s);
9102 q = float64_div(float64_one, q, s);
9103 } else {
9104 /* range 0.5 <= a < 1.0 */
9106 /* a in units of 1/256 rounded down */
9107 /* q1 = (int)(a * 256.0); */
9108 q = float64_mul(float64_256, a, s);
9109 int64_t q_int = float64_to_int64_round_to_zero(q, s);
9111 /* reciprocal root r */
9112 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
9113 q = int64_to_float64(q_int, s);
9114 q = float64_add(q, float64_half, s);
9115 q = float64_div(q, float64_256, s);
9116 q = float64_sqrt(q, s);
9117 q = float64_div(float64_one, q, s);
9119 /* r in units of 1/256 rounded to nearest */
9120 /* s = (int)(256.0 * r + 0.5); */
9122 q = float64_mul(q, float64_256,s );
9123 q = float64_add(q, float64_half, s);
9124 q_int = float64_to_int64_round_to_zero(q, s);
9126 /* return (double)s / 256.0;*/
9127 return float64_div(int64_to_float64(q_int, s), float64_256, s);
9130 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
9132 float_status *s = fpstp;
9133 float32 f32 = float32_squash_input_denormal(input, s);
9134 uint32_t val = float32_val(f32);
9135 uint32_t f32_sbit = 0x80000000 & val;
9136 int32_t f32_exp = extract32(val, 23, 8);
9137 uint32_t f32_frac = extract32(val, 0, 23);
9138 uint64_t f64_frac;
9139 uint64_t val64;
9140 int result_exp;
9141 float64 f64;
9143 if (float32_is_any_nan(f32)) {
9144 float32 nan = f32;
9145 if (float32_is_signaling_nan(f32)) {
9146 float_raise(float_flag_invalid, s);
9147 nan = float32_maybe_silence_nan(f32);
9149 if (s->default_nan_mode) {
9150 nan = float32_default_nan;
9152 return nan;
9153 } else if (float32_is_zero(f32)) {
9154 float_raise(float_flag_divbyzero, s);
9155 return float32_set_sign(float32_infinity, float32_is_neg(f32));
9156 } else if (float32_is_neg(f32)) {
9157 float_raise(float_flag_invalid, s);
9158 return float32_default_nan;
9159 } else if (float32_is_infinity(f32)) {
9160 return float32_zero;
9163 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9164 * preserving the parity of the exponent. */
9166 f64_frac = ((uint64_t) f32_frac) << 29;
9167 if (f32_exp == 0) {
9168 while (extract64(f64_frac, 51, 1) == 0) {
9169 f64_frac = f64_frac << 1;
9170 f32_exp = f32_exp-1;
9172 f64_frac = extract64(f64_frac, 0, 51) << 1;
9175 if (extract64(f32_exp, 0, 1) == 0) {
9176 f64 = make_float64(((uint64_t) f32_sbit) << 32
9177 | (0x3feULL << 52)
9178 | f64_frac);
9179 } else {
9180 f64 = make_float64(((uint64_t) f32_sbit) << 32
9181 | (0x3fdULL << 52)
9182 | f64_frac);
9185 result_exp = (380 - f32_exp) / 2;
9187 f64 = recip_sqrt_estimate(f64, s);
9189 val64 = float64_val(f64);
9191 val = ((result_exp & 0xff) << 23)
9192 | ((val64 >> 29) & 0x7fffff);
9193 return make_float32(val);
9196 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
9198 float_status *s = fpstp;
9199 float64 f64 = float64_squash_input_denormal(input, s);
9200 uint64_t val = float64_val(f64);
9201 uint64_t f64_sbit = 0x8000000000000000ULL & val;
9202 int64_t f64_exp = extract64(val, 52, 11);
9203 uint64_t f64_frac = extract64(val, 0, 52);
9204 int64_t result_exp;
9205 uint64_t result_frac;
9207 if (float64_is_any_nan(f64)) {
9208 float64 nan = f64;
9209 if (float64_is_signaling_nan(f64)) {
9210 float_raise(float_flag_invalid, s);
9211 nan = float64_maybe_silence_nan(f64);
9213 if (s->default_nan_mode) {
9214 nan = float64_default_nan;
9216 return nan;
9217 } else if (float64_is_zero(f64)) {
9218 float_raise(float_flag_divbyzero, s);
9219 return float64_set_sign(float64_infinity, float64_is_neg(f64));
9220 } else if (float64_is_neg(f64)) {
9221 float_raise(float_flag_invalid, s);
9222 return float64_default_nan;
9223 } else if (float64_is_infinity(f64)) {
9224 return float64_zero;
9227 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9228 * preserving the parity of the exponent. */
9230 if (f64_exp == 0) {
9231 while (extract64(f64_frac, 51, 1) == 0) {
9232 f64_frac = f64_frac << 1;
9233 f64_exp = f64_exp - 1;
9235 f64_frac = extract64(f64_frac, 0, 51) << 1;
9238 if (extract64(f64_exp, 0, 1) == 0) {
9239 f64 = make_float64(f64_sbit
9240 | (0x3feULL << 52)
9241 | f64_frac);
9242 } else {
9243 f64 = make_float64(f64_sbit
9244 | (0x3fdULL << 52)
9245 | f64_frac);
9248 result_exp = (3068 - f64_exp) / 2;
9250 f64 = recip_sqrt_estimate(f64, s);
9252 result_frac = extract64(float64_val(f64), 0, 52);
9254 return make_float64(f64_sbit |
9255 ((result_exp & 0x7ff) << 52) |
9256 result_frac);
9259 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
9261 float_status *s = fpstp;
9262 float64 f64;
9264 if ((a & 0x80000000) == 0) {
9265 return 0xffffffff;
9268 f64 = make_float64((0x3feULL << 52)
9269 | ((int64_t)(a & 0x7fffffff) << 21));
9271 f64 = recip_estimate(f64, s);
9273 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
9276 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
9278 float_status *fpst = fpstp;
9279 float64 f64;
9281 if ((a & 0xc0000000) == 0) {
9282 return 0xffffffff;
9285 if (a & 0x80000000) {
9286 f64 = make_float64((0x3feULL << 52)
9287 | ((uint64_t)(a & 0x7fffffff) << 21));
9288 } else { /* bits 31-30 == '01' */
9289 f64 = make_float64((0x3fdULL << 52)
9290 | ((uint64_t)(a & 0x3fffffff) << 22));
9293 f64 = recip_sqrt_estimate(f64, fpst);
9295 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
9298 /* VFPv4 fused multiply-accumulate */
9299 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
9301 float_status *fpst = fpstp;
9302 return float32_muladd(a, b, c, 0, fpst);
9305 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
9307 float_status *fpst = fpstp;
9308 return float64_muladd(a, b, c, 0, fpst);
9311 /* ARMv8 round to integral */
9312 float32 HELPER(rints_exact)(float32 x, void *fp_status)
9314 return float32_round_to_int(x, fp_status);
9317 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
9319 return float64_round_to_int(x, fp_status);
9322 float32 HELPER(rints)(float32 x, void *fp_status)
9324 int old_flags = get_float_exception_flags(fp_status), new_flags;
9325 float32 ret;
9327 ret = float32_round_to_int(x, fp_status);
9329 /* Suppress any inexact exceptions the conversion produced */
9330 if (!(old_flags & float_flag_inexact)) {
9331 new_flags = get_float_exception_flags(fp_status);
9332 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9335 return ret;
9338 float64 HELPER(rintd)(float64 x, void *fp_status)
9340 int old_flags = get_float_exception_flags(fp_status), new_flags;
9341 float64 ret;
9343 ret = float64_round_to_int(x, fp_status);
9345 new_flags = get_float_exception_flags(fp_status);
9347 /* Suppress any inexact exceptions the conversion produced */
9348 if (!(old_flags & float_flag_inexact)) {
9349 new_flags = get_float_exception_flags(fp_status);
9350 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9353 return ret;
9356 /* Convert ARM rounding mode to softfloat */
9357 int arm_rmode_to_sf(int rmode)
9359 switch (rmode) {
9360 case FPROUNDING_TIEAWAY:
9361 rmode = float_round_ties_away;
9362 break;
9363 case FPROUNDING_ODD:
9364 /* FIXME: add support for TIEAWAY and ODD */
9365 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
9366 rmode);
9367 case FPROUNDING_TIEEVEN:
9368 default:
9369 rmode = float_round_nearest_even;
9370 break;
9371 case FPROUNDING_POSINF:
9372 rmode = float_round_up;
9373 break;
9374 case FPROUNDING_NEGINF:
9375 rmode = float_round_down;
9376 break;
9377 case FPROUNDING_ZERO:
9378 rmode = float_round_to_zero;
9379 break;
9381 return rmode;
9384 /* CRC helpers.
9385 * The upper bytes of val (above the number specified by 'bytes') must have
9386 * been zeroed out by the caller.
9388 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
9390 uint8_t buf[4];
9392 stl_le_p(buf, val);
9394 /* zlib crc32 converts the accumulator and output to one's complement. */
9395 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
9398 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
9400 uint8_t buf[4];
9402 stl_le_p(buf, val);
9404 /* Linux crc32c converts the output to one's complement. */
9405 return crc32c(acc, buf, bytes) ^ 0xffffffff;