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include/qemu: Added tsan.h for annotations.
[qemu.git] / hw / arm / allwinner-h3.c
blobf10674da5a8afc9c2ec4064ee9577334742e5098
1 /*
2 * Allwinner H3 System on Chip emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/error.h"
23 #include "qemu/error-report.h"
24 #include "qemu/module.h"
25 #include "qemu/units.h"
26 #include "hw/qdev-core.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "hw/char/serial.h"
30 #include "hw/misc/unimp.h"
31 #include "hw/usb/hcd-ehci.h"
32 #include "hw/loader.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/arm/allwinner-h3.h"
35
36 /* Memory map */
37 const hwaddr allwinner_h3_memmap[] = {
38 [AW_H3_SRAM_A1] = 0x00000000,
39 [AW_H3_SRAM_A2] = 0x00044000,
40 [AW_H3_SRAM_C] = 0x00010000,
41 [AW_H3_SYSCTRL] = 0x01c00000,
42 [AW_H3_MMC0] = 0x01c0f000,
43 [AW_H3_SID] = 0x01c14000,
44 [AW_H3_EHCI0] = 0x01c1a000,
45 [AW_H3_OHCI0] = 0x01c1a400,
46 [AW_H3_EHCI1] = 0x01c1b000,
47 [AW_H3_OHCI1] = 0x01c1b400,
48 [AW_H3_EHCI2] = 0x01c1c000,
49 [AW_H3_OHCI2] = 0x01c1c400,
50 [AW_H3_EHCI3] = 0x01c1d000,
51 [AW_H3_OHCI3] = 0x01c1d400,
52 [AW_H3_CCU] = 0x01c20000,
53 [AW_H3_PIT] = 0x01c20c00,
54 [AW_H3_UART0] = 0x01c28000,
55 [AW_H3_UART1] = 0x01c28400,
56 [AW_H3_UART2] = 0x01c28800,
57 [AW_H3_UART3] = 0x01c28c00,
58 [AW_H3_EMAC] = 0x01c30000,
59 [AW_H3_DRAMCOM] = 0x01c62000,
60 [AW_H3_DRAMCTL] = 0x01c63000,
61 [AW_H3_DRAMPHY] = 0x01c65000,
62 [AW_H3_GIC_DIST] = 0x01c81000,
63 [AW_H3_GIC_CPU] = 0x01c82000,
64 [AW_H3_GIC_HYP] = 0x01c84000,
65 [AW_H3_GIC_VCPU] = 0x01c86000,
66 [AW_H3_RTC] = 0x01f00000,
67 [AW_H3_CPUCFG] = 0x01f01c00,
68 [AW_H3_SDRAM] = 0x40000000
69 };
70
71 /* List of unimplemented devices */
72 struct AwH3Unimplemented {
73 const char *device_name;
74 hwaddr base;
75 hwaddr size;
76 } unimplemented[] = {
77 { "d-engine", 0x01000000, 4 * MiB },
78 { "d-inter", 0x01400000, 128 * KiB },
79 { "dma", 0x01c02000, 4 * KiB },
80 { "nfdc", 0x01c03000, 4 * KiB },
81 { "ts", 0x01c06000, 4 * KiB },
82 { "keymem", 0x01c0b000, 4 * KiB },
83 { "lcd0", 0x01c0c000, 4 * KiB },
84 { "lcd1", 0x01c0d000, 4 * KiB },
85 { "ve", 0x01c0e000, 4 * KiB },
86 { "mmc1", 0x01c10000, 4 * KiB },
87 { "mmc2", 0x01c11000, 4 * KiB },
88 { "crypto", 0x01c15000, 4 * KiB },
89 { "msgbox", 0x01c17000, 4 * KiB },
90 { "spinlock", 0x01c18000, 4 * KiB },
91 { "usb0-otg", 0x01c19000, 4 * KiB },
92 { "usb0-phy", 0x01c1a000, 4 * KiB },
93 { "usb1-phy", 0x01c1b000, 4 * KiB },
94 { "usb2-phy", 0x01c1c000, 4 * KiB },
95 { "usb3-phy", 0x01c1d000, 4 * KiB },
96 { "smc", 0x01c1e000, 4 * KiB },
97 { "pio", 0x01c20800, 1 * KiB },
98 { "owa", 0x01c21000, 1 * KiB },
99 { "pwm", 0x01c21400, 1 * KiB },
100 { "keyadc", 0x01c21800, 1 * KiB },
101 { "pcm0", 0x01c22000, 1 * KiB },
102 { "pcm1", 0x01c22400, 1 * KiB },
103 { "pcm2", 0x01c22800, 1 * KiB },
104 { "audio", 0x01c22c00, 2 * KiB },
105 { "smta", 0x01c23400, 1 * KiB },
106 { "ths", 0x01c25000, 1 * KiB },
107 { "uart0", 0x01c28000, 1 * KiB },
108 { "uart1", 0x01c28400, 1 * KiB },
109 { "uart2", 0x01c28800, 1 * KiB },
110 { "uart3", 0x01c28c00, 1 * KiB },
111 { "twi0", 0x01c2ac00, 1 * KiB },
112 { "twi1", 0x01c2b000, 1 * KiB },
113 { "twi2", 0x01c2b400, 1 * KiB },
114 { "scr", 0x01c2c400, 1 * KiB },
115 { "gpu", 0x01c40000, 64 * KiB },
116 { "hstmr", 0x01c60000, 4 * KiB },
117 { "spi0", 0x01c68000, 4 * KiB },
118 { "spi1", 0x01c69000, 4 * KiB },
119 { "csi", 0x01cb0000, 320 * KiB },
120 { "tve", 0x01e00000, 64 * KiB },
121 { "hdmi", 0x01ee0000, 128 * KiB },
122 { "r_timer", 0x01f00800, 1 * KiB },
123 { "r_intc", 0x01f00c00, 1 * KiB },
124 { "r_wdog", 0x01f01000, 1 * KiB },
125 { "r_prcm", 0x01f01400, 1 * KiB },
126 { "r_twd", 0x01f01800, 1 * KiB },
127 { "r_cir-rx", 0x01f02000, 1 * KiB },
128 { "r_twi", 0x01f02400, 1 * KiB },
129 { "r_uart", 0x01f02800, 1 * KiB },
130 { "r_pio", 0x01f02c00, 1 * KiB },
131 { "r_pwm", 0x01f03800, 1 * KiB },
132 { "core-dbg", 0x3f500000, 128 * KiB },
133 { "tsgen-ro", 0x3f506000, 4 * KiB },
134 { "tsgen-ctl", 0x3f507000, 4 * KiB },
135 { "ddr-mem", 0x40000000, 2 * GiB },
136 { "n-brom", 0xffff0000, 32 * KiB },
137 { "s-brom", 0xffff0000, 64 * KiB }
138 };
139
140 /* Per Processor Interrupts */
141 enum {
142 AW_H3_GIC_PPI_MAINT = 9,
143 AW_H3_GIC_PPI_HYPTIMER = 10,
144 AW_H3_GIC_PPI_VIRTTIMER = 11,
145 AW_H3_GIC_PPI_SECTIMER = 13,
146 AW_H3_GIC_PPI_PHYSTIMER = 14
147 };
148
149 /* Shared Processor Interrupts */
150 enum {
151 AW_H3_GIC_SPI_UART0 = 0,
152 AW_H3_GIC_SPI_UART1 = 1,
153 AW_H3_GIC_SPI_UART2 = 2,
154 AW_H3_GIC_SPI_UART3 = 3,
155 AW_H3_GIC_SPI_TIMER0 = 18,
156 AW_H3_GIC_SPI_TIMER1 = 19,
157 AW_H3_GIC_SPI_MMC0 = 60,
158 AW_H3_GIC_SPI_EHCI0 = 72,
159 AW_H3_GIC_SPI_OHCI0 = 73,
160 AW_H3_GIC_SPI_EHCI1 = 74,
161 AW_H3_GIC_SPI_OHCI1 = 75,
162 AW_H3_GIC_SPI_EHCI2 = 76,
163 AW_H3_GIC_SPI_OHCI2 = 77,
164 AW_H3_GIC_SPI_EHCI3 = 78,
165 AW_H3_GIC_SPI_OHCI3 = 79,
166 AW_H3_GIC_SPI_EMAC = 82
167 };
168
169 /* Allwinner H3 general constants */
170 enum {
171 AW_H3_GIC_NUM_SPI = 128
172 };
173
174 void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
175 {
176 const int64_t rom_size = 32 * KiB;
177 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
178
179 if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
180 error_setg(&error_fatal, "%s: failed to read BlockBackend data",
181 __func__);
182 return;
183 }
184
185 rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
186 rom_size, s->memmap[AW_H3_SRAM_A1],
187 NULL, NULL, NULL, NULL, false);
188 }
189
190 static void allwinner_h3_init(Object *obj)
191 {
192 AwH3State *s = AW_H3(obj);
193
194 s->memmap = allwinner_h3_memmap;
195
196 for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
197 object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
198 ARM_CPU_TYPE_NAME("cortex-a7"),
199 &error_abort, NULL);
200 }
201
202 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
203 TYPE_ARM_GIC);
204
205 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
206 TYPE_AW_A10_PIT);
207 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
208 "clk0-freq");
209 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
210 "clk1-freq");
211
212 sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
213 TYPE_AW_H3_CCU);
214
215 sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
216 TYPE_AW_H3_SYSCTRL);
217
218 sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
219 TYPE_AW_CPUCFG);
220
221 sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
222 TYPE_AW_SID);
223 object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
224 "identifier");
225
226 sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
227 TYPE_AW_SDHOST_SUN5I);
228
229 sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
230 TYPE_AW_SUN8I_EMAC);
231
232 sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
233 TYPE_AW_H3_DRAMC);
234 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
235 "ram-addr");
236 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
237 "ram-size");
238
239 sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
240 TYPE_AW_RTC_SUN6I);
241 }
242
243 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
244 {
245 AwH3State *s = AW_H3(dev);
246 unsigned i;
247
248 /* CPUs */
249 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
250
251 /* Provide Power State Coordination Interface */
252 qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
253 QEMU_PSCI_CONDUIT_HVC);
254
255 /* Disable secondary CPUs */
256 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
257 i > 0);
258
259 /* All exception levels required */
260 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
261 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
262
263 /* Mark realized */
264 qdev_init_nofail(DEVICE(&s->cpus[i]));
265 }
266
267 /* Generic Interrupt Controller */
268 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
269 GIC_INTERNAL);
270 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
271 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
272 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
273 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
274 qdev_init_nofail(DEVICE(&s->gic));
275
276 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
278 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
279 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
280
281 /*
282 * Wire the outputs from each CPU's generic timer and the GICv3
283 * maintenance interrupt signal to the appropriate GIC PPI inputs,
284 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
285 */
286 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
287 DeviceState *cpudev = DEVICE(&s->cpus[i]);
288 int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
289 int irq;
290 /*
291 * Mapping from the output timer irq lines from the CPU to the
292 * GIC PPI inputs used for this board.
293 */
294 const int timer_irq[] = {
295 [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
296 [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
297 [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
298 [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
299 };
300
301 /* Connect CPU timer outputs to GIC PPI inputs */
302 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
303 qdev_connect_gpio_out(cpudev, irq,
304 qdev_get_gpio_in(DEVICE(&s->gic),
305 ppibase + timer_irq[irq]));
306 }
307
308 /* Connect GIC outputs to CPU interrupt inputs */
309 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
310 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
311 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
312 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
313 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
314 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
315 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
316 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
317
318 /* GIC maintenance signal */
319 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
320 qdev_get_gpio_in(DEVICE(&s->gic),
321 ppibase + AW_H3_GIC_PPI_MAINT));
322 }
323
324 /* Timer */
325 qdev_init_nofail(DEVICE(&s->timer));
326 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
327 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
328 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
329 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
330 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
331
332 /* SRAM */
333 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
334 64 * KiB, &error_abort);
335 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
336 32 * KiB, &error_abort);
337 memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
338 44 * KiB, &error_abort);
339 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
340 &s->sram_a1);
341 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
342 &s->sram_a2);
343 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
344 &s->sram_c);
345
346 /* Clock Control Unit */
347 qdev_init_nofail(DEVICE(&s->ccu));
348 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
349
350 /* System Control */
351 qdev_init_nofail(DEVICE(&s->sysctrl));
352 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
353
354 /* CPU Configuration */
355 qdev_init_nofail(DEVICE(&s->cpucfg));
356 sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
357
358 /* Security Identifier */
359 qdev_init_nofail(DEVICE(&s->sid));
360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
361
362 /* SD/MMC */
363 qdev_init_nofail(DEVICE(&s->mmc0));
364 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
365 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
366 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
367
368 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
369 "sd-bus");
370
371 /* EMAC */
372 if (nd_table[0].used) {
373 qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
374 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
375 }
376 qdev_init_nofail(DEVICE(&s->emac));
377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
378 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
379 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
380
381 /* Universal Serial Bus */
382 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
383 qdev_get_gpio_in(DEVICE(&s->gic),
384 AW_H3_GIC_SPI_EHCI0));
385 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
386 qdev_get_gpio_in(DEVICE(&s->gic),
387 AW_H3_GIC_SPI_EHCI1));
388 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
389 qdev_get_gpio_in(DEVICE(&s->gic),
390 AW_H3_GIC_SPI_EHCI2));
391 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
392 qdev_get_gpio_in(DEVICE(&s->gic),
393 AW_H3_GIC_SPI_EHCI3));
394
395 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
396 qdev_get_gpio_in(DEVICE(&s->gic),
397 AW_H3_GIC_SPI_OHCI0));
398 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
399 qdev_get_gpio_in(DEVICE(&s->gic),
400 AW_H3_GIC_SPI_OHCI1));
401 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
402 qdev_get_gpio_in(DEVICE(&s->gic),
403 AW_H3_GIC_SPI_OHCI2));
404 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
405 qdev_get_gpio_in(DEVICE(&s->gic),
406 AW_H3_GIC_SPI_OHCI3));
407
408 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
409 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
410 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
411 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
412 /* UART1 */
413 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
414 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
415 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
416 /* UART2 */
417 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
418 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
419 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
420 /* UART3 */
421 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
422 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
423 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
424
425 /* DRAMC */
426 qdev_init_nofail(DEVICE(&s->dramc));
427 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
428 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
429 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
430
431 /* RTC */
432 qdev_init_nofail(DEVICE(&s->rtc));
433 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
434
435 /* Unimplemented devices */
436 for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
437 create_unimplemented_device(unimplemented[i].device_name,
438 unimplemented[i].base,
439 unimplemented[i].size);
440 }
441 }
442
443 static void allwinner_h3_class_init(ObjectClass *oc, void *data)
444 {
445 DeviceClass *dc = DEVICE_CLASS(oc);
446
447 dc->realize = allwinner_h3_realize;
448 /* Reason: uses serial_hd() in realize function */
449 dc->user_creatable = false;
450 }
451
452 static const TypeInfo allwinner_h3_type_info = {
453 .name = TYPE_AW_H3,
454 .parent = TYPE_DEVICE,
455 .instance_size = sizeof(AwH3State),
456 .instance_init = allwinner_h3_init,
457 .class_init = allwinner_h3_class_init,
458 };
459
460 static void allwinner_h3_register_types(void)
461 {
462 type_register_static(&allwinner_h3_type_info);
463 }
464
465 type_init(allwinner_h3_register_types)
QEmu