target-mips/machine.c

   1 #include "hw/hw.h"
   2
   3 #include "cpu.h"
   4
   5 static int cpu_post_load(void *opaque, int version_id)
   6 {
   7     MIPSCPU *cpu = opaque;
   8     CPUMIPSState *env = &cpu->env;
   9
  10     restore_fp_status(env);
  11     restore_msa_fp_status(env);
  12     compute_hflags(env);
  13     restore_pamask(env);
  14
  15     return 0;
  16 }
  17
  18 /* FPU state */
  19
  20 static int get_fpr(QEMUFile *f, void *pv, size_t size)
  21 {
  22     int i;
  23     fpr_t *v = pv;
  24     /* Restore entire MSA vector register */
  25     for (i = 0; i < MSA_WRLEN/64; i++) {
  26         qemu_get_sbe64s(f, &v->wr.d[i]);
  27     }
  28     return 0;
  29 }
  30
  31 static void put_fpr(QEMUFile *f, void *pv, size_t size)
  32 {
  33     int i;
  34     fpr_t *v = pv;
  35     /* Save entire MSA vector register */
  36     for (i = 0; i < MSA_WRLEN/64; i++) {
  37         qemu_put_sbe64s(f, &v->wr.d[i]);
  38     }
  39 }
  40
  41 const VMStateInfo vmstate_info_fpr = {
  42     .name = "fpr",
  43     .get  = get_fpr,
  44     .put  = put_fpr,
  45 };
  46
  47 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v)                     \
  48     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
  49
  50 #define VMSTATE_FPR_ARRAY(_f, _s, _n)                           \
  51     VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
  52
  53 static VMStateField vmstate_fpu_fields[] = {
  54     VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
  55     VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
  56     VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
  57     VMSTATE_END_OF_LIST()
  58 };
  59
  60 const VMStateDescription vmstate_fpu = {
  61     .name = "cpu/fpu",
  62     .version_id = 1,
  63     .minimum_version_id = 1,
  64     .fields = vmstate_fpu_fields
  65 };
  66
  67 const VMStateDescription vmstate_inactive_fpu = {
  68     .name = "cpu/inactive_fpu",
  69     .version_id = 1,
  70     .minimum_version_id = 1,
  71     .fields = vmstate_fpu_fields
  72 };
  73
  74 /* TC state */
  75
  76 static VMStateField vmstate_tc_fields[] = {
  77     VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
  78     VMSTATE_UINTTL(PC, TCState),
  79     VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
  80     VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
  81     VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
  82     VMSTATE_UINTTL(DSPControl, TCState),
  83     VMSTATE_INT32(CP0_TCStatus, TCState),
  84     VMSTATE_INT32(CP0_TCBind, TCState),
  85     VMSTATE_UINTTL(CP0_TCHalt, TCState),
  86     VMSTATE_UINTTL(CP0_TCContext, TCState),
  87     VMSTATE_UINTTL(CP0_TCSchedule, TCState),
  88     VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
  89     VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
  90     VMSTATE_UINTTL(CP0_UserLocal, TCState),
  91     VMSTATE_INT32(msacsr, TCState),
  92     VMSTATE_END_OF_LIST()
  93 };
  94
  95 const VMStateDescription vmstate_tc = {
  96     .name = "cpu/tc",
  97     .version_id = 1,
  98     .minimum_version_id = 1,
  99     .fields = vmstate_tc_fields
 100 };
 101
 102 const VMStateDescription vmstate_inactive_tc = {
 103     .name = "cpu/inactive_tc",
 104     .version_id = 1,
 105     .minimum_version_id = 1,
 106     .fields = vmstate_tc_fields
 107 };
 108
 109 /* MVP state */
 110
 111 const VMStateDescription vmstate_mvp = {
 112     .name = "cpu/mvp",
 113     .version_id = 1,
 114     .minimum_version_id = 1,
 115     .fields = (VMStateField[]) {
 116         VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
 117         VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
 118         VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
 119         VMSTATE_END_OF_LIST()
 120     }
 121 };
 122
 123 /* TLB state */
 124
 125 static int get_tlb(QEMUFile *f, void *pv, size_t size)
 126 {
 127     r4k_tlb_t *v = pv;
 128     uint16_t flags;
 129
 130     qemu_get_betls(f, &v->VPN);
 131     qemu_get_be32s(f, &v->PageMask);
 132     qemu_get_8s(f, &v->ASID);
 133     qemu_get_be16s(f, &flags);
 134     v->G = (flags >> 10) & 1;
 135     v->C0 = (flags >> 7) & 3;
 136     v->C1 = (flags >> 4) & 3;
 137     v->V0 = (flags >> 3) & 1;
 138     v->V1 = (flags >> 2) & 1;
 139     v->D0 = (flags >> 1) & 1;
 140     v->D1 = (flags >> 0) & 1;
 141     v->EHINV = (flags >> 15) & 1;
 142     v->RI1 = (flags >> 14) & 1;
 143     v->RI0 = (flags >> 13) & 1;
 144     v->XI1 = (flags >> 12) & 1;
 145     v->XI0 = (flags >> 11) & 1;
 146     qemu_get_be64s(f, &v->PFN[0]);
 147     qemu_get_be64s(f, &v->PFN[1]);
 148
 149     return 0;
 150 }
 151
 152 static void put_tlb(QEMUFile *f, void *pv, size_t size)
 153 {
 154     r4k_tlb_t *v = pv;
 155
 156     uint16_t flags = ((v->EHINV << 15) |
 157                       (v->RI1 << 14) |
 158                       (v->RI0 << 13) |
 159                       (v->XI1 << 12) |
 160                       (v->XI0 << 11) |
 161                       (v->G << 10) |
 162                       (v->C0 << 7) |
 163                       (v->C1 << 4) |
 164                       (v->V0 << 3) |
 165                       (v->V1 << 2) |
 166                       (v->D0 << 1) |
 167                       (v->D1 << 0));
 168
 169     qemu_put_betls(f, &v->VPN);
 170     qemu_put_be32s(f, &v->PageMask);
 171     qemu_put_8s(f, &v->ASID);
 172     qemu_put_be16s(f, &flags);
 173     qemu_put_be64s(f, &v->PFN[0]);
 174     qemu_put_be64s(f, &v->PFN[1]);
 175 }
 176
 177 const VMStateInfo vmstate_info_tlb = {
 178     .name = "tlb_entry",
 179     .get  = get_tlb,
 180     .put  = put_tlb,
 181 };
 182
 183 #define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v)                     \
 184     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
 185
 186 #define VMSTATE_TLB_ARRAY(_f, _s, _n)                           \
 187     VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
 188
 189 const VMStateDescription vmstate_tlb = {
 190     .name = "cpu/tlb",
 191     .version_id = 1,
 192     .minimum_version_id = 1,
 193     .fields = (VMStateField[]) {
 194         VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
 195         VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
 196         VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
 197         VMSTATE_END_OF_LIST()
 198     }
 199 };
 200
 201 /* MIPS CPU state */
 202
 203 const VMStateDescription vmstate_mips_cpu = {
 204     .name = "cpu",
 205     .version_id = 7,
 206     .minimum_version_id = 7,
 207     .post_load = cpu_post_load,
 208     .fields = (VMStateField[]) {
 209         /* Active TC */
 210         VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
 211
 212         /* Active FPU */
 213         VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
 214                        CPUMIPSFPUContext),
 215
 216         /* MVP */
 217         VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
 218                                CPUMIPSMVPContext),
 219
 220         /* TLB */
 221         VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
 222                                CPUMIPSTLBContext),
 223
 224         /* CPU metastate */
 225         VMSTATE_UINT32(env.current_tc, MIPSCPU),
 226         VMSTATE_UINT32(env.current_fpu, MIPSCPU),
 227         VMSTATE_INT32(env.error_code, MIPSCPU),
 228         VMSTATE_UINTTL(env.btarget, MIPSCPU),
 229         VMSTATE_UINTTL(env.bcond, MIPSCPU),
 230
 231         /* Remaining CP0 registers */
 232         VMSTATE_INT32(env.CP0_Index, MIPSCPU),
 233         VMSTATE_INT32(env.CP0_Random, MIPSCPU),
 234         VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
 235         VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
 236         VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
 237         VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
 238         VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
 239         VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
 240         VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
 241         VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
 242         VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
 243         VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
 244         VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
 245         VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
 246         VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
 247         VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
 248         VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
 249         VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
 250         VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
 251         VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
 252         VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
 253         VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
 254         VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
 255         VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
 256         VMSTATE_INT32(env.CP0_Count, MIPSCPU),
 257         VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
 258         VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
 259         VMSTATE_INT32(env.CP0_Status, MIPSCPU),
 260         VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
 261         VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
 262         VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
 263         VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
 264         VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
 265         VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
 266         VMSTATE_INT32(env.CP0_EBase, MIPSCPU),
 267         VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
 268         VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
 269         VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
 270         VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
 271         VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
 272         VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
 273         VMSTATE_UINT64(env.lladdr, MIPSCPU),
 274         VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
 275         VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
 276         VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
 277         VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
 278         VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
 279         VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
 280         VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
 281         VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
 282         VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
 283         VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
 284         VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
 285         VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
 286         VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
 287         VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
 288
 289         /* Inactive TC */
 290         VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
 291                              vmstate_inactive_tc, TCState),
 292         VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
 293                              vmstate_inactive_fpu, CPUMIPSFPUContext),
 294
 295         VMSTATE_END_OF_LIST()
 296     },
 297 };