2 * vfio based device assignment support
4 * Copyright Red Hat, Inc. 2012
7 * Alex Williamson <alex.williamson@redhat.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
12 * Based on qemu-kvm device-assignment:
13 * Adapted for KVM by Qumranet.
14 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
15 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
16 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
17 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
22 #include <linux/vfio.h>
23 #include <sys/ioctl.h>
26 #include <sys/types.h>
30 #include "exec/address-spaces.h"
31 #include "exec/memory.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci.h"
35 #include "qemu-common.h"
36 #include "qemu/error-report.h"
37 #include "qemu/event_notifier.h"
38 #include "qemu/queue.h"
39 #include "qemu/range.h"
40 #include "sysemu/kvm.h"
41 #include "sysemu/sysemu.h"
43 /* #define DEBUG_VFIO */
45 #define DPRINTF(fmt, ...) \
46 do { fprintf(stderr, "vfio: " fmt, ## __VA_ARGS__); } while (0)
48 #define DPRINTF(fmt, ...) \
52 /* Extra debugging, trap acceleration paths for more logging */
53 #define VFIO_ALLOW_MMAP 1
54 #define VFIO_ALLOW_KVM_INTX 1
55 #define VFIO_ALLOW_KVM_MSI 1
56 #define VFIO_ALLOW_KVM_MSIX 1
60 typedef struct VFIOQuirk
{
62 struct VFIODevice
*vdev
;
63 QLIST_ENTRY(VFIOQuirk
) next
;
65 uint32_t base_offset
:TARGET_PAGE_BITS
;
66 uint32_t address_offset
:TARGET_PAGE_BITS
;
67 uint32_t address_size
:3;
70 uint32_t address_match
;
71 uint32_t address_mask
;
73 uint32_t address_val
:TARGET_PAGE_BITS
;
74 uint32_t data_offset
:TARGET_PAGE_BITS
;
83 typedef struct VFIOBAR
{
84 off_t fd_offset
; /* offset of BAR within device fd */
85 int fd
; /* device fd, allows us to pass VFIOBAR as opaque data */
86 MemoryRegion mem
; /* slow, read/write access */
87 MemoryRegion mmap_mem
; /* direct mapped access */
90 uint32_t flags
; /* VFIO region flags (rd/wr/mmap) */
91 uint8_t nr
; /* cache the BAR number for debug */
94 QLIST_HEAD(, VFIOQuirk
) quirks
;
97 typedef struct VFIOVGARegion
{
101 QLIST_HEAD(, VFIOQuirk
) quirks
;
104 typedef struct VFIOVGA
{
107 VFIOVGARegion region
[QEMU_PCI_VGA_NUM_REGIONS
];
110 typedef struct VFIOINTx
{
111 bool pending
; /* interrupt pending */
112 bool kvm_accel
; /* set when QEMU bypass through KVM enabled */
113 uint8_t pin
; /* which pin to pull for qemu_set_irq */
114 EventNotifier interrupt
; /* eventfd triggered on interrupt */
115 EventNotifier unmask
; /* eventfd for unmask on QEMU bypass */
116 PCIINTxRoute route
; /* routing info for QEMU bypass */
117 uint32_t mmap_timeout
; /* delay to re-enable mmaps after interrupt */
118 QEMUTimer
*mmap_timer
; /* enable mmaps after periods w/o interrupts */
121 typedef struct VFIOMSIVector
{
122 EventNotifier interrupt
; /* eventfd triggered on interrupt */
123 struct VFIODevice
*vdev
; /* back pointer to device */
124 MSIMessage msg
; /* cache the MSI message so we know when it changes */
125 int virq
; /* KVM irqchip route for QEMU bypass */
136 typedef struct VFIOAddressSpace
{
138 QLIST_HEAD(, VFIOContainer
) containers
;
139 QLIST_ENTRY(VFIOAddressSpace
) list
;
142 static QLIST_HEAD(, VFIOAddressSpace
) vfio_address_spaces
=
143 QLIST_HEAD_INITIALIZER(vfio_address_spaces
);
147 typedef struct VFIOType1
{
148 MemoryListener listener
;
153 typedef struct VFIOContainer
{
154 VFIOAddressSpace
*space
;
155 int fd
; /* /dev/vfio/vfio, empowered by the attached groups */
157 /* enable abstraction to support various iommu backends */
161 void (*release
)(struct VFIOContainer
*);
163 QLIST_HEAD(, VFIOGuestIOMMU
) giommu_list
;
164 QLIST_HEAD(, VFIOGroup
) group_list
;
165 QLIST_ENTRY(VFIOContainer
) next
;
168 typedef struct VFIOGuestIOMMU
{
169 VFIOContainer
*container
;
172 QLIST_ENTRY(VFIOGuestIOMMU
) giommu_next
;
175 /* Cache of MSI-X setup plus extra mmap and memory region for split BAR map */
176 typedef struct VFIOMSIXInfo
{
180 uint32_t table_offset
;
182 MemoryRegion mmap_mem
;
186 typedef struct VFIODevice
{
190 unsigned int config_size
;
191 uint8_t *emulated_config_bits
; /* QEMU emulated bits, little-endian */
192 off_t config_offset
; /* Offset of config space region within device fd */
193 unsigned int rom_size
;
194 off_t rom_offset
; /* Offset of ROM region within device fd */
197 VFIOMSIVector
*msi_vectors
;
199 int nr_vectors
; /* Number of MSI/MSIX vectors currently in use */
200 int interrupt
; /* Current interrupt type */
201 VFIOBAR bars
[PCI_NUM_REGIONS
- 1]; /* No ROM */
202 VFIOVGA vga
; /* 0xa0000, 0x3b0, 0x3c0 */
203 PCIHostDeviceAddress host
;
204 QLIST_ENTRY(VFIODevice
) next
;
205 struct VFIOGroup
*group
;
206 EventNotifier err_notifier
;
208 #define VFIO_FEATURE_ENABLE_VGA_BIT 0
209 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
218 bool rom_read_failed
;
221 typedef struct VFIOGroup
{
224 VFIOContainer
*container
;
225 QLIST_HEAD(, VFIODevice
) device_list
;
226 QLIST_ENTRY(VFIOGroup
) next
;
227 QLIST_ENTRY(VFIOGroup
) container_next
;
230 typedef struct VFIORomBlacklistEntry
{
233 } VFIORomBlacklistEntry
;
236 * List of device ids/vendor ids for which to disable
237 * option rom loading. This avoids the guest hangs during rom
238 * execution as noticed with the BCM 57810 card for lack of a
239 * more better way to handle such issues.
240 * The user can still override by specifying a romfile or
242 * Please see https://bugs.launchpad.net/qemu/+bug/1284874
243 * for an analysis of the 57810 card hang. When adding
244 * a new vendor id/device id combination below, please also add
245 * your card/environment details and information that could
246 * help in debugging to the bug tracking this issue
248 static const VFIORomBlacklistEntry romblacklist
[] = {
249 /* Broadcom BCM 57810 */
253 #define MSIX_CAP_LENGTH 12
255 static QLIST_HEAD(, VFIOGroup
)
256 group_list
= QLIST_HEAD_INITIALIZER(group_list
);
260 * We have a single VFIO pseudo device per KVM VM. Once created it lives
261 * for the life of the VM. Closing the file descriptor only drops our
262 * reference to it and the device's reference to kvm. Therefore once
263 * initialized, this file descriptor is only released on QEMU exit and
264 * we'll re-use it should another vfio device be attached before then.
266 static int vfio_kvm_device_fd
= -1;
269 static void vfio_disable_interrupts(VFIODevice
*vdev
);
270 static uint32_t vfio_pci_read_config(PCIDevice
*pdev
, uint32_t addr
, int len
);
271 static void vfio_pci_write_config(PCIDevice
*pdev
, uint32_t addr
,
272 uint32_t val
, int len
);
273 static void vfio_mmap_set_enabled(VFIODevice
*vdev
, bool enabled
);
276 * Common VFIO interrupt disable
278 static void vfio_disable_irqindex(VFIODevice
*vdev
, int index
)
280 struct vfio_irq_set irq_set
= {
281 .argsz
= sizeof(irq_set
),
282 .flags
= VFIO_IRQ_SET_DATA_NONE
| VFIO_IRQ_SET_ACTION_TRIGGER
,
288 ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, &irq_set
);
294 static void vfio_unmask_intx(VFIODevice
*vdev
)
296 struct vfio_irq_set irq_set
= {
297 .argsz
= sizeof(irq_set
),
298 .flags
= VFIO_IRQ_SET_DATA_NONE
| VFIO_IRQ_SET_ACTION_UNMASK
,
299 .index
= VFIO_PCI_INTX_IRQ_INDEX
,
304 ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, &irq_set
);
307 #ifdef CONFIG_KVM /* Unused outside of CONFIG_KVM code */
308 static void vfio_mask_intx(VFIODevice
*vdev
)
310 struct vfio_irq_set irq_set
= {
311 .argsz
= sizeof(irq_set
),
312 .flags
= VFIO_IRQ_SET_DATA_NONE
| VFIO_IRQ_SET_ACTION_MASK
,
313 .index
= VFIO_PCI_INTX_IRQ_INDEX
,
318 ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, &irq_set
);
323 * Disabling BAR mmaping can be slow, but toggling it around INTx can
324 * also be a huge overhead. We try to get the best of both worlds by
325 * waiting until an interrupt to disable mmaps (subsequent transitions
326 * to the same state are effectively no overhead). If the interrupt has
327 * been serviced and the time gap is long enough, we re-enable mmaps for
328 * performance. This works well for things like graphics cards, which
329 * may not use their interrupt at all and are penalized to an unusable
330 * level by read/write BAR traps. Other devices, like NICs, have more
331 * regular interrupts and see much better latency by staying in non-mmap
332 * mode. We therefore set the default mmap_timeout such that a ping
333 * is just enough to keep the mmap disabled. Users can experiment with
334 * other options with the x-intx-mmap-timeout-ms parameter (a value of
335 * zero disables the timer).
337 static void vfio_intx_mmap_enable(void *opaque
)
339 VFIODevice
*vdev
= opaque
;
341 if (vdev
->intx
.pending
) {
342 timer_mod(vdev
->intx
.mmap_timer
,
343 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + vdev
->intx
.mmap_timeout
);
347 vfio_mmap_set_enabled(vdev
, true);
350 static void vfio_intx_interrupt(void *opaque
)
352 VFIODevice
*vdev
= opaque
;
354 if (!event_notifier_test_and_clear(&vdev
->intx
.interrupt
)) {
358 DPRINTF("%s(%04x:%02x:%02x.%x) Pin %c\n", __func__
, vdev
->host
.domain
,
359 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
360 'A' + vdev
->intx
.pin
);
362 vdev
->intx
.pending
= true;
363 pci_irq_assert(&vdev
->pdev
);
364 vfio_mmap_set_enabled(vdev
, false);
365 if (vdev
->intx
.mmap_timeout
) {
366 timer_mod(vdev
->intx
.mmap_timer
,
367 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + vdev
->intx
.mmap_timeout
);
371 static void vfio_eoi(VFIODevice
*vdev
)
373 if (!vdev
->intx
.pending
) {
377 DPRINTF("%s(%04x:%02x:%02x.%x) EOI\n", __func__
, vdev
->host
.domain
,
378 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
380 vdev
->intx
.pending
= false;
381 pci_irq_deassert(&vdev
->pdev
);
382 vfio_unmask_intx(vdev
);
385 static void vfio_enable_intx_kvm(VFIODevice
*vdev
)
388 struct kvm_irqfd irqfd
= {
389 .fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
),
390 .gsi
= vdev
->intx
.route
.irq
,
391 .flags
= KVM_IRQFD_FLAG_RESAMPLE
,
393 struct vfio_irq_set
*irq_set
;
397 if (!VFIO_ALLOW_KVM_INTX
|| !kvm_irqfds_enabled() ||
398 vdev
->intx
.route
.mode
!= PCI_INTX_ENABLED
||
399 !kvm_check_extension(kvm_state
, KVM_CAP_IRQFD_RESAMPLE
)) {
403 /* Get to a known interrupt state */
404 qemu_set_fd_handler(irqfd
.fd
, NULL
, NULL
, vdev
);
405 vfio_mask_intx(vdev
);
406 vdev
->intx
.pending
= false;
407 pci_irq_deassert(&vdev
->pdev
);
409 /* Get an eventfd for resample/unmask */
410 if (event_notifier_init(&vdev
->intx
.unmask
, 0)) {
411 error_report("vfio: Error: event_notifier_init failed eoi");
415 /* KVM triggers it, VFIO listens for it */
416 irqfd
.resamplefd
= event_notifier_get_fd(&vdev
->intx
.unmask
);
418 if (kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
)) {
419 error_report("vfio: Error: Failed to setup resample irqfd: %m");
423 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
425 irq_set
= g_malloc0(argsz
);
426 irq_set
->argsz
= argsz
;
427 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_UNMASK
;
428 irq_set
->index
= VFIO_PCI_INTX_IRQ_INDEX
;
431 pfd
= (int32_t *)&irq_set
->data
;
433 *pfd
= irqfd
.resamplefd
;
435 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
438 error_report("vfio: Error: Failed to setup INTx unmask fd: %m");
443 vfio_unmask_intx(vdev
);
445 vdev
->intx
.kvm_accel
= true;
447 DPRINTF("%s(%04x:%02x:%02x.%x) KVM INTx accel enabled\n",
448 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
449 vdev
->host
.slot
, vdev
->host
.function
);
454 irqfd
.flags
= KVM_IRQFD_FLAG_DEASSIGN
;
455 kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
);
457 event_notifier_cleanup(&vdev
->intx
.unmask
);
459 qemu_set_fd_handler(irqfd
.fd
, vfio_intx_interrupt
, NULL
, vdev
);
460 vfio_unmask_intx(vdev
);
464 static void vfio_disable_intx_kvm(VFIODevice
*vdev
)
467 struct kvm_irqfd irqfd
= {
468 .fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
),
469 .gsi
= vdev
->intx
.route
.irq
,
470 .flags
= KVM_IRQFD_FLAG_DEASSIGN
,
473 if (!vdev
->intx
.kvm_accel
) {
478 * Get to a known state, hardware masked, QEMU ready to accept new
479 * interrupts, QEMU IRQ de-asserted.
481 vfio_mask_intx(vdev
);
482 vdev
->intx
.pending
= false;
483 pci_irq_deassert(&vdev
->pdev
);
485 /* Tell KVM to stop listening for an INTx irqfd */
486 if (kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
)) {
487 error_report("vfio: Error: Failed to disable INTx irqfd: %m");
490 /* We only need to close the eventfd for VFIO to cleanup the kernel side */
491 event_notifier_cleanup(&vdev
->intx
.unmask
);
493 /* QEMU starts listening for interrupt events. */
494 qemu_set_fd_handler(irqfd
.fd
, vfio_intx_interrupt
, NULL
, vdev
);
496 vdev
->intx
.kvm_accel
= false;
498 /* If we've missed an event, let it re-fire through QEMU */
499 vfio_unmask_intx(vdev
);
501 DPRINTF("%s(%04x:%02x:%02x.%x) KVM INTx accel disabled\n",
502 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
503 vdev
->host
.slot
, vdev
->host
.function
);
507 static void vfio_update_irq(PCIDevice
*pdev
)
509 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
512 if (vdev
->interrupt
!= VFIO_INT_INTx
) {
516 route
= pci_device_route_intx_to_irq(&vdev
->pdev
, vdev
->intx
.pin
);
518 if (!pci_intx_route_changed(&vdev
->intx
.route
, &route
)) {
519 return; /* Nothing changed */
522 DPRINTF("%s(%04x:%02x:%02x.%x) IRQ moved %d -> %d\n", __func__
,
523 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
524 vdev
->host
.function
, vdev
->intx
.route
.irq
, route
.irq
);
526 vfio_disable_intx_kvm(vdev
);
528 vdev
->intx
.route
= route
;
530 if (route
.mode
!= PCI_INTX_ENABLED
) {
534 vfio_enable_intx_kvm(vdev
);
536 /* Re-enable the interrupt in cased we missed an EOI */
540 static int vfio_enable_intx(VFIODevice
*vdev
)
542 uint8_t pin
= vfio_pci_read_config(&vdev
->pdev
, PCI_INTERRUPT_PIN
, 1);
544 struct vfio_irq_set
*irq_set
;
551 vfio_disable_interrupts(vdev
);
553 vdev
->intx
.pin
= pin
- 1; /* Pin A (1) -> irq[0] */
554 pci_config_set_interrupt_pin(vdev
->pdev
.config
, pin
);
558 * Only conditional to avoid generating error messages on platforms
559 * where we won't actually use the result anyway.
561 if (kvm_irqfds_enabled() &&
562 kvm_check_extension(kvm_state
, KVM_CAP_IRQFD_RESAMPLE
)) {
563 vdev
->intx
.route
= pci_device_route_intx_to_irq(&vdev
->pdev
,
568 ret
= event_notifier_init(&vdev
->intx
.interrupt
, 0);
570 error_report("vfio: Error: event_notifier_init failed");
574 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
576 irq_set
= g_malloc0(argsz
);
577 irq_set
->argsz
= argsz
;
578 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_TRIGGER
;
579 irq_set
->index
= VFIO_PCI_INTX_IRQ_INDEX
;
582 pfd
= (int32_t *)&irq_set
->data
;
584 *pfd
= event_notifier_get_fd(&vdev
->intx
.interrupt
);
585 qemu_set_fd_handler(*pfd
, vfio_intx_interrupt
, NULL
, vdev
);
587 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
590 error_report("vfio: Error: Failed to setup INTx fd: %m");
591 qemu_set_fd_handler(*pfd
, NULL
, NULL
, vdev
);
592 event_notifier_cleanup(&vdev
->intx
.interrupt
);
596 vfio_enable_intx_kvm(vdev
);
598 vdev
->interrupt
= VFIO_INT_INTx
;
600 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
601 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
606 static void vfio_disable_intx(VFIODevice
*vdev
)
610 timer_del(vdev
->intx
.mmap_timer
);
611 vfio_disable_intx_kvm(vdev
);
612 vfio_disable_irqindex(vdev
, VFIO_PCI_INTX_IRQ_INDEX
);
613 vdev
->intx
.pending
= false;
614 pci_irq_deassert(&vdev
->pdev
);
615 vfio_mmap_set_enabled(vdev
, true);
617 fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
);
618 qemu_set_fd_handler(fd
, NULL
, NULL
, vdev
);
619 event_notifier_cleanup(&vdev
->intx
.interrupt
);
621 vdev
->interrupt
= VFIO_INT_NONE
;
623 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
624 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
630 static void vfio_msi_interrupt(void *opaque
)
632 VFIOMSIVector
*vector
= opaque
;
633 VFIODevice
*vdev
= vector
->vdev
;
634 int nr
= vector
- vdev
->msi_vectors
;
636 if (!event_notifier_test_and_clear(&vector
->interrupt
)) {
643 if (vdev
->interrupt
== VFIO_INT_MSIX
) {
644 msg
= msi_get_message(&vdev
->pdev
, nr
);
645 } else if (vdev
->interrupt
== VFIO_INT_MSI
) {
646 msg
= msix_get_message(&vdev
->pdev
, nr
);
651 DPRINTF("%s(%04x:%02x:%02x.%x) vector %d 0x%"PRIx64
"/0x%x\n", __func__
,
652 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
653 vdev
->host
.function
, nr
, msg
.address
, msg
.data
);
656 if (vdev
->interrupt
== VFIO_INT_MSIX
) {
657 msix_notify(&vdev
->pdev
, nr
);
658 } else if (vdev
->interrupt
== VFIO_INT_MSI
) {
659 msi_notify(&vdev
->pdev
, nr
);
661 error_report("vfio: MSI interrupt receieved, but not enabled?");
665 static int vfio_enable_vectors(VFIODevice
*vdev
, bool msix
)
667 struct vfio_irq_set
*irq_set
;
668 int ret
= 0, i
, argsz
;
671 argsz
= sizeof(*irq_set
) + (vdev
->nr_vectors
* sizeof(*fds
));
673 irq_set
= g_malloc0(argsz
);
674 irq_set
->argsz
= argsz
;
675 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_TRIGGER
;
676 irq_set
->index
= msix
? VFIO_PCI_MSIX_IRQ_INDEX
: VFIO_PCI_MSI_IRQ_INDEX
;
678 irq_set
->count
= vdev
->nr_vectors
;
679 fds
= (int32_t *)&irq_set
->data
;
681 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
682 if (!vdev
->msi_vectors
[i
].use
) {
687 fds
[i
] = event_notifier_get_fd(&vdev
->msi_vectors
[i
].interrupt
);
690 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
697 static int vfio_msix_vector_do_use(PCIDevice
*pdev
, unsigned int nr
,
698 MSIMessage
*msg
, IOHandler
*handler
)
700 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
701 VFIOMSIVector
*vector
;
704 DPRINTF("%s(%04x:%02x:%02x.%x) vector %d used\n", __func__
,
705 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
706 vdev
->host
.function
, nr
);
708 vector
= &vdev
->msi_vectors
[nr
];
712 msix_vector_use(pdev
, nr
);
714 if (event_notifier_init(&vector
->interrupt
, 0)) {
715 error_report("vfio: Error: event_notifier_init failed");
719 * Attempt to enable route through KVM irqchip,
720 * default to userspace handling if unavailable.
722 vector
->virq
= msg
&& VFIO_ALLOW_KVM_MSIX
?
723 kvm_irqchip_add_msi_route(kvm_state
, *msg
) : -1;
724 if (vector
->virq
< 0 ||
725 kvm_irqchip_add_irqfd_notifier(kvm_state
, &vector
->interrupt
,
726 NULL
, vector
->virq
) < 0) {
727 if (vector
->virq
>= 0) {
728 kvm_irqchip_release_virq(kvm_state
, vector
->virq
);
731 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
732 handler
, NULL
, vector
);
736 * We don't want to have the host allocate all possible MSI vectors
737 * for a device if they're not in use, so we shutdown and incrementally
738 * increase them as needed.
740 if (vdev
->nr_vectors
< nr
+ 1) {
741 vfio_disable_irqindex(vdev
, VFIO_PCI_MSIX_IRQ_INDEX
);
742 vdev
->nr_vectors
= nr
+ 1;
743 ret
= vfio_enable_vectors(vdev
, true);
745 error_report("vfio: failed to enable vectors, %d", ret
);
749 struct vfio_irq_set
*irq_set
;
752 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
754 irq_set
= g_malloc0(argsz
);
755 irq_set
->argsz
= argsz
;
756 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
757 VFIO_IRQ_SET_ACTION_TRIGGER
;
758 irq_set
->index
= VFIO_PCI_MSIX_IRQ_INDEX
;
761 pfd
= (int32_t *)&irq_set
->data
;
763 *pfd
= event_notifier_get_fd(&vector
->interrupt
);
765 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
768 error_report("vfio: failed to modify vector, %d", ret
);
775 static int vfio_msix_vector_use(PCIDevice
*pdev
,
776 unsigned int nr
, MSIMessage msg
)
778 return vfio_msix_vector_do_use(pdev
, nr
, &msg
, vfio_msi_interrupt
);
781 static void vfio_msix_vector_release(PCIDevice
*pdev
, unsigned int nr
)
783 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
784 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[nr
];
786 struct vfio_irq_set
*irq_set
;
789 DPRINTF("%s(%04x:%02x:%02x.%x) vector %d released\n", __func__
,
790 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
791 vdev
->host
.function
, nr
);
794 * XXX What's the right thing to do here? This turns off the interrupt
795 * completely, but do we really just want to switch the interrupt to
796 * bouncing through userspace and let msix.c drop it? Not sure.
798 msix_vector_unuse(pdev
, nr
);
800 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
802 irq_set
= g_malloc0(argsz
);
803 irq_set
->argsz
= argsz
;
804 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
805 VFIO_IRQ_SET_ACTION_TRIGGER
;
806 irq_set
->index
= VFIO_PCI_MSIX_IRQ_INDEX
;
809 pfd
= (int32_t *)&irq_set
->data
;
813 ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
817 if (vector
->virq
< 0) {
818 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
821 kvm_irqchip_remove_irqfd_notifier(kvm_state
, &vector
->interrupt
,
823 kvm_irqchip_release_virq(kvm_state
, vector
->virq
);
827 event_notifier_cleanup(&vector
->interrupt
);
831 static void vfio_enable_msix(VFIODevice
*vdev
)
833 vfio_disable_interrupts(vdev
);
835 vdev
->msi_vectors
= g_malloc0(vdev
->msix
->entries
* sizeof(VFIOMSIVector
));
837 vdev
->interrupt
= VFIO_INT_MSIX
;
840 * Some communication channels between VF & PF or PF & fw rely on the
841 * physical state of the device and expect that enabling MSI-X from the
842 * guest enables the same on the host. When our guest is Linux, the
843 * guest driver call to pci_enable_msix() sets the enabling bit in the
844 * MSI-X capability, but leaves the vector table masked. We therefore
845 * can't rely on a vector_use callback (from request_irq() in the guest)
846 * to switch the physical device into MSI-X mode because that may come a
847 * long time after pci_enable_msix(). This code enables vector 0 with
848 * triggering to userspace, then immediately release the vector, leaving
849 * the physical device with no vectors enabled, but MSI-X enabled, just
850 * like the guest view.
852 vfio_msix_vector_do_use(&vdev
->pdev
, 0, NULL
, NULL
);
853 vfio_msix_vector_release(&vdev
->pdev
, 0);
855 if (msix_set_vector_notifiers(&vdev
->pdev
, vfio_msix_vector_use
,
856 vfio_msix_vector_release
, NULL
)) {
857 error_report("vfio: msix_set_vector_notifiers failed");
860 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
861 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
864 static void vfio_enable_msi(VFIODevice
*vdev
)
868 vfio_disable_interrupts(vdev
);
870 vdev
->nr_vectors
= msi_nr_vectors_allocated(&vdev
->pdev
);
872 vdev
->msi_vectors
= g_malloc0(vdev
->nr_vectors
* sizeof(VFIOMSIVector
));
874 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
875 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
880 if (event_notifier_init(&vector
->interrupt
, 0)) {
881 error_report("vfio: Error: event_notifier_init failed");
884 vector
->msg
= msi_get_message(&vdev
->pdev
, i
);
887 * Attempt to enable route through KVM irqchip,
888 * default to userspace handling if unavailable.
890 vector
->virq
= VFIO_ALLOW_KVM_MSI
?
891 kvm_irqchip_add_msi_route(kvm_state
, vector
->msg
) : -1;
892 if (vector
->virq
< 0 ||
893 kvm_irqchip_add_irqfd_notifier(kvm_state
, &vector
->interrupt
,
894 NULL
, vector
->virq
) < 0) {
895 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
896 vfio_msi_interrupt
, NULL
, vector
);
900 ret
= vfio_enable_vectors(vdev
, false);
903 error_report("vfio: Error: Failed to setup MSI fds: %m");
904 } else if (ret
!= vdev
->nr_vectors
) {
905 error_report("vfio: Error: Failed to enable %d "
906 "MSI vectors, retry with %d", vdev
->nr_vectors
, ret
);
909 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
910 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
911 if (vector
->virq
>= 0) {
912 kvm_irqchip_remove_irqfd_notifier(kvm_state
, &vector
->interrupt
,
914 kvm_irqchip_release_virq(kvm_state
, vector
->virq
);
917 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
920 event_notifier_cleanup(&vector
->interrupt
);
923 g_free(vdev
->msi_vectors
);
925 if (ret
> 0 && ret
!= vdev
->nr_vectors
) {
926 vdev
->nr_vectors
= ret
;
929 vdev
->nr_vectors
= 0;
934 vdev
->interrupt
= VFIO_INT_MSI
;
936 DPRINTF("%s(%04x:%02x:%02x.%x) Enabled %d MSI vectors\n", __func__
,
937 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
938 vdev
->host
.function
, vdev
->nr_vectors
);
941 static void vfio_disable_msi_common(VFIODevice
*vdev
)
943 g_free(vdev
->msi_vectors
);
944 vdev
->msi_vectors
= NULL
;
945 vdev
->nr_vectors
= 0;
946 vdev
->interrupt
= VFIO_INT_NONE
;
948 vfio_enable_intx(vdev
);
951 static void vfio_disable_msix(VFIODevice
*vdev
)
955 msix_unset_vector_notifiers(&vdev
->pdev
);
958 * MSI-X will only release vectors if MSI-X is still enabled on the
959 * device, check through the rest and release it ourselves if necessary.
961 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
962 if (vdev
->msi_vectors
[i
].use
) {
963 vfio_msix_vector_release(&vdev
->pdev
, i
);
967 if (vdev
->nr_vectors
) {
968 vfio_disable_irqindex(vdev
, VFIO_PCI_MSIX_IRQ_INDEX
);
971 vfio_disable_msi_common(vdev
);
973 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
974 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
977 static void vfio_disable_msi(VFIODevice
*vdev
)
981 vfio_disable_irqindex(vdev
, VFIO_PCI_MSI_IRQ_INDEX
);
983 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
984 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
990 if (vector
->virq
>= 0) {
991 kvm_irqchip_remove_irqfd_notifier(kvm_state
,
992 &vector
->interrupt
, vector
->virq
);
993 kvm_irqchip_release_virq(kvm_state
, vector
->virq
);
996 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
1000 event_notifier_cleanup(&vector
->interrupt
);
1003 vfio_disable_msi_common(vdev
);
1005 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
1006 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
1009 static void vfio_update_msi(VFIODevice
*vdev
)
1013 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
1014 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
1017 if (!vector
->use
|| vector
->virq
< 0) {
1021 msg
= msi_get_message(&vdev
->pdev
, i
);
1023 if (msg
.address
!= vector
->msg
.address
||
1024 msg
.data
!= vector
->msg
.data
) {
1026 DPRINTF("%s(%04x:%02x:%02x.%x) MSI vector %d changed\n",
1027 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
1028 vdev
->host
.slot
, vdev
->host
.function
, i
);
1030 kvm_irqchip_update_msi_route(kvm_state
, vector
->virq
, msg
);
1037 * IO Port/MMIO - Beware of the endians, VFIO is always little endian
1039 static void vfio_bar_write(void *opaque
, hwaddr addr
,
1040 uint64_t data
, unsigned size
)
1042 VFIOBAR
*bar
= opaque
;
1055 buf
.word
= cpu_to_le16(data
);
1058 buf
.dword
= cpu_to_le32(data
);
1061 hw_error("vfio: unsupported write size, %d bytes", size
);
1065 if (pwrite(bar
->fd
, &buf
, size
, bar
->fd_offset
+ addr
) != size
) {
1066 error_report("%s(,0x%"HWADDR_PRIx
", 0x%"PRIx64
", %d) failed: %m",
1067 __func__
, addr
, data
, size
);
1072 VFIODevice
*vdev
= container_of(bar
, VFIODevice
, bars
[bar
->nr
]);
1074 DPRINTF("%s(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
", 0x%"PRIx64
1075 ", %d)\n", __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
1076 vdev
->host
.slot
, vdev
->host
.function
, bar
->nr
, addr
,
1082 * A read or write to a BAR always signals an INTx EOI. This will
1083 * do nothing if not pending (including not in INTx mode). We assume
1084 * that a BAR access is in response to an interrupt and that BAR
1085 * accesses will service the interrupt. Unfortunately, we don't know
1086 * which access will service the interrupt, so we're potentially
1087 * getting quite a few host interrupts per guest interrupt.
1089 vfio_eoi(container_of(bar
, VFIODevice
, bars
[bar
->nr
]));
1092 static uint64_t vfio_bar_read(void *opaque
,
1093 hwaddr addr
, unsigned size
)
1095 VFIOBAR
*bar
= opaque
;
1104 if (pread(bar
->fd
, &buf
, size
, bar
->fd_offset
+ addr
) != size
) {
1105 error_report("%s(,0x%"HWADDR_PRIx
", %d) failed: %m",
1106 __func__
, addr
, size
);
1107 return (uint64_t)-1;
1115 data
= le16_to_cpu(buf
.word
);
1118 data
= le32_to_cpu(buf
.dword
);
1121 hw_error("vfio: unsupported read size, %d bytes", size
);
1127 VFIODevice
*vdev
= container_of(bar
, VFIODevice
, bars
[bar
->nr
]);
1129 DPRINTF("%s(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
1130 ", %d) = 0x%"PRIx64
"\n", __func__
, vdev
->host
.domain
,
1131 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
1132 bar
->nr
, addr
, size
, data
);
1136 /* Same as write above */
1137 vfio_eoi(container_of(bar
, VFIODevice
, bars
[bar
->nr
]));
1142 static const MemoryRegionOps vfio_bar_ops
= {
1143 .read
= vfio_bar_read
,
1144 .write
= vfio_bar_write
,
1145 .endianness
= DEVICE_LITTLE_ENDIAN
,
1148 static void vfio_pci_load_rom(VFIODevice
*vdev
)
1150 struct vfio_region_info reg_info
= {
1151 .argsz
= sizeof(reg_info
),
1152 .index
= VFIO_PCI_ROM_REGION_INDEX
1158 if (ioctl(vdev
->fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
)) {
1159 error_report("vfio: Error getting ROM info: %m");
1163 DPRINTF("Device %04x:%02x:%02x.%x ROM:\n", vdev
->host
.domain
,
1164 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
1165 DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
1166 (unsigned long)reg_info
.size
, (unsigned long)reg_info
.offset
,
1167 (unsigned long)reg_info
.flags
);
1169 vdev
->rom_size
= size
= reg_info
.size
;
1170 vdev
->rom_offset
= reg_info
.offset
;
1172 if (!vdev
->rom_size
) {
1173 vdev
->rom_read_failed
= true;
1174 error_report("vfio-pci: Cannot read device rom at "
1175 "%04x:%02x:%02x.%x",
1176 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1177 vdev
->host
.function
);
1178 error_printf("Device option ROM contents are probably invalid "
1179 "(check dmesg).\nSkip option ROM probe with rombar=0, "
1180 "or load from file with romfile=\n");
1184 vdev
->rom
= g_malloc(size
);
1185 memset(vdev
->rom
, 0xff, size
);
1188 bytes
= pread(vdev
->fd
, vdev
->rom
+ off
, size
, vdev
->rom_offset
+ off
);
1191 } else if (bytes
> 0) {
1195 if (errno
== EINTR
|| errno
== EAGAIN
) {
1198 error_report("vfio: Error reading device ROM: %m");
1204 static uint64_t vfio_rom_read(void *opaque
, hwaddr addr
, unsigned size
)
1206 VFIODevice
*vdev
= opaque
;
1207 uint64_t val
= ((uint64_t)1 << (size
* 8)) - 1;
1209 /* Load the ROM lazily when the guest tries to read it */
1210 if (unlikely(!vdev
->rom
&& !vdev
->rom_read_failed
)) {
1211 vfio_pci_load_rom(vdev
);
1214 memcpy(&val
, vdev
->rom
+ addr
,
1215 (addr
< vdev
->rom_size
) ? MIN(size
, vdev
->rom_size
- addr
) : 0);
1217 DPRINTF("%s(%04x:%02x:%02x.%x, 0x%"HWADDR_PRIx
", 0x%x) = 0x%"PRIx64
"\n",
1218 __func__
, vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1219 vdev
->host
.function
, addr
, size
, val
);
1224 static void vfio_rom_write(void *opaque
, hwaddr addr
,
1225 uint64_t data
, unsigned size
)
1229 static const MemoryRegionOps vfio_rom_ops
= {
1230 .read
= vfio_rom_read
,
1231 .write
= vfio_rom_write
,
1232 .endianness
= DEVICE_LITTLE_ENDIAN
,
1235 static bool vfio_blacklist_opt_rom(VFIODevice
*vdev
)
1237 PCIDevice
*pdev
= &vdev
->pdev
;
1238 uint16_t vendor_id
, device_id
;
1241 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1242 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1244 while (count
< ARRAY_SIZE(romblacklist
)) {
1245 if (romblacklist
[count
].vendor_id
== vendor_id
&&
1246 romblacklist
[count
].device_id
== device_id
) {
1255 static void vfio_pci_size_rom(VFIODevice
*vdev
)
1257 uint32_t orig
, size
= cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK
);
1258 off_t offset
= vdev
->config_offset
+ PCI_ROM_ADDRESS
;
1259 DeviceState
*dev
= DEVICE(vdev
);
1262 if (vdev
->pdev
.romfile
|| !vdev
->pdev
.rom_bar
) {
1263 /* Since pci handles romfile, just print a message and return */
1264 if (vfio_blacklist_opt_rom(vdev
) && vdev
->pdev
.romfile
) {
1265 error_printf("Warning : Device at %04x:%02x:%02x.%x "
1266 "is known to cause system instability issues during "
1267 "option rom execution. "
1268 "Proceeding anyway since user specified romfile\n",
1269 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1270 vdev
->host
.function
);
1276 * Use the same size ROM BAR as the physical device. The contents
1277 * will get filled in later when the guest tries to read it.
1279 if (pread(vdev
->fd
, &orig
, 4, offset
) != 4 ||
1280 pwrite(vdev
->fd
, &size
, 4, offset
) != 4 ||
1281 pread(vdev
->fd
, &size
, 4, offset
) != 4 ||
1282 pwrite(vdev
->fd
, &orig
, 4, offset
) != 4) {
1283 error_report("%s(%04x:%02x:%02x.%x) failed: %m",
1284 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
1285 vdev
->host
.slot
, vdev
->host
.function
);
1289 size
= ~(le32_to_cpu(size
) & PCI_ROM_ADDRESS_MASK
) + 1;
1295 if (vfio_blacklist_opt_rom(vdev
)) {
1296 if (dev
->opts
&& qemu_opt_get(dev
->opts
, "rombar")) {
1297 error_printf("Warning : Device at %04x:%02x:%02x.%x "
1298 "is known to cause system instability issues during "
1299 "option rom execution. "
1300 "Proceeding anyway since user specified non zero value for "
1302 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1303 vdev
->host
.function
);
1305 error_printf("Warning : Rom loading for device at "
1306 "%04x:%02x:%02x.%x has been disabled due to "
1307 "system instability issues. "
1308 "Specify rombar=1 or romfile to force\n",
1309 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1310 vdev
->host
.function
);
1315 DPRINTF("%04x:%02x:%02x.%x ROM size 0x%x\n", vdev
->host
.domain
,
1316 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
, size
);
1318 snprintf(name
, sizeof(name
), "vfio[%04x:%02x:%02x.%x].rom",
1319 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1320 vdev
->host
.function
);
1322 memory_region_init_io(&vdev
->pdev
.rom
, OBJECT(vdev
),
1323 &vfio_rom_ops
, vdev
, name
, size
);
1325 pci_register_bar(&vdev
->pdev
, PCI_ROM_SLOT
,
1326 PCI_BASE_ADDRESS_SPACE_MEMORY
, &vdev
->pdev
.rom
);
1328 vdev
->pdev
.has_rom
= true;
1329 vdev
->rom_read_failed
= false;
1332 static void vfio_vga_write(void *opaque
, hwaddr addr
,
1333 uint64_t data
, unsigned size
)
1335 VFIOVGARegion
*region
= opaque
;
1336 VFIOVGA
*vga
= container_of(region
, VFIOVGA
, region
[region
->nr
]);
1343 off_t offset
= vga
->fd_offset
+ region
->offset
+ addr
;
1350 buf
.word
= cpu_to_le16(data
);
1353 buf
.dword
= cpu_to_le32(data
);
1356 hw_error("vfio: unsupported write size, %d bytes", size
);
1360 if (pwrite(vga
->fd
, &buf
, size
, offset
) != size
) {
1361 error_report("%s(,0x%"HWADDR_PRIx
", 0x%"PRIx64
", %d) failed: %m",
1362 __func__
, region
->offset
+ addr
, data
, size
);
1365 DPRINTF("%s(0x%"HWADDR_PRIx
", 0x%"PRIx64
", %d)\n",
1366 __func__
, region
->offset
+ addr
, data
, size
);
1369 static uint64_t vfio_vga_read(void *opaque
, hwaddr addr
, unsigned size
)
1371 VFIOVGARegion
*region
= opaque
;
1372 VFIOVGA
*vga
= container_of(region
, VFIOVGA
, region
[region
->nr
]);
1380 off_t offset
= vga
->fd_offset
+ region
->offset
+ addr
;
1382 if (pread(vga
->fd
, &buf
, size
, offset
) != size
) {
1383 error_report("%s(,0x%"HWADDR_PRIx
", %d) failed: %m",
1384 __func__
, region
->offset
+ addr
, size
);
1385 return (uint64_t)-1;
1393 data
= le16_to_cpu(buf
.word
);
1396 data
= le32_to_cpu(buf
.dword
);
1399 hw_error("vfio: unsupported read size, %d bytes", size
);
1403 DPRINTF("%s(0x%"HWADDR_PRIx
", %d) = 0x%"PRIx64
"\n",
1404 __func__
, region
->offset
+ addr
, size
, data
);
1409 static const MemoryRegionOps vfio_vga_ops
= {
1410 .read
= vfio_vga_read
,
1411 .write
= vfio_vga_write
,
1412 .endianness
= DEVICE_LITTLE_ENDIAN
,
1416 * Device specific quirks
1419 /* Is range1 fully contained within range2? */
1420 static bool vfio_range_contained(uint64_t first1
, uint64_t len1
,
1421 uint64_t first2
, uint64_t len2
) {
1422 return (first1
>= first2
&& first1
+ len1
<= first2
+ len2
);
1425 static bool vfio_flags_enabled(uint8_t flags
, uint8_t mask
)
1427 return (mask
&& (flags
& mask
) == mask
);
1430 static uint64_t vfio_generic_window_quirk_read(void *opaque
,
1431 hwaddr addr
, unsigned size
)
1433 VFIOQuirk
*quirk
= opaque
;
1434 VFIODevice
*vdev
= quirk
->vdev
;
1437 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.read_flags
) &&
1438 ranges_overlap(addr
, size
,
1439 quirk
->data
.data_offset
, quirk
->data
.data_size
)) {
1440 hwaddr offset
= addr
- quirk
->data
.data_offset
;
1442 if (!vfio_range_contained(addr
, size
, quirk
->data
.data_offset
,
1443 quirk
->data
.data_size
)) {
1444 hw_error("%s: window data read not fully contained: %s",
1445 __func__
, memory_region_name(&quirk
->mem
));
1448 data
= vfio_pci_read_config(&vdev
->pdev
,
1449 quirk
->data
.address_val
+ offset
, size
);
1451 DPRINTF("%s read(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
", %d) = 0x%"
1452 PRIx64
"\n", memory_region_name(&quirk
->mem
), vdev
->host
.domain
,
1453 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
1454 quirk
->data
.bar
, addr
, size
, data
);
1456 data
= vfio_bar_read(&vdev
->bars
[quirk
->data
.bar
],
1457 addr
+ quirk
->data
.base_offset
, size
);
1463 static void vfio_generic_window_quirk_write(void *opaque
, hwaddr addr
,
1464 uint64_t data
, unsigned size
)
1466 VFIOQuirk
*quirk
= opaque
;
1467 VFIODevice
*vdev
= quirk
->vdev
;
1469 if (ranges_overlap(addr
, size
,
1470 quirk
->data
.address_offset
, quirk
->data
.address_size
)) {
1472 if (addr
!= quirk
->data
.address_offset
) {
1473 hw_error("%s: offset write into address window: %s",
1474 __func__
, memory_region_name(&quirk
->mem
));
1477 if ((data
& ~quirk
->data
.address_mask
) == quirk
->data
.address_match
) {
1478 quirk
->data
.flags
|= quirk
->data
.write_flags
|
1479 quirk
->data
.read_flags
;
1480 quirk
->data
.address_val
= data
& quirk
->data
.address_mask
;
1482 quirk
->data
.flags
&= ~(quirk
->data
.write_flags
|
1483 quirk
->data
.read_flags
);
1487 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.write_flags
) &&
1488 ranges_overlap(addr
, size
,
1489 quirk
->data
.data_offset
, quirk
->data
.data_size
)) {
1490 hwaddr offset
= addr
- quirk
->data
.data_offset
;
1492 if (!vfio_range_contained(addr
, size
, quirk
->data
.data_offset
,
1493 quirk
->data
.data_size
)) {
1494 hw_error("%s: window data write not fully contained: %s",
1495 __func__
, memory_region_name(&quirk
->mem
));
1498 vfio_pci_write_config(&vdev
->pdev
,
1499 quirk
->data
.address_val
+ offset
, data
, size
);
1500 DPRINTF("%s write(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
", 0x%"
1501 PRIx64
", %d)\n", memory_region_name(&quirk
->mem
),
1502 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1503 vdev
->host
.function
, quirk
->data
.bar
, addr
, data
, size
);
1507 vfio_bar_write(&vdev
->bars
[quirk
->data
.bar
],
1508 addr
+ quirk
->data
.base_offset
, data
, size
);
1511 static const MemoryRegionOps vfio_generic_window_quirk
= {
1512 .read
= vfio_generic_window_quirk_read
,
1513 .write
= vfio_generic_window_quirk_write
,
1514 .endianness
= DEVICE_LITTLE_ENDIAN
,
1517 static uint64_t vfio_generic_quirk_read(void *opaque
,
1518 hwaddr addr
, unsigned size
)
1520 VFIOQuirk
*quirk
= opaque
;
1521 VFIODevice
*vdev
= quirk
->vdev
;
1522 hwaddr base
= quirk
->data
.address_match
& TARGET_PAGE_MASK
;
1523 hwaddr offset
= quirk
->data
.address_match
& ~TARGET_PAGE_MASK
;
1526 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.read_flags
) &&
1527 ranges_overlap(addr
, size
, offset
, quirk
->data
.address_mask
+ 1)) {
1528 if (!vfio_range_contained(addr
, size
, offset
,
1529 quirk
->data
.address_mask
+ 1)) {
1530 hw_error("%s: read not fully contained: %s",
1531 __func__
, memory_region_name(&quirk
->mem
));
1534 data
= vfio_pci_read_config(&vdev
->pdev
, addr
- offset
, size
);
1536 DPRINTF("%s read(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
", %d) = 0x%"
1537 PRIx64
"\n", memory_region_name(&quirk
->mem
), vdev
->host
.domain
,
1538 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
1539 quirk
->data
.bar
, addr
+ base
, size
, data
);
1541 data
= vfio_bar_read(&vdev
->bars
[quirk
->data
.bar
], addr
+ base
, size
);
1547 static void vfio_generic_quirk_write(void *opaque
, hwaddr addr
,
1548 uint64_t data
, unsigned size
)
1550 VFIOQuirk
*quirk
= opaque
;
1551 VFIODevice
*vdev
= quirk
->vdev
;
1552 hwaddr base
= quirk
->data
.address_match
& TARGET_PAGE_MASK
;
1553 hwaddr offset
= quirk
->data
.address_match
& ~TARGET_PAGE_MASK
;
1555 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.write_flags
) &&
1556 ranges_overlap(addr
, size
, offset
, quirk
->data
.address_mask
+ 1)) {
1557 if (!vfio_range_contained(addr
, size
, offset
,
1558 quirk
->data
.address_mask
+ 1)) {
1559 hw_error("%s: write not fully contained: %s",
1560 __func__
, memory_region_name(&quirk
->mem
));
1563 vfio_pci_write_config(&vdev
->pdev
, addr
- offset
, data
, size
);
1565 DPRINTF("%s write(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
", 0x%"
1566 PRIx64
", %d)\n", memory_region_name(&quirk
->mem
),
1567 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1568 vdev
->host
.function
, quirk
->data
.bar
, addr
+ base
, data
, size
);
1570 vfio_bar_write(&vdev
->bars
[quirk
->data
.bar
], addr
+ base
, data
, size
);
1574 static const MemoryRegionOps vfio_generic_quirk
= {
1575 .read
= vfio_generic_quirk_read
,
1576 .write
= vfio_generic_quirk_write
,
1577 .endianness
= DEVICE_LITTLE_ENDIAN
,
1580 #define PCI_VENDOR_ID_ATI 0x1002
1583 * Radeon HD cards (HD5450 & HD7850) report the upper byte of the I/O port BAR
1584 * through VGA register 0x3c3. On newer cards, the I/O port BAR is always
1585 * BAR4 (older cards like the X550 used BAR1, but we don't care to support
1586 * those). Note that on bare metal, a read of 0x3c3 doesn't always return the
1587 * I/O port BAR address. Originally this was coded to return the virtual BAR
1588 * address only if the physical register read returns the actual BAR address,
1589 * but users have reported greater success if we return the virtual address
1592 static uint64_t vfio_ati_3c3_quirk_read(void *opaque
,
1593 hwaddr addr
, unsigned size
)
1595 VFIOQuirk
*quirk
= opaque
;
1596 VFIODevice
*vdev
= quirk
->vdev
;
1597 uint64_t data
= vfio_pci_read_config(&vdev
->pdev
,
1598 PCI_BASE_ADDRESS_0
+ (4 * 4) + 1,
1600 DPRINTF("%s(0x3c3, 1) = 0x%"PRIx64
"\n", __func__
, data
);
1605 static const MemoryRegionOps vfio_ati_3c3_quirk
= {
1606 .read
= vfio_ati_3c3_quirk_read
,
1607 .endianness
= DEVICE_LITTLE_ENDIAN
,
1610 static void vfio_vga_probe_ati_3c3_quirk(VFIODevice
*vdev
)
1612 PCIDevice
*pdev
= &vdev
->pdev
;
1615 if (pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1620 * As long as the BAR is >= 256 bytes it will be aligned such that the
1621 * lower byte is always zero. Filter out anything else, if it exists.
1623 if (!vdev
->bars
[4].ioport
|| vdev
->bars
[4].size
< 256) {
1627 quirk
= g_malloc0(sizeof(*quirk
));
1630 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_ati_3c3_quirk
, quirk
,
1631 "vfio-ati-3c3-quirk", 1);
1632 memory_region_add_subregion(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
1633 3 /* offset 3 bytes from 0x3c0 */, &quirk
->mem
);
1635 QLIST_INSERT_HEAD(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
,
1638 DPRINTF("Enabled ATI/AMD quirk 0x3c3 BAR4for device %04x:%02x:%02x.%x\n",
1639 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1640 vdev
->host
.function
);
1644 * Newer ATI/AMD devices, including HD5450 and HD7850, have a window to PCI
1645 * config space through MMIO BAR2 at offset 0x4000. Nothing seems to access
1646 * the MMIO space directly, but a window to this space is provided through
1647 * I/O port BAR4. Offset 0x0 is the address register and offset 0x4 is the
1648 * data register. When the address is programmed to a range of 0x4000-0x4fff
1649 * PCI configuration space is available. Experimentation seems to indicate
1650 * that only read-only access is provided, but we drop writes when the window
1651 * is enabled to config space nonetheless.
1653 static void vfio_probe_ati_bar4_window_quirk(VFIODevice
*vdev
, int nr
)
1655 PCIDevice
*pdev
= &vdev
->pdev
;
1658 if (!vdev
->has_vga
|| nr
!= 4 ||
1659 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1663 quirk
= g_malloc0(sizeof(*quirk
));
1665 quirk
->data
.address_size
= 4;
1666 quirk
->data
.data_offset
= 4;
1667 quirk
->data
.data_size
= 4;
1668 quirk
->data
.address_match
= 0x4000;
1669 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
1670 quirk
->data
.bar
= nr
;
1671 quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1673 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
),
1674 &vfio_generic_window_quirk
, quirk
,
1675 "vfio-ati-bar4-window-quirk", 8);
1676 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].mem
,
1677 quirk
->data
.base_offset
, &quirk
->mem
, 1);
1679 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1681 DPRINTF("Enabled ATI/AMD BAR4 window quirk for device %04x:%02x:%02x.%x\n",
1682 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1683 vdev
->host
.function
);
1686 #define PCI_VENDOR_ID_REALTEK 0x10ec
1689 * RTL8168 devices have a backdoor that can access the MSI-X table. At BAR2
1690 * offset 0x70 there is a dword data register, offset 0x74 is a dword address
1691 * register. According to the Linux r8169 driver, the MSI-X table is addressed
1692 * when the "type" portion of the address register is set to 0x1. This appears
1693 * to be bits 16:30. Bit 31 is both a write indicator and some sort of
1694 * "address latched" indicator. Bits 12:15 are a mask field, which we can
1695 * ignore because the MSI-X table should always be accessed as a dword (full
1696 * mask). Bits 0:11 is offset within the type.
1700 * Read from MSI-X table offset 0
1701 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x74, 0x1f000, 4) // store read addr
1702 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x74, 4) = 0x8001f000 // latch
1703 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x70, 4) = 0xfee00398 // read data
1705 * Write 0xfee00000 to MSI-X table offset 0
1706 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x70, 0xfee00000, 4) // write data
1707 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x74, 0x8001f000, 4) // do write
1708 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x74, 4) = 0x1f000 // complete
1711 static uint64_t vfio_rtl8168_window_quirk_read(void *opaque
,
1712 hwaddr addr
, unsigned size
)
1714 VFIOQuirk
*quirk
= opaque
;
1715 VFIODevice
*vdev
= quirk
->vdev
;
1718 case 4: /* address */
1719 if (quirk
->data
.flags
) {
1720 DPRINTF("%s fake read(%04x:%02x:%02x.%d)\n",
1721 memory_region_name(&quirk
->mem
), vdev
->host
.domain
,
1722 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
1724 return quirk
->data
.address_match
^ 0x10000000U
;
1728 if (quirk
->data
.flags
) {
1731 DPRINTF("%s MSI-X table read(%04x:%02x:%02x.%d)\n",
1732 memory_region_name(&quirk
->mem
), vdev
->host
.domain
,
1733 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
1735 if (!(vdev
->pdev
.cap_present
& QEMU_PCI_CAP_MSIX
)) {
1739 io_mem_read(&vdev
->pdev
.msix_table_mmio
,
1740 (hwaddr
)(quirk
->data
.address_match
& 0xfff),
1746 DPRINTF("%s direct read(%04x:%02x:%02x.%d)\n",
1747 memory_region_name(&quirk
->mem
), vdev
->host
.domain
,
1748 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
1750 return vfio_bar_read(&vdev
->bars
[quirk
->data
.bar
], addr
+ 0x70, size
);
1753 static void vfio_rtl8168_window_quirk_write(void *opaque
, hwaddr addr
,
1754 uint64_t data
, unsigned size
)
1756 VFIOQuirk
*quirk
= opaque
;
1757 VFIODevice
*vdev
= quirk
->vdev
;
1760 case 4: /* address */
1761 if ((data
& 0x7fff0000) == 0x10000) {
1762 if (data
& 0x10000000U
&&
1763 vdev
->pdev
.cap_present
& QEMU_PCI_CAP_MSIX
) {
1765 DPRINTF("%s MSI-X table write(%04x:%02x:%02x.%d)\n",
1766 memory_region_name(&quirk
->mem
), vdev
->host
.domain
,
1767 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
1769 io_mem_write(&vdev
->pdev
.msix_table_mmio
,
1770 (hwaddr
)(quirk
->data
.address_match
& 0xfff),
1774 quirk
->data
.flags
= 1;
1775 quirk
->data
.address_match
= data
;
1779 quirk
->data
.flags
= 0;
1782 quirk
->data
.address_mask
= data
;
1786 DPRINTF("%s direct write(%04x:%02x:%02x.%d)\n",
1787 memory_region_name(&quirk
->mem
), vdev
->host
.domain
,
1788 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
1790 vfio_bar_write(&vdev
->bars
[quirk
->data
.bar
], addr
+ 0x70, data
, size
);
1793 static const MemoryRegionOps vfio_rtl8168_window_quirk
= {
1794 .read
= vfio_rtl8168_window_quirk_read
,
1795 .write
= vfio_rtl8168_window_quirk_write
,
1797 .min_access_size
= 4,
1798 .max_access_size
= 4,
1801 .endianness
= DEVICE_LITTLE_ENDIAN
,
1804 static void vfio_probe_rtl8168_bar2_window_quirk(VFIODevice
*vdev
, int nr
)
1806 PCIDevice
*pdev
= &vdev
->pdev
;
1809 if (pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_REALTEK
||
1810 pci_get_word(pdev
->config
+ PCI_DEVICE_ID
) != 0x8168 || nr
!= 2) {
1814 quirk
= g_malloc0(sizeof(*quirk
));
1816 quirk
->data
.bar
= nr
;
1818 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_rtl8168_window_quirk
,
1819 quirk
, "vfio-rtl8168-window-quirk", 8);
1820 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].mem
,
1821 0x70, &quirk
->mem
, 1);
1823 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1825 DPRINTF("Enabled RTL8168 BAR2 window quirk for device %04x:%02x:%02x.%x\n",
1826 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1827 vdev
->host
.function
);
1830 * Trap the BAR2 MMIO window to config space as well.
1832 static void vfio_probe_ati_bar2_4000_quirk(VFIODevice
*vdev
, int nr
)
1834 PCIDevice
*pdev
= &vdev
->pdev
;
1837 /* Only enable on newer devices where BAR2 is 64bit */
1838 if (!vdev
->has_vga
|| nr
!= 2 || !vdev
->bars
[2].mem64
||
1839 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1843 quirk
= g_malloc0(sizeof(*quirk
));
1845 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1846 quirk
->data
.address_match
= 0x4000;
1847 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
1848 quirk
->data
.bar
= nr
;
1850 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_generic_quirk
, quirk
,
1851 "vfio-ati-bar2-4000-quirk",
1852 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
1853 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].mem
,
1854 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
1857 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1859 DPRINTF("Enabled ATI/AMD BAR2 0x4000 quirk for device %04x:%02x:%02x.%x\n",
1860 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1861 vdev
->host
.function
);
1865 * Older ATI/AMD cards like the X550 have a similar window to that above.
1866 * I/O port BAR1 provides a window to a mirror of PCI config space located
1867 * in BAR2 at offset 0xf00. We don't care to support such older cards, but
1868 * note it for future reference.
1871 #define PCI_VENDOR_ID_NVIDIA 0x10de
1874 * Nvidia has several different methods to get to config space, the
1875 * nouveu project has several of these documented here:
1876 * https://github.com/pathscale/envytools/tree/master/hwdocs
1878 * The first quirk is actually not documented in envytools and is found
1879 * on 10de:01d1 (NVIDIA Corporation G72 [GeForce 7300 LE]). This is an
1880 * NV46 chipset. The backdoor uses the legacy VGA I/O ports to access
1881 * the mirror of PCI config space found at BAR0 offset 0x1800. The access
1882 * sequence first writes 0x338 to I/O port 0x3d4. The target offset is
1883 * then written to 0x3d0. Finally 0x538 is written for a read and 0x738
1884 * is written for a write to 0x3d4. The BAR0 offset is then accessible
1885 * through 0x3d0. This quirk doesn't seem to be necessary on newer cards
1886 * that use the I/O port BAR5 window but it doesn't hurt to leave it.
1896 static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque
,
1897 hwaddr addr
, unsigned size
)
1899 VFIOQuirk
*quirk
= opaque
;
1900 VFIODevice
*vdev
= quirk
->vdev
;
1901 PCIDevice
*pdev
= &vdev
->pdev
;
1902 uint64_t data
= vfio_vga_read(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
1903 addr
+ quirk
->data
.base_offset
, size
);
1905 if (quirk
->data
.flags
== NV_3D0_READ
&& addr
== quirk
->data
.data_offset
) {
1906 data
= vfio_pci_read_config(pdev
, quirk
->data
.address_val
, size
);
1907 DPRINTF("%s(0x3d0, %d) = 0x%"PRIx64
"\n", __func__
, size
, data
);
1910 quirk
->data
.flags
= NV_3D0_NONE
;
1915 static void vfio_nvidia_3d0_quirk_write(void *opaque
, hwaddr addr
,
1916 uint64_t data
, unsigned size
)
1918 VFIOQuirk
*quirk
= opaque
;
1919 VFIODevice
*vdev
= quirk
->vdev
;
1920 PCIDevice
*pdev
= &vdev
->pdev
;
1922 switch (quirk
->data
.flags
) {
1924 if (addr
== quirk
->data
.address_offset
&& data
== 0x338) {
1925 quirk
->data
.flags
= NV_3D0_SELECT
;
1929 quirk
->data
.flags
= NV_3D0_NONE
;
1930 if (addr
== quirk
->data
.data_offset
&&
1931 (data
& ~quirk
->data
.address_mask
) == quirk
->data
.address_match
) {
1932 quirk
->data
.flags
= NV_3D0_WINDOW
;
1933 quirk
->data
.address_val
= data
& quirk
->data
.address_mask
;
1937 quirk
->data
.flags
= NV_3D0_NONE
;
1938 if (addr
== quirk
->data
.address_offset
) {
1939 if (data
== 0x538) {
1940 quirk
->data
.flags
= NV_3D0_READ
;
1941 } else if (data
== 0x738) {
1942 quirk
->data
.flags
= NV_3D0_WRITE
;
1947 quirk
->data
.flags
= NV_3D0_NONE
;
1948 if (addr
== quirk
->data
.data_offset
) {
1949 vfio_pci_write_config(pdev
, quirk
->data
.address_val
, data
, size
);
1950 DPRINTF("%s(0x3d0, 0x%"PRIx64
", %d)\n", __func__
, data
, size
);
1956 vfio_vga_write(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
1957 addr
+ quirk
->data
.base_offset
, data
, size
);
1960 static const MemoryRegionOps vfio_nvidia_3d0_quirk
= {
1961 .read
= vfio_nvidia_3d0_quirk_read
,
1962 .write
= vfio_nvidia_3d0_quirk_write
,
1963 .endianness
= DEVICE_LITTLE_ENDIAN
,
1966 static void vfio_vga_probe_nvidia_3d0_quirk(VFIODevice
*vdev
)
1968 PCIDevice
*pdev
= &vdev
->pdev
;
1971 if (pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
||
1972 !vdev
->bars
[1].size
) {
1976 quirk
= g_malloc0(sizeof(*quirk
));
1978 quirk
->data
.base_offset
= 0x10;
1979 quirk
->data
.address_offset
= 4;
1980 quirk
->data
.address_size
= 2;
1981 quirk
->data
.address_match
= 0x1800;
1982 quirk
->data
.address_mask
= PCI_CONFIG_SPACE_SIZE
- 1;
1983 quirk
->data
.data_offset
= 0;
1984 quirk
->data
.data_size
= 4;
1986 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_nvidia_3d0_quirk
,
1987 quirk
, "vfio-nvidia-3d0-quirk", 6);
1988 memory_region_add_subregion(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
1989 quirk
->data
.base_offset
, &quirk
->mem
);
1991 QLIST_INSERT_HEAD(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
,
1994 DPRINTF("Enabled NVIDIA VGA 0x3d0 quirk for device %04x:%02x:%02x.%x\n",
1995 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1996 vdev
->host
.function
);
2000 * The second quirk is documented in envytools. The I/O port BAR5 is just
2001 * a set of address/data ports to the MMIO BARs. The BAR we care about is
2002 * again BAR0. This backdoor is apparently a bit newer than the one above
2003 * so we need to not only trap 256 bytes @0x1800, but all of PCI config
2004 * space, including extended space is available at the 4k @0x88000.
2007 NV_BAR5_ADDRESS
= 0x1,
2008 NV_BAR5_ENABLE
= 0x2,
2009 NV_BAR5_MASTER
= 0x4,
2010 NV_BAR5_VALID
= 0x7,
2013 static void vfio_nvidia_bar5_window_quirk_write(void *opaque
, hwaddr addr
,
2014 uint64_t data
, unsigned size
)
2016 VFIOQuirk
*quirk
= opaque
;
2021 quirk
->data
.flags
|= NV_BAR5_MASTER
;
2023 quirk
->data
.flags
&= ~NV_BAR5_MASTER
;
2028 quirk
->data
.flags
|= NV_BAR5_ENABLE
;
2030 quirk
->data
.flags
&= ~NV_BAR5_ENABLE
;
2034 if (quirk
->data
.flags
& NV_BAR5_MASTER
) {
2035 if ((data
& ~0xfff) == 0x88000) {
2036 quirk
->data
.flags
|= NV_BAR5_ADDRESS
;
2037 quirk
->data
.address_val
= data
& 0xfff;
2038 } else if ((data
& ~0xff) == 0x1800) {
2039 quirk
->data
.flags
|= NV_BAR5_ADDRESS
;
2040 quirk
->data
.address_val
= data
& 0xff;
2042 quirk
->data
.flags
&= ~NV_BAR5_ADDRESS
;
2048 vfio_generic_window_quirk_write(opaque
, addr
, data
, size
);
2051 static const MemoryRegionOps vfio_nvidia_bar5_window_quirk
= {
2052 .read
= vfio_generic_window_quirk_read
,
2053 .write
= vfio_nvidia_bar5_window_quirk_write
,
2054 .valid
.min_access_size
= 4,
2055 .endianness
= DEVICE_LITTLE_ENDIAN
,
2058 static void vfio_probe_nvidia_bar5_window_quirk(VFIODevice
*vdev
, int nr
)
2060 PCIDevice
*pdev
= &vdev
->pdev
;
2063 if (!vdev
->has_vga
|| nr
!= 5 ||
2064 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
) {
2068 quirk
= g_malloc0(sizeof(*quirk
));
2070 quirk
->data
.read_flags
= quirk
->data
.write_flags
= NV_BAR5_VALID
;
2071 quirk
->data
.address_offset
= 0x8;
2072 quirk
->data
.address_size
= 0; /* actually 4, but avoids generic code */
2073 quirk
->data
.data_offset
= 0xc;
2074 quirk
->data
.data_size
= 4;
2075 quirk
->data
.bar
= nr
;
2077 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
),
2078 &vfio_nvidia_bar5_window_quirk
, quirk
,
2079 "vfio-nvidia-bar5-window-quirk", 16);
2080 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].mem
, 0, &quirk
->mem
, 1);
2082 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
2084 DPRINTF("Enabled NVIDIA BAR5 window quirk for device %04x:%02x:%02x.%x\n",
2085 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2086 vdev
->host
.function
);
2089 static void vfio_nvidia_88000_quirk_write(void *opaque
, hwaddr addr
,
2090 uint64_t data
, unsigned size
)
2092 VFIOQuirk
*quirk
= opaque
;
2093 VFIODevice
*vdev
= quirk
->vdev
;
2094 PCIDevice
*pdev
= &vdev
->pdev
;
2095 hwaddr base
= quirk
->data
.address_match
& TARGET_PAGE_MASK
;
2097 vfio_generic_quirk_write(opaque
, addr
, data
, size
);
2100 * Nvidia seems to acknowledge MSI interrupts by writing 0xff to the
2101 * MSI capability ID register. Both the ID and next register are
2102 * read-only, so we allow writes covering either of those to real hw.
2103 * NB - only fixed for the 0x88000 MMIO window.
2105 if ((pdev
->cap_present
& QEMU_PCI_CAP_MSI
) &&
2106 vfio_range_contained(addr
, size
, pdev
->msi_cap
, PCI_MSI_FLAGS
)) {
2107 vfio_bar_write(&vdev
->bars
[quirk
->data
.bar
], addr
+ base
, data
, size
);
2111 static const MemoryRegionOps vfio_nvidia_88000_quirk
= {
2112 .read
= vfio_generic_quirk_read
,
2113 .write
= vfio_nvidia_88000_quirk_write
,
2114 .endianness
= DEVICE_LITTLE_ENDIAN
,
2118 * Finally, BAR0 itself. We want to redirect any accesses to either
2119 * 0x1800 or 0x88000 through the PCI config space access functions.
2121 * NB - quirk at a page granularity or else they don't seem to work when
2124 * Here's offset 0x88000...
2126 static void vfio_probe_nvidia_bar0_88000_quirk(VFIODevice
*vdev
, int nr
)
2128 PCIDevice
*pdev
= &vdev
->pdev
;
2131 if (!vdev
->has_vga
|| nr
!= 0 ||
2132 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
) {
2136 quirk
= g_malloc0(sizeof(*quirk
));
2138 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
2139 quirk
->data
.address_match
= 0x88000;
2140 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
2141 quirk
->data
.bar
= nr
;
2143 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_nvidia_88000_quirk
,
2144 quirk
, "vfio-nvidia-bar0-88000-quirk",
2145 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
2146 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].mem
,
2147 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
2150 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
2152 DPRINTF("Enabled NVIDIA BAR0 0x88000 quirk for device %04x:%02x:%02x.%x\n",
2153 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2154 vdev
->host
.function
);
2158 * And here's the same for BAR0 offset 0x1800...
2160 static void vfio_probe_nvidia_bar0_1800_quirk(VFIODevice
*vdev
, int nr
)
2162 PCIDevice
*pdev
= &vdev
->pdev
;
2165 if (!vdev
->has_vga
|| nr
!= 0 ||
2166 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
) {
2170 /* Log the chipset ID */
2171 DPRINTF("Nvidia NV%02x\n",
2172 (unsigned int)(vfio_bar_read(&vdev
->bars
[0], 0, 4) >> 20) & 0xff);
2174 quirk
= g_malloc0(sizeof(*quirk
));
2176 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
2177 quirk
->data
.address_match
= 0x1800;
2178 quirk
->data
.address_mask
= PCI_CONFIG_SPACE_SIZE
- 1;
2179 quirk
->data
.bar
= nr
;
2181 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_generic_quirk
, quirk
,
2182 "vfio-nvidia-bar0-1800-quirk",
2183 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
2184 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].mem
,
2185 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
2188 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
2190 DPRINTF("Enabled NVIDIA BAR0 0x1800 quirk for device %04x:%02x:%02x.%x\n",
2191 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2192 vdev
->host
.function
);
2196 * TODO - Some Nvidia devices provide config access to their companion HDA
2197 * device and even to their parent bridge via these config space mirrors.
2198 * Add quirks for those regions.
2202 * Common quirk probe entry points.
2204 static void vfio_vga_quirk_setup(VFIODevice
*vdev
)
2206 vfio_vga_probe_ati_3c3_quirk(vdev
);
2207 vfio_vga_probe_nvidia_3d0_quirk(vdev
);
2210 static void vfio_vga_quirk_teardown(VFIODevice
*vdev
)
2214 for (i
= 0; i
< ARRAY_SIZE(vdev
->vga
.region
); i
++) {
2215 while (!QLIST_EMPTY(&vdev
->vga
.region
[i
].quirks
)) {
2216 VFIOQuirk
*quirk
= QLIST_FIRST(&vdev
->vga
.region
[i
].quirks
);
2217 memory_region_del_subregion(&vdev
->vga
.region
[i
].mem
, &quirk
->mem
);
2218 memory_region_destroy(&quirk
->mem
);
2219 QLIST_REMOVE(quirk
, next
);
2225 static void vfio_bar_quirk_setup(VFIODevice
*vdev
, int nr
)
2227 vfio_probe_ati_bar4_window_quirk(vdev
, nr
);
2228 vfio_probe_ati_bar2_4000_quirk(vdev
, nr
);
2229 vfio_probe_nvidia_bar5_window_quirk(vdev
, nr
);
2230 vfio_probe_nvidia_bar0_88000_quirk(vdev
, nr
);
2231 vfio_probe_nvidia_bar0_1800_quirk(vdev
, nr
);
2232 vfio_probe_rtl8168_bar2_window_quirk(vdev
, nr
);
2235 static void vfio_bar_quirk_teardown(VFIODevice
*vdev
, int nr
)
2237 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2239 while (!QLIST_EMPTY(&bar
->quirks
)) {
2240 VFIOQuirk
*quirk
= QLIST_FIRST(&bar
->quirks
);
2241 memory_region_del_subregion(&bar
->mem
, &quirk
->mem
);
2242 memory_region_destroy(&quirk
->mem
);
2243 QLIST_REMOVE(quirk
, next
);
2251 static uint32_t vfio_pci_read_config(PCIDevice
*pdev
, uint32_t addr
, int len
)
2253 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
2254 uint32_t emu_bits
= 0, emu_val
= 0, phys_val
= 0, val
;
2256 memcpy(&emu_bits
, vdev
->emulated_config_bits
+ addr
, len
);
2257 emu_bits
= le32_to_cpu(emu_bits
);
2260 emu_val
= pci_default_read_config(pdev
, addr
, len
);
2263 if (~emu_bits
& (0xffffffffU
>> (32 - len
* 8))) {
2266 ret
= pread(vdev
->fd
, &phys_val
, len
, vdev
->config_offset
+ addr
);
2268 error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x) failed: %m",
2269 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
2270 vdev
->host
.slot
, vdev
->host
.function
, addr
, len
);
2273 phys_val
= le32_to_cpu(phys_val
);
2276 val
= (emu_val
& emu_bits
) | (phys_val
& ~emu_bits
);
2278 DPRINTF("%s(%04x:%02x:%02x.%x, @0x%x, len=0x%x) %x\n", __func__
,
2279 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2280 vdev
->host
.function
, addr
, len
, val
);
2285 static void vfio_pci_write_config(PCIDevice
*pdev
, uint32_t addr
,
2286 uint32_t val
, int len
)
2288 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
2289 uint32_t val_le
= cpu_to_le32(val
);
2291 DPRINTF("%s(%04x:%02x:%02x.%x, @0x%x, 0x%x, len=0x%x)\n", __func__
,
2292 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2293 vdev
->host
.function
, addr
, val
, len
);
2295 /* Write everything to VFIO, let it filter out what we can't write */
2296 if (pwrite(vdev
->fd
, &val_le
, len
, vdev
->config_offset
+ addr
) != len
) {
2297 error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x, 0x%x) failed: %m",
2298 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
2299 vdev
->host
.slot
, vdev
->host
.function
, addr
, val
, len
);
2302 /* MSI/MSI-X Enabling/Disabling */
2303 if (pdev
->cap_present
& QEMU_PCI_CAP_MSI
&&
2304 ranges_overlap(addr
, len
, pdev
->msi_cap
, vdev
->msi_cap_size
)) {
2305 int is_enabled
, was_enabled
= msi_enabled(pdev
);
2307 pci_default_write_config(pdev
, addr
, val
, len
);
2309 is_enabled
= msi_enabled(pdev
);
2313 vfio_enable_msi(vdev
);
2317 vfio_disable_msi(vdev
);
2319 vfio_update_msi(vdev
);
2322 } else if (pdev
->cap_present
& QEMU_PCI_CAP_MSIX
&&
2323 ranges_overlap(addr
, len
, pdev
->msix_cap
, MSIX_CAP_LENGTH
)) {
2324 int is_enabled
, was_enabled
= msix_enabled(pdev
);
2326 pci_default_write_config(pdev
, addr
, val
, len
);
2328 is_enabled
= msix_enabled(pdev
);
2330 if (!was_enabled
&& is_enabled
) {
2331 vfio_enable_msix(vdev
);
2332 } else if (was_enabled
&& !is_enabled
) {
2333 vfio_disable_msix(vdev
);
2336 /* Write everything to QEMU to keep emulated bits correct */
2337 pci_default_write_config(pdev
, addr
, val
, len
);
2342 * DMA - Mapping and unmapping for the "type1" IOMMU interface used on x86
2344 static int vfio_dma_unmap(VFIOContainer
*container
,
2345 hwaddr iova
, ram_addr_t size
)
2347 struct vfio_iommu_type1_dma_unmap unmap
= {
2348 .argsz
= sizeof(unmap
),
2354 if (ioctl(container
->fd
, VFIO_IOMMU_UNMAP_DMA
, &unmap
)) {
2355 DPRINTF("VFIO_UNMAP_DMA: %d\n", -errno
);
2362 static int vfio_dma_map(VFIOContainer
*container
, hwaddr iova
,
2363 ram_addr_t size
, void *vaddr
, bool readonly
)
2365 struct vfio_iommu_type1_dma_map map
= {
2366 .argsz
= sizeof(map
),
2367 .flags
= VFIO_DMA_MAP_FLAG_READ
,
2368 .vaddr
= (__u64
)(uintptr_t)vaddr
,
2374 map
.flags
|= VFIO_DMA_MAP_FLAG_WRITE
;
2378 * Try the mapping, if it fails with EBUSY, unmap the region and try
2379 * again. This shouldn't be necessary, but we sometimes see it in
2380 * the the VGA ROM space.
2382 if (ioctl(container
->fd
, VFIO_IOMMU_MAP_DMA
, &map
) == 0 ||
2383 (errno
== EBUSY
&& vfio_dma_unmap(container
, iova
, size
) == 0 &&
2384 ioctl(container
->fd
, VFIO_IOMMU_MAP_DMA
, &map
) == 0)) {
2388 DPRINTF("VFIO_MAP_DMA: %d\n", -errno
);
2392 static bool vfio_listener_skipped_section(MemoryRegionSection
*section
)
2394 return (!memory_region_is_ram(section
->mr
) &&
2395 !memory_region_is_iommu(section
->mr
)) ||
2397 * Sizing an enabled 64-bit BAR can cause spurious mappings to
2398 * addresses in the upper part of the 64-bit address space. These
2399 * are never accessed by the CPU and beyond the address width of
2400 * some IOMMU hardware. TODO: VFIO should tell us the IOMMU width.
2402 section
->offset_within_address_space
& (1ULL << 63);
2405 static void vfio_iommu_map_notify(Notifier
*n
, void *data
)
2407 VFIOGuestIOMMU
*giommu
= container_of(n
, VFIOGuestIOMMU
, n
);
2408 VFIOContainer
*container
= giommu
->container
;
2409 IOMMUTLBEntry
*iotlb
= data
;
2412 hwaddr len
= iotlb
->addr_mask
+ 1;
2416 DPRINTF("iommu map @ %"HWADDR_PRIx
" - %"HWADDR_PRIx
"\n",
2417 iotlb
->iova
, iotlb
->iova
+ iotlb
->addr_mask
);
2420 * The IOMMU TLB entry we have just covers translation through
2421 * this IOMMU to its immediate target. We need to translate
2422 * it the rest of the way through to memory.
2424 mr
= address_space_translate(&address_space_memory
,
2425 iotlb
->translated_addr
,
2426 &xlat
, &len
, iotlb
->perm
& IOMMU_WO
);
2427 if (!memory_region_is_ram(mr
)) {
2428 DPRINTF("iommu map to non memory area %"HWADDR_PRIx
"\n",
2433 * Translation truncates length to the IOMMU page size,
2434 * check that it did not truncate too much.
2436 if (len
& iotlb
->addr_mask
) {
2437 DPRINTF("iommu has granularity incompatible with target AS\n");
2441 if (iotlb
->perm
!= IOMMU_NONE
) {
2442 vaddr
= memory_region_get_ram_ptr(mr
) + xlat
;
2444 ret
= vfio_dma_map(container
, iotlb
->iova
,
2445 iotlb
->addr_mask
+ 1, vaddr
,
2446 !(iotlb
->perm
& IOMMU_WO
) || mr
->readonly
);
2448 error_report("vfio_dma_map(%p, 0x%"HWADDR_PRIx
", "
2449 "0x%"HWADDR_PRIx
", %p) = %d (%m)",
2450 container
, iotlb
->iova
,
2451 iotlb
->addr_mask
+ 1, vaddr
, ret
);
2454 ret
= vfio_dma_unmap(container
, iotlb
->iova
, iotlb
->addr_mask
+ 1);
2456 error_report("vfio_dma_unmap(%p, 0x%"HWADDR_PRIx
", "
2457 "0x%"HWADDR_PRIx
") = %d (%m)",
2458 container
, iotlb
->iova
,
2459 iotlb
->addr_mask
+ 1, ret
);
2464 static void vfio_listener_region_add(MemoryListener
*listener
,
2465 MemoryRegionSection
*section
)
2467 VFIOContainer
*container
= container_of(listener
, VFIOContainer
,
2468 iommu_data
.type1
.listener
);
2474 if (vfio_listener_skipped_section(section
)) {
2475 DPRINTF("SKIPPING region_add %"HWADDR_PRIx
" - %"PRIx64
"\n",
2476 section
->offset_within_address_space
,
2477 section
->offset_within_address_space
+
2478 int128_get64(int128_sub(section
->size
, int128_one())));
2482 if (unlikely((section
->offset_within_address_space
& ~TARGET_PAGE_MASK
) !=
2483 (section
->offset_within_region
& ~TARGET_PAGE_MASK
))) {
2484 error_report("%s received unaligned region", __func__
);
2488 iova
= TARGET_PAGE_ALIGN(section
->offset_within_address_space
);
2489 llend
= int128_make64(section
->offset_within_address_space
);
2490 llend
= int128_add(llend
, section
->size
);
2491 llend
= int128_and(llend
, int128_exts64(TARGET_PAGE_MASK
));
2493 if (int128_ge(int128_make64(iova
), llend
)) {
2497 memory_region_ref(section
->mr
);
2499 if (memory_region_is_iommu(section
->mr
)) {
2500 VFIOGuestIOMMU
*giommu
;
2502 DPRINTF("region_add [iommu] %"HWADDR_PRIx
" - %"HWADDR_PRIx
"\n",
2503 iova
, int128_get64(int128_sub(llend
, int128_one())));
2505 * FIXME: We should do some checking to see if the
2506 * capabilities of the host VFIO IOMMU are adequate to model
2509 * FIXME: For VFIO iommu types which have KVM acceleration to
2510 * avoid bouncing all map/unmaps through qemu this way, this
2511 * would be the right place to wire that up (tell the KVM
2512 * device emulation the VFIO iommu handles to use).
2515 * This assumes that the guest IOMMU is empty of
2516 * mappings at this point.
2518 * One way of doing this is:
2519 * 1. Avoid sharing IOMMUs between emulated devices or different
2521 * 2. Implement VFIO_IOMMU_ENABLE in the host kernel to fail if
2522 * there are some mappings in IOMMU.
2524 * VFIO on SPAPR does that. Other IOMMU models may do that different,
2525 * they must make sure there are no existing mappings or
2526 * loop through existing mappings to map them into VFIO.
2528 giommu
= g_malloc0(sizeof(*giommu
));
2529 giommu
->iommu
= section
->mr
;
2530 giommu
->container
= container
;
2531 giommu
->n
.notify
= vfio_iommu_map_notify
;
2532 QLIST_INSERT_HEAD(&container
->giommu_list
, giommu
, giommu_next
);
2533 memory_region_register_iommu_notifier(giommu
->iommu
, &giommu
->n
);
2538 /* Here we assume that memory_region_is_ram(section->mr)==true */
2540 end
= int128_get64(llend
);
2541 vaddr
= memory_region_get_ram_ptr(section
->mr
) +
2542 section
->offset_within_region
+
2543 (iova
- section
->offset_within_address_space
);
2545 DPRINTF("region_add [ram] %"HWADDR_PRIx
" - %"HWADDR_PRIx
" [%p]\n",
2546 iova
, end
- 1, vaddr
);
2548 ret
= vfio_dma_map(container
, iova
, end
- iova
, vaddr
, section
->readonly
);
2550 error_report("vfio_dma_map(%p, 0x%"HWADDR_PRIx
", "
2551 "0x%"HWADDR_PRIx
", %p) = %d (%m)",
2552 container
, iova
, end
- iova
, vaddr
, ret
);
2555 * On the initfn path, store the first error in the container so we
2556 * can gracefully fail. Runtime, there's not much we can do other
2557 * than throw a hardware error.
2559 if (!container
->iommu_data
.type1
.initialized
) {
2560 if (!container
->iommu_data
.type1
.error
) {
2561 container
->iommu_data
.type1
.error
= ret
;
2564 hw_error("vfio: DMA mapping failed, unable to continue");
2569 static void vfio_listener_region_del(MemoryListener
*listener
,
2570 MemoryRegionSection
*section
)
2572 VFIOContainer
*container
= container_of(listener
, VFIOContainer
,
2573 iommu_data
.type1
.listener
);
2577 if (vfio_listener_skipped_section(section
)) {
2578 DPRINTF("SKIPPING region_del %"HWADDR_PRIx
" - %"PRIx64
"\n",
2579 section
->offset_within_address_space
,
2580 section
->offset_within_address_space
+
2581 int128_get64(int128_sub(section
->size
, int128_one())));
2585 if (unlikely((section
->offset_within_address_space
& ~TARGET_PAGE_MASK
) !=
2586 (section
->offset_within_region
& ~TARGET_PAGE_MASK
))) {
2587 error_report("%s received unaligned region", __func__
);
2591 if (memory_region_is_iommu(section
->mr
)) {
2592 VFIOGuestIOMMU
*giommu
;
2594 QLIST_FOREACH(giommu
, &container
->giommu_list
, giommu_next
) {
2595 if (giommu
->iommu
== section
->mr
) {
2596 memory_region_unregister_iommu_notifier(&giommu
->n
);
2597 QLIST_REMOVE(giommu
, giommu_next
);
2604 * FIXME: We assume the one big unmap below is adequate to
2605 * remove any individual page mappings in the IOMMU which
2606 * might have been copied into VFIO. This works for a page table
2607 * based IOMMU where a big unmap flattens a large range of IO-PTEs.
2608 * That may not be true for all IOMMU types.
2612 iova
= TARGET_PAGE_ALIGN(section
->offset_within_address_space
);
2613 end
= (section
->offset_within_address_space
+ int128_get64(section
->size
)) &
2620 DPRINTF("region_del %"HWADDR_PRIx
" - %"HWADDR_PRIx
"\n",
2623 ret
= vfio_dma_unmap(container
, iova
, end
- iova
);
2624 memory_region_unref(section
->mr
);
2626 error_report("vfio_dma_unmap(%p, 0x%"HWADDR_PRIx
", "
2627 "0x%"HWADDR_PRIx
") = %d (%m)",
2628 container
, iova
, end
- iova
, ret
);
2632 static MemoryListener vfio_memory_listener
= {
2633 .region_add
= vfio_listener_region_add
,
2634 .region_del
= vfio_listener_region_del
,
2637 static void vfio_listener_release(VFIOContainer
*container
)
2639 memory_listener_unregister(&container
->iommu_data
.type1
.listener
);
2645 static void vfio_disable_interrupts(VFIODevice
*vdev
)
2647 switch (vdev
->interrupt
) {
2649 vfio_disable_intx(vdev
);
2652 vfio_disable_msi(vdev
);
2655 vfio_disable_msix(vdev
);
2660 static int vfio_setup_msi(VFIODevice
*vdev
, int pos
)
2663 bool msi_64bit
, msi_maskbit
;
2666 if (pread(vdev
->fd
, &ctrl
, sizeof(ctrl
),
2667 vdev
->config_offset
+ pos
+ PCI_CAP_FLAGS
) != sizeof(ctrl
)) {
2670 ctrl
= le16_to_cpu(ctrl
);
2672 msi_64bit
= !!(ctrl
& PCI_MSI_FLAGS_64BIT
);
2673 msi_maskbit
= !!(ctrl
& PCI_MSI_FLAGS_MASKBIT
);
2674 entries
= 1 << ((ctrl
& PCI_MSI_FLAGS_QMASK
) >> 1);
2676 DPRINTF("%04x:%02x:%02x.%x PCI MSI CAP @0x%x\n", vdev
->host
.domain
,
2677 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
, pos
);
2679 ret
= msi_init(&vdev
->pdev
, pos
, entries
, msi_64bit
, msi_maskbit
);
2681 if (ret
== -ENOTSUP
) {
2684 error_report("vfio: msi_init failed");
2687 vdev
->msi_cap_size
= 0xa + (msi_maskbit
? 0xa : 0) + (msi_64bit
? 0x4 : 0);
2693 * We don't have any control over how pci_add_capability() inserts
2694 * capabilities into the chain. In order to setup MSI-X we need a
2695 * MemoryRegion for the BAR. In order to setup the BAR and not
2696 * attempt to mmap the MSI-X table area, which VFIO won't allow, we
2697 * need to first look for where the MSI-X table lives. So we
2698 * unfortunately split MSI-X setup across two functions.
2700 static int vfio_early_setup_msix(VFIODevice
*vdev
)
2704 uint32_t table
, pba
;
2706 pos
= pci_find_capability(&vdev
->pdev
, PCI_CAP_ID_MSIX
);
2711 if (pread(vdev
->fd
, &ctrl
, sizeof(ctrl
),
2712 vdev
->config_offset
+ pos
+ PCI_CAP_FLAGS
) != sizeof(ctrl
)) {
2716 if (pread(vdev
->fd
, &table
, sizeof(table
),
2717 vdev
->config_offset
+ pos
+ PCI_MSIX_TABLE
) != sizeof(table
)) {
2721 if (pread(vdev
->fd
, &pba
, sizeof(pba
),
2722 vdev
->config_offset
+ pos
+ PCI_MSIX_PBA
) != sizeof(pba
)) {
2726 ctrl
= le16_to_cpu(ctrl
);
2727 table
= le32_to_cpu(table
);
2728 pba
= le32_to_cpu(pba
);
2730 vdev
->msix
= g_malloc0(sizeof(*(vdev
->msix
)));
2731 vdev
->msix
->table_bar
= table
& PCI_MSIX_FLAGS_BIRMASK
;
2732 vdev
->msix
->table_offset
= table
& ~PCI_MSIX_FLAGS_BIRMASK
;
2733 vdev
->msix
->pba_bar
= pba
& PCI_MSIX_FLAGS_BIRMASK
;
2734 vdev
->msix
->pba_offset
= pba
& ~PCI_MSIX_FLAGS_BIRMASK
;
2735 vdev
->msix
->entries
= (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
2737 DPRINTF("%04x:%02x:%02x.%x "
2738 "PCI MSI-X CAP @0x%x, BAR %d, offset 0x%x, entries %d\n",
2739 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2740 vdev
->host
.function
, pos
, vdev
->msix
->table_bar
,
2741 vdev
->msix
->table_offset
, vdev
->msix
->entries
);
2746 static int vfio_setup_msix(VFIODevice
*vdev
, int pos
)
2750 ret
= msix_init(&vdev
->pdev
, vdev
->msix
->entries
,
2751 &vdev
->bars
[vdev
->msix
->table_bar
].mem
,
2752 vdev
->msix
->table_bar
, vdev
->msix
->table_offset
,
2753 &vdev
->bars
[vdev
->msix
->pba_bar
].mem
,
2754 vdev
->msix
->pba_bar
, vdev
->msix
->pba_offset
, pos
);
2756 if (ret
== -ENOTSUP
) {
2759 error_report("vfio: msix_init failed");
2766 static void vfio_teardown_msi(VFIODevice
*vdev
)
2768 msi_uninit(&vdev
->pdev
);
2771 msix_uninit(&vdev
->pdev
, &vdev
->bars
[vdev
->msix
->table_bar
].mem
,
2772 &vdev
->bars
[vdev
->msix
->pba_bar
].mem
);
2779 static void vfio_mmap_set_enabled(VFIODevice
*vdev
, bool enabled
)
2783 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2784 VFIOBAR
*bar
= &vdev
->bars
[i
];
2790 memory_region_set_enabled(&bar
->mmap_mem
, enabled
);
2791 if (vdev
->msix
&& vdev
->msix
->table_bar
== i
) {
2792 memory_region_set_enabled(&vdev
->msix
->mmap_mem
, enabled
);
2797 static void vfio_unmap_bar(VFIODevice
*vdev
, int nr
)
2799 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2805 vfio_bar_quirk_teardown(vdev
, nr
);
2807 memory_region_del_subregion(&bar
->mem
, &bar
->mmap_mem
);
2808 munmap(bar
->mmap
, memory_region_size(&bar
->mmap_mem
));
2809 memory_region_destroy(&bar
->mmap_mem
);
2811 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2812 memory_region_del_subregion(&bar
->mem
, &vdev
->msix
->mmap_mem
);
2813 munmap(vdev
->msix
->mmap
, memory_region_size(&vdev
->msix
->mmap_mem
));
2814 memory_region_destroy(&vdev
->msix
->mmap_mem
);
2817 memory_region_destroy(&bar
->mem
);
2820 static int vfio_mmap_bar(VFIODevice
*vdev
, VFIOBAR
*bar
,
2821 MemoryRegion
*mem
, MemoryRegion
*submem
,
2822 void **map
, size_t size
, off_t offset
,
2827 if (VFIO_ALLOW_MMAP
&& size
&& bar
->flags
& VFIO_REGION_INFO_FLAG_MMAP
) {
2830 if (bar
->flags
& VFIO_REGION_INFO_FLAG_READ
) {
2834 if (bar
->flags
& VFIO_REGION_INFO_FLAG_WRITE
) {
2838 *map
= mmap(NULL
, size
, prot
, MAP_SHARED
,
2839 bar
->fd
, bar
->fd_offset
+ offset
);
2840 if (*map
== MAP_FAILED
) {
2846 memory_region_init_ram_ptr(submem
, OBJECT(vdev
), name
, size
, *map
);
2849 /* Create a zero sized sub-region to make cleanup easy. */
2850 memory_region_init(submem
, OBJECT(vdev
), name
, 0);
2853 memory_region_add_subregion(mem
, offset
, submem
);
2858 static void vfio_map_bar(VFIODevice
*vdev
, int nr
)
2860 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2861 unsigned size
= bar
->size
;
2867 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */
2872 snprintf(name
, sizeof(name
), "VFIO %04x:%02x:%02x.%x BAR %d",
2873 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2874 vdev
->host
.function
, nr
);
2876 /* Determine what type of BAR this is for registration */
2877 ret
= pread(vdev
->fd
, &pci_bar
, sizeof(pci_bar
),
2878 vdev
->config_offset
+ PCI_BASE_ADDRESS_0
+ (4 * nr
));
2879 if (ret
!= sizeof(pci_bar
)) {
2880 error_report("vfio: Failed to read BAR %d (%m)", nr
);
2884 pci_bar
= le32_to_cpu(pci_bar
);
2885 bar
->ioport
= (pci_bar
& PCI_BASE_ADDRESS_SPACE_IO
);
2886 bar
->mem64
= bar
->ioport
? 0 : (pci_bar
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
2887 type
= pci_bar
& (bar
->ioport
? ~PCI_BASE_ADDRESS_IO_MASK
:
2888 ~PCI_BASE_ADDRESS_MEM_MASK
);
2890 /* A "slow" read/write mapping underlies all BARs */
2891 memory_region_init_io(&bar
->mem
, OBJECT(vdev
), &vfio_bar_ops
,
2893 pci_register_bar(&vdev
->pdev
, nr
, type
, &bar
->mem
);
2896 * We can't mmap areas overlapping the MSIX vector table, so we
2897 * potentially insert a direct-mapped subregion before and after it.
2899 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2900 size
= vdev
->msix
->table_offset
& qemu_host_page_mask
;
2903 strncat(name
, " mmap", sizeof(name
) - strlen(name
) - 1);
2904 if (vfio_mmap_bar(vdev
, bar
, &bar
->mem
,
2905 &bar
->mmap_mem
, &bar
->mmap
, size
, 0, name
)) {
2906 error_report("%s unsupported. Performance may be slow", name
);
2909 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2912 start
= HOST_PAGE_ALIGN(vdev
->msix
->table_offset
+
2913 (vdev
->msix
->entries
* PCI_MSIX_ENTRY_SIZE
));
2915 size
= start
< bar
->size
? bar
->size
- start
: 0;
2916 strncat(name
, " msix-hi", sizeof(name
) - strlen(name
) - 1);
2917 /* VFIOMSIXInfo contains another MemoryRegion for this mapping */
2918 if (vfio_mmap_bar(vdev
, bar
, &bar
->mem
, &vdev
->msix
->mmap_mem
,
2919 &vdev
->msix
->mmap
, size
, start
, name
)) {
2920 error_report("%s unsupported. Performance may be slow", name
);
2924 vfio_bar_quirk_setup(vdev
, nr
);
2927 static void vfio_map_bars(VFIODevice
*vdev
)
2931 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2932 vfio_map_bar(vdev
, i
);
2935 if (vdev
->has_vga
) {
2936 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].mem
,
2937 OBJECT(vdev
), &vfio_vga_ops
,
2938 &vdev
->vga
.region
[QEMU_PCI_VGA_MEM
],
2939 "vfio-vga-mmio@0xa0000",
2940 QEMU_PCI_VGA_MEM_SIZE
);
2941 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].mem
,
2942 OBJECT(vdev
), &vfio_vga_ops
,
2943 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
],
2944 "vfio-vga-io@0x3b0",
2945 QEMU_PCI_VGA_IO_LO_SIZE
);
2946 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
2947 OBJECT(vdev
), &vfio_vga_ops
,
2948 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
2949 "vfio-vga-io@0x3c0",
2950 QEMU_PCI_VGA_IO_HI_SIZE
);
2952 pci_register_vga(&vdev
->pdev
, &vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].mem
,
2953 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].mem
,
2954 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
);
2955 vfio_vga_quirk_setup(vdev
);
2959 static void vfio_unmap_bars(VFIODevice
*vdev
)
2963 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2964 vfio_unmap_bar(vdev
, i
);
2967 if (vdev
->has_vga
) {
2968 vfio_vga_quirk_teardown(vdev
);
2969 pci_unregister_vga(&vdev
->pdev
);
2970 memory_region_destroy(&vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].mem
);
2971 memory_region_destroy(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].mem
);
2972 memory_region_destroy(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
);
2979 static uint8_t vfio_std_cap_max_size(PCIDevice
*pdev
, uint8_t pos
)
2981 uint8_t tmp
, next
= 0xff;
2983 for (tmp
= pdev
->config
[PCI_CAPABILITY_LIST
]; tmp
;
2984 tmp
= pdev
->config
[tmp
+ 1]) {
2985 if (tmp
> pos
&& tmp
< next
) {
2993 static void vfio_set_word_bits(uint8_t *buf
, uint16_t val
, uint16_t mask
)
2995 pci_set_word(buf
, (pci_get_word(buf
) & ~mask
) | val
);
2998 static void vfio_add_emulated_word(VFIODevice
*vdev
, int pos
,
2999 uint16_t val
, uint16_t mask
)
3001 vfio_set_word_bits(vdev
->pdev
.config
+ pos
, val
, mask
);
3002 vfio_set_word_bits(vdev
->pdev
.wmask
+ pos
, ~mask
, mask
);
3003 vfio_set_word_bits(vdev
->emulated_config_bits
+ pos
, mask
, mask
);
3006 static void vfio_set_long_bits(uint8_t *buf
, uint32_t val
, uint32_t mask
)
3008 pci_set_long(buf
, (pci_get_long(buf
) & ~mask
) | val
);
3011 static void vfio_add_emulated_long(VFIODevice
*vdev
, int pos
,
3012 uint32_t val
, uint32_t mask
)
3014 vfio_set_long_bits(vdev
->pdev
.config
+ pos
, val
, mask
);
3015 vfio_set_long_bits(vdev
->pdev
.wmask
+ pos
, ~mask
, mask
);
3016 vfio_set_long_bits(vdev
->emulated_config_bits
+ pos
, mask
, mask
);
3019 static int vfio_setup_pcie_cap(VFIODevice
*vdev
, int pos
, uint8_t size
)
3024 flags
= pci_get_word(vdev
->pdev
.config
+ pos
+ PCI_CAP_FLAGS
);
3025 type
= (flags
& PCI_EXP_FLAGS_TYPE
) >> 4;
3027 if (type
!= PCI_EXP_TYPE_ENDPOINT
&&
3028 type
!= PCI_EXP_TYPE_LEG_END
&&
3029 type
!= PCI_EXP_TYPE_RC_END
) {
3031 error_report("vfio: Assignment of PCIe type 0x%x "
3032 "devices is not currently supported", type
);
3036 if (!pci_bus_is_express(vdev
->pdev
.bus
)) {
3038 * Use express capability as-is on PCI bus. It doesn't make much
3039 * sense to even expose, but some drivers (ex. tg3) depend on it
3040 * and guests don't seem to be particular about it. We'll need
3041 * to revist this or force express devices to express buses if we
3042 * ever expose an IOMMU to the guest.
3044 } else if (pci_bus_is_root(vdev
->pdev
.bus
)) {
3046 * On a Root Complex bus Endpoints become Root Complex Integrated
3047 * Endpoints, which changes the type and clears the LNK & LNK2 fields.
3049 if (type
== PCI_EXP_TYPE_ENDPOINT
) {
3050 vfio_add_emulated_word(vdev
, pos
+ PCI_CAP_FLAGS
,
3051 PCI_EXP_TYPE_RC_END
<< 4,
3052 PCI_EXP_FLAGS_TYPE
);
3054 /* Link Capabilities, Status, and Control goes away */
3055 if (size
> PCI_EXP_LNKCTL
) {
3056 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP
, 0, ~0);
3057 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL
, 0, ~0);
3058 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA
, 0, ~0);
3060 #ifndef PCI_EXP_LNKCAP2
3061 #define PCI_EXP_LNKCAP2 44
3063 #ifndef PCI_EXP_LNKSTA2
3064 #define PCI_EXP_LNKSTA2 50
3066 /* Link 2 Capabilities, Status, and Control goes away */
3067 if (size
> PCI_EXP_LNKCAP2
) {
3068 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP2
, 0, ~0);
3069 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL2
, 0, ~0);
3070 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA2
, 0, ~0);
3074 } else if (type
== PCI_EXP_TYPE_LEG_END
) {
3076 * Legacy endpoints don't belong on the root complex. Windows
3077 * seems to be happier with devices if we skip the capability.
3084 * Convert Root Complex Integrated Endpoints to regular endpoints.
3085 * These devices don't support LNK/LNK2 capabilities, so make them up.
3087 if (type
== PCI_EXP_TYPE_RC_END
) {
3088 vfio_add_emulated_word(vdev
, pos
+ PCI_CAP_FLAGS
,
3089 PCI_EXP_TYPE_ENDPOINT
<< 4,
3090 PCI_EXP_FLAGS_TYPE
);
3091 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP
,
3092 PCI_EXP_LNK_MLW_1
| PCI_EXP_LNK_LS_25
, ~0);
3093 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL
, 0, ~0);
3096 /* Mark the Link Status bits as emulated to allow virtual negotiation */
3097 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA
,
3098 pci_get_word(vdev
->pdev
.config
+ pos
+
3100 PCI_EXP_LNKCAP_MLW
| PCI_EXP_LNKCAP_SLS
);
3103 pos
= pci_add_capability(&vdev
->pdev
, PCI_CAP_ID_EXP
, pos
, size
);
3105 vdev
->pdev
.exp
.exp_cap
= pos
;
3111 static void vfio_check_pcie_flr(VFIODevice
*vdev
, uint8_t pos
)
3113 uint32_t cap
= pci_get_long(vdev
->pdev
.config
+ pos
+ PCI_EXP_DEVCAP
);
3115 if (cap
& PCI_EXP_DEVCAP_FLR
) {
3116 DPRINTF("%04x:%02x:%02x.%x Supports FLR via PCIe cap\n",
3117 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3118 vdev
->host
.function
);
3119 vdev
->has_flr
= true;
3123 static void vfio_check_pm_reset(VFIODevice
*vdev
, uint8_t pos
)
3125 uint16_t csr
= pci_get_word(vdev
->pdev
.config
+ pos
+ PCI_PM_CTRL
);
3127 if (!(csr
& PCI_PM_CTRL_NO_SOFT_RESET
)) {
3128 DPRINTF("%04x:%02x:%02x.%x Supports PM reset\n",
3129 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3130 vdev
->host
.function
);
3131 vdev
->has_pm_reset
= true;
3135 static void vfio_check_af_flr(VFIODevice
*vdev
, uint8_t pos
)
3137 uint8_t cap
= pci_get_byte(vdev
->pdev
.config
+ pos
+ PCI_AF_CAP
);
3139 if ((cap
& PCI_AF_CAP_TP
) && (cap
& PCI_AF_CAP_FLR
)) {
3140 DPRINTF("%04x:%02x:%02x.%x Supports FLR via AF cap\n",
3141 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3142 vdev
->host
.function
);
3143 vdev
->has_flr
= true;
3147 static int vfio_add_std_cap(VFIODevice
*vdev
, uint8_t pos
)
3149 PCIDevice
*pdev
= &vdev
->pdev
;
3150 uint8_t cap_id
, next
, size
;
3153 cap_id
= pdev
->config
[pos
];
3154 next
= pdev
->config
[pos
+ 1];
3157 * If it becomes important to configure capabilities to their actual
3158 * size, use this as the default when it's something we don't recognize.
3159 * Since QEMU doesn't actually handle many of the config accesses,
3160 * exact size doesn't seem worthwhile.
3162 size
= vfio_std_cap_max_size(pdev
, pos
);
3165 * pci_add_capability always inserts the new capability at the head
3166 * of the chain. Therefore to end up with a chain that matches the
3167 * physical device, we insert from the end by making this recursive.
3168 * This is also why we pre-caclulate size above as cached config space
3169 * will be changed as we unwind the stack.
3172 ret
= vfio_add_std_cap(vdev
, next
);
3177 /* Begin the rebuild, use QEMU emulated list bits */
3178 pdev
->config
[PCI_CAPABILITY_LIST
] = 0;
3179 vdev
->emulated_config_bits
[PCI_CAPABILITY_LIST
] = 0xff;
3180 vdev
->emulated_config_bits
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
3183 /* Use emulated next pointer to allow dropping caps */
3184 pci_set_byte(vdev
->emulated_config_bits
+ pos
+ 1, 0xff);
3187 case PCI_CAP_ID_MSI
:
3188 ret
= vfio_setup_msi(vdev
, pos
);
3190 case PCI_CAP_ID_EXP
:
3191 vfio_check_pcie_flr(vdev
, pos
);
3192 ret
= vfio_setup_pcie_cap(vdev
, pos
, size
);
3194 case PCI_CAP_ID_MSIX
:
3195 ret
= vfio_setup_msix(vdev
, pos
);
3198 vfio_check_pm_reset(vdev
, pos
);
3200 ret
= pci_add_capability(pdev
, cap_id
, pos
, size
);
3203 vfio_check_af_flr(vdev
, pos
);
3204 ret
= pci_add_capability(pdev
, cap_id
, pos
, size
);
3207 ret
= pci_add_capability(pdev
, cap_id
, pos
, size
);
3212 error_report("vfio: %04x:%02x:%02x.%x Error adding PCI capability "
3213 "0x%x[0x%x]@0x%x: %d", vdev
->host
.domain
,
3214 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
3215 cap_id
, size
, pos
, ret
);
3222 static int vfio_add_capabilities(VFIODevice
*vdev
)
3224 PCIDevice
*pdev
= &vdev
->pdev
;
3226 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
) ||
3227 !pdev
->config
[PCI_CAPABILITY_LIST
]) {
3228 return 0; /* Nothing to add */
3231 return vfio_add_std_cap(vdev
, pdev
->config
[PCI_CAPABILITY_LIST
]);
3234 static void vfio_pci_pre_reset(VFIODevice
*vdev
)
3236 PCIDevice
*pdev
= &vdev
->pdev
;
3239 vfio_disable_interrupts(vdev
);
3241 /* Make sure the device is in D0 */
3246 pmcsr
= vfio_pci_read_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, 2);
3247 state
= pmcsr
& PCI_PM_CTRL_STATE_MASK
;
3249 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
3250 vfio_pci_write_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
, 2);
3251 /* vfio handles the necessary delay here */
3252 pmcsr
= vfio_pci_read_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, 2);
3253 state
= pmcsr
& PCI_PM_CTRL_STATE_MASK
;
3255 error_report("vfio: Unable to power on device, stuck in D%d",
3262 * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master.
3263 * Also put INTx Disable in known state.
3265 cmd
= vfio_pci_read_config(pdev
, PCI_COMMAND
, 2);
3266 cmd
&= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
3267 PCI_COMMAND_INTX_DISABLE
);
3268 vfio_pci_write_config(pdev
, PCI_COMMAND
, cmd
, 2);
3271 static void vfio_pci_post_reset(VFIODevice
*vdev
)
3273 vfio_enable_intx(vdev
);
3276 static bool vfio_pci_host_match(PCIHostDeviceAddress
*host1
,
3277 PCIHostDeviceAddress
*host2
)
3279 return (host1
->domain
== host2
->domain
&& host1
->bus
== host2
->bus
&&
3280 host1
->slot
== host2
->slot
&& host1
->function
== host2
->function
);
3283 static int vfio_pci_hot_reset(VFIODevice
*vdev
, bool single
)
3286 struct vfio_pci_hot_reset_info
*info
;
3287 struct vfio_pci_dependent_device
*devices
;
3288 struct vfio_pci_hot_reset
*reset
;
3293 DPRINTF("%s(%04x:%02x:%02x.%x) %s\n", __func__
, vdev
->host
.domain
,
3294 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
3295 single
? "one" : "multi");
3297 vfio_pci_pre_reset(vdev
);
3298 vdev
->needs_reset
= false;
3300 info
= g_malloc0(sizeof(*info
));
3301 info
->argsz
= sizeof(*info
);
3303 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO
, info
);
3304 if (ret
&& errno
!= ENOSPC
) {
3306 if (!vdev
->has_pm_reset
) {
3307 error_report("vfio: Cannot reset device %04x:%02x:%02x.%x, "
3308 "no available reset mechanism.", vdev
->host
.domain
,
3309 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
3314 count
= info
->count
;
3315 info
= g_realloc(info
, sizeof(*info
) + (count
* sizeof(*devices
)));
3316 info
->argsz
= sizeof(*info
) + (count
* sizeof(*devices
));
3317 devices
= &info
->devices
[0];
3319 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO
, info
);
3322 error_report("vfio: hot reset info failed: %m");
3326 DPRINTF("%04x:%02x:%02x.%x: hot reset dependent devices:\n",
3327 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3328 vdev
->host
.function
);
3330 /* Verify that we have all the groups required */
3331 for (i
= 0; i
< info
->count
; i
++) {
3332 PCIHostDeviceAddress host
;
3335 host
.domain
= devices
[i
].segment
;
3336 host
.bus
= devices
[i
].bus
;
3337 host
.slot
= PCI_SLOT(devices
[i
].devfn
);
3338 host
.function
= PCI_FUNC(devices
[i
].devfn
);
3340 DPRINTF("\t%04x:%02x:%02x.%x group %d\n", host
.domain
,
3341 host
.bus
, host
.slot
, host
.function
, devices
[i
].group_id
);
3343 if (vfio_pci_host_match(&host
, &vdev
->host
)) {
3347 QLIST_FOREACH(group
, &group_list
, next
) {
3348 if (group
->groupid
== devices
[i
].group_id
) {
3354 if (!vdev
->has_pm_reset
) {
3355 error_report("vfio: Cannot reset device %04x:%02x:%02x.%x, "
3356 "depends on group %d which is not owned.",
3357 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3358 vdev
->host
.function
, devices
[i
].group_id
);
3364 /* Prep dependent devices for reset and clear our marker. */
3365 QLIST_FOREACH(tmp
, &group
->device_list
, next
) {
3366 if (vfio_pci_host_match(&host
, &tmp
->host
)) {
3368 DPRINTF("vfio: found another in-use device "
3369 "%04x:%02x:%02x.%x\n", host
.domain
, host
.bus
,
3370 host
.slot
, host
.function
);
3374 vfio_pci_pre_reset(tmp
);
3375 tmp
->needs_reset
= false;
3382 if (!single
&& !multi
) {
3383 DPRINTF("vfio: No other in-use devices for multi hot reset\n");
3388 /* Determine how many group fds need to be passed */
3390 QLIST_FOREACH(group
, &group_list
, next
) {
3391 for (i
= 0; i
< info
->count
; i
++) {
3392 if (group
->groupid
== devices
[i
].group_id
) {
3399 reset
= g_malloc0(sizeof(*reset
) + (count
* sizeof(*fds
)));
3400 reset
->argsz
= sizeof(*reset
) + (count
* sizeof(*fds
));
3401 fds
= &reset
->group_fds
[0];
3403 /* Fill in group fds */
3404 QLIST_FOREACH(group
, &group_list
, next
) {
3405 for (i
= 0; i
< info
->count
; i
++) {
3406 if (group
->groupid
== devices
[i
].group_id
) {
3407 fds
[reset
->count
++] = group
->fd
;
3414 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_PCI_HOT_RESET
, reset
);
3417 DPRINTF("%04x:%02x:%02x.%x hot reset: %s\n", vdev
->host
.domain
,
3418 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
3419 ret
? "%m" : "Success");
3422 /* Re-enable INTx on affected devices */
3423 for (i
= 0; i
< info
->count
; i
++) {
3424 PCIHostDeviceAddress host
;
3427 host
.domain
= devices
[i
].segment
;
3428 host
.bus
= devices
[i
].bus
;
3429 host
.slot
= PCI_SLOT(devices
[i
].devfn
);
3430 host
.function
= PCI_FUNC(devices
[i
].devfn
);
3432 if (vfio_pci_host_match(&host
, &vdev
->host
)) {
3436 QLIST_FOREACH(group
, &group_list
, next
) {
3437 if (group
->groupid
== devices
[i
].group_id
) {
3446 QLIST_FOREACH(tmp
, &group
->device_list
, next
) {
3447 if (vfio_pci_host_match(&host
, &tmp
->host
)) {
3448 vfio_pci_post_reset(tmp
);
3454 vfio_pci_post_reset(vdev
);
3461 * We want to differentiate hot reset of mulitple in-use devices vs hot reset
3462 * of a single in-use device. VFIO_DEVICE_RESET will already handle the case
3463 * of doing hot resets when there is only a single device per bus. The in-use
3464 * here refers to how many VFIODevices are affected. A hot reset that affects
3465 * multiple devices, but only a single in-use device, means that we can call
3466 * it from our bus ->reset() callback since the extent is effectively a single
3467 * device. This allows us to make use of it in the hotplug path. When there
3468 * are multiple in-use devices, we can only trigger the hot reset during a
3469 * system reset and thus from our reset handler. We separate _one vs _multi
3470 * here so that we don't overlap and do a double reset on the system reset
3471 * path where both our reset handler and ->reset() callback are used. Calling
3472 * _one() will only do a hot reset for the one in-use devices case, calling
3473 * _multi() will do nothing if a _one() would have been sufficient.
3475 static int vfio_pci_hot_reset_one(VFIODevice
*vdev
)
3477 return vfio_pci_hot_reset(vdev
, true);
3480 static int vfio_pci_hot_reset_multi(VFIODevice
*vdev
)
3482 return vfio_pci_hot_reset(vdev
, false);
3485 static void vfio_pci_reset_handler(void *opaque
)
3490 QLIST_FOREACH(group
, &group_list
, next
) {
3491 QLIST_FOREACH(vdev
, &group
->device_list
, next
) {
3492 if (!vdev
->reset_works
|| (!vdev
->has_flr
&& vdev
->has_pm_reset
)) {
3493 vdev
->needs_reset
= true;
3498 QLIST_FOREACH(group
, &group_list
, next
) {
3499 QLIST_FOREACH(vdev
, &group
->device_list
, next
) {
3500 if (vdev
->needs_reset
) {
3501 vfio_pci_hot_reset_multi(vdev
);
3507 static void vfio_kvm_device_add_group(VFIOGroup
*group
)
3510 struct kvm_device_attr attr
= {
3511 .group
= KVM_DEV_VFIO_GROUP
,
3512 .attr
= KVM_DEV_VFIO_GROUP_ADD
,
3513 .addr
= (uint64_t)(unsigned long)&group
->fd
,
3516 if (!kvm_enabled()) {
3520 if (vfio_kvm_device_fd
< 0) {
3521 struct kvm_create_device cd
= {
3522 .type
= KVM_DEV_TYPE_VFIO
,
3525 if (kvm_vm_ioctl(kvm_state
, KVM_CREATE_DEVICE
, &cd
)) {
3526 DPRINTF("KVM_CREATE_DEVICE: %m\n");
3530 vfio_kvm_device_fd
= cd
.fd
;
3533 if (ioctl(vfio_kvm_device_fd
, KVM_SET_DEVICE_ATTR
, &attr
)) {
3534 error_report("Failed to add group %d to KVM VFIO device: %m",
3540 static void vfio_kvm_device_del_group(VFIOGroup
*group
)
3543 struct kvm_device_attr attr
= {
3544 .group
= KVM_DEV_VFIO_GROUP
,
3545 .attr
= KVM_DEV_VFIO_GROUP_DEL
,
3546 .addr
= (uint64_t)(unsigned long)&group
->fd
,
3549 if (vfio_kvm_device_fd
< 0) {
3553 if (ioctl(vfio_kvm_device_fd
, KVM_SET_DEVICE_ATTR
, &attr
)) {
3554 error_report("Failed to remove group %d from KVM VFIO device: %m",
3560 static VFIOAddressSpace
*vfio_get_address_space(AddressSpace
*as
)
3562 VFIOAddressSpace
*space
;
3564 QLIST_FOREACH(space
, &vfio_address_spaces
, list
) {
3565 if (space
->as
== as
) {
3570 /* No suitable VFIOAddressSpace, create a new one */
3571 space
= g_malloc0(sizeof(*space
));
3573 QLIST_INIT(&space
->containers
);
3575 QLIST_INSERT_HEAD(&vfio_address_spaces
, space
, list
);
3580 static void vfio_put_address_space(VFIOAddressSpace
*space
)
3582 if (QLIST_EMPTY(&space
->containers
)) {
3583 QLIST_REMOVE(space
, list
);
3588 static int vfio_connect_container(VFIOGroup
*group
, AddressSpace
*as
)
3590 VFIOContainer
*container
;
3592 VFIOAddressSpace
*space
;
3594 space
= vfio_get_address_space(as
);
3596 QLIST_FOREACH(container
, &space
->containers
, next
) {
3597 if (!ioctl(group
->fd
, VFIO_GROUP_SET_CONTAINER
, &container
->fd
)) {
3598 group
->container
= container
;
3599 QLIST_INSERT_HEAD(&container
->group_list
, group
, container_next
);
3604 fd
= qemu_open("/dev/vfio/vfio", O_RDWR
);
3606 error_report("vfio: failed to open /dev/vfio/vfio: %m");
3608 goto put_space_exit
;
3611 ret
= ioctl(fd
, VFIO_GET_API_VERSION
);
3612 if (ret
!= VFIO_API_VERSION
) {
3613 error_report("vfio: supported vfio version: %d, "
3614 "reported version: %d", VFIO_API_VERSION
, ret
);
3619 container
= g_malloc0(sizeof(*container
));
3620 container
->space
= space
;
3623 if (ioctl(fd
, VFIO_CHECK_EXTENSION
, VFIO_TYPE1_IOMMU
)) {
3624 ret
= ioctl(group
->fd
, VFIO_GROUP_SET_CONTAINER
, &fd
);
3626 error_report("vfio: failed to set group container: %m");
3628 goto free_container_exit
;
3631 ret
= ioctl(fd
, VFIO_SET_IOMMU
, VFIO_TYPE1_IOMMU
);
3633 error_report("vfio: failed to set iommu for container: %m");
3635 goto free_container_exit
;
3638 container
->iommu_data
.type1
.listener
= vfio_memory_listener
;
3639 container
->iommu_data
.release
= vfio_listener_release
;
3641 memory_listener_register(&container
->iommu_data
.type1
.listener
,
3642 &address_space_memory
);
3644 if (container
->iommu_data
.type1
.error
) {
3645 ret
= container
->iommu_data
.type1
.error
;
3646 error_report("vfio: memory listener initialization failed for container");
3647 goto listener_release_exit
;
3650 container
->iommu_data
.type1
.initialized
= true;
3653 error_report("vfio: No available IOMMU models");
3655 goto free_container_exit
;
3658 QLIST_INIT(&container
->group_list
);
3659 QLIST_INSERT_HEAD(&space
->containers
, container
, next
);
3661 group
->container
= container
;
3662 QLIST_INSERT_HEAD(&container
->group_list
, group
, container_next
);
3666 listener_release_exit
:
3667 vfio_listener_release(container
);
3669 free_container_exit
:
3676 vfio_put_address_space(space
);
3681 static void vfio_disconnect_container(VFIOGroup
*group
)
3683 VFIOContainer
*container
= group
->container
;
3685 if (ioctl(group
->fd
, VFIO_GROUP_UNSET_CONTAINER
, &container
->fd
)) {
3686 error_report("vfio: error disconnecting group %d from container",
3690 QLIST_REMOVE(group
, container_next
);
3691 group
->container
= NULL
;
3693 if (QLIST_EMPTY(&container
->group_list
)) {
3694 VFIOAddressSpace
*space
= container
->space
;
3696 if (container
->iommu_data
.release
) {
3697 container
->iommu_data
.release(container
);
3699 QLIST_REMOVE(container
, next
);
3700 DPRINTF("vfio_disconnect_container: close container->fd\n");
3701 close(container
->fd
);
3704 vfio_put_address_space(space
);
3708 static VFIOGroup
*vfio_get_group(int groupid
, AddressSpace
*as
)
3712 struct vfio_group_status status
= { .argsz
= sizeof(status
) };
3714 QLIST_FOREACH(group
, &group_list
, next
) {
3715 if (group
->groupid
== groupid
) {
3716 /* Found it. Now is it already in the right context? */
3717 if (group
->container
->space
->as
== as
) {
3720 error_report("vfio: group %d used in multiple address spaces",
3727 group
= g_malloc0(sizeof(*group
));
3729 snprintf(path
, sizeof(path
), "/dev/vfio/%d", groupid
);
3730 group
->fd
= qemu_open(path
, O_RDWR
);
3731 if (group
->fd
< 0) {
3732 error_report("vfio: error opening %s: %m", path
);
3733 goto free_group_exit
;
3736 if (ioctl(group
->fd
, VFIO_GROUP_GET_STATUS
, &status
)) {
3737 error_report("vfio: error getting group status: %m");
3741 if (!(status
.flags
& VFIO_GROUP_FLAGS_VIABLE
)) {
3742 error_report("vfio: error, group %d is not viable, please ensure "
3743 "all devices within the iommu_group are bound to their "
3744 "vfio bus driver.", groupid
);
3748 group
->groupid
= groupid
;
3749 QLIST_INIT(&group
->device_list
);
3751 if (vfio_connect_container(group
, as
)) {
3752 error_report("vfio: failed to setup container for group %d", groupid
);
3756 if (QLIST_EMPTY(&group_list
)) {
3757 qemu_register_reset(vfio_pci_reset_handler
, NULL
);
3760 QLIST_INSERT_HEAD(&group_list
, group
, next
);
3762 vfio_kvm_device_add_group(group
);
3775 static void vfio_put_group(VFIOGroup
*group
)
3777 if (!QLIST_EMPTY(&group
->device_list
)) {
3781 vfio_kvm_device_del_group(group
);
3782 vfio_disconnect_container(group
);
3783 QLIST_REMOVE(group
, next
);
3784 DPRINTF("vfio_put_group: close group->fd\n");
3788 if (QLIST_EMPTY(&group_list
)) {
3789 qemu_unregister_reset(vfio_pci_reset_handler
, NULL
);
3793 static int vfio_get_device(VFIOGroup
*group
, const char *name
, VFIODevice
*vdev
)
3795 struct vfio_device_info dev_info
= { .argsz
= sizeof(dev_info
) };
3796 struct vfio_region_info reg_info
= { .argsz
= sizeof(reg_info
) };
3797 struct vfio_irq_info irq_info
= { .argsz
= sizeof(irq_info
) };
3800 ret
= ioctl(group
->fd
, VFIO_GROUP_GET_DEVICE_FD
, name
);
3802 error_report("vfio: error getting device %s from group %d: %m",
3803 name
, group
->groupid
);
3804 error_printf("Verify all devices in group %d are bound to vfio-pci "
3805 "or pci-stub and not already in use\n", group
->groupid
);
3810 vdev
->group
= group
;
3811 QLIST_INSERT_HEAD(&group
->device_list
, vdev
, next
);
3813 /* Sanity check device */
3814 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_INFO
, &dev_info
);
3816 error_report("vfio: error getting device info: %m");
3820 DPRINTF("Device %s flags: %u, regions: %u, irgs: %u\n", name
,
3821 dev_info
.flags
, dev_info
.num_regions
, dev_info
.num_irqs
);
3823 if (!(dev_info
.flags
& VFIO_DEVICE_FLAGS_PCI
)) {
3824 error_report("vfio: Um, this isn't a PCI device");
3828 vdev
->reset_works
= !!(dev_info
.flags
& VFIO_DEVICE_FLAGS_RESET
);
3830 if (dev_info
.num_regions
< VFIO_PCI_CONFIG_REGION_INDEX
+ 1) {
3831 error_report("vfio: unexpected number of io regions %u",
3832 dev_info
.num_regions
);
3836 if (dev_info
.num_irqs
< VFIO_PCI_MSIX_IRQ_INDEX
+ 1) {
3837 error_report("vfio: unexpected number of irqs %u", dev_info
.num_irqs
);
3841 for (i
= VFIO_PCI_BAR0_REGION_INDEX
; i
< VFIO_PCI_ROM_REGION_INDEX
; i
++) {
3844 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
);
3846 error_report("vfio: Error getting region %d info: %m", i
);
3850 DPRINTF("Device %s region %d:\n", name
, i
);
3851 DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
3852 (unsigned long)reg_info
.size
, (unsigned long)reg_info
.offset
,
3853 (unsigned long)reg_info
.flags
);
3855 vdev
->bars
[i
].flags
= reg_info
.flags
;
3856 vdev
->bars
[i
].size
= reg_info
.size
;
3857 vdev
->bars
[i
].fd_offset
= reg_info
.offset
;
3858 vdev
->bars
[i
].fd
= vdev
->fd
;
3859 vdev
->bars
[i
].nr
= i
;
3860 QLIST_INIT(&vdev
->bars
[i
].quirks
);
3863 reg_info
.index
= VFIO_PCI_CONFIG_REGION_INDEX
;
3865 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
);
3867 error_report("vfio: Error getting config info: %m");
3871 DPRINTF("Device %s config:\n", name
);
3872 DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
3873 (unsigned long)reg_info
.size
, (unsigned long)reg_info
.offset
,
3874 (unsigned long)reg_info
.flags
);
3876 vdev
->config_size
= reg_info
.size
;
3877 if (vdev
->config_size
== PCI_CONFIG_SPACE_SIZE
) {
3878 vdev
->pdev
.cap_present
&= ~QEMU_PCI_CAP_EXPRESS
;
3880 vdev
->config_offset
= reg_info
.offset
;
3882 if ((vdev
->features
& VFIO_FEATURE_ENABLE_VGA
) &&
3883 dev_info
.num_regions
> VFIO_PCI_VGA_REGION_INDEX
) {
3884 struct vfio_region_info vga_info
= {
3885 .argsz
= sizeof(vga_info
),
3886 .index
= VFIO_PCI_VGA_REGION_INDEX
,
3889 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_REGION_INFO
, &vga_info
);
3892 "vfio: Device does not support requested feature x-vga");
3896 if (!(vga_info
.flags
& VFIO_REGION_INFO_FLAG_READ
) ||
3897 !(vga_info
.flags
& VFIO_REGION_INFO_FLAG_WRITE
) ||
3898 vga_info
.size
< 0xbffff + 1) {
3899 error_report("vfio: Unexpected VGA info, flags 0x%lx, size 0x%lx",
3900 (unsigned long)vga_info
.flags
,
3901 (unsigned long)vga_info
.size
);
3905 vdev
->vga
.fd_offset
= vga_info
.offset
;
3906 vdev
->vga
.fd
= vdev
->fd
;
3908 vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].offset
= QEMU_PCI_VGA_MEM_BASE
;
3909 vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].nr
= QEMU_PCI_VGA_MEM
;
3910 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].quirks
);
3912 vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].offset
= QEMU_PCI_VGA_IO_LO_BASE
;
3913 vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].nr
= QEMU_PCI_VGA_IO_LO
;
3914 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].quirks
);
3916 vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].offset
= QEMU_PCI_VGA_IO_HI_BASE
;
3917 vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].nr
= QEMU_PCI_VGA_IO_HI
;
3918 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
);
3920 vdev
->has_vga
= true;
3922 irq_info
.index
= VFIO_PCI_ERR_IRQ_INDEX
;
3924 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_IRQ_INFO
, &irq_info
);
3926 /* This can fail for an old kernel or legacy PCI dev */
3927 DPRINTF("VFIO_DEVICE_GET_IRQ_INFO failure: %m\n");
3929 } else if (irq_info
.count
== 1) {
3930 vdev
->pci_aer
= true;
3932 error_report("vfio: %04x:%02x:%02x.%x "
3933 "Could not enable error recovery for the device",
3934 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3935 vdev
->host
.function
);
3940 QLIST_REMOVE(vdev
, next
);
3947 static void vfio_put_device(VFIODevice
*vdev
)
3949 QLIST_REMOVE(vdev
, next
);
3951 DPRINTF("vfio_put_device: close vdev->fd\n");
3959 static void vfio_err_notifier_handler(void *opaque
)
3961 VFIODevice
*vdev
= opaque
;
3963 if (!event_notifier_test_and_clear(&vdev
->err_notifier
)) {
3968 * TBD. Retrieve the error details and decide what action
3969 * needs to be taken. One of the actions could be to pass
3970 * the error to the guest and have the guest driver recover
3971 * from the error. This requires that PCIe capabilities be
3972 * exposed to the guest. For now, we just terminate the
3973 * guest to contain the error.
3976 error_report("%s(%04x:%02x:%02x.%x) Unrecoverable error detected. "
3977 "Please collect any data possible and then kill the guest",
3978 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
3979 vdev
->host
.slot
, vdev
->host
.function
);
3981 vm_stop(RUN_STATE_IO_ERROR
);
3985 * Registers error notifier for devices supporting error recovery.
3986 * If we encounter a failure in this function, we report an error
3987 * and continue after disabling error recovery support for the
3990 static void vfio_register_err_notifier(VFIODevice
*vdev
)
3994 struct vfio_irq_set
*irq_set
;
3997 if (!vdev
->pci_aer
) {
4001 if (event_notifier_init(&vdev
->err_notifier
, 0)) {
4002 error_report("vfio: Unable to init event notifier for error detection");
4003 vdev
->pci_aer
= false;
4007 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
4009 irq_set
= g_malloc0(argsz
);
4010 irq_set
->argsz
= argsz
;
4011 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
4012 VFIO_IRQ_SET_ACTION_TRIGGER
;
4013 irq_set
->index
= VFIO_PCI_ERR_IRQ_INDEX
;
4016 pfd
= (int32_t *)&irq_set
->data
;
4018 *pfd
= event_notifier_get_fd(&vdev
->err_notifier
);
4019 qemu_set_fd_handler(*pfd
, vfio_err_notifier_handler
, NULL
, vdev
);
4021 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
4023 error_report("vfio: Failed to set up error notification");
4024 qemu_set_fd_handler(*pfd
, NULL
, NULL
, vdev
);
4025 event_notifier_cleanup(&vdev
->err_notifier
);
4026 vdev
->pci_aer
= false;
4031 static void vfio_unregister_err_notifier(VFIODevice
*vdev
)
4034 struct vfio_irq_set
*irq_set
;
4038 if (!vdev
->pci_aer
) {
4042 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
4044 irq_set
= g_malloc0(argsz
);
4045 irq_set
->argsz
= argsz
;
4046 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
4047 VFIO_IRQ_SET_ACTION_TRIGGER
;
4048 irq_set
->index
= VFIO_PCI_ERR_IRQ_INDEX
;
4051 pfd
= (int32_t *)&irq_set
->data
;
4054 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
4056 error_report("vfio: Failed to de-assign error fd: %m");
4059 qemu_set_fd_handler(event_notifier_get_fd(&vdev
->err_notifier
),
4061 event_notifier_cleanup(&vdev
->err_notifier
);
4064 static int vfio_initfn(PCIDevice
*pdev
)
4066 VFIODevice
*pvdev
, *vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
4068 char path
[PATH_MAX
], iommu_group_path
[PATH_MAX
], *group_name
;
4074 /* Check that the host device exists */
4075 snprintf(path
, sizeof(path
),
4076 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/",
4077 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
4078 vdev
->host
.function
);
4079 if (stat(path
, &st
) < 0) {
4080 error_report("vfio: error: no such host device: %s", path
);
4084 strncat(path
, "iommu_group", sizeof(path
) - strlen(path
) - 1);
4086 len
= readlink(path
, iommu_group_path
, sizeof(path
));
4087 if (len
<= 0 || len
>= sizeof(path
)) {
4088 error_report("vfio: error no iommu_group for device");
4089 return len
< 0 ? -errno
: ENAMETOOLONG
;
4092 iommu_group_path
[len
] = 0;
4093 group_name
= basename(iommu_group_path
);
4095 if (sscanf(group_name
, "%d", &groupid
) != 1) {
4096 error_report("vfio: error reading %s: %m", path
);
4100 DPRINTF("%s(%04x:%02x:%02x.%x) group %d\n", __func__
, vdev
->host
.domain
,
4101 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
, groupid
);
4103 group
= vfio_get_group(groupid
, pci_device_iommu_address_space(pdev
));
4105 error_report("vfio: failed to get group %d", groupid
);
4109 snprintf(path
, sizeof(path
), "%04x:%02x:%02x.%01x",
4110 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
4111 vdev
->host
.function
);
4113 QLIST_FOREACH(pvdev
, &group
->device_list
, next
) {
4114 if (pvdev
->host
.domain
== vdev
->host
.domain
&&
4115 pvdev
->host
.bus
== vdev
->host
.bus
&&
4116 pvdev
->host
.slot
== vdev
->host
.slot
&&
4117 pvdev
->host
.function
== vdev
->host
.function
) {
4119 error_report("vfio: error: device %s is already attached", path
);
4120 vfio_put_group(group
);
4125 ret
= vfio_get_device(group
, path
, vdev
);
4127 error_report("vfio: failed to get device %s", path
);
4128 vfio_put_group(group
);
4132 /* Get a copy of config space */
4133 ret
= pread(vdev
->fd
, vdev
->pdev
.config
,
4134 MIN(pci_config_size(&vdev
->pdev
), vdev
->config_size
),
4135 vdev
->config_offset
);
4136 if (ret
< (int)MIN(pci_config_size(&vdev
->pdev
), vdev
->config_size
)) {
4137 ret
= ret
< 0 ? -errno
: -EFAULT
;
4138 error_report("vfio: Failed to read device config space");
4142 /* vfio emulates a lot for us, but some bits need extra love */
4143 vdev
->emulated_config_bits
= g_malloc0(vdev
->config_size
);
4145 /* QEMU can choose to expose the ROM or not */
4146 memset(vdev
->emulated_config_bits
+ PCI_ROM_ADDRESS
, 0xff, 4);
4148 /* QEMU can change multi-function devices to single function, or reverse */
4149 vdev
->emulated_config_bits
[PCI_HEADER_TYPE
] =
4150 PCI_HEADER_TYPE_MULTI_FUNCTION
;
4152 /* Restore or clear multifunction, this is always controlled by QEMU */
4153 if (vdev
->pdev
.cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
4154 vdev
->pdev
.config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
4156 vdev
->pdev
.config
[PCI_HEADER_TYPE
] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
4160 * Clear host resource mapping info. If we choose not to register a
4161 * BAR, such as might be the case with the option ROM, we can get
4162 * confusing, unwritable, residual addresses from the host here.
4164 memset(&vdev
->pdev
.config
[PCI_BASE_ADDRESS_0
], 0, 24);
4165 memset(&vdev
->pdev
.config
[PCI_ROM_ADDRESS
], 0, 4);
4167 vfio_pci_size_rom(vdev
);
4169 ret
= vfio_early_setup_msix(vdev
);
4174 vfio_map_bars(vdev
);
4176 ret
= vfio_add_capabilities(vdev
);
4181 /* QEMU emulates all of MSI & MSIX */
4182 if (pdev
->cap_present
& QEMU_PCI_CAP_MSIX
) {
4183 memset(vdev
->emulated_config_bits
+ pdev
->msix_cap
, 0xff,
4187 if (pdev
->cap_present
& QEMU_PCI_CAP_MSI
) {
4188 memset(vdev
->emulated_config_bits
+ pdev
->msi_cap
, 0xff,
4189 vdev
->msi_cap_size
);
4192 if (vfio_pci_read_config(&vdev
->pdev
, PCI_INTERRUPT_PIN
, 1)) {
4193 vdev
->intx
.mmap_timer
= timer_new_ms(QEMU_CLOCK_VIRTUAL
,
4194 vfio_intx_mmap_enable
, vdev
);
4195 pci_device_set_intx_routing_notifier(&vdev
->pdev
, vfio_update_irq
);
4196 ret
= vfio_enable_intx(vdev
);
4202 add_boot_device_path(vdev
->bootindex
, &pdev
->qdev
, NULL
);
4203 vfio_register_err_notifier(vdev
);
4208 pci_device_set_intx_routing_notifier(&vdev
->pdev
, NULL
);
4209 vfio_teardown_msi(vdev
);
4210 vfio_unmap_bars(vdev
);
4212 g_free(vdev
->emulated_config_bits
);
4213 vfio_put_device(vdev
);
4214 vfio_put_group(group
);
4218 static void vfio_exitfn(PCIDevice
*pdev
)
4220 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
4221 VFIOGroup
*group
= vdev
->group
;
4223 vfio_unregister_err_notifier(vdev
);
4224 pci_device_set_intx_routing_notifier(&vdev
->pdev
, NULL
);
4225 vfio_disable_interrupts(vdev
);
4226 if (vdev
->intx
.mmap_timer
) {
4227 timer_free(vdev
->intx
.mmap_timer
);
4229 vfio_teardown_msi(vdev
);
4230 vfio_unmap_bars(vdev
);
4231 g_free(vdev
->emulated_config_bits
);
4233 vfio_put_device(vdev
);
4234 vfio_put_group(group
);
4237 static void vfio_pci_reset(DeviceState
*dev
)
4239 PCIDevice
*pdev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
4240 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
4242 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
4243 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
4245 vfio_pci_pre_reset(vdev
);
4247 if (vdev
->reset_works
&& (vdev
->has_flr
|| !vdev
->has_pm_reset
) &&
4248 !ioctl(vdev
->fd
, VFIO_DEVICE_RESET
)) {
4249 DPRINTF("%04x:%02x:%02x.%x FLR/VFIO_DEVICE_RESET\n", vdev
->host
.domain
,
4250 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
4254 /* See if we can do our own bus reset */
4255 if (!vfio_pci_hot_reset_one(vdev
)) {
4259 /* If nothing else works and the device supports PM reset, use it */
4260 if (vdev
->reset_works
&& vdev
->has_pm_reset
&&
4261 !ioctl(vdev
->fd
, VFIO_DEVICE_RESET
)) {
4262 DPRINTF("%04x:%02x:%02x.%x PCI PM Reset\n", vdev
->host
.domain
,
4263 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
4268 vfio_pci_post_reset(vdev
);
4271 static Property vfio_pci_dev_properties
[] = {
4272 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIODevice
, host
),
4273 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIODevice
,
4274 intx
.mmap_timeout
, 1100),
4275 DEFINE_PROP_BIT("x-vga", VFIODevice
, features
,
4276 VFIO_FEATURE_ENABLE_VGA_BIT
, false),
4277 DEFINE_PROP_INT32("bootindex", VFIODevice
, bootindex
, -1),
4279 * TODO - support passed fds... is this necessary?
4280 * DEFINE_PROP_STRING("vfiofd", VFIODevice, vfiofd_name),
4281 * DEFINE_PROP_STRING("vfiogroupfd, VFIODevice, vfiogroupfd_name),
4283 DEFINE_PROP_END_OF_LIST(),
4286 static const VMStateDescription vfio_pci_vmstate
= {
4291 static void vfio_pci_dev_class_init(ObjectClass
*klass
, void *data
)
4293 DeviceClass
*dc
= DEVICE_CLASS(klass
);
4294 PCIDeviceClass
*pdc
= PCI_DEVICE_CLASS(klass
);
4296 dc
->reset
= vfio_pci_reset
;
4297 dc
->props
= vfio_pci_dev_properties
;
4298 dc
->vmsd
= &vfio_pci_vmstate
;
4299 dc
->desc
= "VFIO-based PCI device assignment";
4300 set_bit(DEVICE_CATEGORY_MISC
, dc
->categories
);
4301 pdc
->init
= vfio_initfn
;
4302 pdc
->exit
= vfio_exitfn
;
4303 pdc
->config_read
= vfio_pci_read_config
;
4304 pdc
->config_write
= vfio_pci_write_config
;
4305 pdc
->is_express
= 1; /* We might be */
4308 static const TypeInfo vfio_pci_dev_info
= {
4310 .parent
= TYPE_PCI_DEVICE
,
4311 .instance_size
= sizeof(VFIODevice
),
4312 .class_init
= vfio_pci_dev_class_init
,
4315 static void register_vfio_pci_dev_type(void)
4317 type_register_static(&vfio_pci_dev_info
);
4320 type_init(register_vfio_pci_dev_type
)