2 * Device model for Cadence UART
4 * Reference: Xilinx Zynq 7000 reference manual
5 * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
6 * - Chapter 19 UART Controller
7 * - Appendix B for Register details
9 * Copyright (c) 2010 Xilinx Inc.
10 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
11 * Copyright (c) 2012 PetaLogix Pty Ltd.
12 * Written by Haibing Ma
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
25 #include "hw/sysbus.h"
26 #include "migration/vmstate.h"
27 #include "chardev/char-fe.h"
28 #include "chardev/char-serial.h"
29 #include "qemu/timer.h"
31 #include "qemu/module.h"
32 #include "hw/char/cadence_uart.h"
34 #include "hw/qdev-clock.h"
35 #include "hw/qdev-properties-system.h"
38 #ifdef CADENCE_UART_ERR_DEBUG
39 #define DB_PRINT(...) do { \
40 fprintf(stderr, ": %s: ", __func__); \
41 fprintf(stderr, ## __VA_ARGS__); \
47 #define UART_SR_INTR_RTRIG 0x00000001
48 #define UART_SR_INTR_REMPTY 0x00000002
49 #define UART_SR_INTR_RFUL 0x00000004
50 #define UART_SR_INTR_TEMPTY 0x00000008
51 #define UART_SR_INTR_TFUL 0x00000010
52 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
53 #define UART_SR_TTRIG 0x00002000
54 #define UART_INTR_TTRIG 0x00000400
55 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
56 * SR, then the same bit in CISR is set high too */
57 #define UART_SR_TO_CISR_MASK 0x0000001F
59 #define UART_INTR_ROVR 0x00000020
60 #define UART_INTR_FRAME 0x00000040
61 #define UART_INTR_PARE 0x00000080
62 #define UART_INTR_TIMEOUT 0x00000100
63 #define UART_INTR_DMSI 0x00000200
64 #define UART_INTR_TOVR 0x00001000
66 #define UART_SR_RACTIVE 0x00000400
67 #define UART_SR_TACTIVE 0x00000800
68 #define UART_SR_FDELT 0x00001000
70 #define UART_CR_RXRST 0x00000001
71 #define UART_CR_TXRST 0x00000002
72 #define UART_CR_RX_EN 0x00000004
73 #define UART_CR_RX_DIS 0x00000008
74 #define UART_CR_TX_EN 0x00000010
75 #define UART_CR_TX_DIS 0x00000020
76 #define UART_CR_RST_TO 0x00000040
77 #define UART_CR_STARTBRK 0x00000080
78 #define UART_CR_STOPBRK 0x00000100
80 #define UART_MR_CLKS 0x00000001
81 #define UART_MR_CHRL 0x00000006
82 #define UART_MR_CHRL_SH 1
83 #define UART_MR_PAR 0x00000038
84 #define UART_MR_PAR_SH 3
85 #define UART_MR_NBSTOP 0x000000C0
86 #define UART_MR_NBSTOP_SH 6
87 #define UART_MR_CHMODE 0x00000300
88 #define UART_MR_CHMODE_SH 8
89 #define UART_MR_UCLKEN 0x00000400
90 #define UART_MR_IRMODE 0x00000800
92 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH)
93 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH)
94 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH)
95 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH)
96 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH)
97 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH)
98 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH)
99 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH)
100 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
101 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
103 #define UART_DEFAULT_REF_CLK (50 * 1000 * 1000)
105 #define R_CR (0x00/4)
106 #define R_MR (0x04/4)
107 #define R_IER (0x08/4)
108 #define R_IDR (0x0C/4)
109 #define R_IMR (0x10/4)
110 #define R_CISR (0x14/4)
111 #define R_BRGR (0x18/4)
112 #define R_RTOR (0x1C/4)
113 #define R_RTRIG (0x20/4)
114 #define R_MCR (0x24/4)
115 #define R_MSR (0x28/4)
116 #define R_SR (0x2C/4)
117 #define R_TX_RX (0x30/4)
118 #define R_BDIV (0x34/4)
119 #define R_FDEL (0x38/4)
120 #define R_PMIN (0x3C/4)
121 #define R_PWID (0x40/4)
122 #define R_TTRIG (0x44/4)
125 static void uart_update_status(CadenceUARTState
*s
)
129 s
->r
[R_SR
] |= s
->rx_count
== CADENCE_UART_RX_FIFO_SIZE
? UART_SR_INTR_RFUL
131 s
->r
[R_SR
] |= !s
->rx_count
? UART_SR_INTR_REMPTY
: 0;
132 s
->r
[R_SR
] |= s
->rx_count
>= s
->r
[R_RTRIG
] ? UART_SR_INTR_RTRIG
: 0;
134 s
->r
[R_SR
] |= s
->tx_count
== CADENCE_UART_TX_FIFO_SIZE
? UART_SR_INTR_TFUL
136 s
->r
[R_SR
] |= !s
->tx_count
? UART_SR_INTR_TEMPTY
: 0;
137 s
->r
[R_SR
] |= s
->tx_count
>= s
->r
[R_TTRIG
] ? UART_SR_TTRIG
: 0;
139 s
->r
[R_CISR
] |= s
->r
[R_SR
] & UART_SR_TO_CISR_MASK
;
140 s
->r
[R_CISR
] |= s
->r
[R_SR
] & UART_SR_TTRIG
? UART_INTR_TTRIG
: 0;
141 qemu_set_irq(s
->irq
, !!(s
->r
[R_IMR
] & s
->r
[R_CISR
]));
144 static void fifo_trigger_update(void *opaque
)
146 CadenceUARTState
*s
= opaque
;
149 s
->r
[R_CISR
] |= UART_INTR_TIMEOUT
;
150 uart_update_status(s
);
154 static void uart_rx_reset(CadenceUARTState
*s
)
158 qemu_chr_fe_accept_input(&s
->chr
);
161 static void uart_tx_reset(CadenceUARTState
*s
)
166 static void uart_send_breaks(CadenceUARTState
*s
)
168 int break_enabled
= 1;
170 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
174 static void uart_parameters_setup(CadenceUARTState
*s
)
176 QEMUSerialSetParams ssp
;
177 unsigned int baud_rate
, packet_size
, input_clk
;
178 input_clk
= clock_get_hz(s
->refclk
);
180 baud_rate
= (s
->r
[R_MR
] & UART_MR_CLKS
) ? input_clk
/ 8 : input_clk
;
181 baud_rate
/= (s
->r
[R_BRGR
] * (s
->r
[R_BDIV
] + 1));
182 trace_cadence_uart_baudrate(baud_rate
);
184 ssp
.speed
= baud_rate
;
188 switch (s
->r
[R_MR
] & UART_MR_PAR
) {
189 case UART_PARITY_EVEN
:
193 case UART_PARITY_ODD
:
202 switch (s
->r
[R_MR
] & UART_MR_CHRL
) {
203 case UART_DATA_BITS_6
:
206 case UART_DATA_BITS_7
:
214 switch (s
->r
[R_MR
] & UART_MR_NBSTOP
) {
215 case UART_STOP_BITS_1
:
223 packet_size
+= ssp
.data_bits
+ ssp
.stop_bits
;
224 if (ssp
.speed
== 0) {
226 * Avoid division-by-zero below.
227 * TODO: find something better
231 s
->char_tx_time
= (NANOSECONDS_PER_SECOND
/ ssp
.speed
) * packet_size
;
232 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
235 static int uart_can_receive(void *opaque
)
237 CadenceUARTState
*s
= opaque
;
238 int ret
= MAX(CADENCE_UART_RX_FIFO_SIZE
, CADENCE_UART_TX_FIFO_SIZE
);
239 uint32_t ch_mode
= s
->r
[R_MR
] & UART_MR_CHMODE
;
241 if (ch_mode
== NORMAL_MODE
|| ch_mode
== ECHO_MODE
) {
242 ret
= MIN(ret
, CADENCE_UART_RX_FIFO_SIZE
- s
->rx_count
);
244 if (ch_mode
== REMOTE_LOOPBACK
|| ch_mode
== ECHO_MODE
) {
245 ret
= MIN(ret
, CADENCE_UART_TX_FIFO_SIZE
- s
->tx_count
);
250 static void uart_ctrl_update(CadenceUARTState
*s
)
252 if (s
->r
[R_CR
] & UART_CR_TXRST
) {
256 if (s
->r
[R_CR
] & UART_CR_RXRST
) {
260 s
->r
[R_CR
] &= ~(UART_CR_TXRST
| UART_CR_RXRST
);
262 if (s
->r
[R_CR
] & UART_CR_STARTBRK
&& !(s
->r
[R_CR
] & UART_CR_STOPBRK
)) {
267 static void uart_write_rx_fifo(void *opaque
, const uint8_t *buf
, int size
)
269 CadenceUARTState
*s
= opaque
;
270 uint64_t new_rx_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
273 if ((s
->r
[R_CR
] & UART_CR_RX_DIS
) || !(s
->r
[R_CR
] & UART_CR_RX_EN
)) {
277 if (s
->rx_count
== CADENCE_UART_RX_FIFO_SIZE
) {
278 s
->r
[R_CISR
] |= UART_INTR_ROVR
;
280 for (i
= 0; i
< size
; i
++) {
281 s
->rx_fifo
[s
->rx_wpos
] = buf
[i
];
282 s
->rx_wpos
= (s
->rx_wpos
+ 1) % CADENCE_UART_RX_FIFO_SIZE
;
285 timer_mod(s
->fifo_trigger_handle
, new_rx_time
+
286 (s
->char_tx_time
* 4));
288 uart_update_status(s
);
291 static gboolean
cadence_uart_xmit(GIOChannel
*chan
, GIOCondition cond
,
294 CadenceUARTState
*s
= opaque
;
297 /* instant drain the fifo when there's no back-end */
298 if (!qemu_chr_fe_backend_connected(&s
->chr
)) {
307 ret
= qemu_chr_fe_write(&s
->chr
, s
->tx_fifo
, s
->tx_count
);
311 memmove(s
->tx_fifo
, s
->tx_fifo
+ ret
, s
->tx_count
);
315 guint r
= qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
316 cadence_uart_xmit
, s
);
323 uart_update_status(s
);
327 static void uart_write_tx_fifo(CadenceUARTState
*s
, const uint8_t *buf
,
330 if ((s
->r
[R_CR
] & UART_CR_TX_DIS
) || !(s
->r
[R_CR
] & UART_CR_TX_EN
)) {
334 if (size
> CADENCE_UART_TX_FIFO_SIZE
- s
->tx_count
) {
335 size
= CADENCE_UART_TX_FIFO_SIZE
- s
->tx_count
;
337 * This can only be a guest error via a bad tx fifo register push,
338 * as can_receive() should stop remote loop and echo modes ever getting
341 qemu_log_mask(LOG_GUEST_ERROR
, "cadence_uart: TxFIFO overflow");
342 s
->r
[R_CISR
] |= UART_INTR_ROVR
;
345 memcpy(s
->tx_fifo
+ s
->tx_count
, buf
, size
);
348 cadence_uart_xmit(NULL
, G_IO_OUT
, s
);
351 static void uart_receive(void *opaque
, const uint8_t *buf
, int size
)
353 CadenceUARTState
*s
= opaque
;
354 uint32_t ch_mode
= s
->r
[R_MR
] & UART_MR_CHMODE
;
356 /* ignore characters when unclocked or in reset */
357 if (!clock_is_enabled(s
->refclk
) || device_is_in_reset(DEVICE(s
))) {
361 if (ch_mode
== NORMAL_MODE
|| ch_mode
== ECHO_MODE
) {
362 uart_write_rx_fifo(opaque
, buf
, size
);
364 if (ch_mode
== REMOTE_LOOPBACK
|| ch_mode
== ECHO_MODE
) {
365 uart_write_tx_fifo(s
, buf
, size
);
369 static void uart_event(void *opaque
, QEMUChrEvent event
)
371 CadenceUARTState
*s
= opaque
;
374 /* ignore characters when unclocked or in reset */
375 if (!clock_is_enabled(s
->refclk
) || device_is_in_reset(DEVICE(s
))) {
379 if (event
== CHR_EVENT_BREAK
) {
380 uart_write_rx_fifo(opaque
, &buf
, 1);
383 uart_update_status(s
);
386 static void uart_read_rx_fifo(CadenceUARTState
*s
, uint32_t *c
)
388 if ((s
->r
[R_CR
] & UART_CR_RX_DIS
) || !(s
->r
[R_CR
] & UART_CR_RX_EN
)) {
393 uint32_t rx_rpos
= (CADENCE_UART_RX_FIFO_SIZE
+ s
->rx_wpos
-
394 s
->rx_count
) % CADENCE_UART_RX_FIFO_SIZE
;
395 *c
= s
->rx_fifo
[rx_rpos
];
398 qemu_chr_fe_accept_input(&s
->chr
);
403 uart_update_status(s
);
406 static void uart_write(void *opaque
, hwaddr offset
,
407 uint64_t value
, unsigned size
)
409 CadenceUARTState
*s
= opaque
;
411 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset
, (unsigned)value
);
413 if (offset
>= CADENCE_UART_R_MAX
) {
417 case R_IER
: /* ier (wts imr) */
418 s
->r
[R_IMR
] |= value
;
420 case R_IDR
: /* idr (wtc imr) */
421 s
->r
[R_IMR
] &= ~value
;
423 case R_IMR
: /* imr (read only) */
425 case R_CISR
: /* cisr (wtc) */
426 s
->r
[R_CISR
] &= ~value
;
428 case R_TX_RX
: /* UARTDR */
429 switch (s
->r
[R_MR
] & UART_MR_CHMODE
) {
431 uart_write_tx_fifo(s
, (uint8_t *) &value
, 1);
434 uart_write_rx_fifo(opaque
, (uint8_t *) &value
, 1);
438 case R_BRGR
: /* Baud rate generator */
440 s
->r
[offset
] = value
& 0xFFFF;
443 case R_BDIV
: /* Baud rate divider */
445 s
->r
[offset
] = value
& 0xFF;
449 s
->r
[offset
] = value
;
457 uart_parameters_setup(s
);
460 uart_update_status(s
);
463 static uint64_t uart_read(void *opaque
, hwaddr offset
,
466 CadenceUARTState
*s
= opaque
;
470 if (offset
>= CADENCE_UART_R_MAX
) {
472 } else if (offset
== R_TX_RX
) {
473 uart_read_rx_fifo(s
, &c
);
478 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset
<< 2), (unsigned)c
);
482 static const MemoryRegionOps uart_ops
= {
485 .endianness
= DEVICE_NATIVE_ENDIAN
,
488 static void cadence_uart_reset_init(Object
*obj
, ResetType type
)
490 CadenceUARTState
*s
= CADENCE_UART(obj
);
492 s
->r
[R_CR
] = 0x00000128;
495 s
->r
[R_RTRIG
] = 0x00000020;
496 s
->r
[R_BRGR
] = 0x0000028B;
497 s
->r
[R_BDIV
] = 0x0000000F;
498 s
->r
[R_TTRIG
] = 0x00000020;
501 static void cadence_uart_reset_hold(Object
*obj
)
503 CadenceUARTState
*s
= CADENCE_UART(obj
);
508 uart_update_status(s
);
511 static void cadence_uart_realize(DeviceState
*dev
, Error
**errp
)
513 CadenceUARTState
*s
= CADENCE_UART(dev
);
515 s
->fifo_trigger_handle
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
516 fifo_trigger_update
, s
);
518 qemu_chr_fe_set_handlers(&s
->chr
, uart_can_receive
, uart_receive
,
519 uart_event
, NULL
, s
, NULL
, true);
522 static void cadence_uart_refclk_update(void *opaque
)
524 CadenceUARTState
*s
= opaque
;
526 /* recompute uart's speed on clock change */
527 uart_parameters_setup(s
);
530 static void cadence_uart_init(Object
*obj
)
532 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
533 CadenceUARTState
*s
= CADENCE_UART(obj
);
535 memory_region_init_io(&s
->iomem
, obj
, &uart_ops
, s
, "uart", 0x1000);
536 sysbus_init_mmio(sbd
, &s
->iomem
);
537 sysbus_init_irq(sbd
, &s
->irq
);
539 s
->refclk
= qdev_init_clock_in(DEVICE(obj
), "refclk",
540 cadence_uart_refclk_update
, s
);
541 /* initialize the frequency in case the clock remains unconnected */
542 clock_set_hz(s
->refclk
, UART_DEFAULT_REF_CLK
);
544 s
->char_tx_time
= (NANOSECONDS_PER_SECOND
/ 9600) * 10;
547 static int cadence_uart_pre_load(void *opaque
)
549 CadenceUARTState
*s
= opaque
;
551 /* the frequency will be overriden if the refclk field is present */
552 clock_set_hz(s
->refclk
, UART_DEFAULT_REF_CLK
);
556 static int cadence_uart_post_load(void *opaque
, int version_id
)
558 CadenceUARTState
*s
= opaque
;
560 /* Ensure these two aren't invalid numbers */
561 if (s
->r
[R_BRGR
] < 1 || s
->r
[R_BRGR
] & ~0xFFFF ||
562 s
->r
[R_BDIV
] <= 3 || s
->r
[R_BDIV
] & ~0xFF) {
563 /* Value is invalid, abort */
567 uart_parameters_setup(s
);
568 uart_update_status(s
);
572 static const VMStateDescription vmstate_cadence_uart
= {
573 .name
= "cadence_uart",
575 .minimum_version_id
= 2,
576 .pre_load
= cadence_uart_pre_load
,
577 .post_load
= cadence_uart_post_load
,
578 .fields
= (VMStateField
[]) {
579 VMSTATE_UINT32_ARRAY(r
, CadenceUARTState
, CADENCE_UART_R_MAX
),
580 VMSTATE_UINT8_ARRAY(rx_fifo
, CadenceUARTState
,
581 CADENCE_UART_RX_FIFO_SIZE
),
582 VMSTATE_UINT8_ARRAY(tx_fifo
, CadenceUARTState
,
583 CADENCE_UART_TX_FIFO_SIZE
),
584 VMSTATE_UINT32(rx_count
, CadenceUARTState
),
585 VMSTATE_UINT32(tx_count
, CadenceUARTState
),
586 VMSTATE_UINT32(rx_wpos
, CadenceUARTState
),
587 VMSTATE_TIMER_PTR(fifo_trigger_handle
, CadenceUARTState
),
588 VMSTATE_CLOCK_V(refclk
, CadenceUARTState
, 3),
589 VMSTATE_END_OF_LIST()
593 static Property cadence_uart_properties
[] = {
594 DEFINE_PROP_CHR("chardev", CadenceUARTState
, chr
),
595 DEFINE_PROP_END_OF_LIST(),
598 static void cadence_uart_class_init(ObjectClass
*klass
, void *data
)
600 DeviceClass
*dc
= DEVICE_CLASS(klass
);
601 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
603 dc
->realize
= cadence_uart_realize
;
604 dc
->vmsd
= &vmstate_cadence_uart
;
605 rc
->phases
.enter
= cadence_uart_reset_init
;
606 rc
->phases
.hold
= cadence_uart_reset_hold
;
607 device_class_set_props(dc
, cadence_uart_properties
);
610 static const TypeInfo cadence_uart_info
= {
611 .name
= TYPE_CADENCE_UART
,
612 .parent
= TYPE_SYS_BUS_DEVICE
,
613 .instance_size
= sizeof(CadenceUARTState
),
614 .instance_init
= cadence_uart_init
,
615 .class_init
= cadence_uart_class_init
,
618 static void cadence_uart_register_types(void)
620 type_register_static(&cadence_uart_info
);
623 type_init(cadence_uart_register_types
)