1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/core/cpu.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/boards.h"
47 #include "sysemu/tpm_backend.h"
48 #include "hw/rtc/mc146818rtc_regs.h"
49 #include "migration/vmstate.h"
50 #include "hw/mem/memory-device.h"
51 #include "hw/mem/nvdimm.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/reset.h"
54 #include "hw/hyperv/vmbus-bridge.h"
56 /* Supported chipsets: */
57 #include "hw/southbridge/piix.h"
58 #include "hw/acpi/pcihp.h"
59 #include "hw/i386/fw_cfg.h"
60 #include "hw/i386/ich9.h"
61 #include "hw/pci/pci_bus.h"
62 #include "hw/pci-host/q35.h"
63 #include "hw/i386/x86-iommu.h"
65 #include "hw/acpi/aml-build.h"
66 #include "hw/acpi/utils.h"
67 #include "hw/acpi/pci.h"
69 #include "qom/qom-qobject.h"
70 #include "hw/i386/amd_iommu.h"
71 #include "hw/i386/intel_iommu.h"
73 #include "hw/acpi/ipmi.h"
74 #include "hw/acpi/hmat.h"
76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
78 * a little bit, there should be plenty of free space since the DSDT
79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
82 #define ACPI_BUILD_ALIGN_SIZE 0x1000
84 #define ACPI_BUILD_TABLE_SIZE 0x20000
86 /* #define DEBUG_ACPI_BUILD */
87 #ifdef DEBUG_ACPI_BUILD
88 #define ACPI_BUILD_DPRINTF(fmt, ...) \
89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
91 #define ACPI_BUILD_DPRINTF(fmt, ...)
94 typedef struct AcpiPmInfo
{
99 bool smi_on_cpu_unplug
;
103 uint16_t cpu_hp_io_base
;
104 uint16_t pcihp_io_base
;
105 uint16_t pcihp_io_len
;
108 typedef struct AcpiMiscInfo
{
111 TPMVersion tpm_version
;
112 const unsigned char *dsdt_code
;
114 uint16_t pvpanic_port
;
115 uint16_t applesmc_io_base
;
118 typedef struct AcpiBuildPciBusHotplugState
{
119 GArray
*device_table
;
120 GArray
*notify_table
;
121 struct AcpiBuildPciBusHotplugState
*parent
;
122 bool pcihp_bridge_en
;
123 } AcpiBuildPciBusHotplugState
;
125 typedef struct FwCfgTPMConfig
{
126 uint32_t tpmppi_address
;
128 uint8_t tpmppi_version
;
129 } QEMU_PACKED FwCfgTPMConfig
;
131 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
);
133 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio
= {
134 .space_id
= AML_AS_SYSTEM_IO
,
135 .address
= NVDIMM_ACPI_IO_BASE
,
136 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
139 static void init_common_fadt_data(MachineState
*ms
, Object
*o
,
142 X86MachineState
*x86ms
= X86_MACHINE(ms
);
144 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
145 * behavior for compatibility irrelevant to smm_enabled, which doesn't
146 * comforms to ACPI spec.
148 bool smm_enabled
= object_property_get_bool(o
, "smm-compat", NULL
) ?
149 true : x86_machine_is_smm_enabled(x86ms
);
150 uint32_t io
= object_property_get_uint(o
, ACPI_PM_PROP_PM_IO_BASE
, NULL
);
151 AmlAddressSpace as
= AML_AS_SYSTEM_IO
;
152 AcpiFadtData fadt
= {
155 (1 << ACPI_FADT_F_WBINVD
) |
156 (1 << ACPI_FADT_F_PROC_C1
) |
157 (1 << ACPI_FADT_F_SLP_BUTTON
) |
158 (1 << ACPI_FADT_F_RTC_S4
) |
159 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
) |
160 /* APIC destination mode ("Flat Logical") has an upper limit of 8
161 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
164 ((ms
->smp
.max_cpus
> 8) ?
165 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
) : 0),
166 .int_model
= 1 /* Multiple APIC */,
167 .rtc_century
= RTC_CENTURY
,
168 .plvl2_lat
= 0xfff /* C2 state not supported */,
169 .plvl3_lat
= 0xfff /* C3 state not supported */,
170 .smi_cmd
= smm_enabled
? ACPI_PORT_SMI_CMD
: 0,
171 .sci_int
= object_property_get_uint(o
, ACPI_PM_PROP_SCI_INT
, NULL
),
174 object_property_get_uint(o
, ACPI_PM_PROP_ACPI_ENABLE_CMD
, NULL
) :
178 object_property_get_uint(o
, ACPI_PM_PROP_ACPI_DISABLE_CMD
, NULL
) :
180 .pm1a_evt
= { .space_id
= as
, .bit_width
= 4 * 8, .address
= io
},
181 .pm1a_cnt
= { .space_id
= as
, .bit_width
= 2 * 8,
182 .address
= io
+ 0x04 },
183 .pm_tmr
= { .space_id
= as
, .bit_width
= 4 * 8, .address
= io
+ 0x08 },
184 .gpe0_blk
= { .space_id
= as
, .bit_width
=
185 object_property_get_uint(o
, ACPI_PM_PROP_GPE0_BLK_LEN
, NULL
) * 8,
186 .address
= object_property_get_uint(o
, ACPI_PM_PROP_GPE0_BLK
, NULL
)
192 static Object
*object_resolve_type_unambiguous(const char *typename
)
195 Object
*o
= object_resolve_path_type("", typename
, &ambig
);
203 static void acpi_get_pm_info(MachineState
*machine
, AcpiPmInfo
*pm
)
205 Object
*piix
= object_resolve_type_unambiguous(TYPE_PIIX4_PM
);
206 Object
*lpc
= object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE
);
207 Object
*obj
= piix
? piix
: lpc
;
209 pm
->cpu_hp_io_base
= 0;
210 pm
->pcihp_io_base
= 0;
211 pm
->pcihp_io_len
= 0;
212 pm
->smi_on_cpuhp
= false;
213 pm
->smi_on_cpu_unplug
= false;
216 init_common_fadt_data(machine
, obj
, &pm
->fadt
);
218 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
220 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
222 object_property_get_uint(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
224 object_property_get_uint(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
227 uint64_t smi_features
= object_property_get_uint(lpc
,
228 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP
, NULL
);
229 struct AcpiGenericAddress r
= { .space_id
= AML_AS_SYSTEM_IO
,
230 .bit_width
= 8, .address
= ICH9_RST_CNT_IOPORT
};
231 pm
->fadt
.reset_reg
= r
;
232 pm
->fadt
.reset_val
= 0xf;
233 pm
->fadt
.flags
|= 1 << ACPI_FADT_F_RESET_REG_SUP
;
234 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
236 !!(smi_features
& BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT
));
237 pm
->smi_on_cpu_unplug
=
238 !!(smi_features
& BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT
));
241 /* The above need not be conditional on machine type because the reset port
242 * happens to be the same on PIIX (pc) and ICH9 (q35). */
243 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT
!= PIIX_RCR_IOPORT
);
245 /* Fill in optional s3/s4 related properties */
246 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
248 pm
->s3_disabled
= qnum_get_uint(qobject_to(QNum
, o
));
250 pm
->s3_disabled
= false;
253 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
255 pm
->s4_disabled
= qnum_get_uint(qobject_to(QNum
, o
));
257 pm
->s4_disabled
= false;
260 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
262 pm
->s4_val
= qnum_get_uint(qobject_to(QNum
, o
));
268 pm
->pcihp_bridge_en
=
269 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
272 object_property_get_bool(obj
, "acpi-root-pci-hotplug",
276 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
278 Object
*piix
= object_resolve_type_unambiguous(TYPE_PIIX4_PM
);
279 Object
*lpc
= object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE
);
280 assert(!!piix
!= !!lpc
);
283 info
->is_piix4
= true;
286 info
->is_piix4
= false;
289 info
->has_hpet
= hpet_find();
290 info
->tpm_version
= tpm_get_version(tpm_find());
291 info
->pvpanic_port
= pvpanic_port();
292 info
->applesmc_io_base
= applesmc_port();
296 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
297 * On i386 arch we only have two pci hosts, so we can look only for them.
299 static Object
*acpi_get_i386_pci_host(void)
303 host
= OBJECT_CHECK(PCIHostState
,
304 object_resolve_path("/machine/i440fx", NULL
),
305 TYPE_PCI_HOST_BRIDGE
);
307 host
= OBJECT_CHECK(PCIHostState
,
308 object_resolve_path("/machine/q35", NULL
),
309 TYPE_PCI_HOST_BRIDGE
);
315 static void acpi_get_pci_holes(Range
*hole
, Range
*hole64
)
319 pci_host
= acpi_get_i386_pci_host();
322 range_set_bounds1(hole
,
323 object_property_get_uint(pci_host
,
324 PCI_HOST_PROP_PCI_HOLE_START
,
326 object_property_get_uint(pci_host
,
327 PCI_HOST_PROP_PCI_HOLE_END
,
329 range_set_bounds1(hole64
,
330 object_property_get_uint(pci_host
,
331 PCI_HOST_PROP_PCI_HOLE64_START
,
333 object_property_get_uint(pci_host
,
334 PCI_HOST_PROP_PCI_HOLE64_END
,
338 static void acpi_align_size(GArray
*blob
, unsigned align
)
340 /* Align size to multiple of given size. This reduces the chance
341 * we need to change size in the future (breaking cross version migration).
343 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
348 build_facs(GArray
*table_data
)
350 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
351 memcpy(&facs
->signature
, "FACS", 4);
352 facs
->length
= cpu_to_le32(sizeof(*facs
));
355 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
358 int32_t devfn
= PCI_DEVFN(slot
, 0);
360 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
361 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
362 aml_append(method
, if_ctx
);
365 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
366 bool pcihp_bridge_en
)
368 Aml
*dev
, *notify_method
= NULL
, *method
;
373 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
375 uint64_t bsel_val
= qnum_get_uint(qobject_to(QNum
, bsel
));
377 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
378 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
381 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
384 PCIDevice
*pdev
= bus
->devices
[i
];
385 int slot
= PCI_SLOT(i
);
386 bool hotplug_enabled_dev
;
388 bool cold_plugged_bridge
;
391 if (bsel
) { /* add hotplug slots for non present devices */
392 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
393 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
394 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
395 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
397 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
399 aml_append(dev
, method
);
400 aml_append(parent_scope
, dev
);
402 build_append_pcihp_notify_entry(notify_method
, slot
);
407 pc
= PCI_DEVICE_GET_CLASS(pdev
);
408 dc
= DEVICE_GET_CLASS(pdev
);
411 * Cold plugged bridges aren't themselves hot-pluggable.
412 * Hotplugged bridges *are* hot-pluggable.
414 cold_plugged_bridge
= pc
->is_bridge
&& !DEVICE(pdev
)->hotplugged
;
415 bridge_in_acpi
= cold_plugged_bridge
&& pcihp_bridge_en
;
417 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !cold_plugged_bridge
;
419 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
423 /* start to compose PCI slot descriptor */
424 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
425 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
427 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
428 /* add VGA specific AML methods */
431 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
437 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
438 aml_append(method
, aml_return(aml_int(0)));
439 aml_append(dev
, method
);
441 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
442 aml_append(method
, aml_return(aml_int(0)));
443 aml_append(dev
, method
);
445 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
446 aml_append(method
, aml_return(aml_int(s3d
)));
447 aml_append(dev
, method
);
448 } else if (hotplug_enabled_dev
) {
449 /* add _SUN/_EJ0 to make slot hotpluggable */
450 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
452 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
454 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
456 aml_append(dev
, method
);
459 build_append_pcihp_notify_entry(notify_method
, slot
);
461 } else if (bridge_in_acpi
) {
463 * device is coldplugged bridge,
464 * add child device descriptions into its scope
466 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
468 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
470 /* slot descriptor has been composed, add it into parent context */
471 aml_append(parent_scope
, dev
);
475 aml_append(parent_scope
, notify_method
);
478 /* Append PCNT method to notify about events on local and child buses.
479 * Add this method for root bus only when hotplug is enabled since DSDT
482 if (bsel
|| pcihp_bridge_en
) {
483 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
485 /* If bus supports hotplug select it and notify about local events */
487 uint64_t bsel_val
= qnum_get_uint(qobject_to(QNum
, bsel
));
489 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
490 aml_append(method
, aml_call2("DVNT", aml_name("PCIU"),
491 aml_int(1))); /* Device Check */
492 aml_append(method
, aml_call2("DVNT", aml_name("PCID"),
493 aml_int(3))); /* Eject Request */
496 /* Notify about child bus events in any case */
497 if (pcihp_bridge_en
) {
498 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
499 int32_t devfn
= sec
->parent_dev
->devfn
;
501 if (pci_bus_is_root(sec
) || pci_bus_is_express(sec
)) {
505 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
509 aml_append(parent_scope
, method
);
516 * @link_name: link name for PCI route entry
518 * build AML package containing a PCI route entry for @link_name
520 static Aml
*build_prt_entry(const char *link_name
)
522 Aml
*a_zero
= aml_int(0);
523 Aml
*pkg
= aml_package(4);
524 aml_append(pkg
, a_zero
);
525 aml_append(pkg
, a_zero
);
526 aml_append(pkg
, aml_name("%s", link_name
));
527 aml_append(pkg
, a_zero
);
532 * initialize_route - Initialize the interrupt routing rule
533 * through a specific LINK:
534 * if (lnk_idx == idx)
535 * route using link 'link_name'
537 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
538 Aml
*lnk_idx
, int idx
)
540 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
541 Aml
*pkg
= build_prt_entry(link_name
);
543 aml_append(if_ctx
, aml_store(pkg
, route
));
549 * build_prt - Define interrupt rounting rules
551 * Returns an array of 128 routes, one for each device,
552 * based on device location.
553 * The main goal is to equaly distribute the interrupts
554 * over the 4 existing ACPI links (works only for i440fx).
555 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
558 static Aml
*build_prt(bool is_pci0_prt
)
560 Aml
*method
, *while_ctx
, *pin
, *res
;
562 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
565 aml_append(method
, aml_store(aml_package(128), res
));
566 aml_append(method
, aml_store(aml_int(0), pin
));
568 /* while (pin < 128) */
569 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
571 Aml
*slot
= aml_local(2);
572 Aml
*lnk_idx
= aml_local(3);
573 Aml
*route
= aml_local(4);
575 /* slot = pin >> 2 */
576 aml_append(while_ctx
,
577 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
578 /* lnk_idx = (slot + pin) & 3 */
579 aml_append(while_ctx
,
580 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
583 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
584 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
586 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
588 /* device 1 is the power-management device, needs SCI */
589 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
591 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
594 aml_store(build_prt_entry("LNKS"), route
));
596 aml_append(if_device_1
, if_pin_4
);
597 else_pin_4
= aml_else();
599 aml_append(else_pin_4
,
600 aml_store(build_prt_entry("LNKA"), route
));
602 aml_append(if_device_1
, else_pin_4
);
604 aml_append(while_ctx
, if_device_1
);
606 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
608 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
609 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
611 /* route[0] = 0x[slot]FFFF */
612 aml_append(while_ctx
,
613 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
615 aml_index(route
, aml_int(0))));
616 /* route[1] = pin & 3 */
617 aml_append(while_ctx
,
618 aml_store(aml_and(pin
, aml_int(3), NULL
),
619 aml_index(route
, aml_int(1))));
620 /* res[pin] = route */
621 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
623 aml_append(while_ctx
, aml_increment(pin
));
625 aml_append(method
, while_ctx
);
627 aml_append(method
, aml_return(res
));
632 static void build_hpet_aml(Aml
*table
)
638 Aml
*scope
= aml_scope("_SB");
639 Aml
*dev
= aml_device("HPET");
640 Aml
*zero
= aml_int(0);
641 Aml
*id
= aml_local(0);
642 Aml
*period
= aml_local(1);
644 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
645 aml_append(dev
, aml_name_decl("_UID", zero
));
648 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
650 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
651 aml_append(field
, aml_named_field("VEND", 32));
652 aml_append(field
, aml_named_field("PRD", 32));
653 aml_append(dev
, field
);
655 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
656 aml_append(method
, aml_store(aml_name("VEND"), id
));
657 aml_append(method
, aml_store(aml_name("PRD"), period
));
658 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
659 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
660 aml_equal(id
, aml_int(0xffff))));
662 aml_append(if_ctx
, aml_return(zero
));
664 aml_append(method
, if_ctx
);
666 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
667 aml_lgreater(period
, aml_int(100000000))));
669 aml_append(if_ctx
, aml_return(zero
));
671 aml_append(method
, if_ctx
);
673 aml_append(method
, aml_return(aml_int(0x0F)));
674 aml_append(dev
, method
);
676 crs
= aml_resource_template();
677 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
678 aml_append(dev
, aml_name_decl("_CRS", crs
));
680 aml_append(scope
, dev
);
681 aml_append(table
, scope
);
684 static Aml
*build_vmbus_device_aml(VMBusBridge
*vmbus_bridge
)
690 dev
= aml_device("VMBS");
691 aml_append(dev
, aml_name_decl("STA", aml_int(0xF)));
692 aml_append(dev
, aml_name_decl("_HID", aml_string("VMBus")));
693 aml_append(dev
, aml_name_decl("_UID", aml_int(0x0)));
694 aml_append(dev
, aml_name_decl("_DDN", aml_string("VMBUS")));
696 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
697 aml_append(method
, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL
),
699 aml_append(dev
, method
);
701 method
= aml_method("_PS0", 0, AML_NOTSERIALIZED
);
702 aml_append(method
, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL
),
704 aml_append(dev
, method
);
706 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
707 aml_append(method
, aml_return(aml_name("STA")));
708 aml_append(dev
, method
);
710 aml_append(dev
, aml_name_decl("_PS3", aml_int(0x0)));
712 crs
= aml_resource_template();
713 aml_append(crs
, aml_irq_no_flags(vmbus_bridge
->irq
));
714 aml_append(dev
, aml_name_decl("_CRS", crs
));
719 static void build_isa_devices_aml(Aml
*table
)
722 Object
*obj
= object_resolve_path_type("", TYPE_ISA_BUS
, &ambiguous
);
725 assert(obj
&& !ambiguous
);
727 scope
= aml_scope("_SB.PCI0.ISA");
728 build_acpi_ipmi_devices(scope
, BUS(obj
), "\\_SB.PCI0.ISA");
729 isa_build_aml(ISA_BUS(obj
), scope
);
731 aml_append(table
, scope
);
734 static void build_dbg_aml(Aml
*table
)
739 Aml
*scope
= aml_scope("\\");
740 Aml
*buf
= aml_local(0);
741 Aml
*len
= aml_local(1);
742 Aml
*idx
= aml_local(2);
745 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
746 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
747 aml_append(field
, aml_named_field("DBGB", 8));
748 aml_append(scope
, field
);
750 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
752 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
753 aml_append(method
, aml_to_buffer(buf
, buf
));
754 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
755 aml_append(method
, aml_store(aml_int(0), idx
));
757 while_ctx
= aml_while(aml_lless(idx
, len
));
758 aml_append(while_ctx
,
759 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
760 aml_append(while_ctx
, aml_increment(idx
));
761 aml_append(method
, while_ctx
);
763 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
764 aml_append(scope
, method
);
766 aml_append(table
, scope
);
769 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
774 uint32_t irqs
[] = {5, 10, 11};
776 dev
= aml_device("%s", name
);
777 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
778 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
780 crs
= aml_resource_template();
781 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
782 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
783 aml_append(dev
, aml_name_decl("_PRS", crs
));
785 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
786 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
787 aml_append(dev
, method
);
789 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
790 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
791 aml_append(dev
, method
);
793 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
794 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
795 aml_append(dev
, method
);
797 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
798 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
799 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
800 aml_append(dev
, method
);
805 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
812 dev
= aml_device("%s", name
);
813 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
814 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
816 crs
= aml_resource_template();
818 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
819 AML_SHARED
, &irqs
, 1));
820 aml_append(dev
, aml_name_decl("_PRS", crs
));
822 aml_append(dev
, aml_name_decl("_CRS", crs
));
825 * _DIS can be no-op because the interrupt cannot be disabled.
827 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
828 aml_append(dev
, method
);
830 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
831 aml_append(dev
, method
);
836 /* _CRS method - get current settings */
837 static Aml
*build_iqcr_method(bool is_piix4
)
841 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
842 Aml
*crs
= aml_resource_template();
845 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
846 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
847 aml_append(method
, aml_name_decl("PRR0", crs
));
850 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
853 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
854 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
855 aml_append(method
, if_ctx
);
858 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
862 aml_append(method
, aml_return(aml_name("PRR0")));
866 /* _STA method - get status */
867 static Aml
*build_irq_status_method(void)
870 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
872 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
873 aml_append(if_ctx
, aml_return(aml_int(0x09)));
874 aml_append(method
, if_ctx
);
875 aml_append(method
, aml_return(aml_int(0x0B)));
879 static void build_piix4_pci0_int(Aml
*table
)
886 Aml
*sb_scope
= aml_scope("_SB");
887 Aml
*pci0_scope
= aml_scope("PCI0");
889 aml_append(pci0_scope
, build_prt(true));
890 aml_append(sb_scope
, pci0_scope
);
892 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
893 aml_append(field
, aml_named_field("PRQ0", 8));
894 aml_append(field
, aml_named_field("PRQ1", 8));
895 aml_append(field
, aml_named_field("PRQ2", 8));
896 aml_append(field
, aml_named_field("PRQ3", 8));
897 aml_append(sb_scope
, field
);
899 aml_append(sb_scope
, build_irq_status_method());
900 aml_append(sb_scope
, build_iqcr_method(true));
902 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
903 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
904 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
905 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
907 dev
= aml_device("LNKS");
909 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
910 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
912 crs
= aml_resource_template();
914 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
915 AML_ACTIVE_HIGH
, AML_SHARED
,
917 aml_append(dev
, aml_name_decl("_PRS", crs
));
919 /* The SCI cannot be disabled and is always attached to GSI 9,
920 * so these are no-ops. We only need this link to override the
921 * polarity to active high and match the content of the MADT.
923 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
924 aml_append(method
, aml_return(aml_int(0x0b)));
925 aml_append(dev
, method
);
927 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
928 aml_append(dev
, method
);
930 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
931 aml_append(method
, aml_return(aml_name("_PRS")));
932 aml_append(dev
, method
);
934 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
935 aml_append(dev
, method
);
937 aml_append(sb_scope
, dev
);
939 aml_append(table
, sb_scope
);
942 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
947 char base
= name
[3] < 'E' ? 'A' : 'E';
948 char *s
= g_strdup(name
);
949 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
951 assert(strlen(s
) == 4);
953 head
= name
[3] - base
;
954 for (i
= 0; i
< 4; i
++) {
958 s
[3] = base
+ head
+ i
;
959 pkg
= aml_package(4);
960 aml_append(pkg
, a_nr
);
961 aml_append(pkg
, aml_int(i
));
962 aml_append(pkg
, aml_name("%s", s
));
963 aml_append(pkg
, aml_int(0));
964 aml_append(ctx
, pkg
);
969 static Aml
*build_q35_routing_table(const char *str
)
973 char *name
= g_strdup_printf("%s ", str
);
975 pkg
= aml_package(128);
976 for (i
= 0; i
< 0x18; i
++) {
977 name
[3] = 'E' + (i
& 0x3);
978 append_q35_prt_entry(pkg
, i
, name
);
982 append_q35_prt_entry(pkg
, 0x18, name
);
984 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
985 for (i
= 0x0019; i
< 0x1e; i
++) {
987 append_q35_prt_entry(pkg
, i
, name
);
990 /* PCIe->PCI bridge. use PIRQ[E-H] */
992 append_q35_prt_entry(pkg
, 0x1e, name
);
994 append_q35_prt_entry(pkg
, 0x1f, name
);
1000 static void build_q35_pci0_int(Aml
*table
)
1004 Aml
*sb_scope
= aml_scope("_SB");
1005 Aml
*pci0_scope
= aml_scope("PCI0");
1007 /* Zero => PIC mode, One => APIC Mode */
1008 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1009 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1011 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1013 aml_append(table
, method
);
1015 aml_append(pci0_scope
,
1016 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1017 aml_append(pci0_scope
,
1018 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1020 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1025 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1027 /* Note: we provide the same info as the PCI routing
1028 table of the Bochs BIOS */
1029 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1030 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1031 aml_append(method
, if_ctx
);
1032 else_ctx
= aml_else();
1033 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1034 aml_append(method
, else_ctx
);
1036 aml_append(pci0_scope
, method
);
1037 aml_append(sb_scope
, pci0_scope
);
1039 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1040 aml_append(field
, aml_named_field("PRQA", 8));
1041 aml_append(field
, aml_named_field("PRQB", 8));
1042 aml_append(field
, aml_named_field("PRQC", 8));
1043 aml_append(field
, aml_named_field("PRQD", 8));
1044 aml_append(field
, aml_reserved_field(0x20));
1045 aml_append(field
, aml_named_field("PRQE", 8));
1046 aml_append(field
, aml_named_field("PRQF", 8));
1047 aml_append(field
, aml_named_field("PRQG", 8));
1048 aml_append(field
, aml_named_field("PRQH", 8));
1049 aml_append(sb_scope
, field
);
1051 aml_append(sb_scope
, build_irq_status_method());
1052 aml_append(sb_scope
, build_iqcr_method(false));
1054 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1055 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1056 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1057 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1058 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1059 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1060 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1061 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1063 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1064 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1065 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1066 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1067 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1068 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1069 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1070 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1072 aml_append(table
, sb_scope
);
1075 static Aml
*build_q35_dram_controller(const AcpiMcfgInfo
*mcfg
)
1078 Aml
*resource_template
;
1080 /* DRAM controller */
1081 dev
= aml_device("DRAC");
1082 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0C01")));
1084 resource_template
= aml_resource_template();
1085 if (mcfg
->base
+ mcfg
->size
- 1 >= (1ULL << 32)) {
1086 aml_append(resource_template
,
1087 aml_qword_memory(AML_POS_DECODE
,
1094 mcfg
->base
+ mcfg
->size
- 1,
1098 aml_append(resource_template
,
1099 aml_dword_memory(AML_POS_DECODE
,
1106 mcfg
->base
+ mcfg
->size
- 1,
1110 aml_append(dev
, aml_name_decl("_CRS", resource_template
));
1115 static void build_q35_isa_bridge(Aml
*table
)
1120 scope
= aml_scope("_SB.PCI0");
1121 dev
= aml_device("ISA");
1122 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1124 /* ICH9 PCI to ISA irq remapping */
1125 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1126 aml_int(0x60), 0x0C));
1128 aml_append(scope
, dev
);
1129 aml_append(table
, scope
);
1132 static void build_piix4_isa_bridge(Aml
*table
)
1137 scope
= aml_scope("_SB.PCI0");
1138 dev
= aml_device("ISA");
1139 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1141 /* PIIX PCI to ISA irq remapping */
1142 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1143 aml_int(0x60), 0x04));
1145 aml_append(scope
, dev
);
1146 aml_append(table
, scope
);
1149 static void build_piix4_pci_hotplug(Aml
*table
)
1155 scope
= aml_scope("_SB.PCI0");
1158 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1159 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1160 aml_append(field
, aml_named_field("PCIU", 32));
1161 aml_append(field
, aml_named_field("PCID", 32));
1162 aml_append(scope
, field
);
1165 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1166 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1167 aml_append(field
, aml_named_field("B0EJ", 32));
1168 aml_append(scope
, field
);
1171 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x04));
1172 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1173 aml_append(field
, aml_named_field("BNUM", 32));
1174 aml_append(scope
, field
);
1176 aml_append(scope
, aml_mutex("BLCK", 0));
1178 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1179 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1180 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1182 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1183 aml_append(method
, aml_release(aml_name("BLCK")));
1184 aml_append(method
, aml_return(aml_int(0)));
1185 aml_append(scope
, method
);
1187 aml_append(table
, scope
);
1190 static Aml
*build_q35_osc_method(void)
1196 Aml
*a_cwd1
= aml_name("CDW1");
1197 Aml
*a_ctrl
= aml_local(0);
1199 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1200 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1202 if_ctx
= aml_if(aml_equal(
1203 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1204 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1205 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1207 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1210 * Always allow native PME, AER (no dependencies)
1211 * Allow SHPC (PCI bridges can have SHPC controller)
1213 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1F), a_ctrl
));
1215 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1216 /* Unknown revision */
1217 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1218 aml_append(if_ctx
, if_ctx2
);
1220 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1221 /* Capabilities bits were masked */
1222 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1223 aml_append(if_ctx
, if_ctx2
);
1225 /* Update DWORD3 in the buffer */
1226 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1227 aml_append(method
, if_ctx
);
1229 else_ctx
= aml_else();
1230 /* Unrecognized UUID */
1231 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1232 aml_append(method
, else_ctx
);
1234 aml_append(method
, aml_return(aml_arg(3)));
1238 static void build_smb0(Aml
*table
, I2CBus
*smbus
, int devnr
, int func
)
1240 Aml
*scope
= aml_scope("_SB.PCI0");
1241 Aml
*dev
= aml_device("SMB0");
1243 aml_append(dev
, aml_name_decl("_ADR", aml_int(devnr
<< 16 | func
)));
1244 build_acpi_ipmi_devices(dev
, BUS(smbus
), "\\_SB.PCI0.SMB0");
1245 aml_append(scope
, dev
);
1246 aml_append(table
, scope
);
1250 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1251 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1252 Range
*pci_hole
, Range
*pci_hole64
, MachineState
*machine
)
1254 CrsRangeEntry
*entry
;
1255 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1256 CrsRangeSet crs_range_set
;
1257 PCMachineState
*pcms
= PC_MACHINE(machine
);
1258 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1259 X86MachineState
*x86ms
= X86_MACHINE(machine
);
1261 bool mcfg_valid
= !!acpi_get_mcfg(&mcfg
);
1262 uint32_t nr_mem
= machine
->ram_slots
;
1263 int root_bus_limit
= 0xFF;
1265 TPMIf
*tpm
= tpm_find();
1267 VMBusBridge
*vmbus_bridge
= vmbus_bridge_find();
1269 dsdt
= init_aml_allocator();
1271 /* Reserve space for header */
1272 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
1274 build_dbg_aml(dsdt
);
1275 if (misc
->is_piix4
) {
1276 sb_scope
= aml_scope("_SB");
1277 dev
= aml_device("PCI0");
1278 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1279 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1280 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
1281 aml_append(sb_scope
, dev
);
1282 aml_append(dsdt
, sb_scope
);
1284 build_hpet_aml(dsdt
);
1285 build_piix4_isa_bridge(dsdt
);
1286 build_isa_devices_aml(dsdt
);
1287 if (pm
->pcihp_bridge_en
|| pm
->pcihp_root_en
) {
1288 build_piix4_pci_hotplug(dsdt
);
1290 build_piix4_pci0_int(dsdt
);
1292 sb_scope
= aml_scope("_SB");
1293 dev
= aml_device("PCI0");
1294 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1295 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1296 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1297 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
1298 aml_append(dev
, build_q35_osc_method());
1299 aml_append(sb_scope
, dev
);
1301 aml_append(sb_scope
, build_q35_dram_controller(&mcfg
));
1304 if (pm
->smi_on_cpuhp
) {
1305 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1306 dev
= aml_device("PCI0.SMI0");
1307 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1308 aml_append(dev
, aml_name_decl("_UID", aml_string("SMI resources")));
1309 crs
= aml_resource_template();
1318 aml_append(dev
, aml_name_decl("_CRS", crs
));
1319 aml_append(dev
, aml_operation_region("SMIR", AML_SYSTEM_IO
,
1320 aml_int(ACPI_PORT_SMI_CMD
), 2));
1321 field
= aml_field("SMIR", AML_BYTE_ACC
, AML_NOLOCK
,
1322 AML_WRITE_AS_ZEROS
);
1323 aml_append(field
, aml_named_field("SMIC", 8));
1324 aml_append(field
, aml_reserved_field(8));
1325 aml_append(dev
, field
);
1326 aml_append(sb_scope
, dev
);
1329 aml_append(dsdt
, sb_scope
);
1331 build_hpet_aml(dsdt
);
1332 build_q35_isa_bridge(dsdt
);
1333 build_isa_devices_aml(dsdt
);
1334 build_q35_pci0_int(dsdt
);
1335 if (pcms
->smbus
&& !pcmc
->do_not_add_smb_acpi
) {
1336 build_smb0(dsdt
, pcms
->smbus
, ICH9_SMB_DEV
, ICH9_SMB_FUNC
);
1341 sb_scope
= aml_scope("_SB");
1342 aml_append(sb_scope
, build_vmbus_device_aml(vmbus_bridge
));
1343 aml_append(dsdt
, sb_scope
);
1346 if (pcmc
->legacy_cpu_hotplug
) {
1347 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
1349 CPUHotplugFeatures opts
= {
1350 .acpi_1_compatible
= true, .has_legacy_cphp
= true,
1351 .smi_path
= pm
->smi_on_cpuhp
? "\\_SB.PCI0.SMI0.SMIC" : NULL
,
1352 .fw_unplugs_cpu
= pm
->smi_on_cpu_unplug
,
1354 build_cpus_aml(dsdt
, machine
, opts
, pm
->cpu_hp_io_base
,
1355 "\\_SB.PCI0", "\\_GPE._E02");
1358 if (pcms
->memhp_io_base
&& nr_mem
) {
1359 build_memory_hotplug_aml(dsdt
, nr_mem
, "\\_SB.PCI0",
1360 "\\_GPE._E03", AML_SYSTEM_IO
,
1361 pcms
->memhp_io_base
);
1364 scope
= aml_scope("_GPE");
1366 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
1368 if (misc
->is_piix4
&& (pm
->pcihp_bridge_en
|| pm
->pcihp_root_en
)) {
1369 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
1371 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1372 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
1373 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1374 aml_append(scope
, method
);
1377 if (machine
->nvdimms_state
->is_enabled
) {
1378 method
= aml_method("_E04", 0, AML_NOTSERIALIZED
);
1379 aml_append(method
, aml_notify(aml_name("\\_SB.NVDR"),
1381 aml_append(scope
, method
);
1384 aml_append(dsdt
, scope
);
1386 crs_range_set_init(&crs_range_set
);
1387 bus
= PC_MACHINE(machine
)->bus
;
1389 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1390 uint8_t bus_num
= pci_bus_num(bus
);
1391 uint8_t numa_node
= pci_bus_numa_node(bus
);
1393 /* look only for expander root buses */
1394 if (!pci_bus_is_root(bus
)) {
1398 if (bus_num
< root_bus_limit
) {
1399 root_bus_limit
= bus_num
- 1;
1402 scope
= aml_scope("\\_SB");
1403 dev
= aml_device("PC%.02X", bus_num
);
1404 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
1405 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
1406 if (pci_bus_is_express(bus
)) {
1407 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1408 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1409 aml_append(dev
, build_q35_osc_method());
1411 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1414 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
1415 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
1418 aml_append(dev
, build_prt(false));
1419 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
), &crs_range_set
,
1421 aml_append(dev
, aml_name_decl("_CRS", crs
));
1422 aml_append(scope
, dev
);
1423 aml_append(dsdt
, scope
);
1428 * At this point crs_range_set has all the ranges used by pci
1429 * busses *other* than PCI0. These ranges will be excluded from
1430 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1434 crs_range_insert(crs_range_set
.mem_ranges
,
1435 mcfg
.base
, mcfg
.base
+ mcfg
.size
- 1);
1438 scope
= aml_scope("\\_SB.PCI0");
1439 /* build PCI0._CRS */
1440 crs
= aml_resource_template();
1442 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1443 0x0000, 0x0, root_bus_limit
,
1444 0x0000, root_bus_limit
+ 1));
1445 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
1448 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1449 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1450 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1452 crs_replace_with_free_ranges(crs_range_set
.io_ranges
, 0x0D00, 0xFFFF);
1453 for (i
= 0; i
< crs_range_set
.io_ranges
->len
; i
++) {
1454 entry
= g_ptr_array_index(crs_range_set
.io_ranges
, i
);
1456 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1457 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1458 0x0000, entry
->base
, entry
->limit
,
1459 0x0000, entry
->limit
- entry
->base
+ 1));
1463 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
1464 AML_CACHEABLE
, AML_READ_WRITE
,
1465 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1467 crs_replace_with_free_ranges(crs_range_set
.mem_ranges
,
1468 range_lob(pci_hole
),
1469 range_upb(pci_hole
));
1470 for (i
= 0; i
< crs_range_set
.mem_ranges
->len
; i
++) {
1471 entry
= g_ptr_array_index(crs_range_set
.mem_ranges
, i
);
1473 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
1474 AML_NON_CACHEABLE
, AML_READ_WRITE
,
1475 0, entry
->base
, entry
->limit
,
1476 0, entry
->limit
- entry
->base
+ 1));
1479 if (!range_is_empty(pci_hole64
)) {
1480 crs_replace_with_free_ranges(crs_range_set
.mem_64bit_ranges
,
1481 range_lob(pci_hole64
),
1482 range_upb(pci_hole64
));
1483 for (i
= 0; i
< crs_range_set
.mem_64bit_ranges
->len
; i
++) {
1484 entry
= g_ptr_array_index(crs_range_set
.mem_64bit_ranges
, i
);
1486 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1488 AML_CACHEABLE
, AML_READ_WRITE
,
1489 0, entry
->base
, entry
->limit
,
1490 0, entry
->limit
- entry
->base
+ 1));
1494 if (TPM_IS_TIS_ISA(tpm_find())) {
1495 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
1496 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
1498 aml_append(scope
, aml_name_decl("_CRS", crs
));
1500 /* reserve GPE0 block resources */
1501 dev
= aml_device("GPE0");
1502 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
1503 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
1504 /* device present, functioning, decoding, not shown in UI */
1505 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1506 crs
= aml_resource_template();
1510 pm
->fadt
.gpe0_blk
.address
,
1511 pm
->fadt
.gpe0_blk
.address
,
1513 pm
->fadt
.gpe0_blk
.bit_width
/ 8)
1515 aml_append(dev
, aml_name_decl("_CRS", crs
));
1516 aml_append(scope
, dev
);
1518 crs_range_set_free(&crs_range_set
);
1520 /* reserve PCIHP resources */
1521 if (pm
->pcihp_io_len
&& (pm
->pcihp_bridge_en
|| pm
->pcihp_root_en
)) {
1522 dev
= aml_device("PHPR");
1523 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
1525 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1526 /* device present, functioning, decoding, not shown in UI */
1527 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1528 crs
= aml_resource_template();
1530 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
1533 aml_append(dev
, aml_name_decl("_CRS", crs
));
1534 aml_append(scope
, dev
);
1536 aml_append(dsdt
, scope
);
1538 /* create S3_ / S4_ / S5_ packages if necessary */
1539 scope
= aml_scope("\\");
1540 if (!pm
->s3_disabled
) {
1541 pkg
= aml_package(4);
1542 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1543 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1544 aml_append(pkg
, aml_int(0)); /* reserved */
1545 aml_append(pkg
, aml_int(0)); /* reserved */
1546 aml_append(scope
, aml_name_decl("_S3", pkg
));
1549 if (!pm
->s4_disabled
) {
1550 pkg
= aml_package(4);
1551 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
1552 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1553 aml_append(pkg
, aml_int(pm
->s4_val
));
1554 aml_append(pkg
, aml_int(0)); /* reserved */
1555 aml_append(pkg
, aml_int(0)); /* reserved */
1556 aml_append(scope
, aml_name_decl("_S4", pkg
));
1559 pkg
= aml_package(4);
1560 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1561 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1562 aml_append(pkg
, aml_int(0)); /* reserved */
1563 aml_append(pkg
, aml_int(0)); /* reserved */
1564 aml_append(scope
, aml_name_decl("_S5", pkg
));
1565 aml_append(dsdt
, scope
);
1567 /* create fw_cfg node, unconditionally */
1569 scope
= aml_scope("\\_SB.PCI0");
1570 fw_cfg_add_acpi_dsdt(scope
, x86ms
->fw_cfg
);
1571 aml_append(dsdt
, scope
);
1574 if (misc
->applesmc_io_base
) {
1575 scope
= aml_scope("\\_SB.PCI0.ISA");
1576 dev
= aml_device("SMC");
1578 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
1579 /* device present, functioning, decoding, not shown in UI */
1580 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1582 crs
= aml_resource_template();
1584 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
1585 0x01, APPLESMC_MAX_DATA_LENGTH
)
1587 aml_append(crs
, aml_irq_no_flags(6));
1588 aml_append(dev
, aml_name_decl("_CRS", crs
));
1590 aml_append(scope
, dev
);
1591 aml_append(dsdt
, scope
);
1594 if (misc
->pvpanic_port
) {
1595 scope
= aml_scope("\\_SB.PCI0.ISA");
1597 dev
= aml_device("PEVT");
1598 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
1600 crs
= aml_resource_template();
1602 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
1604 aml_append(dev
, aml_name_decl("_CRS", crs
));
1606 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
1607 aml_int(misc
->pvpanic_port
), 1));
1608 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1609 aml_append(field
, aml_named_field("PEPT", 8));
1610 aml_append(dev
, field
);
1612 /* device present, functioning, decoding, shown in UI */
1613 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
1615 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
1616 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
1617 aml_append(method
, aml_return(aml_local(0)));
1618 aml_append(dev
, method
);
1620 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
1621 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
1622 aml_append(dev
, method
);
1624 aml_append(scope
, dev
);
1625 aml_append(dsdt
, scope
);
1628 sb_scope
= aml_scope("\\_SB");
1633 pci_host
= acpi_get_i386_pci_host();
1635 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
1639 Aml
*scope
= aml_scope("PCI0");
1640 /* Scan all PCI buses. Generate tables to support hotplug. */
1641 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
1643 if (TPM_IS_TIS_ISA(tpm
)) {
1644 if (misc
->tpm_version
== TPM_VERSION_2_0
) {
1645 dev
= aml_device("TPM");
1646 aml_append(dev
, aml_name_decl("_HID",
1647 aml_string("MSFT0101")));
1649 dev
= aml_device("ISA.TPM");
1650 aml_append(dev
, aml_name_decl("_HID",
1651 aml_eisaid("PNP0C31")));
1654 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
1655 crs
= aml_resource_template();
1656 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
1657 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
1659 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
1660 Rewrite to take IRQ from TPM device model and
1661 fix default IRQ value there to use some unused IRQ
1663 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
1664 aml_append(dev
, aml_name_decl("_CRS", crs
));
1666 tpm_build_ppi_acpi(tpm
, dev
);
1668 aml_append(scope
, dev
);
1671 aml_append(sb_scope
, scope
);
1675 if (TPM_IS_CRB(tpm
)) {
1676 dev
= aml_device("TPM");
1677 aml_append(dev
, aml_name_decl("_HID", aml_string("MSFT0101")));
1678 crs
= aml_resource_template();
1679 aml_append(crs
, aml_memory32_fixed(TPM_CRB_ADDR_BASE
,
1680 TPM_CRB_ADDR_SIZE
, AML_READ_WRITE
));
1681 aml_append(dev
, aml_name_decl("_CRS", crs
));
1683 aml_append(dev
, aml_name_decl("_STA", aml_int(0xf)));
1685 tpm_build_ppi_acpi(tpm
, dev
);
1687 aml_append(sb_scope
, dev
);
1690 aml_append(dsdt
, sb_scope
);
1692 /* copy AML table into ACPI tables blob and patch header there */
1693 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
1694 build_header(linker
, table_data
,
1695 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
1696 "DSDT", dsdt
->buf
->len
, 1, pcms
->oem_id
, pcms
->oem_table_id
);
1697 free_aml_allocator();
1701 build_hpet(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
1702 const char *oem_table_id
)
1706 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
1707 /* Note timer_block_id value must be kept in sync with value advertised by
1710 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
1711 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
1712 build_header(linker
, table_data
,
1713 (void *)hpet
, "HPET", sizeof(*hpet
), 1, oem_id
, oem_table_id
);
1717 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
,
1718 const char *oem_id
, const char *oem_table_id
)
1720 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
1721 unsigned log_addr_size
= sizeof(tcpa
->log_area_start_address
);
1722 unsigned log_addr_offset
=
1723 (char *)&tcpa
->log_area_start_address
- table_data
->data
;
1725 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
1726 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
1727 acpi_data_push(tcpalog
, le32_to_cpu(tcpa
->log_area_minimum_length
));
1729 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
1730 false /* high memory */);
1732 /* log area start address to be filled by Guest linker */
1733 bios_linker_loader_add_pointer(linker
,
1734 ACPI_BUILD_TABLE_FILE
, log_addr_offset
, log_addr_size
,
1735 ACPI_BUILD_TPMLOG_FILE
, 0);
1737 build_header(linker
, table_data
,
1738 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, oem_id
, oem_table_id
);
1741 #define HOLE_640K_START (640 * KiB)
1742 #define HOLE_640K_END (1 * MiB)
1745 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
1747 AcpiSystemResourceAffinityTable
*srat
;
1748 AcpiSratMemoryAffinity
*numamem
;
1751 int srat_start
, numa_start
, slots
;
1752 uint64_t mem_len
, mem_base
, next_base
;
1753 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1754 X86MachineState
*x86ms
= X86_MACHINE(machine
);
1755 const CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
1756 PCMachineState
*pcms
= PC_MACHINE(machine
);
1757 ram_addr_t hotplugabble_address_space_size
=
1758 object_property_get_int(OBJECT(pcms
), PC_MACHINE_DEVMEM_REGION_SIZE
,
1761 srat_start
= table_data
->len
;
1763 srat
= acpi_data_push(table_data
, sizeof *srat
);
1764 srat
->reserved1
= cpu_to_le32(1);
1766 for (i
= 0; i
< apic_ids
->len
; i
++) {
1767 int node_id
= apic_ids
->cpus
[i
].props
.node_id
;
1768 uint32_t apic_id
= apic_ids
->cpus
[i
].arch_id
;
1770 if (apic_id
< 255) {
1771 AcpiSratProcessorAffinity
*core
;
1773 core
= acpi_data_push(table_data
, sizeof *core
);
1774 core
->type
= ACPI_SRAT_PROCESSOR_APIC
;
1775 core
->length
= sizeof(*core
);
1776 core
->local_apic_id
= apic_id
;
1777 core
->proximity_lo
= node_id
;
1778 memset(core
->proximity_hi
, 0, 3);
1779 core
->local_sapic_eid
= 0;
1780 core
->flags
= cpu_to_le32(1);
1782 AcpiSratProcessorX2ApicAffinity
*core
;
1784 core
= acpi_data_push(table_data
, sizeof *core
);
1785 core
->type
= ACPI_SRAT_PROCESSOR_x2APIC
;
1786 core
->length
= sizeof(*core
);
1787 core
->x2apic_id
= cpu_to_le32(apic_id
);
1788 core
->proximity_domain
= cpu_to_le32(node_id
);
1789 core
->flags
= cpu_to_le32(1);
1794 /* the memory map is a bit tricky, it contains at least one hole
1795 * from 640k-1M and possibly another one from 3.5G-4G.
1798 numa_start
= table_data
->len
;
1800 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
1801 mem_base
= next_base
;
1802 mem_len
= pcms
->node_mem
[i
- 1];
1803 next_base
= mem_base
+ mem_len
;
1805 /* Cut out the 640K hole */
1806 if (mem_base
<= HOLE_640K_START
&&
1807 next_base
> HOLE_640K_START
) {
1808 mem_len
-= next_base
- HOLE_640K_START
;
1810 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1811 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1812 MEM_AFFINITY_ENABLED
);
1815 /* Check for the rare case: 640K < RAM < 1M */
1816 if (next_base
<= HOLE_640K_END
) {
1817 next_base
= HOLE_640K_END
;
1820 mem_base
= HOLE_640K_END
;
1821 mem_len
= next_base
- HOLE_640K_END
;
1824 /* Cut out the ACPI_PCI hole */
1825 if (mem_base
<= x86ms
->below_4g_mem_size
&&
1826 next_base
> x86ms
->below_4g_mem_size
) {
1827 mem_len
-= next_base
- x86ms
->below_4g_mem_size
;
1829 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1830 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1831 MEM_AFFINITY_ENABLED
);
1833 mem_base
= 1ULL << 32;
1834 mem_len
= next_base
- x86ms
->below_4g_mem_size
;
1835 next_base
= mem_base
+ mem_len
;
1839 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1840 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1841 MEM_AFFINITY_ENABLED
);
1845 if (machine
->nvdimms_state
->is_enabled
) {
1846 nvdimm_build_srat(table_data
);
1849 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
1850 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
1851 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1852 build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
1856 * Entry is required for Windows to enable memory hotplug in OS
1857 * and for Linux to enable SWIOTLB when booted with less than
1858 * 4G of RAM. Windows works better if the entry sets proximity
1859 * to the highest NUMA node in the machine.
1860 * Memory devices may override proximity set by this entry,
1861 * providing _PXM method if necessary.
1863 if (hotplugabble_address_space_size
) {
1864 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1865 build_srat_memory(numamem
, machine
->device_memory
->base
,
1866 hotplugabble_address_space_size
, pcms
->numa_nodes
- 1,
1867 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
1870 build_header(linker
, table_data
,
1871 (void *)(table_data
->data
+ srat_start
),
1873 table_data
->len
- srat_start
, 1, pcms
->oem_id
,
1874 pcms
->oem_table_id
);
1878 * VT-d spec 8.1 DMA Remapping Reporting Structure
1879 * (version Oct. 2014 or later)
1882 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
1883 const char *oem_table_id
)
1885 int dmar_start
= table_data
->len
;
1887 AcpiTableDmar
*dmar
;
1888 AcpiDmarHardwareUnit
*drhd
;
1889 AcpiDmarRootPortATS
*atsr
;
1890 uint8_t dmar_flags
= 0;
1891 X86IOMMUState
*iommu
= x86_iommu_get_default();
1892 AcpiDmarDeviceScope
*scope
= NULL
;
1893 /* Root complex IOAPIC use one path[0] only */
1894 size_t ioapic_scope_size
= sizeof(*scope
) + sizeof(scope
->path
[0]);
1895 IntelIOMMUState
*intel_iommu
= INTEL_IOMMU_DEVICE(iommu
);
1898 if (x86_iommu_ir_supported(iommu
)) {
1899 dmar_flags
|= 0x1; /* Flags: 0x1: INT_REMAP */
1902 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
1903 dmar
->host_address_width
= intel_iommu
->aw_bits
- 1;
1904 dmar
->flags
= dmar_flags
;
1906 /* DMAR Remapping Hardware Unit Definition structure */
1907 drhd
= acpi_data_push(table_data
, sizeof(*drhd
) + ioapic_scope_size
);
1908 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
1909 drhd
->length
= cpu_to_le16(sizeof(*drhd
) + ioapic_scope_size
);
1910 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
1911 drhd
->pci_segment
= cpu_to_le16(0);
1912 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
1914 /* Scope definition for the root-complex IOAPIC. See VT-d spec
1915 * 8.3.1 (version Oct. 2014 or later). */
1916 scope
= &drhd
->scope
[0];
1917 scope
->entry_type
= 0x03; /* Type: 0x03 for IOAPIC */
1918 scope
->length
= ioapic_scope_size
;
1919 scope
->enumeration_id
= ACPI_BUILD_IOAPIC_ID
;
1920 scope
->bus
= Q35_PSEUDO_BUS_PLATFORM
;
1921 scope
->path
[0].device
= PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC
);
1922 scope
->path
[0].function
= PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC
);
1924 if (iommu
->dt_supported
) {
1925 atsr
= acpi_data_push(table_data
, sizeof(*atsr
));
1926 atsr
->type
= cpu_to_le16(ACPI_DMAR_TYPE_ATSR
);
1927 atsr
->length
= cpu_to_le16(sizeof(*atsr
));
1928 atsr
->flags
= ACPI_DMAR_ATSR_ALL_PORTS
;
1929 atsr
->pci_segment
= cpu_to_le16(0);
1932 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
1933 "DMAR", table_data
->len
- dmar_start
, 1, oem_id
, oem_table_id
);
1937 * Windows ACPI Emulated Devices Table
1938 * (Version 1.0 - April 6, 2009)
1939 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
1941 * Helpful to speedup Windows guests and ignored by others.
1944 build_waet(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
1945 const char *oem_table_id
)
1947 int waet_start
= table_data
->len
;
1950 acpi_data_push(table_data
, sizeof(AcpiTableHeader
));
1952 * Set "ACPI PM timer good" flag.
1954 * Tells Windows guests that our ACPI PM timer is reliable in the
1955 * sense that guest can read it only once to obtain a reliable value.
1956 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
1958 build_append_int_noprefix(table_data
, 1 << 1 /* ACPI PM timer good */, 4);
1960 build_header(linker
, table_data
, (void *)(table_data
->data
+ waet_start
),
1961 "WAET", table_data
->len
- waet_start
, 1, oem_id
, oem_table_id
);
1965 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
1966 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
1968 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
1971 * Insert IVHD entry for device and recurse, insert alias, or insert range as
1972 * necessary for the PCI topology.
1975 insert_ivhd(PCIBus
*bus
, PCIDevice
*dev
, void *opaque
)
1977 GArray
*table_data
= opaque
;
1980 /* "Select" IVHD entry, type 0x2 */
1981 entry
= PCI_BUILD_BDF(pci_bus_num(bus
), dev
->devfn
) << 8 | 0x2;
1982 build_append_int_noprefix(table_data
, entry
, 4);
1984 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_BRIDGE
)) {
1985 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
));
1986 uint8_t sec
= pci_bus_num(sec_bus
);
1987 uint8_t sub
= dev
->config
[PCI_SUBORDINATE_BUS
];
1989 if (pci_bus_is_express(sec_bus
)) {
1991 * Walk the bus if there are subordinates, otherwise use a range
1992 * to cover an entire leaf bus. We could potentially also use a
1993 * range for traversed buses, but we'd need to take care not to
1994 * create both Select and Range entries covering the same device.
1995 * This is easier and potentially more compact.
1997 * An example bare metal system seems to use Select entries for
1998 * root ports without a slot (ie. built-ins) and Range entries
1999 * when there is a slot. The same system also only hard-codes
2000 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2001 * making no effort to support nested bridges. We attempt to
2002 * be more thorough here.
2004 if (sec
== sub
) { /* leaf bus */
2005 /* "Start of Range" IVHD entry, type 0x3 */
2006 entry
= PCI_BUILD_BDF(sec
, PCI_DEVFN(0, 0)) << 8 | 0x3;
2007 build_append_int_noprefix(table_data
, entry
, 4);
2008 /* "End of Range" IVHD entry, type 0x4 */
2009 entry
= PCI_BUILD_BDF(sub
, PCI_DEVFN(31, 7)) << 8 | 0x4;
2010 build_append_int_noprefix(table_data
, entry
, 4);
2012 pci_for_each_device(sec_bus
, sec
, insert_ivhd
, table_data
);
2016 * If the secondary bus is conventional, then we need to create an
2017 * Alias range for everything downstream. The range covers the
2018 * first devfn on the secondary bus to the last devfn on the
2019 * subordinate bus. The alias target depends on legacy versus
2020 * express bridges, just as in pci_device_iommu_address_space().
2021 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2023 uint16_t dev_id_a
, dev_id_b
;
2025 dev_id_a
= PCI_BUILD_BDF(sec
, PCI_DEVFN(0, 0));
2027 if (pci_is_express(dev
) &&
2028 pcie_cap_get_type(dev
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
2029 dev_id_b
= dev_id_a
;
2031 dev_id_b
= PCI_BUILD_BDF(pci_bus_num(bus
), dev
->devfn
);
2034 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2035 build_append_int_noprefix(table_data
, dev_id_a
<< 8 | 0x43, 4);
2036 build_append_int_noprefix(table_data
, dev_id_b
<< 8 | 0x0, 4);
2038 /* "End of Range" IVHD entry, type 0x4 */
2039 entry
= PCI_BUILD_BDF(sub
, PCI_DEVFN(31, 7)) << 8 | 0x4;
2040 build_append_int_noprefix(table_data
, entry
, 4);
2045 /* For all PCI host bridges, walk and insert IVHD entries */
2047 ivrs_host_bridges(Object
*obj
, void *opaque
)
2049 GArray
*ivhd_blob
= opaque
;
2051 if (object_dynamic_cast(obj
, TYPE_PCI_HOST_BRIDGE
)) {
2052 PCIBus
*bus
= PCI_HOST_BRIDGE(obj
)->bus
;
2055 pci_for_each_device(bus
, pci_bus_num(bus
), insert_ivhd
, ivhd_blob
);
2063 build_amd_iommu(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
2064 const char *oem_table_id
)
2066 int ivhd_table_len
= 24;
2067 int iommu_start
= table_data
->len
;
2068 AMDVIState
*s
= AMD_IOMMU_DEVICE(x86_iommu_get_default());
2069 GArray
*ivhd_blob
= g_array_new(false, true, 1);
2072 acpi_data_push(table_data
, sizeof(AcpiTableHeader
));
2073 /* IVinfo - IO virtualization information common to all
2074 * IOMMU units in a system
2076 build_append_int_noprefix(table_data
, 40UL << 8/* PASize */, 4);
2078 build_append_int_noprefix(table_data
, 0, 8);
2080 /* IVHD definition - type 10h */
2081 build_append_int_noprefix(table_data
, 0x10, 1);
2082 /* virtualization flags */
2083 build_append_int_noprefix(table_data
,
2084 (1UL << 0) | /* HtTunEn */
2085 (1UL << 4) | /* iotblSup */
2086 (1UL << 6) | /* PrefSup */
2087 (1UL << 7), /* PPRSup */
2091 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2092 * complete set of IVHD entries. Do this into a separate blob so that we
2093 * can calculate the total IVRS table length here and then append the new
2094 * blob further below. Fall back to an entry covering all devices, which
2095 * is sufficient when no aliases are present.
2097 object_child_foreach_recursive(object_get_root(),
2098 ivrs_host_bridges
, ivhd_blob
);
2100 if (!ivhd_blob
->len
) {
2102 * Type 1 device entry reporting all devices
2103 * These are 4-byte device entries currently reporting the range of
2104 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2106 build_append_int_noprefix(ivhd_blob
, 0x0000001, 4);
2109 ivhd_table_len
+= ivhd_blob
->len
;
2112 * When interrupt remapping is supported, we add a special IVHD device
2115 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2116 ivhd_table_len
+= 8;
2120 build_append_int_noprefix(table_data
, ivhd_table_len
, 2);
2122 build_append_int_noprefix(table_data
, s
->devid
, 2);
2123 /* Capability offset */
2124 build_append_int_noprefix(table_data
, s
->capab_offset
, 2);
2125 /* IOMMU base address */
2126 build_append_int_noprefix(table_data
, s
->mmio
.addr
, 8);
2127 /* PCI Segment Group */
2128 build_append_int_noprefix(table_data
, 0, 2);
2130 build_append_int_noprefix(table_data
, 0, 2);
2131 /* IOMMU Feature Reporting */
2132 build_append_int_noprefix(table_data
,
2133 (48UL << 30) | /* HATS */
2134 (48UL << 28) | /* GATS */
2135 (1UL << 2) | /* GTSup */
2136 (1UL << 6), /* GASup */
2139 /* IVHD entries as found above */
2140 g_array_append_vals(table_data
, ivhd_blob
->data
, ivhd_blob
->len
);
2141 g_array_free(ivhd_blob
, TRUE
);
2144 * Add a special IVHD device type.
2145 * Refer to spec - Table 95: IVHD device entry type codes
2147 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2148 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2150 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2151 build_append_int_noprefix(table_data
,
2152 (0x1ull
<< 56) | /* type IOAPIC */
2153 (IOAPIC_SB_DEVID
<< 40) | /* IOAPIC devid */
2154 0x48, /* special device */
2158 build_header(linker
, table_data
, (void *)(table_data
->data
+ iommu_start
),
2159 "IVRS", table_data
->len
- iommu_start
, 1, oem_id
,
2164 struct AcpiBuildState
{
2165 /* Copy of table in RAM (for patching). */
2166 MemoryRegion
*table_mr
;
2167 /* Is table patched? */
2170 MemoryRegion
*rsdp_mr
;
2171 MemoryRegion
*linker_mr
;
2174 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2179 pci_host
= acpi_get_i386_pci_host();
2182 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2186 mcfg
->base
= qnum_get_uint(qobject_to(QNum
, o
));
2188 if (mcfg
->base
== PCIE_BASE_ADDR_UNMAPPED
) {
2192 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2194 mcfg
->size
= qnum_get_uint(qobject_to(QNum
, o
));
2200 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2202 PCMachineState
*pcms
= PC_MACHINE(machine
);
2203 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2204 X86MachineState
*x86ms
= X86_MACHINE(machine
);
2205 GArray
*table_offsets
;
2206 unsigned facs
, dsdt
, rsdt
, fadt
;
2210 Range pci_hole
, pci_hole64
;
2213 GArray
*tables_blob
= tables
->table_data
;
2214 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2215 Object
*vmgenid_dev
;
2219 acpi_get_pm_info(machine
, &pm
);
2220 acpi_get_misc_info(&misc
);
2221 acpi_get_pci_holes(&pci_hole
, &pci_hole64
);
2222 acpi_get_slic_oem(&slic_oem
);
2225 oem_id
= slic_oem
.id
;
2227 oem_id
= pcms
->oem_id
;
2230 if (slic_oem
.table_id
) {
2231 oem_table_id
= slic_oem
.table_id
;
2233 oem_table_id
= pcms
->oem_table_id
;
2236 table_offsets
= g_array_new(false, true /* clear */,
2238 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2240 bios_linker_loader_alloc(tables
->linker
,
2241 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2242 64 /* Ensure FACS is aligned */,
2243 false /* high memory */);
2246 * FACS is pointed to by FADT.
2247 * We place it first since it's the only table that has alignment
2250 facs
= tables_blob
->len
;
2251 build_facs(tables_blob
);
2253 /* DSDT is pointed to by FADT */
2254 dsdt
= tables_blob
->len
;
2255 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
,
2256 &pci_hole
, &pci_hole64
, machine
);
2258 /* Count the size of the DSDT and SSDT, we will need it for legacy
2259 * sizing of ACPI tables.
2261 aml_len
+= tables_blob
->len
- dsdt
;
2263 /* ACPI tables pointed to by RSDT */
2264 fadt
= tables_blob
->len
;
2265 acpi_add_table(table_offsets
, tables_blob
);
2266 pm
.fadt
.facs_tbl_offset
= &facs
;
2267 pm
.fadt
.dsdt_tbl_offset
= &dsdt
;
2268 pm
.fadt
.xdsdt_tbl_offset
= &dsdt
;
2269 build_fadt(tables_blob
, tables
->linker
, &pm
.fadt
, oem_id
, oem_table_id
);
2270 aml_len
+= tables_blob
->len
- fadt
;
2272 acpi_add_table(table_offsets
, tables_blob
);
2273 acpi_build_madt(tables_blob
, tables
->linker
, x86ms
,
2274 ACPI_DEVICE_IF(x86ms
->acpi_dev
), pcms
->oem_id
,
2275 pcms
->oem_table_id
);
2277 vmgenid_dev
= find_vmgenid_dev();
2279 acpi_add_table(table_offsets
, tables_blob
);
2280 vmgenid_build_acpi(VMGENID(vmgenid_dev
), tables_blob
,
2281 tables
->vmgenid
, tables
->linker
, pcms
->oem_id
);
2284 if (misc
.has_hpet
) {
2285 acpi_add_table(table_offsets
, tables_blob
);
2286 build_hpet(tables_blob
, tables
->linker
, pcms
->oem_id
,
2287 pcms
->oem_table_id
);
2289 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2290 if (misc
.tpm_version
== TPM_VERSION_1_2
) {
2291 acpi_add_table(table_offsets
, tables_blob
);
2292 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
,
2293 pcms
->oem_id
, pcms
->oem_table_id
);
2294 } else { /* TPM_VERSION_2_0 */
2295 acpi_add_table(table_offsets
, tables_blob
);
2296 build_tpm2(tables_blob
, tables
->linker
, tables
->tcpalog
,
2297 pcms
->oem_id
, pcms
->oem_table_id
);
2300 if (pcms
->numa_nodes
) {
2301 acpi_add_table(table_offsets
, tables_blob
);
2302 build_srat(tables_blob
, tables
->linker
, machine
);
2303 if (machine
->numa_state
->have_numa_distance
) {
2304 acpi_add_table(table_offsets
, tables_blob
);
2305 build_slit(tables_blob
, tables
->linker
, machine
, pcms
->oem_id
,
2306 pcms
->oem_table_id
);
2308 if (machine
->numa_state
->hmat_enabled
) {
2309 acpi_add_table(table_offsets
, tables_blob
);
2310 build_hmat(tables_blob
, tables
->linker
, machine
->numa_state
,
2311 pcms
->oem_id
, pcms
->oem_table_id
);
2314 if (acpi_get_mcfg(&mcfg
)) {
2315 acpi_add_table(table_offsets
, tables_blob
);
2316 build_mcfg(tables_blob
, tables
->linker
, &mcfg
, pcms
->oem_id
,
2317 pcms
->oem_table_id
);
2319 if (x86_iommu_get_default()) {
2320 IommuType IOMMUType
= x86_iommu_get_type();
2321 if (IOMMUType
== TYPE_AMD
) {
2322 acpi_add_table(table_offsets
, tables_blob
);
2323 build_amd_iommu(tables_blob
, tables
->linker
, pcms
->oem_id
,
2324 pcms
->oem_table_id
);
2325 } else if (IOMMUType
== TYPE_INTEL
) {
2326 acpi_add_table(table_offsets
, tables_blob
);
2327 build_dmar_q35(tables_blob
, tables
->linker
, pcms
->oem_id
,
2328 pcms
->oem_table_id
);
2331 if (machine
->nvdimms_state
->is_enabled
) {
2332 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2333 machine
->nvdimms_state
, machine
->ram_slots
,
2334 pcms
->oem_id
, pcms
->oem_table_id
);
2337 acpi_add_table(table_offsets
, tables_blob
);
2338 build_waet(tables_blob
, tables
->linker
, pcms
->oem_id
, pcms
->oem_table_id
);
2340 /* Add tables supplied by user (if any) */
2341 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2342 unsigned len
= acpi_table_len(u
);
2344 acpi_add_table(table_offsets
, tables_blob
);
2345 g_array_append_vals(tables_blob
, u
, len
);
2348 /* RSDT is pointed to by RSDP */
2349 rsdt
= tables_blob
->len
;
2350 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2351 oem_id
, oem_table_id
);
2353 /* RSDP is in FSEG memory, so allocate it separately */
2355 AcpiRsdpData rsdp_data
= {
2357 .oem_id
= pcms
->oem_id
,
2358 .xsdt_tbl_offset
= NULL
,
2359 .rsdt_tbl_offset
= &rsdt
,
2361 build_rsdp(tables
->rsdp
, tables
->linker
, &rsdp_data
);
2362 if (!pcmc
->rsdp_in_ram
) {
2363 /* We used to allocate some extra space for RSDP revision 2 but
2364 * only used the RSDP revision 0 space. The extra bytes were
2365 * zeroed out and not used.
2366 * Here we continue wasting those extra 16 bytes to make sure we
2367 * don't break migration for machine types 2.2 and older due to
2368 * RSDP blob size mismatch.
2370 build_append_int_noprefix(tables
->rsdp
, 0, 16);
2374 /* We'll expose it all to Guest so we want to reduce
2375 * chance of size changes.
2377 * We used to align the tables to 4k, but of course this would
2378 * too simple to be enough. 4k turned out to be too small an
2379 * alignment very soon, and in fact it is almost impossible to
2380 * keep the table size stable for all (max_cpus, max_memory_slots)
2381 * combinations. So the table size is always 64k for pc-i440fx-2.1
2382 * and we give an error if the table grows beyond that limit.
2384 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2385 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2386 * than 2.0 and we can always pad the smaller tables with zeros. We can
2387 * then use the exact size of the 2.0 tables.
2389 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2391 if (pcmc
->legacy_acpi_table_size
) {
2392 /* Subtracting aml_len gives the size of fixed tables. Then add the
2393 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2395 int legacy_aml_len
=
2396 pcmc
->legacy_acpi_table_size
+
2397 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* x86ms
->apic_id_limit
;
2398 int legacy_table_size
=
2399 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2400 ACPI_BUILD_ALIGN_SIZE
);
2401 if (tables_blob
->len
> legacy_table_size
) {
2402 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2403 warn_report("ACPI table size %u exceeds %d bytes,"
2404 " migration may not work",
2405 tables_blob
->len
, legacy_table_size
);
2406 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2407 " or PCI bridges.");
2409 g_array_set_size(tables_blob
, legacy_table_size
);
2411 /* Make sure we have a buffer in case we need to resize the tables. */
2412 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2413 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2414 warn_report("ACPI table size %u exceeds %d bytes,"
2415 " migration may not work",
2416 tables_blob
->len
, ACPI_BUILD_TABLE_SIZE
/ 2);
2417 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2418 " or PCI bridges.");
2420 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2423 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2425 /* Cleanup memory that's no longer used. */
2426 g_array_free(table_offsets
, true);
2429 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2431 uint32_t size
= acpi_data_len(data
);
2433 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2434 memory_region_ram_resize(mr
, size
, &error_abort
);
2436 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2437 memory_region_set_dirty(mr
, 0, size
);
2440 static void acpi_build_update(void *build_opaque
)
2442 AcpiBuildState
*build_state
= build_opaque
;
2443 AcpiBuildTables tables
;
2445 /* No state to update or already patched? Nothing to do. */
2446 if (!build_state
|| build_state
->patched
) {
2449 build_state
->patched
= 1;
2451 acpi_build_tables_init(&tables
);
2453 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2455 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2457 if (build_state
->rsdp
) {
2458 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2460 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2463 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2464 acpi_build_tables_cleanup(&tables
, true);
2467 static void acpi_build_reset(void *build_opaque
)
2469 AcpiBuildState
*build_state
= build_opaque
;
2470 build_state
->patched
= 0;
2473 static const VMStateDescription vmstate_acpi_build
= {
2474 .name
= "acpi_build",
2476 .minimum_version_id
= 1,
2477 .fields
= (VMStateField
[]) {
2478 VMSTATE_UINT8(patched
, AcpiBuildState
),
2479 VMSTATE_END_OF_LIST()
2483 void acpi_setup(void)
2485 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2486 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2487 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
2488 AcpiBuildTables tables
;
2489 AcpiBuildState
*build_state
;
2490 Object
*vmgenid_dev
;
2492 static FwCfgTPMConfig tpm_config
;
2494 if (!x86ms
->fw_cfg
) {
2495 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2499 if (!pcms
->acpi_build_enabled
) {
2500 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2504 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms
))) {
2505 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2509 build_state
= g_malloc0(sizeof *build_state
);
2511 acpi_build_tables_init(&tables
);
2512 acpi_build(&tables
, MACHINE(pcms
));
2514 /* Now expose it all to Guest */
2515 build_state
->table_mr
= acpi_add_rom_blob(acpi_build_update
,
2516 build_state
, tables
.table_data
,
2517 ACPI_BUILD_TABLE_FILE
,
2518 ACPI_BUILD_TABLE_MAX_SIZE
);
2519 assert(build_state
->table_mr
!= NULL
);
2521 build_state
->linker_mr
=
2522 acpi_add_rom_blob(acpi_build_update
, build_state
,
2523 tables
.linker
->cmd_blob
, ACPI_BUILD_LOADER_FILE
, 0);
2525 fw_cfg_add_file(x86ms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2526 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2529 if (tpm
&& object_property_get_bool(OBJECT(tpm
), "ppi", &error_abort
)) {
2530 tpm_config
= (FwCfgTPMConfig
) {
2531 .tpmppi_address
= cpu_to_le32(TPM_PPI_ADDR_BASE
),
2532 .tpm_version
= tpm_get_version(tpm
),
2533 .tpmppi_version
= TPM_PPI_VERSION_1_30
2535 fw_cfg_add_file(x86ms
->fw_cfg
, "etc/tpm/config",
2536 &tpm_config
, sizeof tpm_config
);
2539 vmgenid_dev
= find_vmgenid_dev();
2541 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev
), x86ms
->fw_cfg
,
2545 if (!pcmc
->rsdp_in_ram
) {
2547 * Keep for compatibility with old machine types.
2548 * Though RSDP is small, its contents isn't immutable, so
2549 * we'll update it along with the rest of tables on guest access.
2551 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2553 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2554 fw_cfg_add_file_callback(x86ms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2555 acpi_build_update
, NULL
, build_state
,
2556 build_state
->rsdp
, rsdp_size
, true);
2557 build_state
->rsdp_mr
= NULL
;
2559 build_state
->rsdp
= NULL
;
2560 build_state
->rsdp_mr
= acpi_add_rom_blob(acpi_build_update
,
2561 build_state
, tables
.rsdp
,
2562 ACPI_BUILD_RSDP_FILE
, 0);
2565 qemu_register_reset(acpi_build_reset
, build_state
);
2566 acpi_build_reset(build_state
);
2567 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
2569 /* Cleanup tables but don't free the memory: we track it
2572 acpi_build_tables_cleanup(&tables
, false);