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arm host: Fix linker warning (m68k targets)
[qemu.git] / hw / pci.c
blobeb2043e5003e693d8fe3c3ce7ec6539ae7872372
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "monitor.h"
27 #include "net.h"
28 #include "sysemu.h"
29 #include "loader.h"
30 #include "qemu-objects.h"
31
32 //#define DEBUG_PCI
33 #ifdef DEBUG_PCI
34 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
35 #else
36 # define PCI_DPRINTF(format, ...) do { } while (0)
37 #endif
38
39 struct PCIBus {
40 BusState qbus;
41 int devfn_min;
42 pci_set_irq_fn set_irq;
43 pci_map_irq_fn map_irq;
44 pci_hotplug_fn hotplug;
45 void *irq_opaque;
46 PCIDevice *devices[256];
47 PCIDevice *parent_dev;
48 target_phys_addr_t mem_base;
49
50 QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
51 QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
52
53 /* The bus IRQ state is the logical OR of the connected devices.
54 Keep a count of the number of devices with raised IRQs. */
55 int nirq;
56 int *irq_count;
57 };
58
59 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
60
61 static struct BusInfo pci_bus_info = {
62 .name = "PCI",
63 .size = sizeof(PCIBus),
64 .print_dev = pcibus_dev_print,
65 .props = (Property[]) {
66 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
67 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
68 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
69 DEFINE_PROP_END_OF_LIST()
70 }
71 };
72
73 static void pci_update_mappings(PCIDevice *d);
74 static void pci_set_irq(void *opaque, int irq_num, int level);
75 static int pci_add_option_rom(PCIDevice *pdev);
76
77 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
78 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
79
80 struct PCIHostBus {
81 int domain;
82 struct PCIBus *bus;
83 QLIST_ENTRY(PCIHostBus) next;
84 };
85 static QLIST_HEAD(, PCIHostBus) host_buses;
86
87 static const VMStateDescription vmstate_pcibus = {
88 .name = "PCIBUS",
89 .version_id = 1,
90 .minimum_version_id = 1,
91 .minimum_version_id_old = 1,
92 .fields = (VMStateField []) {
93 VMSTATE_INT32_EQUAL(nirq, PCIBus),
94 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
95 VMSTATE_END_OF_LIST()
96 }
97 };
98
99 static int pci_bar(PCIDevice *d, int reg)
100 {
101 uint8_t type;
102
103 if (reg != PCI_ROM_SLOT)
104 return PCI_BASE_ADDRESS_0 + reg * 4;
105
106 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
107 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
108 }
109
110 static inline int pci_irq_state(PCIDevice *d, int irq_num)
111 {
112 return (d->irq_state >> irq_num) & 0x1;
113 }
114
115 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
116 {
117 d->irq_state &= ~(0x1 << irq_num);
118 d->irq_state |= level << irq_num;
119 }
120
121 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
122 {
123 PCIBus *bus;
124 for (;;) {
125 bus = pci_dev->bus;
126 irq_num = bus->map_irq(pci_dev, irq_num);
127 if (bus->set_irq)
128 break;
129 pci_dev = bus->parent_dev;
130 }
131 bus->irq_count[irq_num] += change;
132 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
133 }
134
135 /* Update interrupt status bit in config space on interrupt
136 * state change. */
137 static void pci_update_irq_status(PCIDevice *dev)
138 {
139 if (dev->irq_state) {
140 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
141 } else {
142 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
143 }
144 }
145
146 static void pci_device_reset(PCIDevice *dev)
147 {
148 int r;
149
150 dev->irq_state = 0;
151 pci_update_irq_status(dev);
152 dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
153 PCI_COMMAND_MASTER);
154 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
155 dev->config[PCI_INTERRUPT_LINE] = 0x0;
156 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
157 if (!dev->io_regions[r].size) {
158 continue;
159 }
160 pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
161 }
162 pci_update_mappings(dev);
163 }
164
165 static void pci_bus_reset(void *opaque)
166 {
167 PCIBus *bus = opaque;
168 int i;
169
170 for (i = 0; i < bus->nirq; i++) {
171 bus->irq_count[i] = 0;
172 }
173 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
174 if (bus->devices[i]) {
175 pci_device_reset(bus->devices[i]);
176 }
177 }
178 }
179
180 static void pci_host_bus_register(int domain, PCIBus *bus)
181 {
182 struct PCIHostBus *host;
183 host = qemu_mallocz(sizeof(*host));
184 host->domain = domain;
185 host->bus = bus;
186 QLIST_INSERT_HEAD(&host_buses, host, next);
187 }
188
189 PCIBus *pci_find_root_bus(int domain)
190 {
191 struct PCIHostBus *host;
192
193 QLIST_FOREACH(host, &host_buses, next) {
194 if (host->domain == domain) {
195 return host->bus;
196 }
197 }
198
199 return NULL;
200 }
201
202 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
203 const char *name, int devfn_min)
204 {
205 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
206 bus->devfn_min = devfn_min;
207
208 /* host bridge */
209 QLIST_INIT(&bus->child);
210 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
211
212 vmstate_register(-1, &vmstate_pcibus, bus);
213 qemu_register_reset(pci_bus_reset, bus);
214 }
215
216 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
217 {
218 PCIBus *bus;
219
220 bus = qemu_mallocz(sizeof(*bus));
221 bus->qbus.qdev_allocated = 1;
222 pci_bus_new_inplace(bus, parent, name, devfn_min);
223 return bus;
224 }
225
226 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
227 void *irq_opaque, int nirq)
228 {
229 bus->set_irq = set_irq;
230 bus->map_irq = map_irq;
231 bus->irq_opaque = irq_opaque;
232 bus->nirq = nirq;
233 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
234 }
235
236 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
237 {
238 bus->qbus.allow_hotplug = 1;
239 bus->hotplug = hotplug;
240 }
241
242 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
243 {
244 bus->mem_base = base;
245 }
246
247 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
248 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
249 void *irq_opaque, int devfn_min, int nirq)
250 {
251 PCIBus *bus;
252
253 bus = pci_bus_new(parent, name, devfn_min);
254 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
255 return bus;
256 }
257
258 static void pci_register_secondary_bus(PCIBus *parent,
259 PCIBus *bus,
260 PCIDevice *dev,
261 pci_map_irq_fn map_irq,
262 const char *name)
263 {
264 qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
265 bus->map_irq = map_irq;
266 bus->parent_dev = dev;
267
268 QLIST_INIT(&bus->child);
269 QLIST_INSERT_HEAD(&parent->child, bus, sibling);
270 }
271
272 static void pci_unregister_secondary_bus(PCIBus *bus)
273 {
274 assert(QLIST_EMPTY(&bus->child));
275 QLIST_REMOVE(bus, sibling);
276 }
277
278 int pci_bus_num(PCIBus *s)
279 {
280 if (!s->parent_dev)
281 return 0; /* pci host bridge */
282 return s->parent_dev->config[PCI_SECONDARY_BUS];
283 }
284
285 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
286 {
287 PCIDevice *s = container_of(pv, PCIDevice, config);
288 uint8_t *config;
289 int i;
290
291 assert(size == pci_config_size(s));
292 config = qemu_malloc(size);
293
294 qemu_get_buffer(f, config, size);
295 for (i = 0; i < size; ++i) {
296 if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
297 qemu_free(config);
298 return -EINVAL;
299 }
300 }
301 memcpy(s->config, config, size);
302
303 pci_update_mappings(s);
304
305 qemu_free(config);
306 return 0;
307 }
308
309 /* just put buffer */
310 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
311 {
312 const uint8_t **v = pv;
313 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
314 qemu_put_buffer(f, *v, size);
315 }
316
317 static VMStateInfo vmstate_info_pci_config = {
318 .name = "pci config",
319 .get = get_pci_config_device,
320 .put = put_pci_config_device,
321 };
322
323 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
324 {
325 PCIDevice *s = container_of(pv, PCIDevice, config);
326 uint32_t irq_state[PCI_NUM_PINS];
327 int i;
328 for (i = 0; i < PCI_NUM_PINS; ++i) {
329 irq_state[i] = qemu_get_be32(f);
330 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
331 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
332 irq_state[i]);
333 return -EINVAL;
334 }
335 }
336
337 for (i = 0; i < PCI_NUM_PINS; ++i) {
338 pci_set_irq_state(s, i, irq_state[i]);
339 }
340
341 return 0;
342 }
343
344 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
345 {
346 int i;
347 PCIDevice *s = container_of(pv, PCIDevice, config);
348
349 for (i = 0; i < PCI_NUM_PINS; ++i) {
350 qemu_put_be32(f, pci_irq_state(s, i));
351 }
352 }
353
354 static VMStateInfo vmstate_info_pci_irq_state = {
355 .name = "pci irq state",
356 .get = get_pci_irq_state,
357 .put = put_pci_irq_state,
358 };
359
360 const VMStateDescription vmstate_pci_device = {
361 .name = "PCIDevice",
362 .version_id = 2,
363 .minimum_version_id = 1,
364 .minimum_version_id_old = 1,
365 .fields = (VMStateField []) {
366 VMSTATE_INT32_LE(version_id, PCIDevice),
367 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
368 vmstate_info_pci_config,
369 PCI_CONFIG_SPACE_SIZE),
370 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
371 vmstate_info_pci_irq_state,
372 PCI_NUM_PINS * sizeof(int32_t)),
373 VMSTATE_END_OF_LIST()
374 }
375 };
376
377 const VMStateDescription vmstate_pcie_device = {
378 .name = "PCIDevice",
379 .version_id = 2,
380 .minimum_version_id = 1,
381 .minimum_version_id_old = 1,
382 .fields = (VMStateField []) {
383 VMSTATE_INT32_LE(version_id, PCIDevice),
384 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
385 vmstate_info_pci_config,
386 PCIE_CONFIG_SPACE_SIZE),
387 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
388 vmstate_info_pci_irq_state,
389 PCI_NUM_PINS * sizeof(int32_t)),
390 VMSTATE_END_OF_LIST()
391 }
392 };
393
394 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
395 {
396 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
397 }
398
399 void pci_device_save(PCIDevice *s, QEMUFile *f)
400 {
401 /* Clear interrupt status bit: it is implicit
402 * in irq_state which we are saving.
403 * This makes us compatible with old devices
404 * which never set or clear this bit. */
405 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
406 vmstate_save_state(f, pci_get_vmstate(s), s);
407 /* Restore the interrupt status bit. */
408 pci_update_irq_status(s);
409 }
410
411 int pci_device_load(PCIDevice *s, QEMUFile *f)
412 {
413 int ret;
414 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
415 /* Restore the interrupt status bit. */
416 pci_update_irq_status(s);
417 return ret;
418 }
419
420 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
421 {
422 uint16_t *id;
423
424 id = (void*)(&pci_dev->config[PCI_SUBSYSTEM_VENDOR_ID]);
425 id[0] = cpu_to_le16(pci_default_sub_vendor_id);
426 id[1] = cpu_to_le16(pci_default_sub_device_id);
427 return 0;
428 }
429
430 /*
431 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
432 */
433 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
434 {
435 const char *p;
436 char *e;
437 unsigned long val;
438 unsigned long dom = 0, bus = 0;
439 unsigned slot = 0;
440
441 p = addr;
442 val = strtoul(p, &e, 16);
443 if (e == p)
444 return -1;
445 if (*e == ':') {
446 bus = val;
447 p = e + 1;
448 val = strtoul(p, &e, 16);
449 if (e == p)
450 return -1;
451 if (*e == ':') {
452 dom = bus;
453 bus = val;
454 p = e + 1;
455 val = strtoul(p, &e, 16);
456 if (e == p)
457 return -1;
458 }
459 }
460
461 if (dom > 0xffff || bus > 0xff || val > 0x1f)
462 return -1;
463
464 slot = val;
465
466 if (*e)
467 return -1;
468
469 /* Note: QEMU doesn't implement domains other than 0 */
470 if (!pci_find_bus(pci_find_root_bus(dom), bus))
471 return -1;
472
473 *domp = dom;
474 *busp = bus;
475 *slotp = slot;
476 return 0;
477 }
478
479 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
480 unsigned *slotp)
481 {
482 /* strip legacy tag */
483 if (!strncmp(addr, "pci_addr=", 9)) {
484 addr += 9;
485 }
486 if (pci_parse_devaddr(addr, domp, busp, slotp)) {
487 monitor_printf(mon, "Invalid pci address\n");
488 return -1;
489 }
490 return 0;
491 }
492
493 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
494 {
495 int dom, bus;
496 unsigned slot;
497
498 if (!devaddr) {
499 *devfnp = -1;
500 return pci_find_bus(pci_find_root_bus(0), 0);
501 }
502
503 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
504 return NULL;
505 }
506
507 *devfnp = slot << 3;
508 return pci_find_bus(pci_find_root_bus(0), bus);
509 }
510
511 static void pci_init_cmask(PCIDevice *dev)
512 {
513 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
514 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
515 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
516 dev->cmask[PCI_REVISION_ID] = 0xff;
517 dev->cmask[PCI_CLASS_PROG] = 0xff;
518 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
519 dev->cmask[PCI_HEADER_TYPE] = 0xff;
520 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
521 }
522
523 static void pci_init_wmask(PCIDevice *dev)
524 {
525 int config_size = pci_config_size(dev);
526
527 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
528 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
529 pci_set_word(dev->wmask + PCI_COMMAND,
530 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
531 PCI_COMMAND_INTX_DISABLE);
532
533 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
534 config_size - PCI_CONFIG_HEADER_SIZE);
535 }
536
537 static void pci_init_wmask_bridge(PCIDevice *d)
538 {
539 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
540 PCI_SEC_LETENCY_TIMER */
541 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
542
543 /* base and limit */
544 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
545 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
546 pci_set_word(d->wmask + PCI_MEMORY_BASE,
547 PCI_MEMORY_RANGE_MASK & 0xffff);
548 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
549 PCI_MEMORY_RANGE_MASK & 0xffff);
550 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
551 PCI_PREF_RANGE_MASK & 0xffff);
552 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
553 PCI_PREF_RANGE_MASK & 0xffff);
554
555 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
556 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
557
558 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
559 }
560
561 static void pci_config_alloc(PCIDevice *pci_dev)
562 {
563 int config_size = pci_config_size(pci_dev);
564
565 pci_dev->config = qemu_mallocz(config_size);
566 pci_dev->cmask = qemu_mallocz(config_size);
567 pci_dev->wmask = qemu_mallocz(config_size);
568 pci_dev->used = qemu_mallocz(config_size);
569 }
570
571 static void pci_config_free(PCIDevice *pci_dev)
572 {
573 qemu_free(pci_dev->config);
574 qemu_free(pci_dev->cmask);
575 qemu_free(pci_dev->wmask);
576 qemu_free(pci_dev->used);
577 }
578
579 /* -1 for devfn means auto assign */
580 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
581 const char *name, int devfn,
582 PCIConfigReadFunc *config_read,
583 PCIConfigWriteFunc *config_write,
584 uint8_t header_type)
585 {
586 if (devfn < 0) {
587 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
588 devfn += 8) {
589 if (!bus->devices[devfn])
590 goto found;
591 }
592 qemu_error("PCI: no devfn available for %s, all in use\n", name);
593 return NULL;
594 found: ;
595 } else if (bus->devices[devfn]) {
596 qemu_error("PCI: devfn %d not available for %s, in use by %s\n", devfn,
597 name, bus->devices[devfn]->name);
598 return NULL;
599 }
600 pci_dev->bus = bus;
601 pci_dev->devfn = devfn;
602 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
603 pci_dev->irq_state = 0;
604 pci_config_alloc(pci_dev);
605
606 header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
607 if (header_type == PCI_HEADER_TYPE_NORMAL) {
608 pci_set_default_subsystem_id(pci_dev);
609 }
610 pci_init_cmask(pci_dev);
611 pci_init_wmask(pci_dev);
612 if (header_type == PCI_HEADER_TYPE_BRIDGE) {
613 pci_init_wmask_bridge(pci_dev);
614 }
615
616 if (!config_read)
617 config_read = pci_default_read_config;
618 if (!config_write)
619 config_write = pci_default_write_config;
620 pci_dev->config_read = config_read;
621 pci_dev->config_write = config_write;
622 bus->devices[devfn] = pci_dev;
623 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
624 pci_dev->version_id = 2; /* Current pci device vmstate version */
625 return pci_dev;
626 }
627
628 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
629 int instance_size, int devfn,
630 PCIConfigReadFunc *config_read,
631 PCIConfigWriteFunc *config_write)
632 {
633 PCIDevice *pci_dev;
634
635 pci_dev = qemu_mallocz(instance_size);
636 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
637 config_read, config_write,
638 PCI_HEADER_TYPE_NORMAL);
639 if (pci_dev == NULL) {
640 hw_error("PCI: can't register device\n");
641 }
642 return pci_dev;
643 }
644
645 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
646 target_phys_addr_t addr)
647 {
648 return addr + bus->mem_base;
649 }
650
651 static void pci_unregister_io_regions(PCIDevice *pci_dev)
652 {
653 PCIIORegion *r;
654 int i;
655
656 for(i = 0; i < PCI_NUM_REGIONS; i++) {
657 r = &pci_dev->io_regions[i];
658 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
659 continue;
660 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
661 isa_unassign_ioport(r->addr, r->filtered_size);
662 } else {
663 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
664 r->addr),
665 r->filtered_size,
666 IO_MEM_UNASSIGNED);
667 }
668 }
669 }
670
671 static int pci_unregister_device(DeviceState *dev)
672 {
673 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
674 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
675 int ret = 0;
676
677 if (info->exit)
678 ret = info->exit(pci_dev);
679 if (ret)
680 return ret;
681
682 pci_unregister_io_regions(pci_dev);
683
684 qemu_free_irqs(pci_dev->irq);
685 pci_dev->bus->devices[pci_dev->devfn] = NULL;
686 pci_config_free(pci_dev);
687 return 0;
688 }
689
690 void pci_register_bar(PCIDevice *pci_dev, int region_num,
691 pcibus_t size, int type,
692 PCIMapIORegionFunc *map_func)
693 {
694 PCIIORegion *r;
695 uint32_t addr;
696 pcibus_t wmask;
697
698 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
699 return;
700
701 if (size & (size-1)) {
702 fprintf(stderr, "ERROR: PCI region size must be pow2 "
703 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
704 exit(1);
705 }
706
707 r = &pci_dev->io_regions[region_num];
708 r->addr = PCI_BAR_UNMAPPED;
709 r->size = size;
710 r->filtered_size = size;
711 r->type = type;
712 r->map_func = map_func;
713
714 wmask = ~(size - 1);
715 addr = pci_bar(pci_dev, region_num);
716 if (region_num == PCI_ROM_SLOT) {
717 /* ROM enable bit is writeable */
718 wmask |= PCI_ROM_ADDRESS_ENABLE;
719 }
720 pci_set_long(pci_dev->config + addr, type);
721 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
722 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
723 pci_set_quad(pci_dev->wmask + addr, wmask);
724 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
725 } else {
726 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
727 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
728 }
729 }
730
731 static uint32_t pci_config_get_io_base(PCIDevice *d,
732 uint32_t base, uint32_t base_upper16)
733 {
734 uint32_t val;
735
736 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
737 if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
738 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
739 }
740 return val;
741 }
742
743 static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
744 {
745 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
746 << 16;
747 }
748
749 static pcibus_t pci_config_get_pref_base(PCIDevice *d,
750 uint32_t base, uint32_t upper)
751 {
752 pcibus_t tmp;
753 pcibus_t val;
754
755 tmp = (pcibus_t)pci_get_word(d->config + base);
756 val = (tmp & PCI_PREF_RANGE_MASK) << 16;
757 if (tmp & PCI_PREF_RANGE_TYPE_64) {
758 val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
759 }
760 return val;
761 }
762
763 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
764 {
765 pcibus_t base;
766 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
767 base = pci_config_get_io_base(bridge,
768 PCI_IO_BASE, PCI_IO_BASE_UPPER16);
769 } else {
770 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
771 base = pci_config_get_pref_base(
772 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
773 } else {
774 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
775 }
776 }
777
778 return base;
779 }
780
781 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
782 {
783 pcibus_t limit;
784 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
785 limit = pci_config_get_io_base(bridge,
786 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
787 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */
788 } else {
789 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
790 limit = pci_config_get_pref_base(
791 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
792 } else {
793 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
794 }
795 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
796 }
797 return limit;
798 }
799
800 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
801 uint8_t type)
802 {
803 pcibus_t base = *addr;
804 pcibus_t limit = *addr + *size - 1;
805 PCIDevice *br;
806
807 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
808 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
809
810 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
811 if (!(cmd & PCI_COMMAND_IO)) {
812 goto no_map;
813 }
814 } else {
815 if (!(cmd & PCI_COMMAND_MEMORY)) {
816 goto no_map;
817 }
818 }
819
820 base = MAX(base, pci_bridge_get_base(br, type));
821 limit = MIN(limit, pci_bridge_get_limit(br, type));
822 }
823
824 if (base > limit) {
825 goto no_map;
826 }
827 *addr = base;
828 *size = limit - base + 1;
829 return;
830 no_map:
831 *addr = PCI_BAR_UNMAPPED;
832 *size = 0;
833 }
834
835 static pcibus_t pci_bar_address(PCIDevice *d,
836 int reg, uint8_t type, pcibus_t size)
837 {
838 pcibus_t new_addr, last_addr;
839 int bar = pci_bar(d, reg);
840 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
841
842 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
843 if (!(cmd & PCI_COMMAND_IO)) {
844 return PCI_BAR_UNMAPPED;
845 }
846 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
847 last_addr = new_addr + size - 1;
848 /* NOTE: we have only 64K ioports on PC */
849 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
850 return PCI_BAR_UNMAPPED;
851 }
852 return new_addr;
853 }
854
855 if (!(cmd & PCI_COMMAND_MEMORY)) {
856 return PCI_BAR_UNMAPPED;
857 }
858 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
859 new_addr = pci_get_quad(d->config + bar);
860 } else {
861 new_addr = pci_get_long(d->config + bar);
862 }
863 /* the ROM slot has a specific enable bit */
864 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
865 return PCI_BAR_UNMAPPED;
866 }
867 new_addr &= ~(size - 1);
868 last_addr = new_addr + size - 1;
869 /* NOTE: we do not support wrapping */
870 /* XXX: as we cannot support really dynamic
871 mappings, we handle specific values as invalid
872 mappings. */
873 if (last_addr <= new_addr || new_addr == 0 ||
874 last_addr == PCI_BAR_UNMAPPED) {
875 return PCI_BAR_UNMAPPED;
876 }
877
878 /* Now pcibus_t is 64bit.
879 * Check if 32 bit BAR wraps around explicitly.
880 * Without this, PC ide doesn't work well.
881 * TODO: remove this work around.
882 */
883 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
884 return PCI_BAR_UNMAPPED;
885 }
886
887 /*
888 * OS is allowed to set BAR beyond its addressable
889 * bits. For example, 32 bit OS can set 64bit bar
890 * to >4G. Check it. TODO: we might need to support
891 * it in the future for e.g. PAE.
892 */
893 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
894 return PCI_BAR_UNMAPPED;
895 }
896
897 return new_addr;
898 }
899
900 static void pci_update_mappings(PCIDevice *d)
901 {
902 PCIIORegion *r;
903 int i;
904 pcibus_t new_addr, filtered_size;
905
906 for(i = 0; i < PCI_NUM_REGIONS; i++) {
907 r = &d->io_regions[i];
908
909 /* this region isn't registered */
910 if (!r->size)
911 continue;
912
913 new_addr = pci_bar_address(d, i, r->type, r->size);
914
915 /* bridge filtering */
916 filtered_size = r->size;
917 if (new_addr != PCI_BAR_UNMAPPED) {
918 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
919 }
920
921 /* This bar isn't changed */
922 if (new_addr == r->addr && filtered_size == r->filtered_size)
923 continue;
924
925 /* now do the real mapping */
926 if (r->addr != PCI_BAR_UNMAPPED) {
927 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
928 int class;
929 /* NOTE: specific hack for IDE in PC case:
930 only one byte must be mapped. */
931 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
932 if (class == 0x0101 && r->size == 4) {
933 isa_unassign_ioport(r->addr + 2, 1);
934 } else {
935 isa_unassign_ioport(r->addr, r->filtered_size);
936 }
937 } else {
938 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
939 r->filtered_size,
940 IO_MEM_UNASSIGNED);
941 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
942 }
943 }
944 r->addr = new_addr;
945 r->filtered_size = filtered_size;
946 if (r->addr != PCI_BAR_UNMAPPED) {
947 /*
948 * TODO: currently almost all the map funcions assumes
949 * filtered_size == size and addr & ~(size - 1) == addr.
950 * However with bridge filtering, they aren't always true.
951 * Teach them such cases, such that filtered_size < size and
952 * addr & (size - 1) != 0.
953 */
954 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
955 r->map_func(d, i, r->addr, r->filtered_size, r->type);
956 } else {
957 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
958 r->filtered_size, r->type);
959 }
960 }
961 }
962 }
963
964 static inline int pci_irq_disabled(PCIDevice *d)
965 {
966 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
967 }
968
969 /* Called after interrupt disabled field update in config space,
970 * assert/deassert interrupts if necessary.
971 * Gets original interrupt disable bit value (before update). */
972 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
973 {
974 int i, disabled = pci_irq_disabled(d);
975 if (disabled == was_irq_disabled)
976 return;
977 for (i = 0; i < PCI_NUM_PINS; ++i) {
978 int state = pci_irq_state(d, i);
979 pci_change_irq_level(d, i, disabled ? -state : state);
980 }
981 }
982
983 uint32_t pci_default_read_config(PCIDevice *d,
984 uint32_t address, int len)
985 {
986 uint32_t val = 0;
987 assert(len == 1 || len == 2 || len == 4);
988 len = MIN(len, pci_config_size(d) - address);
989 memcpy(&val, d->config + address, len);
990 return le32_to_cpu(val);
991 }
992
993 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
994 {
995 int i, was_irq_disabled = pci_irq_disabled(d);
996 uint32_t config_size = pci_config_size(d);
997
998 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
999 uint8_t wmask = d->wmask[addr + i];
1000 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1001 }
1002 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1003 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1004 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1005 range_covers_byte(addr, l, PCI_COMMAND))
1006 pci_update_mappings(d);
1007
1008 if (range_covers_byte(addr, l, PCI_COMMAND))
1009 pci_update_irq_disabled(d, was_irq_disabled);
1010 }
1011
1012 /***********************************************************/
1013 /* generic PCI irq support */
1014
1015 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1016 static void pci_set_irq(void *opaque, int irq_num, int level)
1017 {
1018 PCIDevice *pci_dev = opaque;
1019 int change;
1020
1021 change = level - pci_irq_state(pci_dev, irq_num);
1022 if (!change)
1023 return;
1024
1025 pci_set_irq_state(pci_dev, irq_num, level);
1026 pci_update_irq_status(pci_dev);
1027 if (pci_irq_disabled(pci_dev))
1028 return;
1029 pci_change_irq_level(pci_dev, irq_num, change);
1030 }
1031
1032 /***********************************************************/
1033 /* monitor info on PCI */
1034
1035 typedef struct {
1036 uint16_t class;
1037 const char *desc;
1038 } pci_class_desc;
1039
1040 static const pci_class_desc pci_class_descriptions[] =
1041 {
1042 { 0x0100, "SCSI controller"},
1043 { 0x0101, "IDE controller"},
1044 { 0x0102, "Floppy controller"},
1045 { 0x0103, "IPI controller"},
1046 { 0x0104, "RAID controller"},
1047 { 0x0106, "SATA controller"},
1048 { 0x0107, "SAS controller"},
1049 { 0x0180, "Storage controller"},
1050 { 0x0200, "Ethernet controller"},
1051 { 0x0201, "Token Ring controller"},
1052 { 0x0202, "FDDI controller"},
1053 { 0x0203, "ATM controller"},
1054 { 0x0280, "Network controller"},
1055 { 0x0300, "VGA controller"},
1056 { 0x0301, "XGA controller"},
1057 { 0x0302, "3D controller"},
1058 { 0x0380, "Display controller"},
1059 { 0x0400, "Video controller"},
1060 { 0x0401, "Audio controller"},
1061 { 0x0402, "Phone"},
1062 { 0x0480, "Multimedia controller"},
1063 { 0x0500, "RAM controller"},
1064 { 0x0501, "Flash controller"},
1065 { 0x0580, "Memory controller"},
1066 { 0x0600, "Host bridge"},
1067 { 0x0601, "ISA bridge"},
1068 { 0x0602, "EISA bridge"},
1069 { 0x0603, "MC bridge"},
1070 { 0x0604, "PCI bridge"},
1071 { 0x0605, "PCMCIA bridge"},
1072 { 0x0606, "NUBUS bridge"},
1073 { 0x0607, "CARDBUS bridge"},
1074 { 0x0608, "RACEWAY bridge"},
1075 { 0x0680, "Bridge"},
1076 { 0x0c03, "USB controller"},
1077 { 0, NULL}
1078 };
1079
1080 static void pci_for_each_device_under_bus(PCIBus *bus,
1081 void (*fn)(PCIBus *b, PCIDevice *d))
1082 {
1083 PCIDevice *d;
1084 int devfn;
1085
1086 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1087 d = bus->devices[devfn];
1088 if (d) {
1089 fn(bus, d);
1090 }
1091 }
1092 }
1093
1094 void pci_for_each_device(PCIBus *bus, int bus_num,
1095 void (*fn)(PCIBus *b, PCIDevice *d))
1096 {
1097 bus = pci_find_bus(bus, bus_num);
1098
1099 if (bus) {
1100 pci_for_each_device_under_bus(bus, fn);
1101 }
1102 }
1103
1104 static void pci_device_print(Monitor *mon, QDict *device)
1105 {
1106 QDict *qdict;
1107 QListEntry *entry;
1108 uint64_t addr, size;
1109
1110 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1111 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1112 qdict_get_int(device, "slot"),
1113 qdict_get_int(device, "function"));
1114 monitor_printf(mon, " ");
1115
1116 qdict = qdict_get_qdict(device, "class_info");
1117 if (qdict_haskey(qdict, "desc")) {
1118 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1119 } else {
1120 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1121 }
1122
1123 qdict = qdict_get_qdict(device, "id");
1124 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1125 qdict_get_int(qdict, "device"),
1126 qdict_get_int(qdict, "vendor"));
1127
1128 if (qdict_haskey(device, "irq")) {
1129 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1130 qdict_get_int(device, "irq"));
1131 }
1132
1133 if (qdict_haskey(device, "pci_bridge")) {
1134 QDict *info;
1135
1136 qdict = qdict_get_qdict(device, "pci_bridge");
1137
1138 info = qdict_get_qdict(qdict, "bus");
1139 monitor_printf(mon, " BUS %" PRId64 ".\n",
1140 qdict_get_int(info, "number"));
1141 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1142 qdict_get_int(info, "secondary"));
1143 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1144 qdict_get_int(info, "subordinate"));
1145
1146 info = qdict_get_qdict(qdict, "io_range");
1147 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1148 qdict_get_int(info, "base"),
1149 qdict_get_int(info, "limit"));
1150
1151 info = qdict_get_qdict(qdict, "memory_range");
1152 monitor_printf(mon,
1153 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1154 qdict_get_int(info, "base"),
1155 qdict_get_int(info, "limit"));
1156
1157 info = qdict_get_qdict(qdict, "prefetchable_range");
1158 monitor_printf(mon, " prefetchable memory range "
1159 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1160 qdict_get_int(info, "base"),
1161 qdict_get_int(info, "limit"));
1162 }
1163
1164 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1165 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1166 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1167
1168 addr = qdict_get_int(qdict, "address");
1169 size = qdict_get_int(qdict, "size");
1170
1171 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1172 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1173 " [0x%04"FMT_PCIBUS"].\n",
1174 addr, addr + size - 1);
1175 } else {
1176 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1177 " [0x%08"FMT_PCIBUS"].\n",
1178 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1179 qdict_get_bool(qdict, "prefetch") ?
1180 " prefetchable" : "", addr, addr + size - 1);
1181 }
1182 }
1183
1184 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1185
1186 if (qdict_haskey(device, "pci_bridge")) {
1187 qdict = qdict_get_qdict(device, "pci_bridge");
1188 if (qdict_haskey(qdict, "devices")) {
1189 QListEntry *dev;
1190 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1191 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1192 }
1193 }
1194 }
1195 }
1196
1197 void do_pci_info_print(Monitor *mon, const QObject *data)
1198 {
1199 QListEntry *bus, *dev;
1200
1201 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1202 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1203 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1204 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1205 }
1206 }
1207 }
1208
1209 static QObject *pci_get_dev_class(const PCIDevice *dev)
1210 {
1211 int class;
1212 const pci_class_desc *desc;
1213
1214 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1215 desc = pci_class_descriptions;
1216 while (desc->desc && class != desc->class)
1217 desc++;
1218
1219 if (desc->desc) {
1220 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1221 desc->desc, class);
1222 } else {
1223 return qobject_from_jsonf("{ 'class': %d }", class);
1224 }
1225 }
1226
1227 static QObject *pci_get_dev_id(const PCIDevice *dev)
1228 {
1229 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1230 pci_get_word(dev->config + PCI_VENDOR_ID),
1231 pci_get_word(dev->config + PCI_DEVICE_ID));
1232 }
1233
1234 static QObject *pci_get_regions_list(const PCIDevice *dev)
1235 {
1236 int i;
1237 QList *regions_list;
1238
1239 regions_list = qlist_new();
1240
1241 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1242 QObject *obj;
1243 const PCIIORegion *r = &dev->io_regions[i];
1244
1245 if (!r->size) {
1246 continue;
1247 }
1248
1249 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1250 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1251 "'address': %" PRId64 ", "
1252 "'size': %" PRId64 " }",
1253 i, r->addr, r->size);
1254 } else {
1255 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1256
1257 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1258 "'mem_type_64': %i, 'prefetch': %i, "
1259 "'address': %" PRId64 ", "
1260 "'size': %" PRId64 " }",
1261 i, mem_type_64,
1262 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1263 r->addr, r->size);
1264 }
1265
1266 qlist_append_obj(regions_list, obj);
1267 }
1268
1269 return QOBJECT(regions_list);
1270 }
1271
1272 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1273
1274 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1275 {
1276 uint8_t type;
1277 QObject *obj;
1278
1279 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1280 " 'qdev_id': %s }",
1281 bus_num,
1282 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1283 pci_get_dev_class(dev), pci_get_dev_id(dev),
1284 pci_get_regions_list(dev),
1285 dev->qdev.id ? dev->qdev.id : "");
1286
1287 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1288 QDict *qdict = qobject_to_qdict(obj);
1289 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1290 }
1291
1292 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1293 if (type == PCI_HEADER_TYPE_BRIDGE) {
1294 QDict *qdict;
1295 QObject *pci_bridge;
1296
1297 pci_bridge = qobject_from_jsonf("{ 'bus': "
1298 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1299 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1300 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1301 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1302 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1303 dev->config[PCI_SUBORDINATE_BUS],
1304 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1305 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1306 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1307 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1308 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1309 PCI_BASE_ADDRESS_MEM_PREFETCH),
1310 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1311 PCI_BASE_ADDRESS_MEM_PREFETCH));
1312
1313 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1314 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1315
1316 if (child_bus) {
1317 qdict = qobject_to_qdict(pci_bridge);
1318 qdict_put_obj(qdict, "devices",
1319 pci_get_devices_list(child_bus,
1320 dev->config[PCI_SECONDARY_BUS]));
1321 }
1322 }
1323 qdict = qobject_to_qdict(obj);
1324 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1325 }
1326
1327 return obj;
1328 }
1329
1330 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1331 {
1332 int devfn;
1333 PCIDevice *dev;
1334 QList *dev_list;
1335
1336 dev_list = qlist_new();
1337
1338 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1339 dev = bus->devices[devfn];
1340 if (dev) {
1341 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1342 }
1343 }
1344
1345 return QOBJECT(dev_list);
1346 }
1347
1348 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1349 {
1350 bus = pci_find_bus(bus, bus_num);
1351 if (bus) {
1352 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1353 bus_num, pci_get_devices_list(bus, bus_num));
1354 }
1355
1356 return NULL;
1357 }
1358
1359 /**
1360 * do_pci_info(): PCI buses and devices information
1361 *
1362 * The returned QObject is a QList of all buses. Each bus is
1363 * represented by a QDict, which has a key with a QList of all
1364 * PCI devices attached to it. Each device is represented by
1365 * a QDict.
1366 *
1367 * The bus QDict contains the following:
1368 *
1369 * - "bus": bus number
1370 * - "devices": a QList of QDicts, each QDict represents a PCI
1371 * device
1372 *
1373 * The PCI device QDict contains the following:
1374 *
1375 * - "bus": identical to the parent's bus number
1376 * - "slot": slot number
1377 * - "function": function number
1378 * - "class_info": a QDict containing:
1379 * - "desc": device class description (optional)
1380 * - "class": device class number
1381 * - "id": a QDict containing:
1382 * - "device": device ID
1383 * - "vendor": vendor ID
1384 * - "irq": device's IRQ if assigned (optional)
1385 * - "qdev_id": qdev id string
1386 * - "pci_bridge": It's a QDict, only present if this device is a
1387 * PCI bridge, contains:
1388 * - "bus": bus number
1389 * - "secondary": secondary bus number
1390 * - "subordinate": subordinate bus number
1391 * - "io_range": a QDict with memory range information
1392 * - "memory_range": a QDict with memory range information
1393 * - "prefetchable_range": a QDict with memory range information
1394 * - "devices": a QList of PCI devices if there's any attached (optional)
1395 * - "regions": a QList of QDicts, each QDict represents a
1396 * memory region of this device
1397 *
1398 * The memory range QDict contains the following:
1399 *
1400 * - "base": base memory address
1401 * - "limit": limit value
1402 *
1403 * The region QDict can be an I/O region or a memory region,
1404 * an I/O region QDict contains the following:
1405 *
1406 * - "type": "io"
1407 * - "bar": BAR number
1408 * - "address": memory address
1409 * - "size": memory size
1410 *
1411 * A memory region QDict contains the following:
1412 *
1413 * - "type": "memory"
1414 * - "bar": BAR number
1415 * - "address": memory address
1416 * - "size": memory size
1417 * - "mem_type_64": true or false
1418 * - "prefetch": true or false
1419 */
1420 void do_pci_info(Monitor *mon, QObject **ret_data)
1421 {
1422 QList *bus_list;
1423 struct PCIHostBus *host;
1424
1425 bus_list = qlist_new();
1426
1427 QLIST_FOREACH(host, &host_buses, next) {
1428 QObject *obj = pci_get_bus_dict(host->bus, 0);
1429 if (obj) {
1430 qlist_append_obj(bus_list, obj);
1431 }
1432 }
1433
1434 *ret_data = QOBJECT(bus_list);
1435 }
1436
1437 static const char * const pci_nic_models[] = {
1438 "ne2k_pci",
1439 "i82551",
1440 "i82557b",
1441 "i82559er",
1442 "rtl8139",
1443 "e1000",
1444 "pcnet",
1445 "virtio",
1446 NULL
1447 };
1448
1449 static const char * const pci_nic_names[] = {
1450 "ne2k_pci",
1451 "i82551",
1452 "i82557b",
1453 "i82559er",
1454 "rtl8139",
1455 "e1000",
1456 "pcnet",
1457 "virtio-net-pci",
1458 NULL
1459 };
1460
1461 /* Initialize a PCI NIC. */
1462 /* FIXME callers should check for failure, but don't */
1463 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1464 const char *default_devaddr)
1465 {
1466 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1467 PCIBus *bus;
1468 int devfn;
1469 PCIDevice *pci_dev;
1470 DeviceState *dev;
1471 int i;
1472
1473 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1474 if (i < 0)
1475 return NULL;
1476
1477 bus = pci_get_bus_devfn(&devfn, devaddr);
1478 if (!bus) {
1479 qemu_error("Invalid PCI device address %s for device %s\n",
1480 devaddr, pci_nic_names[i]);
1481 return NULL;
1482 }
1483
1484 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1485 dev = &pci_dev->qdev;
1486 if (nd->name)
1487 dev->id = qemu_strdup(nd->name);
1488 qdev_set_nic_properties(dev, nd);
1489 if (qdev_init(dev) < 0)
1490 return NULL;
1491 return pci_dev;
1492 }
1493
1494 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1495 const char *default_devaddr)
1496 {
1497 PCIDevice *res;
1498
1499 if (qemu_show_nic_models(nd->model, pci_nic_models))
1500 exit(0);
1501
1502 res = pci_nic_init(nd, default_model, default_devaddr);
1503 if (!res)
1504 exit(1);
1505 return res;
1506 }
1507
1508 typedef struct {
1509 PCIDevice dev;
1510 PCIBus bus;
1511 uint32_t vid;
1512 uint32_t did;
1513 } PCIBridge;
1514
1515
1516 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1517 {
1518 pci_update_mappings(d);
1519 }
1520
1521 static void pci_bridge_update_mappings(PCIBus *b)
1522 {
1523 PCIBus *child;
1524
1525 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1526
1527 QLIST_FOREACH(child, &b->child, sibling) {
1528 pci_bridge_update_mappings(child);
1529 }
1530 }
1531
1532 static void pci_bridge_write_config(PCIDevice *d,
1533 uint32_t address, uint32_t val, int len)
1534 {
1535 pci_default_write_config(d, address, val, len);
1536
1537 if (/* io base/limit */
1538 ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1539
1540 /* memory base/limit, prefetchable base/limit and
1541 io base/limit upper 16 */
1542 ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1543 pci_bridge_update_mappings(d->bus);
1544 }
1545 }
1546
1547 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1548 {
1549 PCIBus *sec, *ret;
1550
1551 if (!bus)
1552 return NULL;
1553
1554 if (pci_bus_num(bus) == bus_num) {
1555 return bus;
1556 }
1557
1558 /* try child bus */
1559 QLIST_FOREACH(sec, &bus->child, sibling) {
1560 if (!bus->parent_dev /* pci host bridge */
1561 || (pci_bus_num(sec) <= bus_num &&
1562 bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS]) ) {
1563 ret = pci_find_bus(sec, bus_num);
1564 if (ret) {
1565 return ret;
1566 }
1567 }
1568 }
1569
1570 return NULL;
1571 }
1572
1573 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1574 {
1575 bus = pci_find_bus(bus, bus_num);
1576
1577 if (!bus)
1578 return NULL;
1579
1580 return bus->devices[PCI_DEVFN(slot, function)];
1581 }
1582
1583 static int pci_bridge_initfn(PCIDevice *dev)
1584 {
1585 PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1586
1587 pci_config_set_vendor_id(s->dev.config, s->vid);
1588 pci_config_set_device_id(s->dev.config, s->did);
1589
1590 pci_set_word(dev->config + PCI_STATUS,
1591 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1592 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1593 dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE;
1594 pci_set_word(dev->config + PCI_SEC_STATUS,
1595 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1596 return 0;
1597 }
1598
1599 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1600 {
1601 PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1602 PCIBus *bus = &s->bus;
1603 pci_unregister_secondary_bus(bus);
1604 return 0;
1605 }
1606
1607 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1608 pci_map_irq_fn map_irq, const char *name)
1609 {
1610 PCIDevice *dev;
1611 PCIBridge *s;
1612
1613 dev = pci_create(bus, devfn, "pci-bridge");
1614 qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1615 qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1616 qdev_init_nofail(&dev->qdev);
1617
1618 s = DO_UPCAST(PCIBridge, dev, dev);
1619 pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1620 return &s->bus;
1621 }
1622
1623 PCIDevice *pci_bridge_get_device(PCIBus *bus)
1624 {
1625 return bus->parent_dev;
1626 }
1627
1628 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1629 {
1630 PCIDevice *pci_dev = (PCIDevice *)qdev;
1631 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1632 PCIBus *bus;
1633 int devfn, rc;
1634
1635 /* initialize cap_present for pci_is_express() and pci_config_size() */
1636 if (info->is_express) {
1637 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1638 }
1639
1640 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1641 devfn = pci_dev->devfn;
1642 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1643 info->config_read, info->config_write,
1644 info->header_type);
1645 if (pci_dev == NULL)
1646 return -1;
1647 rc = info->init(pci_dev);
1648 if (rc != 0)
1649 return rc;
1650
1651 /* rom loading */
1652 if (pci_dev->romfile == NULL && info->romfile != NULL)
1653 pci_dev->romfile = qemu_strdup(info->romfile);
1654 pci_add_option_rom(pci_dev);
1655
1656 if (qdev->hotplugged)
1657 bus->hotplug(pci_dev, 1);
1658 return 0;
1659 }
1660
1661 static int pci_unplug_device(DeviceState *qdev)
1662 {
1663 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1664
1665 dev->bus->hotplug(dev, 0);
1666 return 0;
1667 }
1668
1669 void pci_qdev_register(PCIDeviceInfo *info)
1670 {
1671 info->qdev.init = pci_qdev_init;
1672 info->qdev.unplug = pci_unplug_device;
1673 info->qdev.exit = pci_unregister_device;
1674 info->qdev.bus_info = &pci_bus_info;
1675 qdev_register(&info->qdev);
1676 }
1677
1678 void pci_qdev_register_many(PCIDeviceInfo *info)
1679 {
1680 while (info->qdev.name) {
1681 pci_qdev_register(info);
1682 info++;
1683 }
1684 }
1685
1686 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1687 {
1688 DeviceState *dev;
1689
1690 dev = qdev_create(&bus->qbus, name);
1691 qdev_prop_set_uint32(dev, "addr", devfn);
1692 return DO_UPCAST(PCIDevice, qdev, dev);
1693 }
1694
1695 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1696 {
1697 PCIDevice *dev = pci_create(bus, devfn, name);
1698 qdev_init_nofail(&dev->qdev);
1699 return dev;
1700 }
1701
1702 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1703 {
1704 int config_size = pci_config_size(pdev);
1705 int offset = PCI_CONFIG_HEADER_SIZE;
1706 int i;
1707 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1708 if (pdev->used[i])
1709 offset = i + 1;
1710 else if (i - offset + 1 == size)
1711 return offset;
1712 return 0;
1713 }
1714
1715 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1716 uint8_t *prev_p)
1717 {
1718 uint8_t next, prev;
1719
1720 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1721 return 0;
1722
1723 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1724 prev = next + PCI_CAP_LIST_NEXT)
1725 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1726 break;
1727
1728 if (prev_p)
1729 *prev_p = prev;
1730 return next;
1731 }
1732
1733 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1734 {
1735 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1736 }
1737
1738 /* Add an option rom for the device */
1739 static int pci_add_option_rom(PCIDevice *pdev)
1740 {
1741 int size;
1742 char *path;
1743 void *ptr;
1744
1745 if (!pdev->romfile)
1746 return 0;
1747 if (strlen(pdev->romfile) == 0)
1748 return 0;
1749
1750 if (!pdev->rom_bar) {
1751 /*
1752 * Load rom via fw_cfg instead of creating a rom bar,
1753 * for 0.11 compatibility.
1754 */
1755 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1756 if (class == 0x0300) {
1757 rom_add_vga(pdev->romfile);
1758 } else {
1759 rom_add_option(pdev->romfile);
1760 }
1761 return 0;
1762 }
1763
1764 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1765 if (path == NULL) {
1766 path = qemu_strdup(pdev->romfile);
1767 }
1768
1769 size = get_image_size(path);
1770 if (size < 0) {
1771 qemu_error("%s: failed to find romfile \"%s\"\n", __FUNCTION__,
1772 pdev->romfile);
1773 return -1;
1774 }
1775 if (size & (size - 1)) {
1776 size = 1 << qemu_fls(size);
1777 }
1778
1779 pdev->rom_offset = qemu_ram_alloc(size);
1780
1781 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1782 load_image(path, ptr);
1783 qemu_free(path);
1784
1785 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1786 0, pci_map_option_rom);
1787
1788 return 0;
1789 }
1790
1791 /* Reserve space and add capability to the linked list in pci config space */
1792 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1793 {
1794 uint8_t offset = pci_find_space(pdev, size);
1795 uint8_t *config = pdev->config + offset;
1796 if (!offset)
1797 return -ENOSPC;
1798 config[PCI_CAP_LIST_ID] = cap_id;
1799 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1800 pdev->config[PCI_CAPABILITY_LIST] = offset;
1801 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1802 memset(pdev->used + offset, 0xFF, size);
1803 /* Make capability read-only by default */
1804 memset(pdev->wmask + offset, 0, size);
1805 /* Check capability by default */
1806 memset(pdev->cmask + offset, 0xFF, size);
1807 return offset;
1808 }
1809
1810 /* Unlink capability from the pci config space. */
1811 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1812 {
1813 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1814 if (!offset)
1815 return;
1816 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1817 /* Make capability writeable again */
1818 memset(pdev->wmask + offset, 0xff, size);
1819 /* Clear cmask as device-specific registers can't be checked */
1820 memset(pdev->cmask + offset, 0, size);
1821 memset(pdev->used + offset, 0, size);
1822
1823 if (!pdev->config[PCI_CAPABILITY_LIST])
1824 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1825 }
1826
1827 /* Reserve space for capability at a known offset (to call after load). */
1828 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1829 {
1830 memset(pdev->used + offset, 0xff, size);
1831 }
1832
1833 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1834 {
1835 return pci_find_capability_list(pdev, cap_id, NULL);
1836 }
1837
1838 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1839 {
1840 PCIDevice *d = (PCIDevice *)dev;
1841 const pci_class_desc *desc;
1842 char ctxt[64];
1843 PCIIORegion *r;
1844 int i, class;
1845
1846 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1847 desc = pci_class_descriptions;
1848 while (desc->desc && class != desc->class)
1849 desc++;
1850 if (desc->desc) {
1851 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1852 } else {
1853 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1854 }
1855
1856 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1857 "pci id %04x:%04x (sub %04x:%04x)\n",
1858 indent, "", ctxt,
1859 d->config[PCI_SECONDARY_BUS],
1860 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1861 pci_get_word(d->config + PCI_VENDOR_ID),
1862 pci_get_word(d->config + PCI_DEVICE_ID),
1863 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1864 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1865 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1866 r = &d->io_regions[i];
1867 if (!r->size)
1868 continue;
1869 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1870 " [0x%"FMT_PCIBUS"]\n",
1871 indent, "",
1872 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1873 r->addr, r->addr + r->size - 1);
1874 }
1875 }
1876
1877 static PCIDeviceInfo bridge_info = {
1878 .qdev.name = "pci-bridge",
1879 .qdev.size = sizeof(PCIBridge),
1880 .init = pci_bridge_initfn,
1881 .exit = pci_bridge_exitfn,
1882 .config_write = pci_bridge_write_config,
1883 .header_type = PCI_HEADER_TYPE_BRIDGE,
1884 .qdev.props = (Property[]) {
1885 DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1886 DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1887 DEFINE_PROP_END_OF_LIST(),
1888 }
1889 };
1890
1891 static void pci_register_devices(void)
1892 {
1893 pci_qdev_register(&bridge_info);
1894 }
1895
1896 device_init(pci_register_devices)
QEmu